Abstract

An IC structure includes a memory stack, which includes a plurality of semiconductor dies horizontally separate with each other, a memory controller chip, an interposer, a logic processor chip and a packaging substrate. Each semiconductor die includes a top surface, a bottom surface, and four sidewalls, and a plurality of edge pads are arranged along the first sidewall. The memory controller chip is disposed under and electrically connected to the plurality of edge pads of each semiconductor die, wherein the first sidewall of each semiconductor die faces the memory controller chip. The interposer is disposed under and electrically connected to the memory controller chip. The logic processor chip is electrically connected to the memory controller chip. The packaging substrate is disposed under and electrically connected to the interposer.

IPC Classes  ?

• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

A semiconductor device includes a first semiconductor component and a second semiconductor component. The first semiconductor component includes a first substrate, a first dielectric layer and a first pad, wherein the first dielectric layer is disposed over the first substrate and has a first opening, and the first pad is disposed in the first opening. The second semiconductor component includes a second substrate, a second dielectric layer and a second pad, wherein the second dielectric layer is disposed over the second substrate and has a second opening, and the second pad is disposed in the second opening. The first dielectric layer is contact with the second dielectric layer, and the first pad is contact with the second pad.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An IC stack includes: a plurality of integrated circuit (IC) structure horizontally separate with each other, wherein each IC structure comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall; wherein the area of the bottom surface or the top surface is larger than that of any sidewall; a laterally extending RDL structure covering each first sidewall of the plurality of IC structures; and an upward extending thermal conductivity layer between two adjacent IC structures. The thermal conductivity of the upward extending thermal conductivity layer is higher than that of Si.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

An IC stack includes: semiconductor structures horizontally separate with each other, each semiconductor structure having a top surface, a bottom surface opposite the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall; the area of the bottom or top surface larger than that of any sidewall; and a laterally extending RDL structure covering the first sidewall of each semiconductor structure. A first semiconductor structure of the semiconductor structures comprises a first IC structure and a first neighboring structure separate from the first IC structure, the first IC structure and the first neighboring structure arranged along the first sidewall of the first semiconductor structure. The laterally extending RDL structure comprises bonding pads arranged along the first sidewall of the first semiconductor structure, the bonding pads over an edge of the first IC structure and an edge of the first neighboring structure.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass

Abstract

DRAM cell structures and methods for manufacturing the same are provided. The DRAM cell structure includes a semiconductor substrate having a well region and an original semiconductor surface, an access transistor located within the well region and having a gate structure, a bit line electrically coupled to the access transistor, a storage capacitor electrically coupled to the access transistor, a word line electrically coupled to the gate structure of the access transistor, an isolation structure within the well region and surrounding the access transistor, and a conductive interconnection structure positioned within the isolation structure and electrically connected to the well region of the semiconductor substrate.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 21/762 - Dielectric regions
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

An IC structure includes a memory stack including semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads arranged along a sidewall. The IC structure further includes a memory controller under the first memory stack and electrically connected to the edge pads of each semiconductor die, a processor circuit disposed over and electrically connected to the memory controller, and a packaging substrate under and electrically connected to the memory controller. A die area of the memory controller is larger than the sum of a horizontal cross-section area of the memory stack and a die area of the processor circuit. There is no interposer between the packaging substrate and the memory controller, and there is no TSV in each semiconductor die.

IPC Classes  ?

• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
• H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips

Abstract

An IC structure includes a memory stack including semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads arranged along a sidewall. The area of the bottom surface or the top surface of each semiconductor die is larger than that of any sidewall. The IC structure further includes a logic die with memory controller and processor circuit under the memory stack and electrically connected to the plurality of edge pads of each semiconductor memory die, and a packaging substrate under and electrically connected to the logic die with memory controller and processor. There is no interposer between the packaging substrate and the logic die with memory controller and processor circuit, and there is no TSV in each semiconductor die.

IPC Classes  ?

• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

IPC Classes  ?

• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

A 3D integrated circuit package is provided. The 3D integrated circuit package includes a substrate structure having a first surface and a second surface opposite to the first surface, a high-power die over the substrate structure, a lower-power die over the high-power die, a first interposer between the first surface of the substrate structure and the high-power die, and a second interposer between the high-power die and the lower-power die. The substrate structure includes a thermal enhancement portion located under the high-power die, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from other portions of the substrate structure. A substrate structure of the 3D integrated circuit package is also provided.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

A memory chip includes a plurality of memory banks, an I/O data bus, and a plurality of align circuits. Each memory bank outputs or receives a data set in parallel. The plurality of align circuits correspond to the plurality of memory banks respectively. The data set of one memory bank is transferred to one corresponding align circuit which then simultaneously transfers the data set to the I/O data bus in parallel, or the data set is transferred from the I/O data bus to the one corresponding align circuit which then simultaneously transfers the data set to the one memory bank in parallel. There is no parallel-to-serial circuit and serial-to-parallel circuit between the I/O data bus and each memory banks.

IPC Classes  ?

• G06F 13/20 - Handling requests for interconnection or transfer for access to input/output bus

Abstract

A hybrid memory chip as well as a memory system and a computing apparatus including the hybrid memory chip are provided. The hybrid memory chip includes: dynamic random access memory (DRAM) arrays; sense amplifier arrays, disposed around each of the DRAM arrays; and static random access memory (SRAM) arrays, disposed around each of the DRAM arrays, and respectively abutted with one of the sense amplifier arrays. The sense amplifier arrays are configured to perform read operations from the DRAM arrays and the SRAM arrays. Bit lines across the DRAM arrays extend through the sense amplifier arrays and the SRAM arrays.

IPC Classes  ?

• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines

Abstract

A semiconductor device includes a substrate, a memory component and a heat dissipation component. The memory component is disposed on the substrate. The heat dissipation component is disposed on the substrate. The heat dissipation component has a thermal conductivity greater than that of silicon.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/467 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing gases, e.g. air
• H01L 23/528 - Layout of the interconnection structure
• H10B 10/00 - Static random access memory [SRAM] devices

Goods & Services

Design of integrated circuits; Design of semiconductor chips

Abstract

A memory device is provided. The memory device includes: a package substrate; a memory chip, with chip inputs/outputs (I/Os), and attached to the package substrate; and package terminals, disposed on the package substrate, and having: functional package terminals, connected to the chip I/Os; no-connect (NC) package terminals, arranged among the functional package terminals and not connected to any of the chip I/Os; and redesigned NC package terminals, as additional ones of the NC package terminals but connected to the chip I/Os, so as to be functioned as additional functional package terminals.

IPC Classes  ?

• G11C 29/56 - External testing equipment for static stores, e.g. automatic test equipment [ATE]Interfaces therefor

Abstract

A semiconductor package includes: a first semiconductor die disposed over a first substrate; a plurality of second semiconductor dies disposed over the first semiconductor die or adjacent to the first semiconductor die; a plurality of first connectors arranged between and electrically connecting the first semiconductor die and the first substrate; a plurality of second connectors arranged between and electrically connecting two of the second semiconductor dies; a first dielectric layer encapsulating the plurality of second connectors; and a dielectric coating, different from the first dielectric layer, conformally formed on exposed surfaces of the plurality of first connectors and laterally surrounding the first dielectric layer. A plurality of air gaps are arranged between the plurality of first connectors.

IPC Classes  ?

• H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates

Abstract

A semiconductor device package is provided. The semiconductor device package comprises a first electronic component, a second electronic component above the first electronic component and an interconnection structure disposed external to both the first electronic component and the second electronic component and configured to electrically connect the first electronic component to the second electronic component, a package material configured to hold the first electronic component and the second electronic component together and an external connector configured to electrically connect the first and second electronic components to an external device. The first electronic component has a portion free from being covered by the second electronic component. The external connector is positioned directly above the portion of the first electronic component.

IPC Classes  ?

• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

A semiconductor circuit includes a semiconductor substrate, a transistor, and a voltage source. The semiconductor substrate has an original semiconductor surface. The transistor based on the semiconductor substrate includes a gate structure, a channel region, and a first conductive region. The channel region includes a first terminal and a second terminal. The first conductive region is electrically coupled to the first terminal of the channel region, and the first conductive region includes a top surface and a bottom surface, wherein the bottom surface is below the original semiconductor surface. The voltage source, through the semiconductor substrate, is electrically coupled to the transistor from the bottom surface of the first conductive region.

IPC Classes  ?

• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
• H01L 21/762 - Dielectric regions
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/45 - Ohmic electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.

IPC Classes  ?

• G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
• G11C 11/408 - Address circuits
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/4094 - Bit-line management or control circuits

Abstract

A memory includes a plurality of e-fuse sets, a sensing circuit, an Error-Correcting Code (ECC) circuit, and a plurality of registers. Each e-fuse set includes a plurality of e-fuses, and each e-fuse of the plurality of e-fuses corresponds to a first blown result. The sensing circuit senses the plurality of e-fuses to output a plurality of first blown results. The ECC circuit receives the plurality of first blown results and corrects a first blown result if the first blown result includes an error or directly outputs the first blown result if the first blown result comprises no error to generate a second blown result. The plurality of registers receive a plurality of second blown results. The plurality of second blown results adjusts predetermined settings of the memory, and a number of the plurality of registers is less than a number of the plurality of e-fuses.

IPC Classes  ?

• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

Abstract

A memory with e-fuses includes a receiving circuit and a plurality of e-fuse groups. Each e-fuse group of the e-fuse groups is coupled to the receiving circuit through a corresponding bus group. The receiving circuit receives a plurality of blown signal sets each time and transmits each of the blown signal sets to a e-fuse group, and predetermined e-fuses of the e-fuse group are blown according to the each of the blown signal sets to adjust predetermined settings of the memory, and the each of the blown signal sets only corresponds to the e-fuse group. A number of the plurality of blown signal sets is not greater than a number of the e-fuse groups.

IPC Classes  ?

• G11C 29/56 - External testing equipment for static stores, e.g. automatic test equipment [ATE]Interfaces therefor

Abstract

A memory device is provided. The memory device includes: a latch circuit, having a first inverter and a second inverter cross-coupled with each other, wherein a first pull up transistor and a first pull down transistor of the first inverter are coupled through a first selection transistor, and a second pull up transistor and a second pull down transistor of the second inverter are coupled through a second selection transistor; a first access transistor, coupled to a first storage node of the latch circuit; and a second access transistor, coupled to a second storage node of the latch circuit.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits
• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

A transistor with low leakage currents includes a substrate, a gate, spacers, pad dielectric layers, a source, and a drain. The gate is formed above a gate dielectric layer, wherein the gate dielectric layer has a first dielectric constant. The spacers have a second dielectric constant. The pad dielectric layers are formed under the spacers and having a third dielectric constant. The source and the drain are adjacent to the spacers and in two opposite directions of the gate. The first dielectric constant, the second dielectric constant, and the third dielectric constant are different from each other.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device

Abstract

A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.

IPC Classes  ?

• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A semiconductor package is provided. The semiconductor package includes a first die having a plurality of first metal pads at a first bonding side and a second die over the first die, having a plurality of second metal pads at a second bonding side facing the first bonding side. Each of the first metal pads corresponds to each of the second metal pads with a pitch no greater than about 10 μm. The semiconductor package further includes a first dielectric layer surrounding and in contact with a sidewall of the first metal pads and a second dielectric layer surrounding and in contact with a sidewall of the second metal pads. A method for manufacturing a semiconductor package is also provided.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

A memory chip includes a memory bank, I/O data bus, and a first plurality of sensing amplifiers. The first plurality of sensing amplifiers are between the memory bank and the I/O data bus and configured to output a first plurality of data in parallel to the I/O data bus. There is no parallel-to-serial circuit and no serial-to-parallel circuit in the memory chip.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.

IPC Classes  ?

• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present application discloses a semiconductor package which includes a processor die powered by either a front-side or a backside power delivery network, a plurality of memory dies and control dies stacked over the processor die, a plurality of high-thermal-conductivity (HTC) interconnects formed on, located between and/or placed side-by-side with the dies, a HTC substrate carrying all the dies, a HTC structural member, and a HTC heat spreader/heatsink with the dies and the HTC heat spreader thermally coupled to other HTC components in the semiconductor package. The semiconductor components can be configured to go beyond the traditional single-sided interconnection and cooling topologies to enable dual-or multi-sided cooling, power supply, and signaling.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/528 - Layout of the interconnection structure
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

A semiconductor package includes a first integrated circuit (IC) structure. The first IC structure includes: a first body having a first primary surface and a first secondary surface, the first primary surface being substantially perpendicular to the first secondary surface; and an interconnect structure. The interconnect structure includes a primary redistribution layer (RDL) over the first primary surface, the primary RDL having a second secondary surface that is aligned with the first secondary surface of the first body, wherein the first secondary surface and the second secondary surface jointly form a secondary plane. The primary RDL further comprises a first conductive element exposed through the second secondary surface of the primary RDL; and a secondary RDL over the secondary plane, wherein the secondary RDL is electrically connected to the first conductive element of the primary RDL and other conductive elements of the first body exposed through the first secondary plane.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

A semiconductor package is provided, which includes a processor die powered by either a front-side or a backside power delivery network, a plurality of memory dies and control dies stacked over the processor die, a plurality of high-thermal-conductivity interconnects located between and/or placed side-by-side with the dies, a substrate carrying all the dies with the substrate having a first cavity allowing a liquid to pass through, and a cold plate disposed over and in direct thermal contact with the top dies with the cold plate having a second cavity configured to connect to the first cavity and allowing the liquid to flow between the first and second cavities. This semiconductor package can be configured to go beyond the traditional single-sided interconnection and cooling topologies to enable dual- or multi-sided cooling, power supply, and signaling.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An IC system includes a package, a plurality of memory dies, and a logic chip. The plurality of memory dies are within the package, each memory die includes a memory region and abridge area, the memory region of each memory die includes a plurality of memory cells and each memory cell includes a first transistor, and the bridge area of each memory die includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The logic chip includes a logic bridge area and a plurality of second transistors, and the logic bridge area includes a plurality of logic I/O pads. Each memory die is horizontally spaced apart from the logic chip, and the plurality of memory I/O pads of each memory die are electrically coupled to the plurality of logic I/O pads. Each memory die is horizontally spaced apart from each other.

IPC Classes  ?

• G11C 5/04 - Supports for storage elementsMounting or fixing of storage elements on such supports
• G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H10B 12/00 - Dynamic random access memory [DRAM] devices
• H10D 88/00 - Three-dimensional [3D] integrated devices

Abstract

A semiconductor structure includes a substrate and a first circuit containing composite block over the substrate. The first circuit containing composite block includes a through via therein and a re-distribution layer thereon. The first circuit containing composite block includes a semiconductor block and a diamond block.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids

Abstract

A method to form a first diamond composite wafer, a second diamond composite wafer or a third diamond composite wafer with a predetermined diameter includes the following steps: preparing a plurality of diamond blocks, wherein each diamond block has a dimension smaller than the predetermined diameter; attaching the plurality of diamond blocks to a first semiconductor substrate with the predetermined diameter to form a first temporary composite wafer, wherein a thermal conductivity of the first semiconductor substrate is smaller than that of the diamond block; and filling gaps among the plurality of diamond blocks of the first temporary composite wafer to form the first diamond composite wafer; or attaching the first diamond composite wafer to a second semiconductor substrate with the predetermined diameter to form the second diamond composite wafer, or removing the first semiconductor substrate from the first diamond composite wafer to form the third diamond composite wafer.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

A method to process a diamond composite wafer includes the following steps: (a). forming a plurality of through vias in the diamond composite wafer and a first re-distribution layer on a firs side of the diamond composite wafer; (b). attaching a temporary carrier to the first re-distribution layer, and forming a second re-distribution layer on a second side of the diamond composite wafer; and (c). releasing the temporary carrier to form a circuit containing diamond composite wafer.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

Abstract

A probe card system is provided. The probe card system, including a tester assembly, a probe head body configured to couple with the tester assembly, a first interconnection structure on a first side of the probe head body, and a probe layer structure on the first interconnection structure on the first side of the probe head body which is configured to engage with a wafer under test (WUT). The probe layer structure includes a sacrificial layer in connection with the first interconnection structure, a bonding layer in connection with the sacrificial layer, and a plurality of probe tips each in connection with respective conductive patterns exposed from the bonding layer and electrically coupled to the first interconnection structure. The sacrificial layer allows removal of the bonding layer and the plurality of probe tips via an etching operation. A method of manufacturing a probe card system is also provided.

IPC Classes  ?

• G01R 1/073 - Multiple probes
• G01R 1/04 - HousingsSupporting membersArrangements of terminals
• G01R 1/067 - Measuring probes
• G01R 1/20 - Modifications of basic electric elements for use in electric measuring instrumentsStructural combinations of such elements with such instruments
• G01R 3/00 - Apparatus or processes specially adapted for the manufacture of measuring instruments
• G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
• G01R 31/26 - Testing of individual semiconductor devices
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

Abstract

A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

IPC Classes  ?

• H01L 29/76 - Unipolar devices
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS

Abstract

A semiconductor package is provided. The semiconductor package includes an integrated circuit (IC) block and a first substrate. The IC block has a first interconnect layer. The first substrate carries the IC block. The first substrate includes a second interconnect layer facing the first interconnect layer and a third interconnect layer opposite to the second interconnect layer. Furthermore, at least one of the second interconnect layer or the third interconnect layer is composed of a dielectric material and a conductive material substantially identical to a corresponding dielectric material and a corresponding conductive material of the first interconnect layer.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

The present invention discloses a memory cell structure. The memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a storage electrode, wherein the capacitor is over the transistor and the storage electrode is electrically coupled to the second conductive region of the transistor. The capacitor includes a capacitor periphery, and the transistor is located within the capacitor periphery.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

IPC Classes  ?

• G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Abstract

An error correction method comprises: when a decoder determines that an input analog code is at a forbidden state, setting a digital binary code as a first predetermined code and inputting the digital binary code to an ECC engine; determining whether the digital binary code has no error or two errors; when the digital binary code has no error, outputting the digital binary code after ECC by the ECC engine; when the digital binary code has two errors, resetting the digital binary code as a second predetermined code and inputting the digital binary code to the ECC engine for ECC; and when the decoder determines that the input analog code is not at the forbidden state, decoding the input analog code into the digital binary code and inputting the digital binary code to the ECC engine for ECC.

IPC Classes  ?

• H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

−3 fF.

IPC Classes  ?

• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

The present invention discloses a method to form a composite semiconductor wafer with a first dimension. The method comprises: attaching a set of thermal dissipation layers to a temporary carrier; bonding the temporary carrier with the set of thermal dissipation layers to a semiconductor substrate with the first dimension, such that the set of thermal dissipation layers are bonded to the semiconductor substrate; and removing the temporary carrier to form composite semiconductor wafer with the first dimension.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

A die package includes a semiconductor die, a passive component, a molding compound and a redistribution layer (RDL). The semiconductor die includes a first bonding pad. The passive component includes a second bonding pad. The molding compound encloses the semiconductor die and the passive component. The RDL is disposed over the semiconductor die and the passive component and electrically connecting the first bonding pad with the second bonding pad. The semiconductor die is vertically overlapped with the passive component.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

An error correction method comprises: when a decoder determines that an input analog code is at a forbidden state, setting a digital binary code as a first predetermined code and inputting the digital binary code to an ECC engine; determining whether the digital binary code has no error or two errors; when the digital binary code has no error, outputting the digital binary code after ECC by the ECC engine; when the digital binary code has two errors, resetting the digital binary code as a second predetermined code and inputting the digital binary code to the ECC engine for ECC; and when the decoder determines that the input analog code is not at the forbidden state, decoding the input analog code into the digital binary code and inputting the digital binary code to the ECC engine for ECC.

IPC Classes  ?

• H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

A transistor structure includes a gate, a spacer, a channel region, a first concave, and a first conductive region. The gate is above a silicon surface. The spacer is above the silicon surface and at least covers a sidewall of the gate. The channel region is under the silicon surface. The first conductive region is at least partially formed in the first concave, wherein a conductive region of a neighborhood transistor structure next to the transistor structure is at least partially formed in the first concave.

IPC Classes  ?

• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Abstract

The invention provides a memory module, comprising a first memory die with a first surface and a third surface opposite to the first surface, wherein a first redistribution layer and a first original pad set are formed over the first surface; a second memory die with a second surface and a fourth surface opposite to the second surface, wherein a second original pad set are formed over the second surface; a wire bonding pad set disposed over the first surface, wherein the wire bonding pad set are electrically connected with the first original pad set; and a plurality of wires bonded to the wire bonding pad set, wherein the first memory die is bonded to the second memory die, the first surface faces the second surface, and the second original pad set are electrically connected with the wire bonding pad set.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A data collection and analysis method includes applying a first noise step to an original data stream with an original character to generate a first data stream with a first character; and applying a second noise step to the first data stream to generate a second data stream with a second character, wherein a first variation between the original character and the first character is greater than a second variation between the original character and the second character.

IPC Classes  ?

• G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
• H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
• G06F 7/58 - Random or pseudo-random number generators

Abstract

A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/40 - Electrodes

Abstract

A transistor structure includes a substrate, a gate conductive region, a gate dielectric layer and a first conductive region. At least a portion of the gate conductive region is disposed below a surface of the substrate. The gate dielectric layer surrounds a bottom wall and sidewalls of the gate conductive region. A bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.

IPC Classes  ?

• H01L 29/786 - Thin-film transistors
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

Abstract

An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices
• G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A transistor structure includes a gate conductive region, a gate dielectric region, a channel region and a drain region. The gate conductive region is below an original surface of a substrate. The gate dielectric region surrounds the gate conductive region. The channel region surrounds the gate dielectric region. The drain region is horizontally spaced apart from the gate conductive region, wherein the drain region includes a highly doped region; wherein the gate dielectric region includes a first dielectric portion and a second dielectric portion, the first dielectric portion is positioned between the gate conductive region and the highly doped region, and the second dielectric portion is positioned between the gate conductive region and the channel region; wherein a horizontal thickness of the first dielectric portion is greater than that of the second dielectric portion.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/66 - Types of semiconductor device

Abstract

A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.

IPC Classes  ?

• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present invention provides a new complementary MOSFET structure with localized isolations in silicon substrate to reduce leakages and prevent latch-up. The complementary MOSFET structure comprises a semiconductor wafer substrate with a semiconductor surface, a P type MOSFET comprising a first conductive region, a N type MOSFET comprising a second conductive region, and a cross-shape localized isolation region between the P type MOSFET and the N type MOSFET. Wherein, the cross-shape localized isolation region includes a horizontally extended isolation region below the semiconductor surface, and the horizontally extended isolation region contacts to a bottom side of the first conductive region and a bottom side of the second conductive region.

IPC Classes  ?

• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

A transistor structure includes a semiconductor substrate, a channel layer, a gate structure and a first conductive region. The semiconductor substrate includes a semiconductor surface. The channel layer is independent from the semiconductor substrate and covers the semiconductor surface. The gate structure, covers the channel layer. The first conductive region is coupled to the channel layer.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device

Abstract

The present invention provides a new MOSFET structure with controllable channel length by forming lightly doped drains without using ion implantation. The MOSFET structure comprises a semiconductor wafer substrate with a semiconductor surface, a gate structure over the semiconductor surface, a channel region under the semiconductor surface, and a first conductive region electrically coupled to the channel region. The first conductive region comprises a lightly doped drain region independent from the semiconductor wafer substrate.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/66 - Types of semiconductor device

Abstract

The present invention provides a single monolithic the comprising a first schematic circuit manufactured based on a first technology node. A die area of the single monolithic die is smaller than a die area of another monolithic die with a second schematic circuit made based on the first technology node, wherein the first schematic circuit is the same as the second schematic circuit, and the first schematic circuit is a SRAM circuit, a logic circuit, a combination of SRAM and logic circuit, or a major function block circuit.

IPC Classes  ?

• G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
• G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
• H03K 19/17728 - Reconfigurable logic blocks, e.g. lookup tables
• H03K 19/1776 - Structural details of configuration resources for memories
• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

An interconnection structure includes a first dielectric layer, a first conduction layer, a conductor pillar, an upper dielectric layer and an upper conduction layer. The first dielectric layer is disposed over a first terminal of a device. The first conduction layer is disposed over the first dielectric layer. The conductor pillar is connected to the first terminal. The upper dielectric layer is disposed over the first conduction layer. The upper conduction layer is disposed over the upper dielectric layer. The conductor pillar connects to the upper conduction layer but disconnects from the first conduction layer.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

The present invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word line coupled to a gate terminal of the access transistor. During the period between the word line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

IPC Classes  ?

• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Abstract

The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.

IPC Classes  ?

• G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
• G11C 11/408 - Address circuits
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/4094 - Bit-line management or control circuits

Goods & Services

Computer memory hardware; Computer memory devices; Random access memory (RAM) cards; Facial recognition plant being downloadable computer programs using artificial intelligence for facial recognition; Microchips; Microcomputers; Random access storage, namely, Dynamic random-access memory (DRAM), Static random-access memory (SRAM), and pseudo Static random-access memory (pseudo SRAM); Read-only integrated circuit memory chips; Portable blank flash memory cards; Biometric identity cards; Very-large-scale integration (VLSI) being semiconductor integrated circuits; Silicon chips; Silicon Wafers; Wafers for integrated circuits; Semiconductor devices; Integrated circuits; Semiconductor chips; Computer hardware; Random access memory card; Blank flash memory cards; Semi-conductors; Integrated circuits substrate; Electronic semiconductor component, namely, semiconductors, and integrated circuits; Micro circuits; Integrated circuit board; Large Scale Integration semiconductor integrated circuits

Abstract

A memory system comprises a memory and a physical layer circuit. The memory system comprises a memory, a data bus and a single-pin STB. The memory receives a parallel command though the data bus, and receives a serial command through the STB. The physical layer circuit is configured to transmit the parallel command to the data bus. The physical layer circuit is configured to convert STB input data from the controller into the serial command and transmit the serial command to the STB.

IPC Classes  ?

• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

Goods & Services

Chips having multi-well arrays that can be used in chemical analysis, biological analysis or patterning for scientific, laboratory or medical research use; Semiconductor chips or chipsets for use in enabling memory, multiway communications and processing capabilities; Known good die memory (KGDM); known good die; known good die memory; DRAM module; specialty DRAM; automotive DRAM; industrial DRAM; micro circuits; micro integrated circuits; electronic circuits; semiconductor components; chips; computer memory; computer memory devices; Integrated circuits and integrated circuit cores for use in wireless communications and wireless communication equipment and apparatus and digital signal processors (DSP); Integrated circuit modules; Electronic integrated circuits; Decision circuits; Large scale integrated circuits; Circuits for heavy current; Cards with integrated circuits; Microcircuits; Very large scale integration (VLSI) semiconductor integrated circuits; Electric and electronic circuits; Design libraries, namely, downloadable electronic data files for use in integrated circuit and semiconductor design; Electronic components in the nature of semiconductors and integrated circuits; Wafers for integrated circuits; Integrated circuit cards and components; Flexible circuit boards; Dynamic random access memory (DRAM); Computer software in the field of collision avoidance, object detection, object recognition, object tracking, volume measurement, SLAM (Simultaneous Localization And Mapping) and SLAM tracking, eye and gesture tracking and control, human pose detection and tracking, hand tracking, face recognition, and VR (Virtual Reality), AR (Augmented Reality) and MR (Mixed Reality); Electronic hardware and software for use in collision avoidance, object detection, object recognition, object tracking, volume measurement, SLAM (Simultaneous Localization And Mapping) and SLAM tracking, eye and gesture tracking and control, human pose detection and tracking, hand tracking, face recognition; Electronic security apparatus and surveillance apparatus; Software and electronic hardware utilizing eye and gesture tracking technology; Algorithm software programs for collision avoidance, object detection, object recognition, object tracking, volume measurement, SLAM (Simultaneous Localization And Mapping) and SLAM tracking, eye and gesture tracking and control, human pose detection and tracking, hand tracking, face recognition; Semiconductor chip sets for use in enabling image signal processing; Integrated circuits and integrated circuit cores for use in image signal processing; Chipsets; Semiconductor chip sets; Microchips (computer hardware); Silicon chips; Semiconductor chips; Multiprocessor chips; Computer chips; integrated circuits (IC); computer hardware; computer components; computer circuits; Semiconductors; Semiconductor devices; Semiconductor wafers; Chips, chip sets, and modules for 3D sensing (collection of information in 3D dimension), 3D sensor fusion and 3D perception (reactions and decisions made based on collected information). Design of integrated circuits; Design of computer hardware, integrated circuits, communications hardware and software and computer networks for others; Development of technologies for the fabrication of circuits for wireless communication, electronic data processing, consumer electronic, automotive electronics; Design for others of integrated circuits and integrated circuit cores for use in wireless communications and wireless communication equipment and apparatus and digital signal processors (DSP); Research, development, and design of various electronic products and semiconductor products, including known good die, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductor, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Structure design for semiconductor products, including known good die, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductor, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Testing and consulting of various electronic products and semiconductor products, including known good die, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductor, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Quality inspection, testing and identification of semiconductor products, including known good die, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductor, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Research in the area of semiconductor processing technology; Design and development of automated controller systems, namely, temperature, humidity and electrical controllers; Development and implementation of software for testing of electronic components and electronic systems; Development of electronic hardware; Development and implementation of software for productization of electronic components and electronic systems; Development of technology in the field of semiconductor process for the purpose of productization of electronic components and electronic systems.

Goods & Services

Electronic computer hardware and downloadable and recorded software for use in collision avoidance, object detection, object recognition, object tracking, volume measurement, SLAM (Simultaneous Localization And Mapping) and SLAM tracking, eye and gesture tracking and control, human pose detection and tracking, hand tracking, face recognition; Electronic security apparatus and surveillance apparatus, namely, camera modules being cameras to be incorporated into electronic devices; Downloadable and recorded computer software programs for collision avoidance, object detection, object recognition, object tracking, volume measurement, SLAM (Simultaneous Localization And Mapping) and SLAM tracking, eye and gesture tracking and control, human pose detection and tracking, hand tracking, face recognition; Semiconductor chip sets for use in enabling image signal processing; Integrated circuits for use in image signal processing; Design libraries, namely, downloadable electronic data files featuring integrated circuit and semiconductor designs for use in integrated circuit and semiconductor design; Electronic components in the nature of semiconductors and integrated circuits; Semiconductor chipsets; Semiconductor chip sets; Microchips being components of computer hardware; Silicon chips; Semiconductor chips; Multiprocessor chips; Computer chips; Integrated circuits (IC); Micro integrated circuits; Electronic circuits; Computer hardware; Electronic components for computers; Computer circuit boards; Integrated circuit modules; Electronic integrated circuits; Decision circuits; Large scale integrated circuits; Electric and electronic circuits; Wafers for integrated circuits; Integrated circuit cards and components; Semiconductors; Semiconductor devices; Semiconductor wafers; Semiconductor chips, chip sets, and modules for 3D sensing in the nature of collecting information in three dimensions, 3D sensor fusion, and 3D perception in the nature of making certain decisions and reactions in accordance with the collected information; Plates, glass slides or chips having multi-well arrays that can be used in chemical analysis, biological analysis or patterning for scientific, laboratory or medical research use; Semiconductor chip sets for use in enabling memory, multiway communications and processing capabilities; Known good die computer memory; Dynamic random access memory (DRAM module); Specialty dynamic random access memory (DRAM); Automotive dynamic random access memory (DRAM); Industrial dynamic random access memory (DRAM); Computer memory; Computer memory devices; Integrated circuits for use in wireless communications and wireless communication equipment and apparatus and digital signal processors (DSP); Circuits for heavy current; Cards with integrated circuits; Microcircuits; Very large scale integration (VLSI) semiconductor integrated circuits; Flexible circuit boards; Dynamic random access memory (DRAM) Design of integrated circuits; Design of computer hardware, integrated circuits, communications hardware and software and computer networks for others; Development of technologies for the fabrication of circuits for wireless communication, electronic data processing, consumer electronics, automotive electronics; Design for others of integrated circuits for use in wireless communications and wireless communication equipment and apparatus and digital signal processors (DSP); Research, development, and design of various electronic products and semiconductor products, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductor, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Structure design for semiconductor products, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductor, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Testing of and technology consulting in the field of various electronic products and semiconductor products, namely, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductor, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Inspection for quality control purposes and testing of semiconductor products, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductors, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Research in the area of semiconductor processing technology; Design and development of automated controller systems, namely, temperature, humidity and electrical controllers; Development and implementation of software, hardware and technology solutions for the purpose of testing of electronic components and electronic systems; Development and implementation of software, hardware and technology solutions for the purpose of productization of electronic components and electronic systems

Goods & Services

Chips having multi-well arrays that can be used in chemical analysis, biological analysis or patterning for scientific, laboratory or medical research use; Semiconductor chips or chipsets for use in enabling memory, multiway communications and processing capabilities; known good die memory (KGDM); known good die; known good die memory; DRAM module; specialty DRAM; automotive DRAM; industrial DRAM; micro circuits; micro integrated circuits; electronic circuits; semiconductor components; chips; computer memory; computer memory devices; Integrated circuits and integrated circuit cores for use in wireless communications and wireless communication equipment and apparatus and digital signal processors (DSP); Integrated circuit modules; Electronic integrated circuits; Decision circuits; Large scale integrated circuits; Circuits for heavy current; Cards with integrated circuits; Microcircuits; Very large scale integration (VLSI) semiconductor integrated circuits; Electric and electronic circuits; Design libraries, namely, downloadable electronic data files for use in integrated circuit and semiconductor design; Electronic components in the nature of semiconductors and integrated circuits; Wafers for integrated circuits; Integrated circuit cards and components; Flexible circuit boards; Dynamic random access memory (DRAM); Computer software in the field of collision avoidance, object detection, object recognition, object tracking, volume measurement, SLAM (Simultaneous Localization And Mapping) and SLAM tracking, eye and gesture tracking and control, human pose detection and tracking, hand tracking, face recognition, and VR (Virtual Reality), AR (Augmented Reality) and MR (Mixed Reality); Electronic hardware and software for use in collision avoidance, object detection, object recognition, object tracking, volume measurement, SLAM (Simultaneous Localization And Mapping) and SLAM tracking, eye and gesture tracking and control, human pose detection and tracking, hand tracking, face recognition; Electronic security apparatus and surveillance apparatus; Software and electronic hardware utilizing eye and gesture tracking technology; Algorithm software programs for collision avoidance, object detection, object recognition, object tracking, volume measurement, SLAM (Simultaneous Localization And Mapping) and SLAM tracking, eye and gesture tracking and control, human pose detection and tracking, hand tracking, face recognition; Semiconductor chip sets for use in enabling image signal processing; Integrated circuits and integrated circuit cores for use in image signal processing; Chipsets; Semiconductor chip sets; Microchips (computer hardware); Silicon chips; Semiconductor chips; Multiprocessor chips; Computer chips; integrated circuits (IC); computer hardware; computer components; computer circuits; Semiconductors; Semiconductor devices; Semiconductor wafers; Chips, chip sets, and modules for 3D sensing (collection of information in 3D dimension), 3D sensor fusion and 3D perception (reactions and decisions made based on collected information). Design of integrated circuits; Design of computer hardware, integrated circuits, communications hardware and software and computer networks for others; Development of technologies for the fabrication of circuits for wireless communication, electronic data processing, consumer electronic, automotive electronics; Design for others of integrated circuits and integrated circuit cores for use in wireless communications and wireless communication equipment and apparatus and digital signal processors (DSP); Research, development, and design of various electronic products and semiconductor products, including known good die, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductor, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Structure design for semiconductor products, including known good die, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductor, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Testing and consulting of various electronic products and semiconductor products, including known good die, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductor, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Quality inspection, testing and identification of semiconductor products, including known good die, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductor, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Research in the area of semiconductor processing technology; Design and development of automated controller systems, namely, temperature, humidity and electrical controllers; Development and implementation of software for testing of electronic components and electronic systems; Development of electronic hardware; Development and implementation of software for productization of electronic components and electronic systems; Development of electronic hardware; Development of technology in the field of semiconductor process for the purpose of productization of electronic components and electronic systems.

Goods & Services

Chips having multi-well arrays that can be used in chemical analysis, biological analysis or patterning for scientific, laboratory or medical research use; Semiconductor chips or chipsets for use in enabling memory, multiway communications and processing capabilities; known good die memory (KGDM); known good die; known good die memory; DRAM module; specialty DRAM; automotive DRAM; industrial DRAM; micro circuits; micro integrated circuits; electronic circuits; semiconductor components; chips; computer memory; computer memory devices; Integrated circuits and integrated circuit cores for use in wireless communications and wireless communication equipment and apparatus and digital signal processors (DSP); Integrated circuit modules; Electronic integrated circuits; Decision circuits; Large scale integrated circuits; Circuits for heavy current; Cards with integrated circuits; Microcircuits; Very large scale integration (VLSI) semiconductor integrated circuits; Electric and electronic circuits; Design libraries, namely, downloadable electronic data files for use in integrated circuit and semiconductor design; Electronic components in the nature of semiconductors and integrated circuits; Wafers for integrated circuits; Integrated circuit cards and components; Flexible circuit boards; Dynamic random access memory (DRAM); Computer software in the field of collision avoidance, object detection, object recognition, object tracking, volume measurement, SLAM (Simultaneous Localization And Mapping) and SLAM tracking, eye and gesture tracking and control, human pose detection and tracking, hand tracking, face recognition, and VR (Virtual Reality), AR (Augmented Reality) and MR (Mixed Reality); Electronic hardware and software for use in collision avoidance, object detection, object recognition, object tracking, volume measurement, SLAM (Simultaneous Localization And Mapping) and SLAM tracking, eye and gesture tracking and control, human pose detection and tracking, hand tracking, face recognition; Electronic security apparatus and surveillance apparatus; Software and electronic hardware utilizing eye and gesture tracking technology; Algorithm software programs for collision avoidance, object detection, object recognition, object tracking, volume measurement, SLAM (Simultaneous Localization And Mapping) and SLAM tracking, eye and gesture tracking and control, human pose detection and tracking, hand tracking, face recognition; Semiconductor chip sets for use in enabling image signal processing; Integrated circuits and integrated circuit cores for use in image signal processing; Chipsets; Semiconductor chip sets; Microchips (computer hardware); Silicon chips; Semiconductor chips; Multiprocessor chips; Computer chips; integrated circuits (IC); computer hardware; computer components; computer circuits; Semiconductors; Semiconductor devices; Semiconductor wafers; Chips, chip sets, and modules for 3D sensing (collection of information in 3D dimension), 3D sensor fusion and 3D perception (reactions and decisions made based on collected information). Design of integrated circuits; Design of computer hardware, integrated circuits, communications hardware and software and computer networks for others; Development of technologies for the fabrication of circuits for wireless communication, electronic data processing, consumer electronic, automotive electronics; Design for others of integrated circuits and integrated circuit cores for use in wireless communications and wireless communication equipment and apparatus and digital signal processors (DSP); Research, development, and design of various electronic products and semiconductor products, including known good die, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductor, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Structure design for semiconductor products, including known good die, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductor, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Testing and consulting of various electronic products and semiconductor products, including known good die, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductor, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Quality inspection, testing and identification of semiconductor products, including known good die, known good die memory, dynamic random access memory, DRAM modules, integrated circuits, micro circuits, micro integrated circuits, electronic circuits, semiconductor, semiconductor components, semiconductor chips, computer hardware, computer memory, computer memory devices, and computer components; Research in the area of semiconductor processing technology; Design and development of automated controller systems, namely, temperature, humidity and electrical controllers; Development and implementation of software for testing of electronic components and electronic systems; Development of electronic hardware; Development and implementation of software for productization of electronic components and electronic systems; Development of electronic hardware; Development of technology in the field of semiconductor process for the purpose of productization of electronic components and electronic systems.

Goods & Services

Downloadable and recorded computer software for collision avoidance, object detection, object recognition, object tracking, volume measurement, SLAM (Simultaneous Localization And Mapping) and SLAM tracking, eye and gesture tracking and control, human pose detection and tracking, hand tracking, face recognition, VR (Virtual Reality), AR (Augmented Reality) and MR(Mixed Reality); Electronic computer hardware and downloadable and recorded software for use in collision avoidance, object detection, object recognition, object tracking, volume measurement, SLAM (Simultaneous Localization And Mapping) and SLAM tracking, eye and gesture tracking and control, human pose detection and tracking, hand tracking, face recognition; Electronic security apparatus and surveillance apparatus, namely, camera modules being cameras to be incorporated into electronic devices; Downloadable and recorded computer software and electronic computer hardware utilizing eye and gesture tracking technology for collision avoidance, object detection, object recognition, object tracking, volume measurement, SLAM (Simultaneous Localization And Mapping) and SLAM tracking, eye and gesture tracking and control, human pose detection and tracking, hand tracking, face recognition; Downloadable and recorded computer software programs for collision avoidance, object detection, object recognition, object tracking, volume measurement, SLAM (Simultaneous Localization And Mapping) and SLAM tracking, eye and gesture tracking and control, human pose detection and tracking, hand tracking, face recognition; Semiconductor chip sets for use in enabling image signal processing; Integrated circuits for use in image signal processing; Design libraries, namely, downloadable electronic data files featuring integrated circuit and semiconductor designs for use in integrated circuit and semiconductor design; Electronic components in the nature of semiconductors and integrated circuits; Semiconductor chipsets; Semiconductor chip sets; Microchips being components of computer hardware; Silicon chips; Semiconductor chips; Multiprocessor chips; Computer chips; Integrated circuits; Integrated circuits (IC); Micro integrated circuits; Electronic circuits; Semiconductor components, namely, image signal processors (ISPs), system-on-chip (SoC), and application specific integrated circuits (ASICs); Computer hardware; Electronic components for computers; Computer circuit boards; Integrated circuit modules; Electronic integrated circuits; Decision circuits; Large scale integrated circuits; Electric and electronic circuits; Wafers for integrated circuits; Integrated circuit cards and components; Integrated circuit module; Semiconductors; Semiconductor devices; Semiconductor wafers; Semiconductor chips, chip sets, and modules for 3D sensing, 3D sensor fusion, and 3D perception

Abstract

A memory controller includes a command processor. When an access command is performed by the memory controller, the command processor generates a column address information to the memory between issuing an active command to the memory and issuing a read or write command to the memory. The column address information and the active command are issued by the command processor based on the access command.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

IPC Classes  ?

• G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Abstract

An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.

IPC Classes  ?

• G11C 11/24 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using capacitors
• H01L 27/108 - Dynamic random access memory structures
• G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

The invention relates to a DRAM structure which comprise a capacitor set and at least a transistor. The capacitor set includes a first capacitor with a first electrode and a second capacitor with a second electrode, and a counter electrode is shared by the first and the second capacitors. The counter electrode is perpendicular or substantially perpendicular to an extension direction of an active region of the transistor, or the counter electrode is not positioned above or below the first and second electrode.

IPC Classes  ?

• G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• H01L 27/108 - Dynamic random access memory structures
• H01L 49/02 - Thin-film or thick-film devices
• G11C 11/408 - Address circuits

Abstract

A memory controller includes a command processor. When an access command is performed by the memory controller, the command processor generates a row address information to the memory before issuing an active command to the memory. The row address information and the active command are issued by the command processor based on the access command.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management

Abstract

A memory chip includes a memory bank, an I/O data bus, and a first plurality of sensing amplifiers. The first plurality of sensing amplifiers is configured to parallelly output a first plurality of data. A width of the I/O data bus is equal to a width of the first plurality of data parallelly outputted by the first plurality of sensing amplifiers.

IPC Classes  ?

• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers

Goods & Services

Chipsets; Semiconductor chip sets; Silicon chips; Semiconductor chips; known good die memory (KGDM); known good die; dynamic random access memory (DRAM) module; integrated circuits; Integrated Circuit (IC); micro integrated circuits; chips; computer memory; computer circuits; Integrated circuit modules; Large scale integrated circuits; Microcircuits; Very large scale integration (VLSI); Wafers for integrated circuits; Integrated circuit module; Semiconductor wafers; Dynamic random access memory (DRAM). Marketing, promotion and retailing of known good die memory (KGDM) and known good die; Marketing, promotion and retailing of dynamic random access memory, dynamic random access memory (DRAM) module; Marketing, promotion and retailing of memory, random access memory module, random access memory; Marketing, promotion and retailing of integrated circuits, and Integrated Circuit (IC), micro integrated circuits; Marketing, promotion and retailing of semiconductor chips and silicon chips. Design of integrated circuits; Development of technologies for the fabrication of circuits for wireless communication, electronic data processing; Research, development, and design of semiconductor products, including known good die, known good die memory, dynamic random access memory, dynamic random access memory (DRAM) modules, micro integrated circuits, and semiconductor chips; Structure design for semiconductor products, including known good die, known good die memory, dynamic random access memory, dynamic random access memory (DRAM) modules, integrated circuits, micro integrated circuits, and semiconductor chips; Testing and consulting of semiconductor products, including known good die, known good die memory, dynamic random access memory, dynamic random access memory (DRAM) modules, integrated circuits and micro integrated circuits; Research in the area of semiconductor processing technology.

Goods & Services

Chipsets; Semiconductor chip sets; Silicon chips; Semiconductor chips; known good die memory (KGDM); known good die; dynamic random access memory (DRAM) module; integrated circuits; Integrated Circuit (IC); micro integrated circuits; chips; computer memory; computer circuits; Integrated circuit modules; Large scale integrated circuits; Microcircuits; Very large scale integration (VLSI); Wafers for integrated circuits; Integrated circuit module; Semiconductor wafers; Dynamic random access memory (DRAM). Marketing, promotion and retailing of known good die memory (KGDM) and known good die; Marketing, promotion and retailing of dynamic random access memory, dynamic random access memory (DRAM) module; Marketing, promotion and retailing of memory, random access memory module, random access memory; Marketing, promotion and retailing of integrated circuits, and Integrated Circuit (IC), micro integrated circuits; Marketing, promotion and retailing of semiconductor chips and silicon chips. Design of integrated circuits; Development of technologies for the fabrication of circuits for wireless communication, electronic data processing; Research, development, and design of semiconductor products, including known good die, known good die memory, dynamic random access memory, dynamic random access memory (DRAM) modules, micro integrated circuits, and semiconductor chips; Structure design for semiconductor products, including known good die, known good die memory, dynamic random access memory, dynamic random access memory (DRAM) modules, integrated circuits, micro integrated circuits, and semiconductor chips; Testing and consulting of semiconductor products, including known good die, known good die memory, dynamic random access memory, dynamic random access memory (DRAM) modules, integrated circuits and micro integrated circuits; Research in the area of semiconductor processing technology.

Goods & Services

Chipsets; Semiconductor chip sets; Silicon chips; Semiconductor chips; known good die memory (KGDM); known good die; dynamic random access memory (DRAM) module; integrated circuits; Integrated Circuit (IC); micro integrated circuits; chips; computer memory; computer circuits; Integrated circuit modules; Large scale integrated circuits; Microcircuits; Very large scale integration (VLSI); Wafers for integrated circuits; Integrated circuit module; Semiconductor wafers; Dynamic random access memory (DRAM). Marketing, promotion and retailing of known good die memory (KGDM) and known good die; Marketing, promotion and retailing of dynamic random access memory, dynamic random access memory (DRAM) module; Marketing, promotion and retailing of memory, random access memory module, random access memory; Marketing, promotion and retailing of integrated circuits, and Integrated Circuit (IC), micro integrated circuits; Marketing, promotion and retailing of semiconductor chips and silicon chips. Design of integrated circuits; Development of technologies for the fabrication of circuits for wireless communication, electronic data processing; Research, development, and design of semiconductor products, including known good die, known good die memory, dynamic random access memory, dynamic random access memory (DRAM) modules, micro integrated circuits, and semiconductor chips; Structure design for semiconductor products, including known good die, known good die memory, dynamic random access memory, dynamic random access memory (DRAM) modules, integrated circuits, micro integrated circuits, and semiconductor chips; Testing and consulting of semiconductor products, including known good die, known good die memory, dynamic random access memory, dynamic random access memory (DRAM) modules, integrated circuits and micro integrated circuits; Research in the area of semiconductor processing technology.

Goods & Services

Chipsets; Semiconductor chip sets; Silicon chips; Semiconductor chips; known good die memory (KGDM); known good die; dynamic random access memory (DRAM) module; integrated circuits; Integrated Circuit (IC); micro integrated circuits; chips; computer memory; computer circuits; Integrated circuit modules; Large scale integrated circuits; Microcircuits; Very large scale integration (VLSI); Wafers for integrated circuits; Integrated circuit module; Semiconductor wafers; Dynamic random access memory (DRAM). Marketing, promotion and retailing of known good die memory (KGDM) and known good die; Marketing, promotion and retailing of dynamic random access memory, dynamic random access memory (DRAM) module; Marketing, promotion and retailing of memory, random access memory module, random access memory; Marketing, promotion and retailing of integrated circuits, and Integrated Circuit (IC), micro integrated circuits; Marketing, promotion and retailing of semiconductor chips and silicon chips. Design of integrated circuits; Development of technologies for the fabrication of circuits for wireless communication, electronic data processing; Research, development, and design of semiconductor products, including known good die, known good die memory, dynamic random access memory, dynamic random access memory (DRAM) modules, micro integrated circuits, and semiconductor chips; Structure design for semiconductor products, including known good die, known good die memory, dynamic random access memory, dynamic random access memory (DRAM) modules, integrated circuits, micro integrated circuits, and semiconductor chips; Testing and consulting of semiconductor products, including known good die, known good die memory, dynamic random access memory, dynamic random access memory (DRAM) modules, integrated circuits and micro integrated circuits; Research in the area of semiconductor processing technology.

Goods & Services

Chipsets; Semiconductor chip sets; Computer hardware, namely, Microchips; Silicon chips; Semiconductor chips; Multiprocessor chips; Computer chips; Electronic memory, namely, known good die memory; Dynamic random access memory (DRAM) module; Specialty dynamic random access memory (DRAM); Dynamic random access memory (DRAM) for automotive and industrial uses; integrated circuits; electronic micro circuits; electronic circuits; Electronic components in the nature of semiconductors; semiconductor components, namely, semiconductor wafers and semiconductor chips in package; computer hardware; computer memory; computer memory devices; Electronic components for computers; Integrated circuit modules; Electronic integrated circuits; Decision circuits; Large scale integrated circuits; Microcircuits; Very large scale integration (VLSI) semiconductor integrated circuits; Electric and electronic circuits; Electronic components in the nature of semiconductors and integrated circuits; Wafers for integrated circuits; Integrated circuit module; Flexible circuit boards; Semiconductors; Semiconductor devices; Semiconductor wafers; Dynamic random access memory (DRAM)

Goods & Services

Chipsets; Semiconductor chip sets; Computer hardware, namely, Microchips; Silicon chips; Semiconductor chips; Multiprocessor chips; Computer chips; Electronic memory, namely, known good die memory; Dynamic random access memory (DRAM) module; Specialty dynamic random access memory (DRAM); Dynamic random access memory (DRAM) for automotive and industrial uses; integrated circuits; electronic micro circuits; electronic circuits; Electronic components in the nature of semiconductors; semiconductor components, namely, semiconductor wafers and semiconductor chips in package; computer hardware; computer memory; computer memory devices; Electronic components for computers; Integrated circuit modules; Electronic integrated circuits; Decision circuits; Large scale integrated circuits; Microcircuits; Very large scale integration (VLSI) semiconductor integrated circuits; Electric and electronic circuits; Electronic components in the nature of semiconductors and integrated circuits; Wafers for integrated circuits; Integrated circuit module; Flexible circuit boards; Semiconductors; Semiconductor devices; Semiconductor wafers; Dynamic random access memory (DRAM)

Goods & Services

Chipsets; Semiconductor chip sets; Computer hardware, namely, Microchips; Silicon chips; Semiconductor chips; Multiprocessor chips; Computer chips; Electronic memory, namely, known good die memory; Dynamic random access memory (DRAM) module; Specialty dynamic random access memory (DRAM); Dynamic random access memory (DRAM) for automotive and industrial uses; integrated circuits; electronic micro circuits; electronic circuits; Electronic components in the nature of semiconductors; semiconductor components, namely, semiconductor wafers and semiconductor chips in package; computer hardware; computer memory; computer memory devices; Electronic components for computers; Integrated circuit modules; Electronic integrated circuits; Decision circuits; Large scale integrated circuits; Microcircuits; Very large scale integration (VLSI) semiconductor integrated circuits; Electric and electronic circuits; Electronic components in the nature of semiconductors and integrated circuits; Wafers for integrated circuits; Integrated circuit module; Flexible circuit boards; Semiconductors; Semiconductor devices; Semiconductor wafers; Dynamic random access memory (DRAM)

Abstract

A multi-bank Superscalar Memory IC and system for use therein is disclosed. Using multiple independent addressing ports, multiple memory locations can be accessed simultaneously leading to a higher level of concurrency than supported by common DDR type memories. One disclosed embodiment is a Memory IC with two separate Data IO Ports that can support simultaneous read and write operations to the same memory IC, leading to reduced operating power for a given realtime video processing workload by exploiting the higher level of concurrency to deserialize operations leading to a reduction in operating clock frequency.

IPC Classes  ?

• G06F 12/02 - Addressing or allocationRelocation
• G06F 12/1036 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

Abstract

A digital filter for filtering signals includes a processer and a memory. The processer receives a plurality of input signal values and a plurality of input aggregated values corresponding to the plurality of input signal values. The memory saves a signal value set and a statistical information set. The processer generates a check result according to the plurality of input signal values and the signal value set. The processer updates the statistical information set of the memory according to the check result, and decides whether to insert at least one new signal value into the signal value set of the memory, wherein the processer generates an output value according to the signal value set and the statistical information set of the memory.

IPC Classes  ?

• G06T 5/50 - Image enhancement or restoration using two or more images, e.g. averaging or subtraction
• G06T 7/593 - Depth or shape recovery from multiple images from stereo images
• G06F 17/18 - Complex mathematical operations for evaluating statistical data
• G06T 5/00 - Image enhancement or restoration

Abstract

A low dropout regulator with wide input supply voltage includes a controller, an comparing circuit, a feedback circuit, an adjustable source follower, and an adjustable driving circuit. The controller is used for detecting a supply voltage. The feedback circuit, the comparing circuit, the adjustable source follower, and the adjustable driving circuit are used for regulating an output voltage according to a reference voltage. When the adjustable source follower and the adjustable driving circuit operate in the low-voltage mode, the controller further activates a first parallel metal-oxide-semiconductor transistor in the adjustable source follower and a second parallel metal-oxide-semiconductor transistor in the adjustable driving circuit.

IPC Classes  ?

• G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
• G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
• H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
• H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
• H02M 1/00 - Details of apparatus for conversion
• G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC

Abstract

A data collection and analysis method includes applying a first noise step to an original data stream with an original character to generate a first data stream with a first character; and applying a second noise step to the first data stream to generate a second data stream with a second character, wherein a first variation between the original character and the first character is greater than a second variation between the original character and the second character.

IPC Classes  ?

• G06F 21/60 - Protecting data
• G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
• H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
• G06F 7/58 - Random or pseudo-random number generators

Abstract

A memory with an error correction function includes a controller and a memory cell array. The controller optionally writes written data to a normal storage area and a backup area of the memory cell array, and when the controller reads first data corresponding to the written data from the normal storage area, if at least two errors are included in the first data, the controller reads the backup area to output second data corresponding to the written data from the backup area.

IPC Classes  ?

• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
• G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
• G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result

Abstract

A power delivery integrated circuit is installed within a cable, and a switch circuit applied to the power delivery integrated circuit includes a first switch module, a second switch module, and a logic controller. When a first terminal of the cable receives a first voltage and a second terminal of the cable receives a second voltage, the logic controller optionally makes the first switch module transmit the first voltage to an identification circuit of the power delivery integrated circuit, or makes the second switch module transmit the second voltage to the identification circuit.

IPC Classes  ?

• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• G06F 1/26 - Power supply means, e.g. regulation thereof
• H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
• H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

Abstract

A memory subsystem is provided, including a memory controller integrated circuit (IC) (120), a memory bus and a memory IC (110), all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC (110) concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport. The physical layout of one version of the memory IC (110) dispatches switching signal terminals adjacent to one short edge of the memory die to minimize the die area overhead for controller IC (120) memory interface circuitry when used in a stacked die multi-chip package (100) with said memory controller IC (120). The memory IC (110) interface signal placement and signal count minimize signal length and circuitry for the memory bus signals.

IPC Classes  ?

• G06F 13/40 - Bus structure

Goods & Services

DYNAMIC RANDOM ACCESS MEMORY (DRAM)

Goods & Services

DYNAMIC RANDOM ACCESS MEMORY (DRAM)

Abstract

A memory circuit with thyristor includes a plurality of memory cells. Each memory cell of the plurality of memory cells includes an access transistor and a thyristor. The thyristor is coupled to the access transistor. At least one of a gate of the access transistor and a gate of the thyristor has a fin structure.

IPC Classes  ?

• H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 27/102 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 29/745 - Gate-turn-off devices with turn-off by field effect
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action

Abstract

A memory includes a plurality of memory cells and a plurality of peripheral circuits. Each memory cell has a first inverter and a second inverter, the first inverter is supplied by a first power supply rail and a second power supply rail, and the second inverter is supplied by a third power supply rail and a fourth power supply rail. A first voltage difference is applied across the first power supply rail and the second power supply rail, a second voltage difference is applied across the third power supply rail and the fourth power supply rail, and the first voltage difference is less than the second voltage difference. The plurality of peripheral circuits use at least one of boosted power supplies corresponding to the second voltage difference and gate-source differentially-driven circuits.

IPC Classes  ?

• G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
• G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

Abstract

A manufacturing method of dynamic random access memory (DRAM) with low leakage current includes forming a plurality of gates within a substrate of the DRAM; forming a plurality of drain/sources within the substrate of the DRAM by a first ion implantation; and forming a plurality of lightly doped drains under all of the plurality of drain/sources or partial drain/sources of the plurality of drain/sources by a second ion implantation after the plurality of drain/sources are formed. The plurality of lightly doped drains is used for reducing a leakage current within the DRAM, and the second ion implantation has a predetermined incident angle.

IPC Classes  ?

• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
• H01L 27/108 - Dynamic random access memory structures
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A memory subsystem is provided, including a memory controller integrated circuit (IC) (120), a memory bus and a memory IC (110), all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC (110) concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport. The physical layout of one version of the memory IC (110) dispatches switching signal terminals adjacent to one short edge of the memory die to minimize the die area overhead for controller IC (120) memory interface circuitry when used in a stacked die multi-chip package (100) with said memory controller IC (120). The memory IC (110) interface signal placement and signal count minimize signal length and circuitry for the memory bus signals.

IPC Classes  ?

• G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Abstract

A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus.

IPC Classes  ?

• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• G06F 13/40 - Bus structure

Abstract

A system-in-package module with memory includes a non-memory chip, a substrate, and a memory chip. The non-memory chip has a first portion and a second portion. The substrate has a window and the substrate is electrically connected to the second portion of the non-memory chip. The memory chip is placed into the window of the substrate to electrically connect the first portion of the non-memory chip, and there is no direct metal connection between the memory chip and the substrate.

IPC Classes  ?

• G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• G11C 5/04 - Supports for storage elementsMounting or fixing of storage elements on such supports
• G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
• G11C 29/56 - External testing equipment for static stores, e.g. automatic test equipment [ATE]Interfaces therefor
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

A dynamic memory structure is disclosed. The dynamic memory structure includes: a substrate; a first strip semiconductor material disposed on the substrate and extending along a first direction; a gate standing astride the first strip semiconductor material, extending along a second direction and dividing the first strip semiconductor material into a first source terminal, a first drain terminal and a first channel region; a first dielectric layer sandwiched between the gate and the first strip semiconductor material; a first capacitor unit disposed on the substrate and comprising the first source terminal serving as a bottom electrode, a second dielectric layer covering the first source terminal to serve as a capacitor dielectric layer and a capacitor metal layer covering the second dielectric layer to serve as a top electrode. Preferably, the first source terminal and the first drain terminal have asymmetric shapes.

IPC Classes  ?

• H01L 27/108 - Dynamic random access memory structures
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 49/02 - Thin-film or thick-film devices

Abstract

A memory circuit capable of being quickly written in data includes a plurality of banks, and each bank of the plurality of banks includes a plurality of segments. Each segment of the plurality of segments includes a plurality of bit line groups, and each bit line group of the plurality of bit line groups corresponds to a pre-charge line. When a predetermined signal is enabled, a potential is written into memory cells of the each segment corresponding to the each bit line group through the pre-charge line and the each bit line group.

IPC Classes  ?

• G11C 11/409 - Read-write [R-W] circuits
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/408 - Address circuits
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• G06F 3/06 - Digital input from, or digital output to, record carriers
• G06F 12/0893 - Caches characterised by their organisation or structure
• G11C 16/06 - Auxiliary circuits, e.g. for writing into memory
• G11C 29/34 - Accessing multiple bits simultaneously
• G11C 11/4076 - Timing circuits
• G11C 29/06 - Acceleration testing

Abstract

A memory circuit includes a plurality of banks and a controller, each bank of the plurality of banks includes a plurality of segments, and each segment of the plurality of segments includes a plurality of bit lines and a plurality of word lines. A word line switch corresponding to a word line of a segment of the memory circuit is turned on and data are written into memory cells of the segment coupled to a plurality of bit lines of the segment and corresponding to the word line in turn after the controller enables an active command corresponding to the word line. When the controller enables at least one copy row write command, the data are simultaneously written into memory cells sharing a plurality of sense amplifiers with the plurality of bit lines of the segment and corresponding to at least one another word line.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/408 - Address circuits
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• G06F 12/0893 - Caches characterised by their organisation or structure
• G11C 16/06 - Auxiliary circuits, e.g. for writing into memory
• G11C 29/34 - Accessing multiple bits simultaneously
• G11C 11/4076 - Timing circuits
• G11C 29/06 - Acceleration testing

Abstract

A dynamic memory structure is disclosed. The dynamic memory structure includes: a substrate; a first strip semiconductor material disposed on the substrate and extending along a first direction; a gate standing astride the first strip semiconductor material, extending along a second direction and dividing the first strip semiconductor material into a first source terminal, a first drain terminal and a first channel region; a first dielectric layer sandwiched between the gate and the first strip semiconductor material; a first capacitor unit disposed on the substrate and comprising the first source terminal serving as a bottom electrode, a second dielectric layer covering the first source terminal to serve as a capacitor dielectric layer and a capacitor metal layer covering the second dielectric layer to serve as a top electrode. Preferably, the first source terminal and the first drain terminal have asymmetric shapes.

IPC Classes  ?

• H01L 27/108 - Dynamic random access memory structures
• H01L 49/02 - Thin-film or thick-film devices
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Goods & Services

Computer software for designing objects for 3D printing; [ Computer software for controlling the operation of 3D printers and 3D scanners; components for 3D printers and 3D scanners, namely, printer cables; ] Computer hardware; [ Scanners; Photographic cameras; ] Cameras and integrated circuits thereof [ ; Camcorders; 3D Scanners ]

Goods & Services

Computer software for designing objects for 3D printing; [ Computer software for controlling the operation of 3D printers and 3D scanners; components for 3D printers and 3D scanners, namely, printer cables; ] Computer hardware; [ Scanners; Photographic cameras; ] Cameras and integrated circuits thereof [ ; Camcorders; 3D Scanners ]

Abstract

A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus.

IPC Classes  ?

• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• G06F 13/40 - Bus structure
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or