Abstract

The present invention discloses a digital video broadcasting system. The digital video broadcasting system comprises an Inverse Discrete Fourier Transform operator, a channel impulse response estimating device, a Discrete Fourier Transform operator and a first multiplier. The Inverse Discrete Fourier Transform operator performs the operation of Inverse Discrete Fourier Transform; the channel impulse response estimating device sets a window according to an output of the Inverse Discrete Fourier Transform operator; the Discrete Fourier Transform operator performs the operation of Discrete Fourier Transform on the output of the Inverse Discrete Fourier Transform operator within the window; the first multiplier multiplies the output of the Discrete Fourier Transform operator by three times to adjust the whole energy rate. The present invention also discloses a method for estimating channel of digital video broadcasting system. In the present invention, the accurate degree of channel estimation is improved, so that a larger gain could be provided when the QAM manner using higher encoding speed is adopted.

IPC Classes  ?

• H04N 5/44 - Receiver circuitry

Abstract

An FFT/IFFT (Fast Fourier Transform/Inverse Fast Fourier Transform) operation core includes: an input buffer, the first multiplexer, an operation module and a control module. The input buffer stores and outputs the first FFT input sequence. The first multiplexer switches on one of the first and the third FFT input sequences. The control module generates a signal process mode indicating signal, and a bypass indicating signal. The operation module has many operation stages in series, answers to the signal process mode indicating signal and the bypass indicating signal, transforms the first FFT input sequence and the third FFT input sequence, respectively generates the first FFT output sequence and the third FFT output sequence, transforms the second IFFT input sequence and generates the second IFFT output sequence.

IPC Classes  ?

• G06F 17/14 - Fourier, Walsh or analogous domain transformations

Abstract

A bandgap reference voltage generator (500). The bandgap reference voltage generator (500) includes a voltage generator circuit (510) for generating a voltage in response to temperature, a voltage level optimization circuit (520) and a reference voltage generator circuit (530). A first voltage (VPTAT) and a second voltage (Vbe) are generated by the voltage generator circuit (510). A current component increased with the temperature increment is generated by the first voltage (VPTAT). A current component decreased with the temperature increment is generated by the second voltage (Vbe). A third voltage (MVbe) which is obtained by optimizing the voltage level of the second voltage (Vbe) is generated by the voltage level optimization circuit (520). A reference voltage of a certain voltage level independent of temperature is generated by the reference voltage generator circuit (530) based on the first voltage (VPTAT) and the third voltage (MVbe).

IPC Classes  ?

• G05F 3/20 - Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations

Abstract

A variable resistor array and a channel selection filter using the variable resistor array are provided. The variable resistor array comprises a base resistor, the first resistor array, the second resistor array, the Nth (N is an integer) resistor array and a plurality of switches. The first resistor array is composed of M (M is an integer) resistors connected in series and its total resistance value is equal to the resistance value of the base resistor. The second resistor array is composed of M resistors connected in series and its total resistance value is twice as much as the total resistance value of the first resistor array. The Nth resistor array is composed of M resistors connected in series and its total resistance value is twice as much as the total resistance value of the (N-1)th resistor array.

IPC Classes  ?

• H01C 10/50 - Adjustable resistors structurally combined with switching arrangement

Abstract

The present invention relates to a DC offset removal circuit of a wireless receiver, more particularly to a DC offset removal circuit with low noise for a wireless receiver. The DC offset removal circuit with low noise removes the noises generated from the DC offset removal circuit by including a low-pass filter between a DC offset removal unit and the input terminal of a baseband part. The DC offset removal circuit according to the invention removes noises generated by itself by including the low-pass filter at the place where the input from the baseband part reaches the DC offset removal circuit. Therefore, the DC offset removal circuit has an effect on the reduction of the total noise in the wireless receiver.

IPC Classes  ?

• H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference

Abstract

This invention discloses an OFDM receiver that does not require reordering of a sub-carrier and a method for processing an OFDM signal. The OFDM receiver comprises an I/Q demodulator, an FFT processor, a block for correcting fractional frequency errors, a first multiplier, a block for correcting integral frequency errors, a first adder and a second adder. The method for processing an OFDM signal comprises steps of: demodulating a received OFDM signal to an I/Q signal, applying an offset to the I/Q signal, and generating a spectrum signal by quickly Fourier-transforming the I/Q signal to which the offset is applied.

IPC Classes  ?

• H04J 11/00 - Orthogonal multiplex systems

Abstract

The invention relates to a phase locked loop (PLL), more particularly to a PLL having a retiming part for the removal of jitter in a programmable frequency divider.  An advantage of the invention is that in-band noises caused by the output jitter of a programmable frequency divider which divides the phase of an output signal from a voltage controlled oscillator can be removed by retiming an output of the divider and transmitting to a phase detector for comparison.

IPC Classes  ?

• H03L 7/08 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop

Abstract

A communication domain restricting device for an ETCS (Electric Toll Collection System) terminal of an OBU (On Board Unit) having an antenna, an RF receiving unit, an RF transmitting unit, and a baseband transmitting/receiving unit, includes an OBU receiving performance restricting unit arranged at a receiving end of an ASK (Amplitude Shift Keying) demodulator of the RF receiving unit. The OBU receiving performance restricting unit includes a digital control block and an RSSI control block which operate to restrict the receiving performance of the OBU such that transmission or reception can be performed only in a communication domain of a predetermined range. The communication domain restricting device of the present invention overcomes the drawbacks of noises which degrade performance of ETCS in a region other than the communication domain and the deterioration of the efficiency of switching between reception and transmission when the OBU enters the communication domain.

IPC Classes  ?

• G07B 15/06 - Arrangements for road pricing or congestion charging of vehicles or vehicle users, e.g. automatic toll systems

Abstract

The present invention concerns a charge pump (CP) which is capable of controlling the turn-on time of a sharing transistor. More specifically, the disclosed charge pump sets up a time interval between a control signal controlling a source switch and a control signal controlling movement of a sharing transistor, then turns on the sharing transistor so that it reaches a certain voltage level. Therefore, the reverse current caused after the source switch is turned off is prevented and the dynamic current applied to a roof filter is stably maintained.

IPC Classes  ?

• G11C 5/14 - Power supply arrangements

Abstract

This invention relates to a voltage controlled oscillator (VCO), more particularly to a voltage controlled oscillator with low-noise current and voltage sources. The voltage controlled oscillator has a low-noise voltage source by using a low-noise current source through the connection of a mirroring transistor to a path for the low-noise current source. As a voltage divider with a variable resistor is connected to a terminal of the mirroring transistor in the voltage controlled oscillator, the voltage controlled oscillator is able to supply a reference bias voltage to a tuner without the lowering of performance thereof.

IPC Classes  ?

• H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device

Abstract

A peak detector capable of rapidly detecting a peak value of a signal is provided. The peak detector includes first and second operational amplifiers and an auxiliary current source to detect two rail to rail signals. The first operational amplifier outputs a detection signal by buffering a first rail to rail input signal. The second operational amplifier outputs a control signal in response to a second rail to rail input signal and the detection signal. The auxiliary current source includes a terminal connected to an output terminal of the first operational amplifier and the other terminal connected to the first or second source voltage. The auxiliary current source operates in response to the control signal. The auxiliary current source supplies a current from the first source voltage to the output terminal in response to the control signal or supplies a path for discharging a current from the output terminal to the second source voltage.

IPC Classes  ?

• G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values

Abstract

A variable gain amplifier (VGA) with a linear-in-dB gain characteristic is provided. The VGA includes: a control signal converter which converts an input gain control signal V, which is input so that the VGA obtains a linear-in-dB gain characteristic to the maximum gain, into an output gain control signal VX =VT ln((l/m)exp(-VC /VT )-l)(m is a constant, VT =kT/q); and a variable gain amplifier which receives and converts the output gain control signal V X. output from the control signal converter so that the gain has a linear-in-dB characteristic. A shape of a gain curve is externally controlled.

IPC Classes  ?

• H03G 3/10 - Manually-operated control in untuned amplifiers having semiconductor devices

IPC Classes  ?

• H03L 7/16 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

Abstract

An adaptive frequency calibration unit employing an N-target algorithm for a high speed automatic frequency calibration for CDMA application is provided. The adaptive frequency calibration device calibrating a frequency of a voltage controlled oscillator (VCO) bank of a phase-locked loop (PLL), the adaptive frequency calibration device includes: a reference frequency divider dividing an output frequency of a temperature compensated crystal oscillator (TCXO); a feedback frequency divider dividing an output frequency of a prescaler; a frequency comparator comparing a frequency with the reference frequency divider output and the feedback frequency divider output; and a state machine providing a predetermined bit with a predetermined frequency resolution for the VCO to calibrate the frequency of the VCO bank using the frequency comparison result. Accordingly, it is possible to reduce power consumption and have a small silicon region by designing the adaptive frequency calibration device using the TCXO input and the prescaler output. In addition, a short switching time, phase noise reduction, and low power consumption can be achieved.

IPC Classes  ?

• H03L 7/00 - Automatic control of frequency or phase; Synchronisation

Abstract

Provided are a structure of a series sampling capacitor, which reduces impedance of a series sampling capacitor and prevents erroneous operations of an analog-to-digital converter, and an analog-to-digital converter using the same. The structure includes: two capacitors connected in series; and a transistor which functions as a switch and is connected between a center node of the two capacitors connected in series and a common mode voltage, wherein a reset clock operates immediately before the two capacitors connected in series initially perform sampling, so that voltage at the center node can be reset based on the common mode voltage. Accordingly, erroneous operations of an analog-to-digital converter can be prevented by lowering impedance of a series sampling capacitor.

IPC Classes  ?

• H03M 1/54 - Input signal sampled and held with linear return to datum

Abstract

A cascode low-noise amplifier for enhancing linearity is provided. The cascode low-noise amplifier has a two-stage structure in which a common-emitter stage cascaded to a common-base stage, wherein a phase difference of 180 is produced between a third-order intermodulation signal resulting from a fundamental signal input to the common-base stage and a third-order intermodulation signal previously generated at the common-emitter stage. Accordingly, the fundamental signal and the third-order intermodulation signal can be adjusted to have a phase difference of 180 by disposing an impedance matching circuit between a common-emitter (or a common-source) stage of a buffer transistor and a common-base (or a common-gate) stage of an amplifier transistor, and the magnitude difference can be adjusted as well. In addition, the entire linearity of the cascode low-noise amplifier is enhanced by adjusting the impedance value of the impedance matching circuit to an appropriate value so as to cancel the impedance with the third- order intermodulation signal in the subsequent stage.

IPC Classes  ?

• H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively

Abstract

There is provided a variable gain mixer capable of controlling a gain at a low source voltage in a wide range without additional current consumption. The mixer includes: mixers constructed with variable gain amplifiers having two transistor pairs Qp+/Qp- and Qn+/Qn- to have a predetermined gain by using LO+ and LO- signals; and LO bias circuits connected to have bias voltages different from each other with respect to the LO+ and LO signals of the mixers and share an input signal. Accordingly, by integrating the variable gain amplifiers into the mixers, a gain change can be obtained at a low source voltage in a wide range without connecting a number of variable gain amplifiers. In addition, by properly applying the LO signals used in the mixers, the gain change can have a linearity in dB characteristic

IPC Classes  ?

• H03D 7/10 - Transference of modulation from one carrier to another, e.g. frequency-changing by means of discharge tubes having more than two electrodes the signals to be mixed being applied between different pairs of electrodes