An example system for encoding OFDM data may comprise a processor and a transmitter. The processor may be configured to encode OFDM symbols into a first sigma-delta (ΣΔ) modulated bitstream, such that spectral content of the first sigma-delta (ΣΔ) modulated bitstream contains tones at subcarrier frequencies corresponding to the encoded symbols. The transmitter may be configured to transmit the sigma-delta (ΣΔ) modulated bitstream to a receiver.
H04B 14/06 - Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using differential modulation, e.g. delta modulation
H03M 3/02 - Delta modulation, i.e. one-bit differential modulation
2.
SYSTEMS AND METHODS FOR AN ANALOG NEURAL NETWORK CALCULATING FFT USING CURRENT
Analog circuit for receiving a current signal for frequency decomposition using a plurality of transistors configured to receive a first current, a first drain coupled to a third drain at a third transistor, and a signal input applied to a first gate for determining current flowing through the first/second transistors; second transistor including a second source configured to receive the first current, second drain coupled to a fourth drain at fourth transistor, and the signal input applied to a second gate for determining current flowing through the second transistor, third transistor including a third source configured to receive a second current and signal input applied to a third gate for determining current flowing through the third transistor, and fourth transistor including a fourth source configured to receive the second current and signal input applied to a first gate for determining current flowing through the fourth transistor.
G06G 7/19 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for forming integrals of products, e.g. Fourier integrals, Laplace integrals, correlation integralsArrangements for performing computing operations, e.g. amplifiers specially adapted therefor for analysis or synthesis of functions using orthogonal functions
An analog circuit configured to receive a current signal for frequency decomposition, the first analog circuit comprising a first transistor including a first source configured to receive a first current, a first drain coupled to a third drain at a third transistor, and a signal input applied to a first gate, a voltage at the first gate determining how much current flows through the first transistor, a second transistor including a second source configured to receive the first current, a second drain coupled to a fourth drain at fourth transistor, and the signal input applied to a second gate, the voltage at the second gate determining how much current flows through the second transistor, the third transistor including a third source configured to receive a second current and the signal input applied to a third gate, the voltage at the third gate determining how much current flows through the third transistor, and the fourth transistor including a fourth source configured to receive the second current and the signal input applied to a first gate, the voltage at the first gate determining how much current flows through the fourth transistor.
An example system for encoding OFDM data may comprise a processor and a transmitter. The processor may be configured to encode OFDM symbols into a first sigma-delta (ΣΔ) modulated bitstream, such that spectral content of the first sigma-delta (ΣΔ) modulated bitstream contains tones at subcarrier frequencies corresponding to the encoded symbols. The transmitter may be configured to transmit the sigma-delta (ΣΔ) modulated bitstream to a receiver.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
An apparatus for removing noise due to a DC offset voltage from the frequency band of interest of a signal. Input noise errors are moved out of the band of interest by changing the noise gain of the system without placing a switch in the signal path. The resistance through which an input signal passes to the amplifier remains unchanged, but the noise gain is selectively changed by use of a single switch that inserts an additional resistance from a zero signal source in response to a switching signal, thus switching the amplifier between two states with different noise gains. The output signal may be passed through a sigma-delta modulator and an exclusive-or gate clocked at a duty cycle such that the signal gain of the amplifier is unchanged while the different noise gain states cancel out, thus relocating the input noise errors to harmonic frequencies of the switching signal.
An apparatus and method for improving the efficiency of a D class amplifier, particularly at lower output levels. A class D amplifier having a load with inductance, such as a transducer, is configured to concurrently act as its own buck regulator. A capacitor connected to ground and to both ends of the transducer through switches functions as the buck regulator in connection with the inductance of the transducer, providing the class D amplifier with additional voltage levels such as might be provided by a G/H class amplifier but without the added complexity or expense of the G/H configurations. Better efficiency is possible than that provided by a 100% efficient conventional buck regulator. No envelope detector is required, nor any change to the gain of the digital signal to the class D amplifier. Both synchronous and asynchronous applications are possible. Feedback may be used if desired, but is not required.
An apparatus and method for voice activity detection. A multiphase differential output rotating capacitive sampler achieves a frequency down conversion over as many specific frequency bands as are required for analysis. A chirp is created in the rotating sampler as the sum of arbitrary frequencies across the desired analysis band multiplied by a window function. The chirp is sampled at a rate of rotation synchronous with the last state of burst of the chirp, allowing a non-phase synchronous pattern in the coefficient values and allowing a high-Q and arbitrary decomposition of the signal. After the sample is taken, the next clock signal to the sampler is used to define the output voltage of the sampler by shorting the output, which is entirely capacitive, to ground. Processing occurs in the analog domain rather than digitally, avoiding the need for FFTs and allowing for greater speed and lower power consumption.
Combinatorial logic circuits with feedback, which include at least two combinatorial logic elements, are disclosed. At least one of the combinatorial logic elements receives an external input (i.e., from outside the circuit), at least one of the combinatorial logic elements receives an input that is feedback of the circuit output, and at least one of the combinatorial logic elements receives an input that is neither an external input nor an output of the circuit but rather is from another of the combinatorial logic elements and thus only “implicit” to the circuit. No staticizers are needed; the logic circuits effectively create implicit equations to perform functions that were previously thought to require sequential logic. The combinatorial logic circuits result in a stable output (in some instances after a brief period of time) due to the implicit equations, rather than achieving stability from an explicit expression of some input to the circuit.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
An analog element for use as a neuron in a recurrent neural network is described, the analog element having memory of a prior layer state and being a continuous time circuit rather than having a discrete clocking interval. The element is characterized and described by the Laplace s-domain operator, as distinct from a digital solution that uses the z-domain operator appropriate for quantized time descriptions. Rather than using an all-pass filter, the analog equivalent of a unit delay in the z-domain, a finite gain integrator, which is a simpler circuit, may be used to provide the delay in the analog s-domain. The resulting circuit may be easily implemented at the transistor level.
A method for performing a fast Fourier transform. The bin spreading effect of conventional FFT methodology may be removed by a mathematical technique that relies on an incomplete replacement of the input data sequence. In the present approach this replacement is accomplished by a “round robin” method. In this approach no window function is required and the FFT calculation proceeds after each new sample is added round robin fashion to the input sequence. The resulting output bins from the FFT show the signal evolution with time, overlapping as in the known art but by a single sample. The output of a FFT so constructed is not time invariant, but rather there is a rotation present in each output bin when viewed as an analytical signal. This rotation is predictable and hence removeable, but is also exploitable as a means to remove the bin spill over.
An apparatus and method for performing a fast Fourier transform in the analog domain with passive components. A complex analog signal that is shift and scale invariant is derived from analog circuit properties. A butterfly circuit processes such signals using only passive components by mapping the Kirchhoff current and voltage laws into operations on the signals. A fast Fourier transform circuit of any desired width is constructed from such butterfly circuits. The passive networks require no power as the operations are on the presented signal; energy is taken from the source signal so no battery or power supply is needed. Thus, when the signal becomes quiescent, the power consumed is zero. Further there is no need of a clock or other timing device; rather, it is the operation of Kirchhoff laws in the network, which apply essentially upon arrival of the signal, that is made analogous to the desired operation.
G06F 17/14 - Fourier, Walsh or analogous domain transformations
H03F 3/00 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
H03F 3/16 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
An apparatus and method for processing signals in the analog domain. A signal is derived from analog circuit properties that is shift and scale invariant. Although the circuit properties are not quantized as in traditional digital signal processing, the signal is immune from effects of the properties, such as common mode noise, absolute voltage or current level, finite settling time, etc., as a digital signal would be. The shift and scale invariance allows for mathematical operations of addition, subtraction, multiplication and division of signals. By combining these operations, various circuits may be constructed, including a voltage controlled amplifier, a time gain amplifier, and an analog-to-digital converter. The circuits are constructed using almost no non-linear, active devices, and will thus use less power for a given speed than comparable digital devices, and will often be faster as there are no delay elements and no need to wait for the circuit properties to settle.
H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
H03G 3/00 - Gain control in amplifiers or frequency changers
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
An apparatus and method for processing signals in the analog domain. A signal is derived from analog circuit properties that is shift and scale invariant. Although the circuit properties are not quantized as in traditional digital signal processing, the signal is immune from effects of the properties, such as common mode noise, absolute voltage or current level, finite settling time, etc., as a digital signal would be. The shift and scale invariance allows for mathematical operations of addition, subtraction, multiplication and division of signals. By combining these operations, various circuits may be constructed, including a voltage controlled amplifier, a time gain amplifier, and an analog-to-digital converter. The circuits are constructed using almost no non-linear, active devices, and will thus use less power for a given speed than comparable digital devices, and will often be faster as there are no delay elements and no need to wait for the circuit properties to settle.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
H03G 3/00 - Gain control in amplifiers or frequency changers
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
H03M 1/34 - Analogue value compared with reference values
H03M 1/36 - Analogue value compared with reference values simultaneously only, i.e. parallel type
An apparatus and method for processing signals in the analog domain. A signal is derived from analog circuit properties that is shift and scale invariant. Although the circuit properties are not quantized as in traditional digital signal processing, the signal is immune from effects of the properties, such as common mode noise, absolute voltage or current level, finite settling time, etc., as a digital signal would be. The shift and scale invariance allows for mathematical operations of addition, subtraction, multiplication and division of signals. By combining these operations, various circuits may be constructed, including a voltage controlled amplifier, a time gain amplifier, and an analog-to-digital converter. The circuits are constructed using almost no non-linear, active devices, and will thus use less power for a given speed than comparable digital devices, and will often be faster as there are no delay elements and no need to wait for the circuit properties to settle.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
H03G 3/00 - Gain control in amplifiers or frequency changers
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03M 1/34 - Analogue value compared with reference values
H03M 1/36 - Analogue value compared with reference values simultaneously only, i.e. parallel type
H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
A programmable impedance element consists of a plurality of nominally identical two-port elements, each two-port element having an impedance element and two switches, the two-port elements arranged in a chain fashion with a structured set of switches such that a range of impedances can be obtained from each cell by dynamically changing the connections between the impedance elements in the cell. The common cell is constructed by connecting the nominally identical two-port impedance elements in a way that the number of possible combinations of the impedance elements is reduced to the subset of all possible combinations that uses the minimum possible number of connections. This structure allows the creation of matched impedances using industry standard devices. The connections between impedance elements are switches that may be “field-programmable,” i.e., that may be set on the chip after manufacture and configured during operation of the circuit, or alternatively may be mask programmable.
An apparatus and method for improving the efficiency of a D class amplifier, particularly at lower output levels. A class D amplifier having a load with inductance, such as a transducer, is configured to concurrently act as its own buck regulator. A capacitor connected to ground and to both ends of the transducer through switches functions as the buck regulator in connection with the inductance of the transducer, providing the class D amplifier with additional voltage levels such as might be provided by a G/H class amplifier but without the added complexity or expense of the G/H configurations. Better efficiency is possible than that provided by a 100% efficient conventional buck regulator. No envelope detector is required, nor any change to the gain of the digital signal to the class D amplifier. Feedback may be used if desired, but is not required to obtain a high quality output signal.
An apparatus and method for using the known phenomena of quantum gate tunneling in semiconductor transistors to define the DC state of a charge-coupled amplifier is described. A first stage in which the tunneling current is bipolar (by pairing PMOS and NMOS transistors) in combination with a second stage with a controlled common mode voltage that can be used to control the first stage tunneling current, and thus the common mode voltage at the input. This can be done without the use of additional elements that may degrade performance or power consumption, since the input devices both process the input signal and maintain the DC operating point of the circuit. The approach may be advantageously used not only in charge-coupled amplifiers as described herein, but also in other capacitively coupled circuits such as charge balancing analog to digital converters (ADCs) and digital to analog converters (DACs).
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 1/42 - Modifications of amplifiers to extend the bandwidth
H04N 19/182 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel
Combinatorial logic circuits with feedback, which include at least two combinatorial logic elements, are disclosed. At least one of the combinatorial logic elements receives an external input (i.e., from outside the circuit), at least one of the combinatorial logic elements receives an input that is feedback of the circuit output, and at least one of the combinatorial logic elements receives an input that is neither an external input nor an output of the circuit but rather is from another of the combinatorial logic elements and thus only “implicit” to the circuit. No staticizers are needed; the logic circuits effectively create implicit equations to perform functions that were previously thought to require sequential logic. The combinatorial logic circuits result in a stable output (in some instances after a brief period of time) due to the implicit equations, rather than achieving stability from an explicit expression of some input to the circuit.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Combinatorial logic circuits with feedback, which include at least two combinatorial logic elements, are disclosed. At least one of the combinatorial logic elements receives an external input (i.e., from outside the circuit), at least one of the combinatorial logic elements receives an input that is feedback of the circuit output, and at least one of the combinatorial logic elements receives an input that is neither an external input nor an output of the circuit but rather is from another of the combinatorial logic elements and thus only "implicit" to the circuit. No staticizers are needed; the logic circuits effectively create implicit equations to perform functions that were previously thought to require sequential logic. The combinatorial logic circuits result in a stable output (in some instances after a brief period of time) due to the implicit equations, rather than achieving stability from an explicit expression of some input to the circuit.
An apparatus and method for determining signals representative of events in the environment of a reactive transducer while being driven by a switching amplifier is disclosed. While the switching amplifier is in a zero voltage state, a signal capture circuit that is also in a zero voltage state is connected to the transducer for a relatively brief period of time during which a measurement is made of the residual current flow due to the inductance of the transducer. A prediction of the output signal is then subtracted from the signal measured across the transducer, reducing the overall range of the signal and increasing the relative size of the back-EMF signal compared to any remaining output signal. If desired, conventional echo cancellation can then be performed. The back-EMF signal can then be subjected to further processing by an analog-to-digital converter as known in the art.
An apparatus and method for determining signals representative of events in the environment of a reactive transducer while being driven by a switching amplifier is disclosed. While the switching amplifier is in a zero voltage state, a signal capture circuit that is also in a zero voltage state is connected to the transducer for a relatively brief period of time during which a measurement is made of the residual current flow due to the inductance of the transducer. A prediction of the output signal is then subtracted from the signal measured across the transducer, reducing the overall range of the signal and increasing the relative size of the back-EMF signal compared to any remaining output signal. If desired, conventional echo cancellation can then be performed. The back-EMF signal can then be subjected to further processing by an analog-to-digital converter as known in the art.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
G01H 11/08 - Measuring mechanical vibrations or ultrasonic, sonic or infrasonic waves by detecting changes in electric or magnetic properties by electric means using piezoelectric devices
22.
Neural network with weight-controlling auxiliary path
An apparatus and method for creating data dependency in a neural network without the need for historical data or training is described. An “auxiliary path” that is adjacent to the main path of the neural network contains neurons that receive input data, creating non-linearity beyond that normally present in the network. The outputs of the neurons in the auxiliary path do not directly feed into the layers of neurons in the main path of the network as inputs, but instead are used to “adjust” the input weights to neurons in the main path by selecting which of existing, pre-determined weights are used for any given input. No training phase is required, and the weights in the network do not change, but instead existing paths are simply opened or closed to inputs depending upon the inputs, effectively altering the input weights to the neurons in the main path.
A pipelined ADC that does not wait for the residue of a signal to settle to be delivered to the next stage of the pipeline, and thus passes signals to subsequent stages at faster than conventional speeds is described. A pipelined ADC is used that processes signals representing the boundaries of the search space. Thus, each stage does not necessarily receive the signal as pre-processed by the prior stage, but rather the search space boundaries as pre-processed by the prior stage. Reducing the "search space" of the ADC is equivalent to creating the residues in each step of a pipeline as in the prior art. An ADC operating in this fashion operates without error even if the residual search space boundary outputs from one state are presented to the next stage before the outputs have settled, and can run faster for a given power and bandwidth.
An apparatus and method for using the known phenomena of quantum gate tunneling in semiconductor transistors to define the DC state of a charge-coupled amplifier is described. A first stage in which the tunneling current is bipolar (by pairing PMOS and NMOS transistors) in combination with a second stage with a controlled common mode voltage that can be used to control the first stage tunneling current, and thus the common mode voltage at the input. This can be done without the use of additional elements that may degrade performance or power consumption, since the input devices both process the input signal and maintain the DC operating point of the circuit. The approach may be advantageously used not only in charge-coupled amplifiers as described herein, but also in other capacitively coupled circuits such as charge balancing analog to digital converters (ADCs) and digital to analog converters (DACs).
An apparatus and method for using the known phenomena of quantum gate tunneling in semiconductor transistors to define the DC state of a charge-coupled amplifier is described. A first stage in which the tunneling current is bipolar (by pairing PMOS and NMOS transistors) in combination with a second stage with a controlled common mode voltage that can be used to control the first stage tunneling current, and thus the common mode voltage at the input. This can be done without the use of additional elements that may degrade performance or power consumption, since the input devices both process the input signal and maintain the DC operating point of the circuit. The approach may be advantageously used not only in charge-coupled amplifiers as described herein, but also in other capacitively coupled circuits such as charge balancing analog to digital converters (ADCs) and digital to analog converters (DACs).
H03F 3/187 - Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements
H03F 3/16 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
A pipelined ADC that does not wait for the residue of a signal to settle to be delivered to the next stage of the pipeline, and thus passes signals to subsequent stages at faster than conventional speeds. A pipelined ADC is used that processes signals representing the boundaries of the search space. Thus, each stage does not necessarily receive the signal as pre-processed by the prior stage, but rather the search space boundaries as pre-processed by the prior stage. Reducing the “search space” of the ADC is equivalent to creating the residues in each step of a pipeline as in the prior art. An ADC operating in this fashion operates without error even if the residual search space boundary outputs from one state are presented to the next stage before the outputs have settled, and can run faster for a given power and bandwidth.
H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type
H03M 1/16 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
A programmable impedance element consists of a plurality of nominally identical two-port elements, each two-port element having an impedance element and two switches, the two-port elements arranged in a chain fashion with a structured set of switches such that a range of impedances can be obtained from each cell by dynamically changing the connections between the impedance elements in the cell. The common cell is constructed by connecting the nominally identical two-port impedance elements in a way that the number of possible combinations of the impedance elements is reduced to the subset of all possible combinations that uses the minimum possible number of connections. This structure allows the creation of matched impedances using industry standard devices. The connections between impedance elements are switches that may be “field-programmable,” i.e., that may be set on the chip after manufacture and configured during operation of the circuit, or alternatively may be mask programmable.
A signal processing circuit that achieves functionality similar to that of a switched capacitor circuit without the necessity a clock. The circuit compensates for finite open loop gain and for offset voltages in the components, allowing the circuit to “calculate” the result of a problem represented by the circuit essentially immediately upon the presentation of a new input or set of inputs. After the circuit is initialized to remove gain, an input is applied to the circuit, and propagates through the network and affects the state of amplifier outputs; the propagation from the input through capacitors to the ultimate output(s) of the circuit is the analog calculation taking place. The calculation is not mediated by a clock, but rather the calculation corresponds to the circuit's one-time response to the application of the inputs. Using these techniques complex signal processing circuits and even analog neural networks may be constructed.
H03F 3/00 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
H03K 17/94 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the way in which the control signals are generated
A signal processing circuit that achieves functionality similar to that of a switched capacitor circuit without the necessity a clock. The circuit compensates for finite open loop gain and for offset voltages in the components, allowing the circuit to "calculate" the result of a problem represented by the circuit essentially immediately upon the presentation of a new input or set of inputs. After the circuit is initialized to remove gain, an input is applied to the circuit, and propagates through the network and affects the state of amplifier outputs; the propagation from the input through capacitors to the ultimate output(s) of the circuit is the analog calculation taking place. The calculation is not mediated by a clock, but rather the calculation corresponds to the circuit's one-time response to the application of the inputs. Using these techniques complex signal processing circuits and even analog neural networks may be constructed.
Described herein is a system and method for controlling a computing system by an AI network based upon an electroencephalograph (EEG) signal from a user. The user's EEG signals are first detected as the user operates an existing controller, during which time the associated artificial intelligence (AI) system learns by correlating the EEG signals with the commands received from the controller. Once the AI system determines that there is sufficient correlation to predict the user's actions, it can take control of the computing system and initiate commands based upon the user's EEG signal in place of the user's actions with the controller. At this point, weights in the AI network may be locked so that further commands from the controller, or the lack thereof, do not reduce correlation with the EEG signals. In some embodiments, the AI network may initiate commands faster than the user would be able to do.
A multiport memory in which one of the ports is analog rather than digital is described. In one embodiment, the analog port functions as a read-only port and the digital port functions as a write only port. This allows the data in the core memory to be applied to an analog signal, while retaining a digital port having access to the core memory for rapid storage of data. One potential use of such a multiport memory is as a bridge between a digital computer and an analog computer; for example, this allows a digitally programmed two-port memory to derive a sum-of-products signal from a plurality of analog input signals, and a plurality of such multiport memories to be used in an analog neural network such as a programmable neural net implementing analog artificial intelligence (AI).
A hybrid delta modulator that can be used as a variable threshold neuron in a neural network is described. The hybrid delta modulator exhibits a memory of the prior state of the modulator, similar to a delta modulator, and receives a sum-of-products signal from a weighting circuit and generates a quantized output stream that represents the sum-of-products signal, potentially including an activation function and offset. With appropriately selected components, the hybrid delta modulator separates the integral function of the feedback from the gain function. Further, the gain can be selected, and the characteristic of the output pattern can be tailored to include an arbitrary combination of the input and the rate of change of the input. The use of a hybrid delta modulator of the present approach provides a simpler solution and better performance than many prior art neurons.
A multiport memory in which one of the ports is analog rather than digital is described. In one embodiment, the analog port functions as a read-only port and the digital port functions as a write only port. This allows the data in the core memory to be applied to an analog signal, while retaining a digital port having access to the core memory for rapid storage of data. One potential use of such a multiport memory is as a bridge between a digital computer and an analog computer; for example, this allows a digitally programmed two-port memory to derive a sum-of-products signal from a plurality of analog input signals, and a plurality of such multiport memories to be used in an analog neural network such as a programmable neural net implementing analog artificial intelligence (AI).
A self-clocking (or self-oscillating) modulator in signal processing, similar to a ΣΔ modulator, with particular application in the design of neural networks based on such modulators is described. A system of multiple self-clocking modulators and supporting structures may be configured to perform a calculation similar to that of an analog computer, such as a neural network, at lower power and smaller size than a digital implementation. Such a system constructed using the present approach does not require a sequential solution, but rather converges on a solution in one step; unlike the typical prior art, it thus requires no clock and operates asynchronously in a manner similar to a conventional analog computer. The self-clocking modulator can function as a neuron in a neural network, receiving a sum-of-products signal and generating an output stream like that of a ΣΔ modulator that represents this sum-of-products, potentially also including an activation function and offset.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
Described herein is an improved apparatus for increasing the performance of a ΣΔ modulator, which may function as an ADC. In one embodiment, the ΣΔ modulator comprises a voltage to current converter, a capacitor connected between two outputs of the voltage to current converter to receive a differential input current, and a switch that can switch between connecting each output of the voltage to current converter to ground while disconnecting the other output of the voltage to current converter. In this embodiment, the ΣΔ modulator has no common mode control loop, and no reference current. This results in decreased complexity, i.e., fewer components, as well as reduced noise.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference
H04L 25/06 - DC level restoring meansBias distortion correction
Improved performance of analog computers is obtained by utilizing a deliberate reduction in gain of the gain elements present in the analog computer. While a prior output of the circuit (if any) is present, the gain of the gain elements is reduced to a level that is low enough that the input signal cannot propagate through the circuit. The input signal is then changed to a new value, or set of values, while the gain of the gain elements remains reduced. Finally, the gain of the gain elements is increased to a level that is high enough to allow the input signal to propagate through the circuit, resulting in an output that is a solution to the problem represented by the analog computer.
H03G 3/30 - Automatic control in amplifiers having semiconductor devices
H03F 3/16 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
An analog element for use as a neuron in a recurrent neural network is described, the analog element having memory of a prior layer state and being a continuous time circuit rather than having a discrete clocking interval. The element is characterized and described by the Laplace s-domain operator, as distinct from a digital solution that uses the z-domain operator appropriate for quantized time descriptions. Rather than using an all-pass filter, the analog equivalent of a unit delay in the z-domain, a finite gain integrator, which is a simpler circuit, may be used to provide the delay in the analog s-domain. The resulting circuit may be easily implemented at the transistor level.
Improved performance of analog computers is obtained by utilizing a deliberate reduction in gain of the gain elements present in the analog computer. While a prior output of the circuit (if any) is present, the gain of the gain elements is reduced to a level that is low enough that the input signal cannot propagate through the circuit. The input signal is then changed to a new value, or set of values, while the gain of the gain elements remains reduced. Finally, the gain of the gain elements is increased to a level that is high enough to allow the input signal to propagate through the circuit, resulting in an output that is a solution to the problem represented by the analog computer.
Described herein is an apparatus for the recovery of asynchronous data into a fixed clock domain. A phase-locked loop (PLL) of the known art is replaced by a modified quadrature resolver, and the output from the resolver re-creates the selected frequency component of the input asynchronous data. The zero-crossings of this re-created data clock are used to sample the input data stream. One advantage of this technique is that it operates as a state machine on a single clock, and no analog components such as phase detectors or VCOs are needed. In another embodiment, the samples from the input data stream are changed from pulses to Gaussians, allowing for conversion of the sample rate from one clock domain to another.
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
H03K 3/00 - Circuits for generating electric pulsesMonostable, bistable or multistable circuits
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03D 13/00 - Circuits for comparing the phase or frequency of two mutually-independent oscillations
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
Described herein is an apparatus for the recovery of asynchronous data into a fixed clock domain. A phase-locked loop (PLL) of the known art is replaced by a modified quadrature resolver, and the output from the resolver re-creates the selected frequency component of the input asynchronous data. The zero-crossings of this re-created data clock are used to sample the input data stream. One advantage of this technique is that it operates as a state machine on a single clock, and no analog components such as phase detectors or VCOs are needed. In another embodiment, the samples from the input data stream are changed from pulses to Gaussians, allowing for conversion of the sample rate from one clock domain to another.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
Described herein is a method and apparatus for reducing ISI in a single-bit ΣΔ modulator without reducing the dynamic range of the modulator. In one embodiment, the signal fed back to the input of the modulator is not the single-bit outputs of a quantizer as in the prior art, but rather patterns of such outputs. The patterns are selected so that each pattern has the same number of transition edges and there is thus no mismatch of transition times. In one embodiment, the patterns are created by digital logic. In another embodiment, an analog signal is added to the error signal in the feedback loop which causes the quantizer to generate the patterns. When the amplitude of the input signal exceeds a certain level, the modulator reverts to the typical operation of a prior art modulator, thus preserving the full dynamic range of the modulator.
H03M 3/00 - Conversion of analogue values to or from differential modulation
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
Described herein is an improved apparatus for increasing the performance of a ΣΔ modulator, which may function as an ADC. In one embodiment, the ΣΔ modulator comprises a voltage to current converter, a capacitor connected between two outputs of the voltage to current converter to receive a differential input current, and a switch that can switch between connecting each output of the voltage to current converter to ground while disconnecting the other output of the voltage to current converter. In this embodiment, the ΣΔ modulator has no common mode control loop, and no reference current. This results in decreased complexity, i.e., fewer components, as well as reduced noise.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference
H04L 25/06 - DC level restoring meansBias distortion correction
43.
Use of differently delayed feedback to suppress metastability in noise shaping control loops
Described herein is a ΣΔ modulator with improved metastability in which the control loop remains stable. In one embodiment, the ΣΔ modulator utilizes differently delayed feedback to successive integrators of the control loop to suppress metastability errors without compromising the stability of the control loop. This is accomplished by including one or more quantizers in the control loop. This technique may be applied to control loops of at least second order, i.e., having two or more integrator stages, where at least one feedback term after the first is non-zero.
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