Abstract

Methods, systems, and apparatuses for adaptive power supply voltage transient protection are disclosed. One system includes a power supply, a transient sensor, and a power control processing entity. The power supply operates to provide power to one or more processors. The transient sensor is connected to the power supply and operates to sense transients on the power supply at greater than a predetermined speed or rate. The power control processing entity operates to receive a representation of the sensed transients and adjust a power load based on the sensed transients.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
• H02H 1/00 - Details of emergency protective circuit arrangements
• H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection

Abstract

Disclosed herein is a graph streaming neural network processing system comprising a first processor array, a second processor, and a thread scheduler. The thread scheduler dispatches a thread of a first node to the first processor array or the second processor, wherein the thread is executed to generate output data comprising a data unit stored in a private data buffer of the second processor. The thread scheduler determines that the data unit is sufficient for executing a thread of a second node. The second node is dependent on the output data generated by execution of a plurality of threads of the first node. Upon determining that the data unit is sufficient, the thread scheduler dispatches the thread of the second node. The thread scheduler determines to dispatch a subsequent thread of the first node for execution when a predefined threshold buffer size is available on the private data buffer.

IPC Classes  ?

• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt

Abstract

Methods, systems and apparatuses for discovering novel artificial neural network architectures (ANN) architecture are disclosed. One method includes calculating ANN architecture fingerprints including an ANN architecture fingerprint of each of a plurality of existing ANN architectures, creating a plurality of next-generation candidate ANN architectures, calculating a plurality of next-generation candidate ANN architecture fingerprints including an ANN architecture fingerprint of each of the plurality of next-generation candidate ANN architectures, calculating ANN architecture pairwise similarities between each of the plurality of existing ANN architectures and each of the plurality of next-generation candidate ANN architectures using the plurality of existing ANN architecture fingerprints and the plurality of next-generation candidate ANN architecture fingerprints, retraining each of the plurality of next-generation candidate ANN architectures on the training dataset, obtaining a performance score of each of the next-generation candidate ANN architectures, and calculating a fitness score for each of the next-generation candidate ANN architectures.

IPC Classes  ?

• G06N 3/082 - Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections
• G06F 18/214 - Generating training patternsBootstrap methods, e.g. bagging or boosting
• G06N 3/086 - Learning methods using evolutionary algorithms, e.g. genetic algorithms or genetic programming

Goods & Services

Computer hardware, namely, electronic circuits, computer chips and circuit boards for AI inferencing, machine learning, deep learning, and vision processing; graph streaming data processors; downloadable computer software, namely, software for the creation, processing and streaming of graphs; downloadable computer software development tools, compiler software and electronic coding units for programming graph streaming data processors; downloadable computer software for providing an integrated development environment (IDE) for artificial intelligence (AI) and/or machine learning (ML) software design, development, deployment, and management. Platform as a Service (PaaS) services for artificial intelligence (AI) and/or machine learning (ML) software design, development, deployment, and management.

Abstract

Methods, systems, and apparatuses for graph streaming processing are disclosed. One method includes receiving, by a thread scheduler, a group of threads, calculating a resource requirement for execution of the group of threads, calculating resource availability in a plurality of processors of each of a plurality of processor arrays, dispatching the group of threads to a selected one of plurality of processors of processor arrays, scheduling a group load instruction for all threads of the group of threads, including loading into a group load register a subset of inputs of the input tensor for processing of each thread of the group of threads, wherein the group load register provides the subset of the inputs of the input tensor to the group of threads of the selected one of the plurality of processors, wherein all threads of the group of threads are synchronized when executing the group load instruction.

IPC Classes  ?

• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Goods & Services

(1) Computer hardware, namely, electronic circuits, computer chips and circuit boards for AI inferencing, machine learning, deep learning, and vision processing; graph streaming data processors; downloadable computer software, namely, software for the creation, processing and streaming of graphs; downloadable computer software development tools, compiler software and electronic coding units for programming graph streaming data processors; downloadable computer software for providing an integrated development environment (IDE) for artificial intelligence (AI) and/or machine learning (ML) software design, development, deployment, and management. (1) Platform as a Service (PaaS) services for artificial intelligence (AI) and/or machine learning (ML) software design, development, deployment, and management.

Goods & Services

Computer hardware, namely, electronic circuits, computer chips and circuit boards for AI inferencing, machine learning, deep learning, and vision processing; graph streaming data processors; Downloadable computer software, namely, software for the creation, processing and streaming of graphs; Downloadable computer software development tools, downloadable compiler software and electronic coding units for programming graph streaming data processors; Downloadable computer software for providing an integrated development environment (IDE) for artificial intelligence (AI) and machine learning (ML) software design, development, deployment, and management Platform as a service (PAAS) featuring computer software platforms for artificial intelligence (AI) and machine learning (ML) software design, development, deployment, and management

Abstract

Systems and methods are disclosed for predicting one or more medical conditions utilizing digital images and employing artificial intelligent algorithms. The system offers accurate predictions utilizing quantized pre-trained deep learning model. The pre-trained deep learning model is trained on data samples and later refined as the system processes more digital images or new medical conditions are incorporated. One pre-trained deep learning model is used to predict the probability of one or more medical conditions and identify locations in the digital image effected by the one or more medical conditions. Further, one pre-trained deep learning model utilizing additional data and plurality of digital images, forecasts rate of infection and spread of the medical condition over time.

IPC Classes  ?

• G06T 7/00 - Image analysis
• G06F 18/21 - Design or setup of recognition systems or techniquesExtraction of features in feature spaceBlind source separation
• G06F 18/214 - Generating training patternsBootstrap methods, e.g. bagging or boosting
• G06N 3/08 - Learning methods
• G06T 5/70 - DenoisingSmoothing
• G06V 10/774 - Generating sets of training patternsBootstrap methods, e.g. bagging or boosting
• G06V 10/776 - ValidationPerformance evaluation
• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
• G16H 30/40 - ICT specially adapted for the handling or processing of medical images for processing medical images, e.g. editing
• G16H 50/20 - ICT specially adapted for medical diagnosis, medical simulation or medical data miningICT specially adapted for detecting, monitoring or modelling epidemics or pandemics for computer-aided diagnosis, e.g. based on medical expert systems

Abstract

Methods, systems. and apparatuses for graph streaming processing are disclosed. One method includes receiving, by a thread scheduler, a group of threads, calculating a resource requirement for execution of the group of threads, calculating resource availability in a plurality of processors of each of a plurality of processor arrays, dispatching the group of threads to a selected one of plurality of processors of processor arrays, scheduling a group load instruction for all threads of the group of threads, including loading into a group load register a subset of inputs of the input tensor for processing of each thread of the group of threads, wherein the group load register provides the subset of the inputs of the input tensor to the group of threads of the selected one of the plurality of processors, wherein all threads of the group of threads are synchronized when executing the group load instruction.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

Disclosed herein is a graph streaming processing system comprising a thread scheduler comprising a first component and a second component. The first component is configured to schedule a first set of threads of a first node to a first processor associated with the first node and initialize status of a completion pointer to an initial value. The completion pointer is associated with a command buffer of the first node. The first component is configured to detect the execution of the first set of threads and generation of a data unit and update the status of the completion pointer to an updated value indicating execution of the first set of threads in response to the generation of the data unit. The second component is configured to schedule a second set of threads of a plurality of second nodes to a second processor based on the status of the completion pointer. The second processor is associated with the plurality of second nodes and the second set of threads of the plurality of second nodes are dependent on execution of the first set of threads.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 9/54 - Interprogram communication

Abstract

The present disclosure relates to a system and method of performing quantization of a neural network having multiple layers. The method comprises receiving a floating-point dataset as input dataset and determining a first shift constant for first layer of the neural network based on the input dataset. The method also comprises performing quantization for the first layer using the determined shift constant of the first layer. The method further comprises determining a next shift constant for next layer of the neural network based on output of a layer previous to the next layer, and performing quantization for the next layer using the determined next shift constant. The method further comprises iterating the steps of determining shift constant and performing quantization for all layers of the neural network to generate fixed point dataset as output.

IPC Classes  ?

• G06V 10/776 - ValidationPerformance evaluation
• G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersectionsConnectivity analysis, e.g. of connected components

Abstract

Methods, systems, and apparatuses for adaptive power supply voltage transient protection are disclosed. One system includes a power supply, a voltage transient sensor, and a power control processing entity. The power supply operates to provide power to one or more processors. The voltage transient sensor is connected to the power supply and operates to sense voltage transients on the power supply at greater than a predetermined speed or rate. The power control processing entity operates to receive a representation of the sensed voltage transients and adjust a power load based on the sensed voltage transients.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
• H02H 1/00 - Details of emergency protective circuit arrangements
• H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection

Abstract

Methods, systems and apparatuses for a custom artificial neural network (ANN) architecture are disclosed. One method includes selecting existing ANN architectures, calculating ANN architecture fingerprints, calculating ANN architecture pairwise similarities among the existing ANN architectures, calculating centrality scores for the existing ANN architectures using the ANN architecture pairwise similarities, calculating dataset pairwise similarities between the target dataset and each of the existing datasets using dataset fingerprints, calculating target performance scores for the existing ANN architectures on the target dataset using performance scores of the existing ANN architectures on the existing datasets and the dataset pairwise similarities, calculating interpolation weights for the existing ANN architectures using the target performance scores of the existing ANN architectures on the target dataset and the centrality scores, and obtaining the custom ANN architecture by interpolating among the existing ANN architectures using the calculated interpolation weights.

IPC Classes  ?

• G06V 20/40 - ScenesScene-specific elements in video content
• G06F 18/20 - Analysing
• G06F 18/21 - Design or setup of recognition systems or techniquesExtraction of features in feature spaceBlind source separation
• G06F 18/22 - Matching criteria, e.g. proximity measures
• G06N 3/084 - Backpropagation, e.g. using gradient descent
• G06N 5/046 - Forward inferencingProduction systems
• G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
• G06V 40/12 - Fingerprints or palmprints

Abstract

Systems and methods are disclosed for predicting one or more medical conditions utilizing digital images and employing artificial intelligent algorithms. The system offers accurate predictions utilizing quantized pre-trained deep learning model. The pre-trained deep learning model is trained on data samples and later refined as the system processes more digital images or new medical conditions are incorporated. One pre-trained deep learning model is used to predict the probability of one or more medical conditions and identify locations in the digital image effected by the one or more medical conditions. Further, one pre-trained deep learning model utilizing additional data and plurality of digital images, forecasts rate of infection and spread of the medical condition over time.

IPC Classes  ?

• G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
• G06F 18/21 - Design or setup of recognition systems or techniquesExtraction of features in feature spaceBlind source separation
• G06F 18/214 - Generating training patternsBootstrap methods, e.g. bagging or boosting
• G06N 3/08 - Learning methods
• G06T 5/70 - DenoisingSmoothing
• G06T 7/00 - Image analysis
• G06V 10/774 - Generating sets of training patternsBootstrap methods, e.g. bagging or boosting
• G06V 10/776 - ValidationPerformance evaluation
• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
• G16H 30/40 - ICT specially adapted for the handling or processing of medical images for processing medical images, e.g. editing
• G16H 50/20 - ICT specially adapted for medical diagnosis, medical simulation or medical data miningICT specially adapted for detecting, monitoring or modelling epidemics or pandemics for computer-aided diagnosis, e.g. based on medical expert systems

Abstract

Methods, systems, and apparatuses for unsupervised data drift detection for classification neural networks are disclosed. One method includes providing the data stream of images to a neural network, generating, by the neural network, class wise probabilities, storing each image of the data stream of images, storing the class wise probabilities generated by the neural network, comparing artifacts of images of the data stream at a first time with artifacts of images of the data stream at a second time, comparing artifacts produced by the class wise probabilities of the data stream retrieved from the stored class wise probabilities at a third time with artifacts produced by the class wise probabilities of the data stream retrieved from the stored class wise probabilities at a fourth time, and generating an informative communication based on the comparisons.

IPC Classes  ?

• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
• G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries
• G06V 10/776 - ValidationPerformance evaluation

Abstract

Methods, systems, and apparatuses for graph stream processing are disclosed. One apparatus includes a cascade of graph streaming processors, wherein each of the graph streaming processor includes a processor array, and a graph streaming processor scheduler. The cascade of graph streaming processors further includes a plurality of shared command buffers, wherein each shared command buffer includes a buffer address, a write pointer, and a read pointer, wherein for each of the plurality of shared command buffers a graph streaming processor writes commands to the shared command buffer as indicated by the write pointer of the shared command buffer and the graph streaming processor reads commands from the shared command buffer as indicated by the read pointer, wherein at least one graph streaming processor scheduler operates to manage the write pointer and the read pointer to avoid overwriting unused commands of the shared command buffer.

IPC Classes  ?

• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
• G06F 8/41 - Compilation
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt

Abstract

Disclosed herein is a graph streaming neural network processing system comprising a first processor array, a second processor, and a thread scheduler. The thread scheduler dispatches a thread of a first node to the first processor array or the second processor, wherein the thread is executed to generate output data comprising a data unit stored in a private data buffer of the second processor. The thread scheduler determines that the data unit is sufficient for executing a thread of a second node. The second node is dependent on the output data generated by execution of a plurality of threads of the first node. Upon determining that the data unit is sufficient, the thread scheduler dispatches the thread of the second node. The thread scheduler determines to dispatch a subsequent thread of the first node for execution when a predefined threshold buffer size is available on the private data buffer.

IPC Classes  ?

• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors

Abstract

Systems, apparatuses and methods are disclosed for efficient management of registers in a graph stream processing (GSP) system. The GSP system includes a thread scheduler module operative to initiate a Single Instruction Multiple Data (SIMD) thread, the SIMD thread including a dispatch mask with an initial value. A thread arbiter module operative to select an instruction from the instructions and provide the instruction to each of one or more compute resources, and an instruction iterator module, associated with the each of one or more compute resources operative to determine a data type of the instruction. The instruction iterator module iteratively executes the instruction based on the data type and the dispatch mask.

IPC Classes  ?

• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt

Abstract

Disclosed herein is a method and a system for generating a mixed precision quantization model for performing image processing. The method comprises receiving a validation dataset of images to train a neural network model. The method comprises for each image of the validation dataset, generating a union sensitivity list, selecting a group of layers, generating a mixed precision quantization model by quantizing the selected group of layers into a high precision format; computing accuracy of the mixed precision quantization model for comparison with a target accuracy; in response to determining the accuracy is less than the target accuracy, generating another mixed precision model by selecting a next group of layers and computing the accuracy. In response to determining the accuracy is greater than or equal to the target accuracy, storing the mixed precision quantization model as a final mixed precision quantization model for image processing.

IPC Classes  ?

• G06N 3/04 - Architecture, e.g. interconnection topology
• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
• G06V 10/28 - Quantising the image, e.g. histogram thresholding for discrimination between background and foreground patterns

Abstract

The present disclosure relates to a system and a method of optimizing register allocation by a processor. The method comprising receiving an intermediate representation (IR) code of a source code and initializing single instruction multiple data (SIMD) width for the IR code. The method comprising analyzing each basic block of the IR code to classify determine one or more instructions of the IR code as vector instructions, wherein each basic block is one of LOAD, STORE and arithmetic logical and multiply (ALM) instructions. The method comprising dynamically setting the SIMD width for each of the vector instructions.

IPC Classes  ?

• G06F 8/41 - Compilation
• G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]

Abstract

Methods, systems, and apparatuses for adaptive power supply voltage transient protection are disclosed. One system includes a system on a chip (SOC), wherein the SOC includes a power supply, a voltage transient sensor, and a power control processing entity. The power supply operates to provide power to one or more processors operating on the SOC. The voltage transient sensor is connected to the power supply and operates to sense voltage transients on the power supply at greater than a predetermined speed or rate. The power control processing entity operates to receive a digital representation of the sensed voltage transients and adjust a power load of the SOC based on the sensed voltage transients.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
• H02H 1/00 - Details of emergency protective circuit arrangements
• H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection

Goods & Services

downloadable computer software development platform for artificial intelligence (ai) and machine learning (ml) software design, development, deployment, and management; downloadable computer software development platform for graph streaming data processors; downloadable computer software, namely, software for creating and optimizing artificial intelligence applications; downloadable computer software, namely, software for artificial intelligence inferencing, machine learning, deep learning, and vision processing. Platform as a service (PaaS) services for artificial intelligence (AI) and machine learning (ML) software design, development, deployment, and management; platform as a service (PaaS) services for graph streaming data processors.

Goods & Services

Computer hardware, namely, electronic circuits, computer chips and circuit boards for ai inferencing, machine learning, deep learning, and vision processing; graph streaming data processors; downloadable computer software, namely, software for ai inferencing, machine learning, deep learning, and vision processing; downloadable computer software development tools.

Goods & Services

Computer hardware, namely, electronic circuits, computer chips and circuit boards for ai inferencing, machine learning, deep learning, and vision processing; graph streaming data processors; downloadable computer software, namely, software for ai inferencing, machine learning, deep learning, and vision processing; downloadable computer software development tools.

Goods & Services

(1) Computer hardware, namely, electronic circuits, computer chips and circuit boards for ai inferencing, machine learning, deep learning, and vision processing; graph streaming data processors; downloadable computer software, namely, software for providing an integrated development environment for ai inferencing, machine learning, deep learning, and vision processing; downloadable computer software development tools, namely, compiler software and electronic coding units for programming graph streaming data processors.

Goods & Services

(1) Computer hardware, namely, electronic circuits, computer chips and circuit boards for ai inferencing, machine learning, deep learning, and vision processing; graph streaming data processors; downloadable computer software, namely, software for providing an integrated development environment for ai inferencing, machine learning, deep learning, and vision processing; downloadable computer software development tools, namely, compiler software and electronic coding units for programming graph streaming data processors

Goods & Services

(1) Downloadable computer software development platform for providing an integrated development environment for artificial intelligence (ai) and machine learning (ml) software design, development, deployment, and management; downloadable computer software development platform for the creation, processing and streaming of graphs; downloadable computer software, namely, software for providing an integrated development environment for creating and optimizing artificial intelligence applications; downloadable computer software, namely, software for providing an integrated development environment for artificial intelligence inferencing, machine learning, deep learning, and vision processing (1) Platform as a service (PaaS) services for artificial intelligence (AI) and machine learning (ML) software design, development, deployment, and management; platform as a service (PaaS) services for the creation, processing and streaming of graphs

Goods & Services

Computer hardware, namely, electronic circuits, computer chips and circuit boards for AI inferencing, machine learning, deep learning, and vision processing; graph streaming data processors; Downloadable computer software, namely, software for AI inferencing, machine learning, deep learning, and vision processing; Downloadable computer software development tools

Goods & Services

Computer hardware, namely, electronic circuits, computer chips and circuit boards for AI inferencing, machine learning, and deep learning; graph streaming data processors.

Goods & Services

Downloadable computer software development platform for the design, development, deployment, and management of artificial intelligence (AI) and machine learning (ML) software; Downloadable computer software, namely, software development platforms for graph streaming data processors; Downloadable computer software, namely, software for creating and optimizing artificial intelligence applications Platform as a Service (PaaS) services featuring computer software platforms for the design, development, deployment, and management of artificial intelligence (AI) and machine learning (ML) software; Platform as a Service (PaaS) services featuring computer software platforms for graph streaming data processors.

Abstract

Methods, systems and apparatuses for performing walk operations of single instruction, multiple data (SIMD) instructions are disclosed. One method includes initiating, by a scheduler, a SIMD thread, where the scheduler is operative to schedule the SIMD thread. The method further includes fetching a plurality of instructions for the SIMD thread. The method further includes determining, by a thread arbiter, at least one instruction that is a walk instruction, where the walk instruction iterates a block of instructions for a subset of channels of the SIMD thread, where the walk instruction includes a walk size, and where the walk size is a number of channels in the subset of channels of the SIMD thread that are processed in a walk iteration in association with the walk instruction. The method further includes executing the walk instruction based on the walk size.

IPC Classes  ?

• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

The present disclosure relates to a system and method of performing quantization of a neural network having multiple layers. The method comprises receiving a floating-point dataset as input dataset and determining a first shift constant for first layer of the neural network based on the input dataset. The method also comprises performing quantization for the first layer using the determined shift constant of the first layer. The method further comprises determining a next shift constant for next layer of the neural network based on output of a layer previous to the next layer, and performing quantization for the next layer using the determined next shift constant. The method further comprises iterating the steps of determining shift constant and performing quantization for all layers of the neural network to generate fixed point dataset as output.

IPC Classes  ?

• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
• G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersectionsConnectivity analysis, e.g. of connected components
• G06V 10/776 - ValidationPerformance evaluation

Abstract

Systems, apparatuses, and methods are disclosed for scheduling threads comprising of code blocks in a graph streaming processor (GSP) system. One system includes a scheduler for scheduling plurality of prefetch threads, main threads, invalidate threads. The plurality of prefetch threads includes prefetching data from main memory required for execution of the main threads of the next stage. The plurality of main threads includes a set of instructions operating on the graph streaming processors of GSP system. The plurality of the invalidate threads includes invalidating data location/s consumed by the plurality of the main threads of the previous stage. A portion of the scheduler is implemented in hardware.

IPC Classes  ?

• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt

Abstract

Methods, systems, and apparatuses for graph streaming processing system are disclosed. One system includes a plurality of graph streaming processors operative to process a plurality of threads, wherein the plurality of threads is organized as nodes. The system further includes a scheduler that includes a plurality of stages. Each stage includes a command parser operative to interpret commands within a corresponding input command buffer, an alternate command buffer, and a thread generator coupled to the command parser. The thread generator is operative to generate the plurality of threads, and dispatch the plurality of threads, where the processing of the plurality of thread for each stage includes storing write commands in the corresponding output command buffer or in the alternate command buffer.

IPC Classes  ?

• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 16/901 - IndexingData structures thereforStorage structures
• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining

Abstract

Methods, systems, and apparatuses for graph stream processing are disclosed. One apparatus includes a cascade of graph streaming processors, wherein each of the graph streaming processor includes a processor array, and a graph streaming processor scheduler. The cascade of graph streaming processors further includes a plurality of shared command buffers, wherein each shared command buffer includes a buffer address, a write pointer, and a read pointer, wherein for each of the plurality of shared command buffers a first graph streaming processor writes commands to the shared command buffer as indicated by the write pointer of the shared command buffer and a second graph streaming processor reads commands from the shared command buffer as indicated by the read pointer, wherein at least one graph streaming processor scheduler operates to manage the write pointer and the read pointer to avoid overwriting unused commands of the shared command buffer.

IPC Classes  ?

• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 8/41 - Compilation
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

Disclosed embodiments relate to a method and device for optimizing compilation of source code. The proposed method receives a first intermediate representation code of a source code and analyses each basic block instruction of the plurality of basic block instructions contained in the first intermediate representation code for blockification. In order to blockify the identical instructions, the one or more groups of basic block instructions are assessed for eligibility of blockification. Upon determining as eligible, the group of basic block instructions are blockified using one of one dimensional SIMD vectorization and two-dimensional SIMD vectorization. The method further generates a second intermediate representation of the source code which is translated to executable target code with more efficient processing capacity.

IPC Classes  ?

• G06F 8/41 - Compilation
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 9/4401 - Bootstrapping
• G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]

Abstract

Systems, apparatuses and methods are disclosed for efficient management of registers in a graph stream processing (GSP) system. The GSP system includes a thread scheduler module operative to initiate a Single Instruction Multiple Data (SIMD) thread, the SIMD thread including a dispatch mask with an initial value. A thread arbiter module operative to select an instruction from the instructions and provide the instruction to each of one or more compute resources, and an instruction iterator module, associated with the each of one or more compute resources operative to determine a data type of the instruction. The instruction iterator module iteratively executes the instruction based on the data type and the dispatch mask.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt

Goods & Services

Downloadable computer software for providing an integrated development environment (IDE) for artificial intelligence (AI) and/or machine learning (ML) software design, development, deployment, and management. Platform as a Service (PaaS) services for artificial intelligence (AI) and/or machine learning (ML) software design, development, deployment, and management.

Abstract

The present disclosure relates to a system and a method of optimizing scalar register allocation by a processor. The method comprises receiving an intermediate code and information about one or more available physical registers in a memory of the processor, as input. The method further comprises allocating one or more virtual registers based on the received information, wherein each virtual register is having size of each available physical register. The method also comprises mapping one or more groups of 8-bit location of the one or more virtual registers to one or more register classes. The method further comprises identifying a plurality of scalar variables from the input intermediate code, and dynamically assigning the one or more available physical registers to the identified scalar variables using the one or more register classes.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
• G06F 9/4401 - Bootstrapping

Abstract

Systems, apparatuses, and methods are disclosed for scheduling threads comprising of code blocks in a graph streaming processor (GSP) system. One system includes a scheduler for scheduling plurality of prefetch threads, main threads, invalidate threads. The plurality of prefetch threads includes prefetching data from main memory required for execution of the main threads of the next stage. The plurality of main threads includes a set of instructions operating on the graph streaming processors of GSP system. The plurality of the invalidate threads includes invalidating data location/s consumed by the plurality of the main threads of the previous stage. A portion of the scheduler is implemented in hardware.

IPC Classes  ?

• G06F 9/46 - Multiprogramming arrangements
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt

Abstract

Methods, systems and apparatuses for performing walk operations of single instruction, multiple data (SIMD) instructions are disclosed. One method includes initiating, by a scheduler, a SIMD thread, where the scheduler is operative to schedule the SIMD thread. The method further includes fetching a plurality of instructions for the SIMD thread. The method further includes determining, by a thread arbiter, at least one instruction that is a walk instruction, where the walk instruction iterates a block of instructions for a subset of channels of the SIMD thread, where the walk instruction includes a walk size, and where the walk size is a number of channels in the subset of channels of the SIMD thread that are processed in a walk iteration in association with the walk instruction. The method further includes executing the walk instruction based on the walk size.

IPC Classes  ?

• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Goods & Services

(1) Downloadable computer software for providing an integrated development environment (IDE) for artificial intelligence (AI) and machine learning (ML) software design, development, deployment, and management (1) Platform as a Service (PaaS) services for artificial intelligence (AI) and machine learning (ML) software design, development, deployment, and management

Goods & Services

(1) Computer hardware, namely, electronic circuits, computer chips and circuit boards for machine learning, deep learning, and vision processing; graph streaming data processors; downloadable computer software, namely, software for the creation, processing and streaming of graphs; downloadable computer software development tools, compiler software and electronic coding units for programming graph streaming data processors.

Goods & Services

(1) Computer hardware, namely, electronic circuits, computer chips and circuit boards for machine learning, deep learning, and vision processing; graph streaming data processors; downloadable computer software, namely, software for the creation, processing and streaming of graphs; downloadable computer software development tools, compiler software and electronic coding units for programming graph streaming data processors.

Goods & Services

Downloadable computer software for providing an integrated development environment (IDE) for artificial intelligence (AI) and machine learning (ML) software design, development, deployment, and management Platform as a Service (PaaS) services for artificial intelligence (AI) and machine learning (ML) software design, development, deployment, and management

Abstract

Systems and methods are disclosures for scheduling code in a multiprocessor system. Code is portioned into code blocks by a compiler. The compiler schedules execution of code blocks in nodes. The nodes are connected in a directed acyclical graph with a top node, terminal node and a plurality of intermediate nodes. Execution of the top node is initiated by the compiler. After executing at least one instance of the top node, an instruction in the code block indicates to the scheduler to initiate at least one intermediary node. The scheduler schedules a thread for execution of the intermediary node. The data for the nodes resides in a plurality of data buffers; the index to the data buffer is stored in a command buffer.

IPC Classes  ?

• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
• G06F 8/41 - Compilation

Abstract

The described embodiments include systems, methods, and apparatuses for increased efficiency processing flow. One method includes a plurality of stages configured to process an execution graph that includes a plurality of logical nodes with defined properties and resources associated with each logical node of the plurality of logical nodes, a recirculating ring buffer, wherein the recirculating ring buffer is configured to holding only any one of a control information, input, and, or out data necessary to stream a temporary data between each logical node of the execution graph, and a data producer, wherein the data producer is configured to stall from writing control information into a command buffer upon the command buffer being full, preventing command buffer over-writing.

IPC Classes  ?

• G06T 1/60 - Memory management
• G06T 15/00 - 3D [Three Dimensional] image rendering
• A01C 3/02 - Storage places for manure, e.g. cisterns for liquid manureInstallations for fermenting manure
• A01D 3/02 - Non-abrasive sharpening devices for scythes, sickles, or the like with percussive tools

Abstract

Methods, systems and apparatuses for graph processing are disclosed. One graph streaming processor includes a thread manager, wherein the thread manager is operative to dispatch operation of the plurality of threads of a plurality of thread processors before dependencies of the dependent threads have been resolved, maintain a scorecard of operation of the plurality of threads of the plurality of thread processors, and provide an indication to at least one of the plurality of thread processors when a dependency between the at least one of the plurality of threads that a request has or has not been satisfied. Further, a producer thread provides a response to the dependency when the dependency has been satisfied, and each of the plurality of thread processors is operative to provide processing updates to the thread manager, and provide queries to the thread manager upon reaching a dependency.

IPC Classes  ?

• G06F 9/52 - Program synchronisationMutual exclusion, e.g. by means of semaphores
• G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 16/903 - Querying
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 16/901 - IndexingData structures thereforStorage structures

Abstract

Disclosed embodiments relate to a method and device for optimizing compilation of source code. The proposed method receives a first intermediate representation code of a source code and analyses each basic block instruction of the plurality of basic block instructions contained in the first intermediate representation code for blockification. In order to blockify the identical instructions, the one or more groups of basic block instructions are assessed for eligibility of blockification. Upon determining as eligible, the group of basic block instructions are blockified using one of one dimensional SIMD vectorization and two-dimensional SIMD vectorization. The method further generates a second intermediate representation of the source code which is translated to executable target code with more efficient processing capacity.

IPC Classes  ?

• G06F 8/41 - Compilation
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

Methods, systems and apparatuses for discovering novel artificial neural network architectures (ANN) architecture are disclosed. One method includes calculating ANN architecture fingerprints including an ANN architecture fingerprint of each of a plurality of existing ANN architectures, creating a plurality of next-generation candidate ANN architectures, calculating a plurality of next-generation candidate ANN architecture fingerprints including an ANN architecture fingerprint of each of the plurality of next-generation candidate ANN architectures, calculating ANN architecture pairwise similarities between each of the plurality of existing ANN architectures and each of the plurality of next-generation candidate ANN architectures using the plurality of existing ANN architecture fingerprints and the plurality of next-generation candidate ANN architecture fingerprints, retraining each of the plurality of next-generation candidate ANN architectures on the training dataset, obtaining a performance score of each of the next-generation candidate ANN architectures, and calculating a fitness score for each of the next-generation candidate ANN architectures.

IPC Classes  ?

• G06N 3/045 - Combinations of networks
• G06F 18/214 - Generating training patternsBootstrap methods, e.g. bagging or boosting
• G06N 3/082 - Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections
• G06N 3/084 - Backpropagation, e.g. using gradient descent
• G06N 3/086 - Learning methods using evolutionary algorithms, e.g. genetic algorithms or genetic programming
• G06N 20/00 - Machine learning

Abstract

Systems and methods are disclosed for predicting one or more medical conditions utilizing digital images and employing artificial intelligent algorithms. The system offers accurate predictions utilizing quantized pre-trained deep learning model. The pre-trained deep learning model is trained on data samples and later refined as the system processes more digital images or new medical conditions are incorporated. One pre-trained deep learning model is used to predict the probability of one or more medical conditions and identify locations in the digital image effected by the one or more medical conditions. Further, one pre-trained deep learning model utilizing additional data and plurality of digital images, forecasts rate of infection and spread of the medical condition over time.

IPC Classes  ?

• G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
• G06T 7/00 - Image analysis
• G16H 30/40 - ICT specially adapted for the handling or processing of medical images for processing medical images, e.g. editing
• G16H 50/20 - ICT specially adapted for medical diagnosis, medical simulation or medical data miningICT specially adapted for detecting, monitoring or modelling epidemics or pandemics for computer-aided diagnosis, e.g. based on medical expert systems
• G06T 5/00 - Image enhancement or restoration
• G06N 3/08 - Learning methods
• G06F 18/214 - Generating training patternsBootstrap methods, e.g. bagging or boosting
• G06F 18/21 - Design or setup of recognition systems or techniquesExtraction of features in feature spaceBlind source separation
• G06V 10/774 - Generating sets of training patternsBootstrap methods, e.g. bagging or boosting
• G06V 10/776 - ValidationPerformance evaluation
• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks

Abstract

Methods, systems and apparatuses for a custom artificial neural network (ANN) architecture are disclosed. One method includes selecting existing ANN architectures, calculating ANN architecture fingerprints, calculating ANN architecture pairwise similarities among the existing ANN architectures, calculating centrality scores for the existing ANN architectures using the ANN architecture pairwise similarities, calculating dataset pairwise similarities between the target dataset and each of the existing datasets using dataset fingerprints, calculating target performance scores for the existing ANN architectures on the target dataset using performance scores of the existing ANN architectures on the existing datasets and the dataset pairwise similarities, calculating interpolation weights for the existing ANN architectures using the target performance scores of the existing ANN architectures on the target dataset and the centrality scores, and obtaining the custom ANN architecture by interpolating among the existing ANN architectures using the calculated interpolation weights.

IPC Classes  ?

• G06N 3/084 - Backpropagation, e.g. using gradient descent
• G06N 5/046 - Forward inferencingProduction systems
• G06V 20/40 - ScenesScene-specific elements in video content
• G06V 40/12 - Fingerprints or palmprints
• G06F 18/22 - Matching criteria, e.g. proximity measures
• G06F 18/21 - Design or setup of recognition systems or techniquesExtraction of features in feature spaceBlind source separation
• G06F 18/20 - Analysing
• G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks

Abstract

Methods, systems and apparatuses for performing walk operations of single instruction, multiple data (SIMD) instructions are disclosed. One method includes initiating, by a scheduler, a SIMD thread, where the scheduler is operative to schedule the SIMD thread. The method further includes fetching, a plurality of instructions for the SIMD thread. The method further includes determining, by a thread arbiter, at least one instruction that is a walk instruction, where the walk instruction iterates a block of instructions for a subset of channels of the SIMD thread, where the walk instruction includes a walk size, and where the walk size is a number of channels in the subset of channels of the SIMD thread that are processed in a walk iteration in association with the walk instruction. The method further includes executing the walk instruction based on the walk size.

IPC Classes  ?

• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

Methods, systems and apparatuses for reducing operations of Sum-Of-Multiply-Accumulate (SOMAC) instructions are disclosed. One method includes scheduling, by a scheduler, a thread for execution, executing, by a processor of a plurality of processors, the thread, fetching, by the processor, a plurality of instructions for the thread from a memory, selecting, by a thread arbiter of the processor, an instruction of the plurality of instructions for execution in an arithmetic logic unit (ALU) pipeline of the processor, and reading the instruction, and determining, by a macro-instruction iterator of the processor, whether the instruction is a Sum-Of-Multiply-Accumulate (SOMAC) instruction with an instruction size, wherein the instruction size indicates a number of iterations that the SOMAC instruction is to be executed.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

Methods, systems and apparatuses for graph streaming processing are disclosed. One method includes loading, by a group load register, a subset of a an input tensor from a data cache, wherein the group load register provides the subset of the input tensor to all of a plurality of processors, loading, by a plurality of weight data registers, a plurality of weights of a weight tensor, wherein each of the weight data registers provide an weight to a single of the plurality of processors, and performing, by the plurality of processors, a SOMAC (Sum-Of-Multiply-Accumulate) instruction, including simultaneously determining, by each of the plurality of processors, an instruction size of the SOMAC instruction, wherein the instruction size indicates a number of iterations that the SOMAC instruction is to be executed and is equal to a number of outputs within a subset of a plurality of output tensors.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

The described embodiments include systems, methods, and apparatuses for increased efficiency processing flow. One method includes a plurality of stages configured to process an execution graph that includes a plurality of logical nodes with defined properties and resources associated with each logical node of the plurality of logical nodes, a recirculating ring buffer, wherein the recirculating ring buffer is configured to holding only any one of a control information, input, and, or out data necessary to stream a temporary data between each logical node of the execution graph, and a data producer, wherein the data producer is configured to stall from writing control information into a command buffer upon the command buffer being full, preventing command buffer over-writing.

IPC Classes  ?

• G06T 1/60 - Memory management
• G06T 15/00 - 3D [Three Dimensional] image rendering
• A01C 3/02 - Storage places for manure, e.g. cisterns for liquid manureInstallations for fermenting manure
• A01D 3/02 - Non-abrasive sharpening devices for scythes, sickles, or the like with percussive tools

Goods & Services

Computer hardware, namely, electronic circuits, computer chips and circuit boards for machine learning, deep learning, and vision processing; graph streaming data processors; downloadable computer software, namely, software for the creation, processing and streaming of graphs; downloadable computer software development tools, compiler software and electronic coding units for programming graph streaming data processors.

Goods & Services

Processor cores in the nature of computing hardware as components of Systems-on-a-Chip; Instruction set architecture and processor architectures in the nature of computing hardware for integrated circuits; Underlying processor architecture in the nature of computing hardware for integrated circuits

Goods & Services

Computer hardware, namely, electronic circuits, computer chips and circuit boards for machine learning, deep learning, and vision processing; graph streaming data processors; downloadable computer software, namely, software for the creation, processing and streaming of graphs; downloadable computer software development tools, compiler software and electronic coding units for programming graph streaming data processors.

Abstract

The described embodiments include systems, methods, and apparatuses for increased efficiency processing flow. One method includes a plurality of stages configured to process an execution graph that includes a plurality of logical nodes with defined properties and resources associated with each logical node of the plurality of logical nodes, a recirculating ring buffer, wherein the recirculating ring buffer is configured to holding only any one of a control information, input, and, or out data necessary to stream a temporary data between each logical node of the execution graph, and a data producer, wherein the data producer is configured to stall from writing control information into a command buffer upon the command buffer being full, preventing command buffer over-writing.

IPC Classes  ?

• G06T 1/60 - Memory management
• G06T 15/00 - 3D [Three Dimensional] image rendering

Goods & Services

Processor cores in the nature of computing hardware as components of Systems-on-a-Chip; Instruction set architecture and processor architectures for integrated circuits in the nature of computing hardware; Underlying processor architecture for integrated circuits in the nature of computing hardware

Abstract

Systems and methods are disclosures for scheduling code in a multiprocessor system. Code is portioned into code blocks by a compiler. The compiler schedules execution of code blocks in nodes. The nodes are connected in a directed acyclical graph with a top node, terminal node and a plurality of intermediate nodes. Execution of the top node is initiated by the compiler. After executing at least one instance of the top node, an instruction in the code block indicates to the scheduler to initiate at least one intermediary node. The scheduler schedules a thread for execution of the intermediary node. The data for the nodes resides in a plurality of data buffers; the index to the data buffer is stored in a command buffer.

IPC Classes  ?

• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 8/41 - Compilation
• G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]

Abstract

The claimed invention discloses system comprising a plurality of logical nodes comprised in a single or plurality of stages, with defined properties and resources associated with each node, for reducing compute resources, said system further comprising: at least a recirculating ring buffer holding only any one of a control information, input, and, or out data necessary to stream a temporary data between node and, or nodes in an execution graph, thereby reducing size of said recirculating ring buffer; said recirculating ring buffer being sufficiently reduced in size to reside in an on-chip cache, such that any one of the control information, input, and, or out data between node and, or nodes need not be stored in memory; wherein the control information further comprises a command related to invalidating any one of the input and, or out data held in a recirculating ring data buffer, clearing the buffer of tasked data; and wherein a producer is stalled from writing any more control information into a recirculating ring command buffer upon the buffer being full, preventing command buffer over-writing, and thereby reducing compute resources associated with a DRAM memory transaction.

IPC Classes  ?

• G06T 1/60 - Memory management
• G06T 15/00 - 3D [Three Dimensional] image rendering

Abstract

Systems and methods are disclosures for scheduling code in a multiprocessor system. Code is portioned into code blocks by a compiler. The compiler schedules execution of code blocks in nodes. The nodes are connected in a directed acyclical graph with a top node, terminal node and a plurality of intermediate nodes. Execution of the top node is initiated by the compiler. After executing at least one instance of the top node, an instruction in the code block indicates to the scheduler to initiate at least one intermediary node. The scheduler schedules a thread for execution of the intermediary node. The data for the nodes resides in a plurality of data buffers; the index to the data buffer is stored in a command buffer.

IPC Classes  ?

• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 8/41 - Compilation

Goods & Services

Computer hardware, namely, electronic circuits, computer chips and circuit boards for machine learning, deep learning, and vision processing; graph streaming data processors; Downloadable computer software, namely, software for the creation, processing and streaming of graphs; Downloadable computer software development tools, compiler software and electronic coding units for programming graph streaming data processors

Goods & Services

Computer hardware, namely, electronic circuits, computer chips and circuit boards for machine learning, deep learning, and vision processing; graph streaming data processors; Downloadable computer software, namely, software for the creation, processing and streaming of graphs; Downloadable computer software development tools, compiler software and electronic coding units for programming graph streaming data processors

Abstract

Methods, systems and apparatuses for graph streaming processing system are disclosed. One system includes a plurality of graph streaming processors operative to process a plurality of threads, wherein the plurality of threads is organized as nodes. The system further includes a scheduler that includes a plurality of stages. Each stage includes a command parser operative to interpret commands within a corresponding input command buffer, an alternate command buffer, and a thread generator coupled to the command parser. The thread generator is operative to generate the plurality of threads, and dispatch the plurality of threads, where the processing of the plurality of thread for each stage includes storing write commands in the corresponding output command buffer or in the alternate command buffer.

IPC Classes  ?

• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 16/901 - IndexingData structures thereforStorage structures
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining

Abstract

Systems, apparatuses and methods are disclosed for scheduling threads comprising of code blocks in a graph streaming processor (GSP) system. One system includes a scheduler for scheduling plurality of threads, the plurality of threads includes a set of instructions operating on the graph streaming processors of GSP system. The scheduler comprises a plurality of stages where each stage is coupled to an input command buffer and an output command buffer. A portion of the scheduler is implemented in hardware and comprises of a command parser operative to interpret commands within a corresponding input command buffer, a thread generator coupled to the command parser operate to generate the plurality of threads, and a thread scheduler coupled to the thread generator for dispatching the plurality of threads for operating on the plurality of graph streaming processors.

IPC Classes  ?

• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]

Abstract

Methods, systems and apparatuses for graph stream processing are disclosed. One apparatus includes a cascade of graph streaming processors, wherein each of the graph streaming processor includes a processor array, and a graph streaming processor scheduler. The cascade of graph streaming processors further includes a plurality of shared command buffers, wherein each shared command buffer includes a buffer address, a write pointer, and a read pointer, wherein for each of the plurality of shared command buffers a first graph streaming processor writes commands to the shared command buffer as indicated by the write pointer of the shared command buffer and a second graph streaming processor reads commands from the shared command buffer as indicated by the read pointer, wherein at least one graph streaming processor scheduler operates to manage the write pointer and the read pointer to avoid overwriting unused commands of the shared command buffer.

IPC Classes  ?

• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 8/41 - Compilation
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

Methods, systems and apparatuses for graph processing are disclosed. One graph streaming processor includes a thread manager, wherein the thread manager is operative to dispatch operation of the plurality of threads of a plurality of thread processors before dependencies of the dependent threads have been resolved, maintain a scorecard of operation of the plurality of threads of the plurality of thread processors, and provide an indication to at least one of the plurality of thread processors when a dependency between the at least one of the plurality of threads that a request has or has not been satisfied. Further, a producer thread provides a response to the dependency when the dependency has been satisfied, and each of the plurality of thread processors is operative to provide processing updates to the thread manager, and provide queries to the thread manager upon reaching a dependency.

IPC Classes  ?

• G06F 9/52 - Program synchronisationMutual exclusion, e.g. by means of semaphores
• G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
• G06F 16/903 - Querying
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 16/901 - IndexingData structures thereforStorage structures

Abstract

The claimed invention discloses system comprising a plurality of logical nodes comprised in a single or plurality of stages, with defined properties and resources associated with each node, for reducing compute resources, said system further comprising: at least a recirculating ring buffer holding only any one of a control information, input, and, or out data necessary to stream a temporary data between node and, or nodes in an execution graph, thereby reducing size of said recirculating ring buffer; said recirculating ring buffer being sufficiently reduced in size to reside in an on-chip cache, such that any one of the control information, input, and, or out data between node and, or nodes need not be stored in memory; wherein the control information further comprises a command related to invalidating any one of the input and, or out data held in a recirculating ring data buffer, clearing the buffer of tasked data; and wherein a producer is stalled from writing any more control information into a recirculating ring command buffer upon the buffer being full, preventing command buffer over-writing, and thereby reducing compute resources associated with a DRAM memory transaction.

IPC Classes  ?

• G06T 1/60 - Memory management
• G06T 15/00 - 3D [Three Dimensional] image rendering

Abstract

Embodiments disclosed include a mechanism in a system and method for significantly reducing power consumption by reducing computation and bandwidth. This mechanism is particularly applicable for modern 3D synthetic images which contain high pixel overdraw and dynamically generated intermediates images. Only blocks of computation which contribute to the final image are performed. This is accomplished by rendering in reverse order and by performing multiple visibility sort in a streaming fashion through the pipeline. Rendering of dynamically generated intermediate images is performed sparsely by projecting texture coordinates from a current image back into one or more dependent images in a recursive manner. The newly computed pixel values are then filtered and control is returned to the sampling shader of the current image. When only visible pixels are projected optimal computation is performed. Several implementations are presented with increasing efficiency. An acceleration structure, termed a Draw Buffer, simplifies the process of projecting backward and utilizes a hardware managed dynamic memory object. This mechanism reduces computation by 50%, with significant bandwidth and power savings.

IPC Classes  ?

• G06T 17/00 - 3D modelling for computer graphics
• G06T 1/60 - Memory management
• G06T 15/40 - Hidden part removal
• G06T 15/00 - 3D [Three Dimensional] image rendering
• G06T 15/04 - Texture mapping
• G06T 17/20 - Wire-frame description, e.g. polygonalisation or tessellation
• G06T 15/80 - Shading

Abstract

Methods, systems and apparatuses for selecting graphics data of a server system for transmission are disclosed. One method includes reading data from memory of the server system, checking if the data is being read for the first time, checking if the data was written by a processor of the server system during processing, comprising checking if the data is available on a client system or present in a transmit buffer, placing the data in the transmit buffer if the data is being read for the first time and was not written by the processor during the processing as determined by the checking if the data was written by the processor of the server system during processing, wherein if the data is being read for the first time and was written by the processor of the server system during processing the data is not placed in the transmit buffer.

IPC Classes  ?

• G09G 5/395 - Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
• G09G 5/36 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory
• G06T 15/00 - 3D [Three Dimensional] image rendering
• H04N 21/426 - Internal components of the client
• H04N 21/434 - Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams or extraction of additional data from a video streamRemultiplexing of multiplex streamsExtraction or processing of SIDisassembling of packetised elementary stream
• H04N 21/81 - Monomedia components thereof
• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
• H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
• G06F 3/14 - Digital output to display device
• H04N 21/236 - Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator ] into a video stream, multiplexing software data into a video streamRemultiplexing of multiplex streamsInsertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rateAssembling of a packetised elementary stream

Abstract

Methods, systems and apparatuses for selecting graphics data of a server system for transmission are disclosed. One method includes a plurality of graphic render passes, wherein one or more of the graphics render passes includes reading data from graphics memory of the server system. The data read from the graphics memory is placed in a transmit buffer if the data is being read for the first time, and was not written by a processor of the server system. One system includes a server system including graphics memory, a frame buffer and a processor. The server system is operable to read data from the graphics memory. The server system is operable to place the data in a transmit buffer if the data is being read for the first time, and was not written by the processor during rendering.

IPC Classes  ?

• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
• G06F 3/14 - Digital output to display device
• G06T 15/00 - 3D [Three Dimensional] image rendering
• H04N 21/236 - Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator ] into a video stream, multiplexing software data into a video streamRemultiplexing of multiplex streamsInsertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rateAssembling of a packetised elementary stream
• H04N 21/426 - Internal components of the client
• H04N 21/434 - Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams or extraction of additional data from a video streamRemultiplexing of multiplex streamsExtraction or processing of SIDisassembling of packetised elementary stream
• H04N 21/81 - Monomedia components thereof
• G09G 5/36 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory
• H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation

Abstract

Methods, systems and apparatuses for selecting graphics data of a server system for transmission are disclosed. One method includes reading data from graphics memory of the server system. The data read from the graphics memory is placed in a transmit buffer if the data is being read for the first time, and was not written by a processor of the server system. One system includes a server system including graphics memory, a frame buffer and a processor. The server system is operable to read data from the graphics memory. The server system is operable to place the data in a transmit buffer if the data is being read for the first time, and was not written by the processor during rendering.

IPC Classes  ?

• G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
• G06F 15/00 - Digital computers in generalData processing equipment in general
• G06T 1/00 - General purpose image data processing
• G09G 5/36 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory
• G09G 5/37 - Details of the operation on graphic patterns
• G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
• G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal