An image processing device according to the present disclosure generates a feature map based on an image, determines whether a value of each cell of the feature map is equal to or larger than a lower limit threshold value, calculates an activation value by inputting the value of each cell of the feature map equal to or larger than the lower limit threshold value to an activation function, and generates an existence probability map indicating distribution of existence probability of an object in the image by using the activation value.
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
G06V 10/40 - Extraction of image or video features
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
To improve the temperature measurement accuracy of a semiconductor device. The semiconductor device includes a temperature sensor having a plurality of switches As, a first terminal couped to the temperature sensor via the switches As, a second terminal coupled to the temperature sensor via the switches As, a third terminal coupled to the temperature sensor via the switches As, and a fourth terminal coupled to the temperature sensor via switches As and being supplied with a predetermined voltage VCC. The fourth terminal is capable of coupling with the first terminal, the second terminal, and third terminal via the switches As.
A semiconductor device includes a first semiconductor layer and a second semiconductor layer formed in a semiconductor substrate, a first buried region formed in the first semiconductor layer, a drain region, a drift region, a source region, and a body region formed in the second semiconductor layer, a back-gate region formed in the body region, a gate electrode formed on an upper surface of the semiconductor substrate, and a second buried region formed in the second semiconductor layer and disposed between the first buried region and the body region. A side surface of the second buried region is located between the gate electrode and the drain region in plan view. The second buried region is connected to the body region.
A semiconductor wafer held by a Bernoulli chuck is reliably rotated. A wafer holding apparatus includes: a chuck for holding a semiconductor wafer; and a rotating mechanism for rotating the chuck. On a facing surface of the chuck facing the semiconductor wafer, a plurality of pads and a plurality of support parts are formed. The chuck holds the semiconductor wafer by jetting gas from each of the plurality of pads. The plurality of support parts is formed at positions each deviated from a center of the facing surface of the chuck. When the chuck holds the semiconductor wafer, the plurality of pads is not in contact with the semiconductor wafer while the plurality of support parts is in contact with a principal surface of the semiconductor wafer.
Techniques are provided for suppressing the accumulation of holes in floating region and improving the switching time of a semiconductor device such as an Insulated Gate Bipolar. The semiconductor device includes a trench gate and a trench emitter formed in a semiconductor substrate, and a floating region of a first conductivity type formed in the semiconductor substrate sandwiched between the trench gate and the trench emitter. The bottom of the floating region is located below the bottom of the trench gate and the trench emitter, and the floating region has a crystal defect region including crystal defects selectively formed at a position near an upper surface of the semiconductor substrate in the floating region.
Provide a technology that can estimate a propagation length. An evaluation element includes a diffusion layer formed in a semiconductor substrate and a plurality of a pair of contacts electrically connected to the diffusion layer. The plurality of the pair of contacts are separated by a distance in the X direction. A width of the third contacts in the X direction is smaller than a width of a second contacts in the X direction. The width of the second contacts is smaller than a width of the first contacts in the X direction.
H10D 62/80 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
8.
SIC MOSFET WITH IMPROVED HIGH CURRENT ON-RESISTANCE PERFORMANCE
A method of forming a semiconductor structure includes forming a silicon carbide semiconductor substrate of a first conductivity type. A drift layer of the first conductivity type is formed above an upper surface of the semiconductor substrate. A junction field-effect transistor (JFET) region of the first conductivity type is formed above the drift layer with base regions of a second conductivity type positioned on opposite sides of a top portion of the JFET region. Each base region contacts a bottom portion of the JFET region. A hard mask is formed above the top portion of the JFET region located between the base regions. First doped regions of the first conductivity type are formed within the JFET region, at an interface between the base regions and the JFET region, extending into the JFET region such that the first doped regions reduce a width of the top portion of the JFET region.
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
H10D 64/62 - Electrodes ohmically coupled to a semiconductor
The semiconductor device comprises a first and a second comparator configured to compare an input voltage corresponding to a sense current detected by an output current of a power transistor with a first reference voltage and a second reference voltage respectively, the second reference voltage being lower than the first reference voltage. The semiconductor device further comprises a first and second counter respectively coupled to the first and second comparator and configured to count up and down, an adder circuit coupled to the first counter and the second counter and configured to calculate a total value of count values of the first counter and the second counter, and a detection signal output circuit configured to output a detection signal when the total value of the count values is equal to or greater than a threshold value.
H02H 3/08 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current
H02H 1/00 - Details of emergency protective circuit arrangements
10.
SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING SEMICONDUCTOR DEVICE, AND CONTROL PROGRAM
To provide a semiconductor device, a control method for the semiconductor device, and a control program that can update the initial setting values of the interface circuit after a mask ROM is implemented. The semiconductor device includes an interface circuit, the mask ROM storing initial setting values and an initialization function, a CPU (Central Processing Unit) that sets the initial setting values in the interface circuit by executing the initialization function during initialization, and non-volatile memory. The initialization function stored in the mask ROM includes a patch function that updates the initial setting values set in the interface circuit during initialization using address information of the storage area to be accessed, data-related information, and processing-related information, which are written in the non-volatile memory.
An image processing device according to the present disclosure generates a second image by executing quantization processing on a first image, generates a feature map based on the second image, generates an existence probability map indicating distribution of existence probability of an object in the first image by using the feature map, performs matching determination processing that is processing of determining whether a value of each cell matches a fixed value for the feature map or the existence probability map, and performs dequantization processing on the feature map or the existence probability map based on a result of the matching determination processing.
G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries
G06V 10/28 - Quantising the image, e.g. histogram thresholding for discrimination between background and foreground patterns
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
A semiconductor device includes a plurality of precharge circuits in addition to a plurality of read bit lines through which read data is transferred from a plurality of latch cells in a latch cell array. Each of the plurality of latch cells is composed of 10 or 12 MOS transistors including a first CMOS switch that transfers write data and a second CMOS switch that transfers read data. The plurality of precharge circuits precharges the plurality of read bit lines to an intermediate voltage between a high potential side power supply voltage and a low potential side power supply voltage before the second CMOS switches are controlled to turn on.
A semiconductor device including: a semiconductor substrate including a chip region; and an interlayer insulating film on the semiconductor substrate is used, the chip region having: a circuit region; and a seal ring region positioned around the circuit region. The semiconductor device includes: a first wiring formed on the interlayer insulating film in the circuit region; and a second wiring formed on the interlayer insulating film in the seal ring region. The semiconductor device further includes: an insulating film covering the first wiring and the second wiring; and an organic insulating film on the insulating film IFT. A concave portion is formed on the upper surface of the second wiring. An end portion of the organic insulating film is positioned on a first portion, which is positioned closer to an edge portion of the chip region than the concave portion, of the second wiring.
A support mark inspection equipment includes: an input unit for obtaining an inspection image of a wafer; a partial image generating unit for extracting a plurality of partial images, each including a portion where a support portion of a boat contacts the wafer, from the inspection image; a generated image obtaining unit for inputting each of the plurality of partial images into an AI (Artificial Intelligence) model and obtaining a plurality of generated images respectively corresponding to the plurality of partial images; an abnormality determination unit for determining whether a support mark is present in each of the plurality of partial images based on each of the plurality of partial images and each of the plurality of generated images; and an output unit for outputting an inspection result of the support mark.
A semiconductor structure includes a gate electrode disposed above a semiconductor substrate of a first conductivity type. The semiconductor structure further includes a source region of the first conductivity type positioned, at least partially, below the gate electrode, and a doped region of a second conductivity type, opposite to the first conductivity type, located adjacent to the source region. The semiconductor structure further includes a first ohmic contact positioned above and in contact with the source region and the doped region. The first ohmic contact having a length and a contact area in electrical communication with the doped region. The semiconductor structure further includes a field oxide adjacent to the doped region, with the length of the first ohmic contact extending above the doped region until a distance between the first ohmic contact and the field oxide is equal to a threshold value.
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
16.
BLOCKCHAIN-SECURED MACHINE LEARNING MODEL MANAGEMENT
Systems and methods for implementing blockchain-secured machine learning model management are described. The system can include a Machine Learning Operations (MLOps) user interface (UI), an MLOps processor, a model operation tool stack, and a model registry. The MLOps UI is configured to allow a user to interact with the system and receive a request for operating a machine learning model. The request includes a model transaction and blockchain ledger. The MLOps processor is communicatively connected to the MLOps UI. The MLOps processor is configured to manage the machine learning model and to execute workflows associated with the model transaction. The model operation tool stack is configured to perform tasks for operating the machine learning model. The model storage is configured to store encrypted machine-learning models. The model registry is configured to manage the machine learning model and the model transaction using the blockchain ledger.
To improve the performance of the differential circuit. Additionally, to suppress the increase in development cost and development period without causing characteristic variations in the pair elements. The plurality of MOS units 0Q are composed of at least one MOSFET, each having the same structure, and are arranged adjacent to each other on the main surface of the semiconductor substrate in plan view. The plurality of MOS units 0Q include MOS unit 1Q and MOS unit 2Q, which constitute part of the differential circuit as pair elements, and MOS unit 3Q, which functions as a capacitive element.
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
G06F 115/08 - Intellectual property [IP] blocks or IP cores
G06F 119/06 - Power analysis or power optimisation
A semiconductor device including a Zener diode, includes: an n-type semiconductor substrate; a p-type well region; an n-type diffusion region; and a p-type impurity region. An impurity concentration of the p-type impurity region is higher than an impurity concentration of the p-type well region. The p-type impurity region surrounds at least a part of the n-type diffusion region in plan view. The p-type well region forms a quadrangular shape in plan view. Each corner of the p-type well region is exposed from the p-type impurity region in plan view. A cathode of the Zener diode includes the n-type diffusion region. An anode of the Zener diode includes the p-type well region and the p-type impurity region.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
A semiconductor device includes: an oscillator circuit including a plurality of logic gate groups connected in series; a frequency counter measuring an oscillation frequency of the oscillator circuit; and a comparator comparing a reference value and the oscillation frequency of the oscillator circuit measured by the frequency counter. Each of the logic gate groups includes first to third logic gates each made of a transistor and connected in series. A first fan-out number of the first logic gate is larger than a second fan-out number of the second logic gate and the third logic gate. The first to third logic gates have the same driving force from one another.
Disclosed is a technique for improving performance of a semiconductor device having a trench gate type power MOSFET. Concretely, a method of manufacturing a semiconductor device having a trench gate type power MOSFET comprising: forming a trench in a semiconductor substrate; introducing both of a p-type impurity (Boron) and carbon (C) into a bottom surface of the trench to form a p-type impurity introduced region; forming a gate electrode to fill the trench; forming a channel forming region and a source region at the side of the trench in which the gate electrode is filled; and subjecting a heat treatment to the p-type impurity introduced region to form an electric field relaxation layer having suppressed crystal defects and a controlled shape.
A wireless power apparatus may include a first planar coil having a first coil winding orientation, the first planar coil may be disposed in a plane, a second planar coil may have a second coil winding orientation that is opposite the first coil winding orientation, the second planar coil may be disposed at a distance from the first planar coil in the plane, and a conductor configured to serially connect the first planar coil with the second planar coil to form a split planar coil.
H01F 27/36 - Electric or magnetic shields or screens
H02J 50/10 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
H02J 50/70 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the reduction of electric, magnetic or electromagnetic leakage fields
Systems and methods for implementing addressable SPI are described. The system includes a controller and a plurality of devices. The controller includes a SPI bus and a node address (NAD) line. The controller is configured to transmit a chip select signal and a clock signal via the SPI bus, and receive a respective node address signal via the NAD line. The plurality of devices is connected to the SPI bus of the controller. A respective device of the plurality of devices is configured to receive the chip select signal and the clock signal from the controller via the SPI bus; determines a respective node address associated with the respective device based on the chip select signal and the clock signal; generate a respective node address signal indicating the respective node address; and transmit the respective node address signal to an adjacent device in the chain or the NAD line.
Methods and apparatus for protecting data frames at a transmission side of a frame-based communication link are described. The apparatus includes a receiver module, a cipher suite module and a transmitter module. The receiver module receives the data frame and protection information for the data frame. The protection information specifies whether the data frame is to be protected. The receiver module transmits the data frame to the cipher suite module, if the protection information specifies that the data frame is to be protected. If the protection information specifies that the data frame is not to be protected, the receiver transmits the data frames the data frame to the transmitter module. The cipher suite module protects the data frame and transmits the protected data frame to the transmit module. The transmit module provides the data frame or the protected data frame for transmission over the frame-based communication link.
Systems and methods for implementing pass-through mode (PTM) of a power conversion circuit are described. The system can include a first stage controller and a first stage. The first stage controller is configured to monitor an input voltage and generate a PTM control signal based on the input voltage to control an operation of. The first stage is connected to the first stage controller. The first stage can include the power conversion circuit configured to convert the input voltage to a converter output voltage.
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A wireless power apparatus may include a receiver coil with a first conductor assembly having a first conductor type, the receiver coil with a second conductor assembly having a second conductor type that may be different from the first conductor type, the first conductor assembly and the second conductor assembly may be connected in series to form a hybrid coil.
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
H01F 41/061 - Winding flat conductive wires or sheets
H02J 50/00 - Circuit arrangements or systems for wireless supply or distribution of electric power
To provide a power supply device that includes a comparison circuit in the feedback circuit and employs an optical isolator in the voltage conversion unit. The power supply device comprises a switching circuit that controls the input voltage and converts it to output voltage, a power transmission unit that transmits the output voltage to the output stage, an optical isolator connected to the power transmission unit that transmits the voltage signal of the output stage to the feedback circuit while isolating it, and a feedback circuit that generates a control signal to control the switch based on the voltage signal input from the optical isolator and outputs it to the switching circuit, wherein the feedback circuit generates the control signal using a comparison circuit that binarizes the input voltage signal.
An integrated circuit 1 comprises a processor 10, a memory 12 that holds data defined in the software 18 executed by the processor 10, a data cache 11 positioned between the processor 10 and the memory 12, and a recording circuit 13. The data cache 11 temporarily holds write data output from processor 10 to be written to memory 12. The recording circuit 13 is connected to the bus 20 between the processor 10 and the data cache 11 and records the write data.
A semiconductor device is provided that can improve heat dissipation while suppressing cracking in one of the topmost semiconductor chips among a plurality of semiconductor chips. The semiconductor device includes a plurality of semiconductor chips and a mold resin. The semiconductor chips are stacked and include a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is located at the topmost position among the semiconductor chips and the second semiconductor chip is located at the bottommost position among the semiconductor chips. Each of the semiconductor chips has a lower surface and an upper surface located opposite the lower surface. The upper surface of the first semiconductor chip has, in a plan view, a peripheral region and a central region located inside the peripheral region. The mold resin is formed to cover the peripheral region and has a through-hole that at least partially exposes the central region.
A log management apparatus, an in-vehicle system, and a data transfer method for the log management apparatus are provided to preferentially transfer desired log data to a storage. The log management apparatus 1 includes a CPU 2 that outputs log data, a log buffer 41 that stores log data, and a DMA controller 3 that transfers the log data stored in the log buffer 41 to a storage 5. The DMA controller 3 includes a priority table storage unit 31 that stores a priority table including a priority set that determines a priority for each tag associated with log data, and a transfer necessity determination circuit 32 that determines which log data not to be transferred to the storage 5 from among the log data stored in the log buffer 41 based on the priority set.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
To provide a failure detection circuit for detecting abnormality within a semiconductor device that operates in synchronization with a clock signal, by detecting a signal path delay in the semiconductor device with respect to the clock signal. The failure detection circuit comprises a first flip-flop element configured to receive a first input data signal and to provide a first output data signal according to the first input data signal in response to the clock signal. The failure detection circuit also comprises a second flip-flop element configured to receive a second input data signal and to provide a second output data signal according to the second input data signal in response to the clock signal.
After a silicon oxide film is formed on a main surface of a semiconductor substrate so as to cover a floating gate electrode and a gate electrode, an isotropic etching is performed on the silicon oxide film with a photoresist pattern formed thereon used as an etching mask, and an anisotropic etching is further performed on the silicon oxide film. Accordingly, the silicon oxide film exposed from the photoresist pattern is removed, and a first insulating film made of the silicon oxide film remaining below the photoresist pattern is formed. The first insulating film covers the floating gate electrode. After a metal silicide layer is formed on the gate electrode, a second insulating film made of silicon nitride is formed on the main surface of the semiconductor substrate so as to cover the floating gate electrode, the gate electrode, the metal silicide layer, and the first insulating film.
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
A semiconductor device includes a reference current generation circuit, a replica current generation circuit, a first ramp wave signal generation circuit and a second ramp wave signal generation circuit, and a correction circuit. The reference current generation circuit includes a first MOSFET and a first resistor, and is configured such that a reference current flows through the first MOSFET and the first resistor. The replica current generation circuit includes a second MOSFET through which a replica current of M times the reference current flows. A first ramp wave signal generation circuit and a second ramp wave signal generation circuit alternately generate ramp wave signals. A correction circuit that generates a voltage according to a current value of the reference current, and generates the first potential as a potential, which is shifted to a positive side, from the gate potential of the first MOSFET by the generated voltage.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
33.
POWER AMPLIFIER, AMPLIFICATION METHOD, AND TRANSMITTER
A power amplifier that includes a power amplifier core unit that is capable of performing amplitude control in discrete integer steps, and a variable attenuator. The power amplifier core unit performs the amplitude control to reproduce an envelope of an RF signal. The variable attenuator changes an attenuation amount, and controls average transmission power by using a combination of the amplitude control performed by the power amplifier core unit and the attenuation amount of the variable attenuator.
A failure analysis device is for analyzing a failure of the semiconductor device equipped with a logic circuit and a memory circuit. It has a storage device and a processor. The storage device stores fail bit data obtained by testing the memory circuit and failure diagnosis data obtained by failure diagnosis for test results of the logic circuit. The processor extracts a fail I/O value from the fail bit data, extracts the data of the memory connection port which is the connection port to the memory circuit from among the estimated failure parts included in the failure diagnosis data, and determines match/not-match between the fail I/O value and the port ID value included in the data of the memory connection port.
Systems and methods for implementing a continuous current monitor based on a low-side pilot power device is generally described. The semiconductor device includes a first circuit to filter an output signal from a power stage to generate a filtered signal that is coherent with an inductor current through an inductor in the power stage, a second circuit to generate a calibration code, and a third circuit to monitor current from a pilot device integrated in a low-side device of the power stage. The first circuit can calibrate the filtered signal to generate a calibrated signal based on the calibration code and the current from the pilot device. The second circuit can adjust the calibration code based on the calibrated signal. A combination of samples corresponding to the calibrated signal and samples corresponding to the current from the pilot device can recreate the inductor current.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
36.
DRAIN SOURCE VOLTAGE MONITOR USING SOURCE STRAY INDUCTANCE
Semiconductor devices, systems and methods are described. A system can include a controller configured to generate a control signal, a power module and a gate driver. The gate driver can be configured to drive the power device according to the control signal. The gate driver can be further configured to measure a voltage across a source wire of the power device. The gate driver can be further configured to output the voltage across the source wire to the controller. The controller can be further configured to determine, based on at least the voltage across the source wire, an overshoot voltage associated with the power device. The controller can be further configured to determine, based on at least the overshoot voltage, a peak drain-source voltage of the power device. The controller can be further configured to adjust the control signal based on the determined peak drain-source voltage.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
37.
DUAL-PROCESS OXIDE TRENCH STRUCTURE FOR SILICON CARBIDE MOSFETS
A method of forming a semiconductor device includes forming a first oxide layer having a first thickness to line a trench formed in a Silicon Carbide (SiC) substrate. The method further includes etching the first oxide layer to form a second oxide layer having the first thickness. A portion of the trench lined by the second oxide layer being less than a portion of the trench lined by the first oxide layer. The method further includes forming a third oxide layer having a second thickness on the trench and on a top surface of the second oxide layer. A combination of the second oxide layer and the third oxide layer forming an oxide region that lines different portions of the trench with different oxide thickness. The method further includes forming a gate electrode in the trench lined with the oxide region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A semiconductor device includes one or more LDMOS transistors and a semiconductor substrate having an upper surface. Each of the one or more LDMOS transistors includes: a plurality of impurity diffusion layers formed in the semiconductor substrate at the upper surface; a plurality of drain layers formed in the semiconductor substrate at the upper surface; and a plurality of insulating films formed on the upper surface. Each of the plurality of impurity diffusion layers, each of the plurality of drain layers, and each of the plurality of insulating films extend along a first direction in plan view. The plurality of impurity diffusion layers are arranged along a second direction perpendicular to the first direction in plan view while interposing a gap between two adjacent impurity diffusion layers among the plurality of impurity diffusion layers.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 62/60 - Impurity distributions or concentrations
To provide a semiconductor device circuit configured to switch glitchfree between a plurality of independent Ethernet clock sources for operating a network interface. The semiconductor device comprises a clock provision unit comprising at least a first circuit branch configured to receive a first clock signal from a first clock source associated with a first network interface, and a second circuit branch configured to receive a second clock signal from a second clock source associated with a second network interface, the second clock source having a different clock rate than the first clock source.
Systems and integrated circuits for implementing a low quiescent current low-dropout (LDO) regulator are described. The system can include a super follower circuit, a current limit circuit and an LDO core circuit. The super follower circuit is configured to supply a first current. The current limit circuit is configured to receive a system input voltage and supply a second current. The LDO core circuit is coupled to the super follower circuit and the current limit circuit. The LDO core circuit is configured to receive the first current from the super follower circuit and the second current from the current limit circuit. The LDO core circuit is configured to supply and regulate a system output voltage at a system output node. The LDO core circuit can include a feedforward capacitor connected between the system output node and a feedback node.
G05F 1/573 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
41.
FLASH SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH ERROR CORRECTION
Systems and methods for analog-to-digital conversion are described. A device can include a successive approximation register (SAR) analog-to-digital converter (ADC) and a flash ADC with a fractional bit resolution. The flash ADC can determine a digital code that encodes a voltage range of an input voltage, provide redundancy for digital error correction and output the digital code to the SAR ADC. The SAR ADC can decode the digital code to obtain a first set of bit values of a set of most significant bits (MSBs) of a digital output that is a digital representation of the input voltage, determine a second set of bit values of a set of least significant bits (LSBs) of the digital output, and generate the digital output based on the first set of bit values and the second set of bit values.
A variable gain amplifier has cascode stages formed of pairs of cross-coupled transistors. Each pair of cross-coupled transistors is provided with a transformer which keeps impedances presented to the cross coupled transistors constant with gain.
A configuration unit 20 includes: a storage unit 21 that stores RTL waveform data 21a, which shows the waveforms of multiple signals output from the RTL simulator 10 simulating the operation of the first model representing the target circuit; a determination unit 25A; and a generation unit 26. The multiple signals include a clock signal. The determination unit 25A determines, by analyzing the RTL waveform data 21a, a mask time period during which one or more analysis target signals, other than the clock signal, among the multiple signals do not fluctuate. The generation unit 26 generates an input signal to the model simulator 12, which simulates the operation of the second model obtained by converting the first model. The generation unit 26 generates a masked clock signal as an input signal by masking the mask time period in the clock signal.
substrate; a first insulating layer formed on the semiconductor substrate; first and second coils formed on the first insulating layer and located adjacent to each other in plan view; a first conductor pattern formed on the semiconductor substrate, extending in a second direction perpendicular to a first direction in plan view, and formed between the first coil and the second coil in the first direction; a second insulating layer formed on the first insulating layer so as to cover the first coil, the second coil, and the first conductor pattern; third and fourth coils formed on the second insulating layer and respectively overlapping the first and second coils in plan view. Here, the first direction is an arrangement direction of the first coil and the second coil. Also, the first conductor pattern is electrically connected to the semiconductor substrate.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A semiconductor device includes: a hole amplifier circuit; and an input terminal to which a sensor control signal generated in a period in which an image acquiring operation by an image sensor is not performed is input. In the hole amplifier circuit, a differential amplifier includes differential input nodes for input of a hole voltage from a hole sensor. One end of a plurality of capacitors is connected to the differential input nodes to determine a gain of the hole amplifier circuit. A refresh circuit causes the differential input nodes to retain correction voltages for canceling an offset voltage in accordance with a refresh signal synchronizing with a sensor control signal.
A power circuit includes one or more power supplies controlled by a controller, a sensor, and a filter. Each power supply comprises an electrical component adapted to store energy. The sensor senses a first current having a first bandwidth through the electrical component. The filter filters a signal based on the first current to obtain a filtered current having a second bandwidth that is less than the first bandwidth. The controller is configured to process the filtered current to generate an estimated current having a third bandwidth greater than the second bandwidth.
A plurality of external terminals arranged on a first bottom surface of an interposer substrate includes a plurality of power supply terminals capable of supplying a first power supply potential supplied from an external source to a first circuit. A second bottom surface includes a terminal arrangement region on which the plurality of external terminals are arranged, and a peripheral region surrounding the periphery of the terminal arrangement region. The terminal arrangement region includes a first region closest to a first edge of the interposer substrate and extending along the first edge. In the first region, only the plurality of power supply terminals among the plurality of external terminals are arranged so as to be adjacent to each other. Power consumption of the first circuit is the largest among the power consumption of each of the plurality of circuits of the semiconductor chip.
A method of manufacturing a semiconductor device includes: a step of forming a liner film so as to cover a first gate electrode and a second gate electrode; a step of forming an insulating film on the liner film; a step of exposing the liner film positioned on each of the first gate electrode and the second gate electrode by performing anisotropic dry etching to the insulating film, and forming a buried layer between the first gate electrode and the second gate electrode; a step of forming an interlayer insulating film on the buried layer; and a step of forming a contact hole in the interlayer insulating film, the buried layer and the liner film, and forming a plug electrode in the contact hole.
First and second reference current sources generate currents with opposing temperature characteristics and output a summed reference current. A ring oscillator outputs an output signal with an oscillation frequency corresponding to the reference current. The first reference current source has a first diode and first, second, and twelfth n-type transistors connected in series. A gate of the second n-type transistor is connected to a node, and a gate of the first n-type transistor is connected to a ground. The second reference current source has a third n-type transistor and a second diode in series, a fourth n-type transistor, a fifth p-type transistor, and a first resistor in series, and a sixth p-type transistor forming a current mirror with the fifth p-type transistor. Gates of the third and fourth n-type transistors are connected to an anode of the second diode. The second n-type transistor is connected to another node.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A semiconductor device includes: a semiconductor substrate having an upper surface; and wiring layers and insulating layers alternately stacked on the upper surface. The insulating layers include: a first insulating layer located between the first wiring layer located at the lowest layer among the wiring layers in cross-sectional view and the semiconductor substrate; and a second insulating layer located between a second wiring layer located at one layer above the first wiring layer among the wiring layers in cross-sectional view and the first wiring layer. The first wiring layer includes: a first coil; a first lead-out wiring electrically connected to the outermost peripheral portion of the first coil; and a second lead-out wiring electrically connected to the innermost peripheral portion of the first coil. The wiring layer located above the first wiring layer among the wiring layers in cross-sectional view includes a second coil overlapping the first coil.
A semiconductor device includes: a first semiconductor component mounted on a wiring substrate; a second semiconductor component mounted on the wiring substrate; and a lid. A height of a first upper surface of the first semiconductor component is lower than a height of a second upper surface of the second semiconductor component. A cover portion of the lid includes a portion that forms a shape protruding in a direction toward the first semiconductor component at a position facing the first semiconductor component. A third upper surface of the cover portion includes: a bottom surface that is a part of the portion; a fourth upper surface arranged at a position which is higher than the bottom surface; and a side surface connecting the bottom surface and the fourth upper surface.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
A semiconductor device includes a parameter storage unit and an image processing circuit. The image processing circuit includes a scaling calculation unit that changes a size of an input image based on an enlargement ratio or reduction ratio set in scale factor setting information. The image processing circuit further includes an optimized image area calculation unit that calculates a necessary image area size for outputting an output image based on an output size of the output image and a scale factor, and an input image area comparison unit that compares the necessary image area size with the input size of the input image, selects an image area with a smaller size out of the necessary image area size and the input size, and uses the image area selected for the image processing of the input image.
According to the present disclosure, a semiconductor device includes a first electronic circuit including a first semiconductor element group having a first threshold voltage, and a second semiconductor element group having a second threshold voltage higher than the first threshold voltage, a second electronic circuit having a same logical configuration as the first electronic circuit, and in which a ratio occupied by the second semiconductor element group among the first semiconductor element group and the second semiconductor element group is greater than that in the first electronic circuit, a power supply connection portion that connects one of the first electronic circuit and the second electronic circuit to a power supply, a storage unit that stores power supply connection information, and a control circuit that controls the power supply connection portion to connect the power supply to one of the first electronic circuit and the second electronic circuit selected based on the power supply connection information read from the storage unit.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
54.
AUTONOMOUS SYSTEM SEQUENCING OF DISCRETE REGULATORS WITH CASCADED INTERFACE SIGNAL
Systems and methods for operating one or more power regulators are described. A power regulator can include an enable pin configured to receive an enable signal for enabling generation of an output voltage. The power regulator can further include a power good pin configured to output a power good signal indicating a status of the output voltage. The power regulator can further include a circuit configured to detect a presence of a fault condition. The circuit can be further configured to, in response to detecting the fault condition, de-assert the power good pin to disable a downstream device and de-assert the enable pin to disable an upstream device.
H02H 7/12 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for convertersEmergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for rectifiers for static converters or rectifiers
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
55.
FRACTIONAL DIVIDER CALIBRATION WITH DUAL DIGITAL CONTROL DELAY CIRCUITS
Systems and methods for calibrating a fractional divider are described. A system can include a divider and a circuit. The divider can divide an input clock signal to generate an integer output divider (IOD) signal. The circuit can include a first digital control delay (DCD) circuit configured to delay the IOD signal to generate a first delayed IOD signal. The circuit can further include a second DCD circuit configured to delay the first delayed IOD signal to generate a second delayed IOD signal. The circuit can further include an edge sampler configured to compare an edge of the second delayed IOD signal with an edge of the input clock signal. The circuit can further include a controller configured to calibrate the first DCD circuit based on a result of the comparison between the edge of the second delayed IOD signal with the edge of the input clock signal.
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
H03K 23/68 - Pulse counters comprising counting chainsFrequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer
An inductive sensor assembly is provided. The inductive sensor assembly includes a coil assembly and a movable conductive target. The coil assembly is discontinuously excited by a sequence of signal pulses. The coil assembly includes three coils in a predefined arrangement coupled among three terminals. The movable conductive target at least partly covers the coils during its movement. The inductive sensor assembly is configured for measuring respective currents of the coil assembly at a predetermined time synchronized with excitation of the coil assembly at respective terminals, for determining a displacement of the target.
G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapersMeasuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes
G01B 7/00 - Measuring arrangements characterised by the use of electric or magnetic techniques
57.
SILICON CARBIDE PLANAR MOSFET WITH HYBRID LINEAR AND HEXAGONAL CHANNEL ARCHITECTURE
A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type having an upper and bottom surface. A drift region of the first conductivity type is located on the upper surface. Above the drift region, a channel region of a second conductivity type, opposite to the first conductivity type, is located featuring a hybrid configuration. The hybrid configuration includes a first channel segment of a first channel geometry located between and directly connected to two second channel segments of a second channel geometry. A source region of the first conductivity type is located adjacent to the channel region. A first doped semiconductor region of the second conductivity type, featuring a third geometry, is placed above the drift region and adjacent to the first channel segment. Finally, a gate electrode is located above the drift region via a gate oxide.
H10D 30/83 - FETs having PN junction gate electrodes
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
58.
METHOD, A PROGRAM, AND A COMPUTER FOR TIMING ADJUSTMENT OF A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
The timing adjustment method, program, and computer for a semiconductor integrated circuit are provided to suppress the increase in the size of layout data. The timing adjustment method for a semiconductor integrated circuit includes adding one or more dummy cells each having a plurality of dummy metals to layout data of the semiconductor integrated circuit, selecting a dummy cell to be connected to a signal wiring when the delay time of the signal wiring included in the layout data indicates a hold error, and connecting one or more of the plurality of dummy metals included in the dummy cell that has been selected in the selecting to the signal wiring.
To achieve desired performance, a data reception device comprises receiving unit and an adaptive equalization processing unit. The receiving unit generates a received signal based on a first wireless signal received by a first antenna and a second wireless signal received by a second antenna. The adaptive equalization processing unit performs adaptive equalization processing to asymptotically match the received signal based on the first wireless signal and the second wireless signal generated by the receiving unit to a predetermined training signal.
H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
60.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An interlayer insulating film is formed on an upper surface of a semiconductor substrate. A plurality of wirings is formed on the interlayer insulating film. The interlayer insulating film has a BPSG film and a PSG film formed on the BPSG film. A gettering layer containing phosphorus is formed in the PSG film. A concentration of phosphorus in the gettering layer is higher than a concentration of phosphorus in the PSG film.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
A semiconductor wafer includes a semiconductor substrate, a plurality of chip regions, a scribe region, and an interlayer insulating film. A TEG is formed in the scribe region. The TEG includes a first active region formed in the semiconductor substrate, a second active region formed in the semiconductor substrate, and adjacent to the first active region in a first direction, a gate electrode formed on the first active region and the second active region, and extending in the first direction, an insulating region adjacent to the second active region in a second direction orthogonal to the first direction, and formed in the semiconductor substrate so as not to overlap with the first gate electrode in plan view, a plug formed in the interlayer insulating film and connected to the first active region, and a dummy plug formed in the interlayer insulating film and connected to the insulating region.
It can blow an electric fuse with a small blowing current. A metal film is connected to a first wiring through a first via, and is connected to a second wiring through a second via. A disconnect transistor is coupled to the second wiring. An area of a contact surface, which is in contact with the metal film, of the first via is smaller than an area of a contact surface, which is in contact with the metal film, of the second via.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
63.
CAMERA INSPECTION SYSTEM AND CAMERA INSPECTION METHOD
The camera inspection system includes an external environment changer that receives an inspection signal and changes the imaging illumination of a camera fixed to a vehicle, thereby changing the brightness within the frame image captured by the camera. It also includes an average brightness calculator that calculates the average brightness within the image for each frame image captured within a predetermined period by the camera, and an inspector that compares the inspection signal with the average brightness within the image for each frame image and generates a fault detection signal indicating image fixation when the timing of the change in the inspection signal does not match the change in the average brightness within the image.
A semiconductor device includes: a plurality of pads; a plurality of redistribution wirings connected to the plurality of pads; a terminal provided on a land portion of each of the plurality of redistribution wirings; and a conductive film connected to each of the terminal and the land portion. The plurality of redistribution wirings includes: a first redistribution wiring having a first land portion; and a second redistribution wiring having a second wiring portion. A planar shape of the conductive film is circular. A planar shape of the first land portion is non-circular. In plan view, the first land portion is arranged adjacent to the second wiring portion which is extending in the Y direction. In plan view, the first land portion has a first side which is linearly extending along the second wiring portion.
To provide a semiconductor device and its manufacturing method capable of designing the intended delay with high precision using fewer steps. The manufacturing method of the semiconductor device disclosed herein arranges multiple circuits on a plane and connects wiring to each, comprising: a placement step of arranging a digital circuit that operates based on timing signals and a delay circuit configured with multiple delay paths having different input/output delay amounts, where one of the multiple delay paths can be selected by a selection signal; a wiring step of connecting the output of the delay circuit so that it becomes the timing signal of the digital circuit; and a delay adjustment step of selecting one of the multiple delay paths by connecting a predetermined voltage as the selection signal, and selecting the delay amount so that the input/output timing of the digital circuit meets predetermined conditions.
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
A drive circuit can calculate an optimal phase adjustment amount by passing a current through an external load. The drive circuit includes a control circuit that outputs a first AC signal and a second AC signal from an AC signal source, and a reference voltage generation circuit that has a differential amplifier generating a first AC voltage from the first AC signal and outputs the first AC voltage to one end of an external load. It also includes a voltage-current conversion circuit that supplies an AC current to the external load from the second AC signal, and a comparator connected across both ends of the external load. The comparator compares the first AC voltage at one end of the external load with the second AC voltage at the other end of the external load and changes the output voltage when the first and second AC voltages are inverted.
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
Apparatuses, devices, and systems for operating a voltage converter to reduce current spike are described. A controller can measure a feedback of a current of an alternating current (AC) voltage of a switching circuit. The controller can measure a direct current (DC) voltage of the switching circuit. The controller can operate a current control loop using the feedback of the current to determine a target voltage. The controller can determine a duty cycle of the switching circuit based on the target voltage and the DC voltage. The controller can operate the switching circuit under the determined duty cycle to control the current of the AC voltage.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
68.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A gate electrode is formed on a semiconductor substrate via a second gate insulating film, and a floating gate electrode is formed on the semiconductor substrate via a first gate insulating film. A second sidewall spacer is formed on a side surface of the gate electrode, and a first sidewall spacer is formed on a side surface of the floating gate electrode. A first insulating film made of silicon oxide covers the floating gate electrode, and a second insulating film made of silicon nitride covers the gate electrode, the floating gate electrode, the second sidewall spacer, the first sidewall spacer, and the first insulating film. The first insulating film is interposed between an upper surface of the floating gate electrode and the second insulating film. A density of the upper portion of the first insulating film BL is larger than that of the lower portion of the first insulating film.
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
A semiconductor device includes an n-type offset drain region, an n-type semiconductor region, and a gate electrode. The n-type semiconductor region is arranged apart from the n-type offset drain region.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A semiconductor device, a control method for the semiconductor device, and a program for efficiently storing values in memory are provided. The semiconductor device 100 includes a data acquisition unit 1, a determination unit 2, and memory 3. The data acquisition unit 1 acquires a data signal SIG input from the outside at a predetermined cycle. Determination unit 2 stores a threshold. Determination unit 2 performs a threshold determination by comparing the measurement value M indicated by the data signal SIG acquired by the data acquisition unit 1 with the threshold. If, in the threshold determination, the measurement value M is determined to be an abnormal value that does not meet the predetermined criteria, the measurement value M is stored in memory 3.
A semiconductor device includes a timer control circuit (timer) and an AD converter (ADC), and generates a PWM signal by using a periodic signal of the timer on the basis of an ADC output. After receiving an AD conversion start request signal (ADR signal), the ADC starts AD conversion in synchronization with a latest AD synchronization signal. The timer outputs a timer phase signal that is a basis for starting generation of a periodic signal and the ADR signal when a phase-locked loop counter value matches a value of a timer phase register, outputs an AD synchronization phase signal that is a basis for starting generation of the AD synchronization signal when the counter value matches the value of an AD synchronization phase register, and controls a phase difference between the ADR signal and the AD synchronization signal to be constant regardless of activation timing of the device.
H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
H02P 6/08 - Arrangements for controlling the speed or torque of a single motor
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
A semiconductor device includes an n-type semiconductor substrate, a seal ring wiring formed in an annular shape so as to surround a first region and a second region of the semiconductor substrate in plan view, and a p-type impurity region formed in the semiconductor substrate. The impurity region is provided between the first region and the second region so as to extend to a position overlapping, in plan view, with the seal ring wiring. A ground potential is supplied to the impurity region.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
Described herein is a method of determining visibility of predefined content in a display displaying dynamic background content. The method may comprise: after determining that the predefined content is to be overlayered on the dynamic background content for rendering in the display, obtaining at least one image representative of visual information displayed in the display; and performing a computer vision-based process based on the obtained at least one image to determine the visibility of the predefined content in the display.
G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
G06T 19/00 - Manipulating 3D models or images for computer graphics
G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersectionsConnectivity analysis, e.g. of connected components
G06V 10/56 - Extraction of image or video features relating to colour
74.
ANALOGUE TO DIGITAL CONVERTER AND METHOD FOR CONTROLLING THE SAME
The analogue to digital converter outputs a conversion value obtained by performing analogue to digital conversion on an input signal. The non-volatile memory stores a plurality of correction values. The correction circuit selects, in response to a status affecting an offset in the conversion value of the analogue to digital converter, a correction value corresponding to the status from among the plurality of correction values as a selected correction value, and outputs an output value where the offset in the conversion value is corrected based on the selected correction value.
A differential amplification system for receiving first and second input signals, and for generating first and second differential output signals, the differential amplification system comprising a differential amplifier configured to receive the first input signal and the second input signal, provide a first output current at a first current channel, and provide a second output current at a second current channel, a cascode stage configured to receive the first and second output currents, and generate the first and second differential output signals, a detector configured to detect when the first output current flowing through the first current channel meets a first condition, and/or detect when the second output current flowing through the second current channel meets a second condition, wherein a current sink stage configured to redirect at least a portion of the first output current and at least a portion of the second output current away from the cascode stage when the first condition is met by the first output current, and/or redirect at least a portion of the first output current and at least a portion of the second output current away from the cascode stage when the second condition is met by the second output current, wherein the first condition is met by the first output current when the first output current falls below a first threshold current value and/or the first output current rises above the first threshold current value, and the second condition is met by the second output current when the second output current falls below a second threshold current value and/or the second output current rises above the second threshold current value.
To suppress false detection of fault injection, the fault injection detector detects the fault injection. The encryption module generates the first encrypted data by encrypting the plaintext data. The controller verifies the encrypted data generated by the encryption module and determines whether the encrypted data is valid if fault injection is detected in the fault injection detector.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type having an upper surface and a bottom surface. The semiconductor structure further includes a drift region of the first conductivity type located on the upper surface of the semiconductor substrate. The upper surface having a transistor region and peripheral regions located at each corner of the transistor region. The transistor region further includes a channel region of a second conductivity type, opposite to the first conductivity type, located above the drift region and positioned on a center portion of the transistor region, a source region of the first conductivity type adjacent to the channel region, and a gate electrode located above the drift region via a gate oxide, the gate electrode surrounds the source region. Each of the peripheral regions includes a first semiconductor region of the second conductivity type formed above the drift region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
78.
METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR WITH DOUBLE SEQUENTIAL TRENCH STRUCTURE
A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type. The semiconductor structure further includes a drift layer of the first conductivity type located above the semiconductor substrate, a channel layer of a second conductivity type, opposite to the first conductivity type, located above the drift layer, and a source region of the first conductivity type located above the channel layer. The semiconductor structure further includes a stepped shaped trench structure that extends through the source region and the channel layer until a top portion of the drift layer, a gate electrode located within the trench structure and surrounded by a gate insulating film, and a shield region of the second conductivity type covering a bottom of the trench structure such that the shield region extends laterally along the trench structure to a trench corner.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
Each latch cell in a latch cell array is made of 12 MOS transistors including a first CMOS switch transferring write data and a second CMOS switch transferring read data. A test for rewriting a storage node on a write bit line side in each latch cell from a first logic level to a second logic level in a state in which the first and second CMOS switches are respectively controlled to be on in overlapping time periods is assumed. In this case, a disturb test circuit precharges a read bit line to the second logic level before the second CMOS switch is controlled to be on.
G11C 29/50 - Marginal testing, e.g. race, voltage or current testing
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Systems and methods for implementing multi-phase TLVR secondary voltage stress reduction are generally described. A semiconductor device can include a controller configured to map a plurality of pulse width modulation (PWM) signals in a default order as a first sequence to operate a trans-inductor voltage regulator (TLVR). The TLVR can include a primary circuit and a secondary circuit, and the primary circuit can include a plurality of phases. The semiconductor device can further include a circuit configured to map the plurality of PWM signals to a second sequence different from the first sequence. The controller can be configured to output the plurality of PWM signals in the second sequence to operate the TLVR.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
Systems and methods for adaptive voltage regulation with multiple ports are described. The device can include a first voltage regulator coupled to a first port and can regulate voltages between the first port and a battery. The device can further include a second voltage regulator coupled to a second port and can regulate voltages between the second port and the battery. The device can also include a bypass switch coupled to the first voltage regulator, the first port, the second voltage regulator and the second port. The device can further include an integrated circuit configured to operate the bypass switch. When the bypass switch can be turned on, the first voltage regulator can be further configured to regulate voltages between the second port and the battery. The second voltage regulator can be further configured to regulate voltages between the first port and the battery.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
82.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
To provide a semiconductor device capable of preventing a contact barrier metal film from peeling off from the trench gate lead-out electrode. In the gate wiring lead-out region MGR defined on a semiconductor substrate, a convex portion is formed on the trench gate lead-out electrode TGI, extending towards a gate lead-out contact member. The convex portion is formed by a natural oxidation film and a polysilicon film PSF. The gate lead-out contact member is formed to cover the convex portion by interposing the contact barrier metal film.
A semiconductor device includes a power device, a booster circuit, and an overcurrent detection circuit. The overcurrent detection circuit includes a sense circuit that outputs a voltage corresponding to a current flowing in the power device, and a detection current generation circuit that generates a detection current depending on an output from the sense circuit. The detection current generation circuit includes a first control circuit that operates with a boosted voltage from the booster circuit and controls a first current circuit depending on the voltage output from the sense circuit, and a second control circuit that operates with a power source voltage and controls a second current circuit depending on the voltage output from the sense circuit.
In an embodiment, a semiconductor device is disclosed that includes a buffer circuit that is configured to selectively output a charge signal to an inductor-capacitor node of a power driver to charge the inductor-capacitor node to a predetermined voltage level and an amplifier circuit that is configured to monitor a voltage differential across a capacitor of the inductor-capacitor node of the power driver. The amplifier circuit is configured to output a positive side signal and a negative side signal. The semiconductor device further includes an output that is configured to provide at least one signal based on the positive side signal and negative side signal to an analog-to-digital converter for measurement by a controller.
H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
H02J 50/60 - Circuit arrangements or systems for wireless supply or distribution of electric power responsive to the presence of foreign objects, e.g. detection of living beings
Systems and methods for fault detection in heads-up display are described. A processor can receive an image signal encoding image data of a virtual image to be projected on a surface of a windshield of a vehicle. The processor can select a group of pixels corresponding to a region of the virtual image. The processor can determine at least one characteristic for each pixel in the group of pixels. The processor can determine one or more group attributes representative of the group of pixels based on the at least one characteristic for each pixel in the group of pixels. The processor can determine that the one or more group attributes fails to satisfy a condition associated with a set of predefined threshold group attributes. The processor can, in response to determining that the one or more group attributes fails to satisfy the condition, generate a fault detection signal.
A method of manufacturing a semiconductor device includes: forming a diffusion source on a lower surface of a semiconductor substrate to diffuse conductive impurities into the semiconductor substrate, and irradiating the lower surface of the semiconductor substrate with laser light through the diffusion source.
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
A semiconductor device has a die pad, a semiconductor chip mounted on the die pad via a conductive material, and a lead terminal electrically connected to a source electrode of the semiconductor chip via a bonding member. Here, the source electrode includes a detection point for detecting a value of a current flowing in a power transistor provided in the semiconductor chip, and a bonding portion to which the bonding member is bonded. Then, a sense transistor provided in the semiconductor chip, the detection point, and the bonding portion do not overlap with a first region of the die pad, but overlap with a second region of the die pad. In addition, a thickness of the conductive material provided in the second region is larger than a thickness of the conductive material provided in the first region.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
88.
SEMICONDUCTOR DEVICE AND CERTIFICATION METHOD THEREOF
Improve the tamper resistance against physical attacks on semiconductor devices. The semiconductor device according to the present disclosure includes a transition circuit that transitions the state at a predetermined Hamming distance based on the comparison result between the certification target value and the reference value, and a determination circuit that determines the validity of the certification by determining whether the Hamming distance between the state before the transition and the state after the transition matches the predetermined Hamming distance.
The time required for processing measurement data is reduced. The data processing device, according to the present disclosure, acquires reception intensity data representing a reception intensity of signals reflected at measurement points located at distances from the target vehicle for each of multiple distances. It identifies a short-range measurement point that is within a first predetermined distance from the target vehicle. If the short-range measurement point meets predetermined data reduction conditions, it specifies the data corresponding to the distance within a second predetermined distance from the target vehicle, among data indicated in the reception intensity data, as the data to be analyzed.
A semiconductor device is provided, the semiconductor device including: a RAM which stores an encryption key; a secure CPU which is permitted to access the encryption key stored in the RAM; and a first non-secure CPU which is connected to the RAM via a key access protect module and has a first user ID. The key access protect module stores user ID information of a non-secure CPU which is permitted to access the encryption key stored in the RAM, in association with the encryption key. When the first non-secure CPU tries to access the encryption key stored in the RAM, if the stored user ID information and the first user ID match each other, the key access protect module permits the first non-secure CPU to access the encryption key.
A semiconductor device capable of reducing power consumption is provided. The nMOS transistor MNo inputs the external power supply voltage Vcc into the drain and outputs the internal power supply voltage Vdd from the source. The charge pump circuit CP inputs the external power supply voltage Vcc and generates a boosted power supply voltage Vcp higher than it. The reference voltage generation circuit VREFG1 uses a replica nMOS transistor MNr formed by the same manufacturing process as the nMOS transistor MNo to generate a first reference voltage Vref1 reflecting the characteristic variations of the nMOS transistor MNo. The voltage regulator circuit VREGb applies a gate voltage VGn determined based on the first reference voltage Vref1 to the gate of the nMOS transistor MNo.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
92.
METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR WITH INTEGRATED BURIED OXIDE AND P-SHIELD LAYERS
A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type, having an upper surface and a bottom surface. A drift layer of the first conductivity type is positioned on the upper surface of the semiconductor substrate. A pair of source regions of the first conductivity type is disposed on the drift layer. A first semiconductor region of the first conductivity type disposed on a center portion of the drift layer is sandwiched between the pair of source regions. Laterally abutting a bottom portion of the first semiconductor region is a pair of second semiconductor regions of a second conductivity type opposite to the first conductivity. Embedded within the first semiconductor region is a third semiconductor region of the second conductivity type. An oxide layer is located, at least partially, within the first semiconductor region, extending above an upper surface of the first semiconductor region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A discharge transistor is formed on a semiconductor substrate, and controls a power transistor to the OFF state by short-circuiting a gate of the power transistor and a reference node when being controlled to the ON state. A reverse current detection circuit detects generation of a reverse current from a power output terminal toward a power supply terminal, and asserts a reverse current detection signal in a period in which a reverse current is generated. A switch control circuit controls a first switch to the ON state and a second switch to the OFF state during the negation period of the reverse current detection signal, and controls the first switch to the OFF state and the second switch to the ON state during the assertion period of the reverse current detection signal.
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
94.
SINGLE PIN IMPEDANCE MEASUREMENT SYSTEM AND PHASE OFFSET COMPENSATION FOR A SINGLE PIN IMPEDANCE MEASUREMENT SYSTEM
An impedance measurement system including: a signal generator including a memory and arranged to generate a digital test signal and at least one digital demodulation signal based on the memory, wherein the digital test signal has a first frequency and the at least one digital demodulation signal has the first frequency; a single pin for providing to a Device Under Test (DUT), an analogue test signal based on the digital test signal and measuring, in response to providing the analogue test signal to the DUT, an analogue input signal; and a demodulator configured to obtain: a first filtered digital signal based on the input signal; and the at least one digital demodulation signal to produce at least one digital demodulated signal indicative of the impedance.
A System of a wearable device powered by a battery and built to emit a digital pulse signal and a static device built to process a multilateration of the wearable device, wherein the static device comprises:
at least two receivers, both built to receive the digital pulse signal with a time difference caused by their individual distance to the wearable device;
a multilateration stage built to process a multilateration of the wearable device based on the time difference between the two received digital pulse signals;
a static device communication stage built to communicate commands and/or data with the wearable device,
and wherein the wearable device comprises:
a transmitter stage built to transmit the digital pulse signal composed of several ranging rounds, each with a sequence of digital pulses, and sleep mode periods without digital pulses between the ranging rounds,
which wearable device comprises:
a measurement stage built to measure a current provided by the battery of the wearable device to a capacitor of the wearable device, which capacitor is dimensioned that its capacitor load of the fully charged capacitor powers the wearable device during one ranging round;
a determination stage built to determine a charge time needed to fully charge the capacitor until the end of the sleep mode period based on the capacitor size and the measured current;
a wearable device communication stage built to communicate a request for a minimum extended time slot duration with the static device communication stage to fully charge the capacitor with the measured current until the end of each sleep mode period, if the determined charge time needed is longer than the duration of the sleep mode period between ranging rounds.
A semiconductor device includes a plurality of data lines, a plurality of memory cells connected to the plurality of data lines, and a plurality of FF circuits corresponding to the plurality of data lines. The semiconductor device further includes a memory array circuit including an input circuit that is supplied with a high voltage during writing and writes data to the memory cell connected to the corresponding data line according to data held in the FF circuit. The semiconductor device further includes a memory controller that supplies a data string having a number of pieces of data corresponding to a number of FF circuits to the input circuit and causes the FF circuit to hold the data string. The memory controller includes a pop counter circuit that counts a number of pieces of inverted data included in the data string, and the memory controller divides the FF circuit into a plurality of regions based on counting by the pop counter circuit so that the number of FF circuits that store inverted data is equal to or less than a predetermined number. The input circuit is controlled to select the plurality of regions at different timings and simultaneously write data held in the FF circuits arranged in the selected regions.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
97.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A gate electrode is formed in a trench. An insulating film is formed on the gate electrode so as to protrude from an upper surface of a semiconductor substrate. A sidewall spacer is formed on a side surface of the insulating film and on the upper surface of the semiconductor substrate. A hole is formed in a portion of the semiconductor substrate exposed from the insulating film and the sidewall spacer. A barrier metal film is formed in the hole. A second opening width of the hole at a second position, corresponding to a position of a junction surface between a body region and a source region, is larger than a first opening width of the hole at a first position, corresponding to a position of the upper surface of the semiconductor substrate. The barrier metal film includes a silicide film and a metal film.
A steering device for a vehicle. The device includes one or more sensors configured to detect a plurality of hand motions from an operator of the vehicle and one or more circuits coupled to the one or more sensors. The one or more circuits are configured to adjust one or more elements of the vehicle based on a hand motion detected such that the operator of the vehicle can adjust the operation of the vehicle.
A semiconductor structure includes a semiconductor substrate of a first conductivity type. The semiconductor substrate can have an upper surface and a bottom surface. The semiconductor substrate can be made of polycrystalline silicon carbide. The semiconductor structure can further include a drift region of the first conductivity type located on the upper surface of the semiconductor substrate. The semiconductor structure can further include a first region of the upper surface of the semiconductor substrate including a formation region of a transistor, and a second region of the upper surface of the semiconductor substrate, adjacent to the first region, including a formation region of a Schottky barrier diode.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A method for controlling a semiconductor device capable of ensuring robust security is provided. The method is implemented by a semiconductor device comprising an encryption key protection circuit, a processor, and a memory. It includes instructing, by the processor, the encryption key protection circuit to generate an encryption key pair, generating, by the encryption key protection circuit, the encryption key pair internally according to the instruction, encrypting, by the encryption key protection circuit, the generated encryption key pair using a common key, storing, by the processor, the encrypted encryption key pair output from the encryption key protection circuit into the memory, receiving, by the encryption key protection circuit, the encrypted encryption key pair stored in the memory when utilizing the encryption key pair, and decrypting, by the encryption key protection circuit, the encrypted encryption key pair received from the memory using the common key.
