A protection cell has a first MISFET group composed of a plurality of first MISFETs and a second MISFET group composed of a plurality of second MISFETs. The first MISFET group and the second MISFET group are provided separately from each other. The first MISFET group is electrically connected to a first power wiring group and a first ground wiring group so as to electrically short-circuit them. The second MISFET group is electrically connected to a second power wiring group and a first ground wiring group so as to electrically short-circuit them. The first MISFET group overlaps with a part of the first power wiring group and a part of the first ground wiring group in a plan view.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
H01L 23/528 - Layout of the interconnection structure
2.
PROGRAM, IMAGE PROCESSING METHOD, AND IMAGE PROCESSING DEVICE
An image processing device according to an embodiment includes: an image division unit dividing input image data into first division image data and second division image data having a predetermined overlap region with the first division image data according to a size of a kernel used for image processing; a reuse data determination unit determining first reuse data reused in performing the image processing to the second division image data among the first division image data; and a memory management unit, in a memory, storing first processed data of a first division image obtained by performing the image processing to the first division image data, in a region other than a region storing the first reuse data, and allocates a region storing the second division image data so as to be adjacent to the region storing the first reuse data.
A semiconductor device is provided, which includes a boundary member between an auxiliary element and a main surface of a semiconductor substrate to reduce the step of a protective film covering the auxiliary element. A semiconductor device is provided, comprising a semiconductor substrate having a first main surface having a first region, a second region, and a third region located between the first region and the second region in plan view, a transistor formed in the first region, an auxiliary element formed in the second region, a boundary member formed in the third region, and a protective film covering the auxiliary element and the boundary member. The height from the first main surface to the upper surface of the boundary member is lower than the height from the first main surface to the upper surface of the auxiliary element.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A semiconductor device is provided, the semiconductor device including: a first electrode; an N-type semiconductor layer arranged on the first electrode; a P-type semiconductor layer arranged on the N-type semiconductor layer; a first insulating layer surrounding and partitioning a first region in plan view, arranged on the P-type semiconductor layer; a second electrode arranged on the P-type semiconductor layer; a second insulating layer arranged on the first insulating layer surrounding and partitioning the first region in plan view on the second electrode; a metal plating layer arranged on the second electrode; a solder layer arranged on the metal plating layer; and a clip arranged on the solder layer, and the first region is a region where the clip is joined with the metal plating layer.
A first stacked structure and a first sidewall spacer are formed in a first region. A second stacked structure including a metal film is formed in a second region. In the first region, an epitaxial layer is formed on a semiconductor layer. The first sidewall spacer is removed. A first silicon oxide film is formed on a surface of the epitaxial layer exposed from a first insulating film. A thickness of each of the first insulating film and the first silicon oxide film is reduced by performing a cleaning treatment using an aqueous solution containing ammonia and an activator on each of the first insulating film and the first silicon oxide film. An extension region is formed in each of the semiconductor layer and the epitaxial layer by performing an ion implantation so as to pass through each of the first insulating film and the first silicon oxide film.
A semiconductor device package is disclosed that includes an address voltage supply pin connection, an address voltage output pin connection, a first power driver having a first address pin connection and a second power driver having a second address pin connection. The first address pin connection is connected to the address voltage supply pin connection via a resistor. The first power driver is configured to generate a first indication of a first address based on a voltage on the first address pin connection that is obtainable by a controller to determine the first address. The second address pin connection is connected to the first address pin connection and the address voltage output pin connection. The second power driver is configured to generate a second indication of a second address based on a voltage on the second address pin connection that is obtainable by the controller to determine the second address.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A radar system comprising a plurality of receivers, each receiver having its clock generator generating a clock signal with a sampling frequency for sampling a radar signal received on one or more receiving antennas and a plurality of delay estimation and compensation (DEC) blocks implemented within the corresponding plurality of receivers, wherein, each DEC block is configured to synchronise the clock generator of one receiver with every other receiver. A method in a radar comprising, generating a sync pulse in a first receiver in the plurality of receives, measuring a delay between the sync pulse and the clock signal in the first receiver, transmitting the sync pulse to other receivers in the plurality of receivers measuring a second delay between the sync pulse and the clock pulse in the other receivers and changing the frequency of the clock generator in the other receivers from the sampling frequency to first frequency for a first time duration.
A regulator includes a reference potential generation circuit that generates a reference potential serving as a reference for an intermediate potential and an intermediate potential lower than the intermediate potential, a differential amplifier to which the intermediate potential is supplied as a low potential side power supply and which amplifies a difference voltage between a feedback potential corresponding to the intermediate potential and the reference potential, and a transistor having a gate to which the amplified difference voltage is input, a drain connected to a ground potential via a constant current source or a resistor, and a source that generates the intermediate potential.
G05F 1/573 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
A communication device includes a communication control unit. The communication control unit includes a plurality of protocol processing units and a plurality of received data storage areas. A received message that is a CAN message received by the communication device is input into the plurality of protocol processing units. In a case where the destination of the received message is a virtual machine corresponding to the protocol processing unit itself, each protocol processing unit stores the payload of the received message in the received data storage area accessible from the destination virtual machine.
A method of transporting a semiconductor device includes: a step of placing a semiconductor device in a pocket portion, a step of attaching the cover tape to the carrier tape so as to cover the semiconductor device placed in the pocket portion, and a step of transporting the carrier tape containing the semiconductor device. Here, the pocket portion includes: a plurality of corner portions where a step section is formed, and a plurality of side portions located between these corner portions and having a first protruding portion and a second protruding portion formed thereon. Also, a width of a tip portion of the second protruding portion is smaller than a width of the tip portion of the first protruding portion. Furthermore, a protrusion amount of the second protruding portion from the side portion is larger than a protrusion amount of the first protruding portion from the side portion.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
11.
LAMINATE SUBSTRATE-BASED DIFFERENTIAL PRESSURE SENSOR PACKAGE COMBINING AIR CAVITY CHANNEL SUBSTRATE, OVERMOLD, AND LID WITH TWO CHIMNEYS
The sensor device includes a substrate having upper and lower surfaces with a channel formed therebetween. First and second port holes are formed through the upper surface to the channel. The sensor device also includes an application-specific integrated circuit (ASIC) die mounted on the upper surface so as not to cover the first and second port holes. The sensor device further includes an overmolding formed on the upper surface that is molded over the ASIC die and forms first and second cavities surrounding the first and second port holes, respectively. The sensor device also includes a transducer electrically connected with the ASIC die and mounted within the first cavity on the upper surface so as to cover the first port hole. The sensor device further includes a lid attached to the overmolding having first and second chimneys.
G01L 13/02 - Devices or apparatus for measuring differences of two or more fluid pressure values using elastically-deformable members or pistons as sensing elements
G01L 19/00 - Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
12.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a first resistor element. The first resistor element includes a first resistor, and a second resistor electrically connected in series to the first resistor. The first resistor and the second resistor are each made of a first material. One of a temperature coefficient of an electrical resistance value of the first resistor and a temperature coefficient of an electrical resistance value of the second resistor is a positive value. The other of the temperature coefficient of the electrical resistance value of the first resistor and the temperature coefficient of the electrical resistance value of the second resistor is a negative value.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/373 - Cooling facilitated by selection of materials for the device
A semiconductor device includes a variable-resistance memory cell array, a sense amplifier electrically connected to the variable-resistance memory cell array, and a clamp voltage generation circuit electrically connected to the sense amplifier. The sense amplifier includes an amplification unit that amplifies a voltage at a sense node, a first clamp circuit having first and second NMOS transistors whose gate terminals are electrically connected, a second clamp circuit having third and fourth NMOS transistors whose gate terminals are electrically connected, a fifth NMOS transistor electrically connected to the variable-resistance memory cell array, a reference resistor, and a sixth NMOS transistor electrically connected to the reference resistor.
A semiconductor device includes a variable-resistance memory cell array, a sense amplifier electrically connected to the variable-resistance memory cell array, and a clamp voltage generation circuit electrically connected to the sense amplifier. The sense amplifier includes an amplification unit that amplifies a voltage at a sense node, a first clamp circuit having first and second NMOS transistors whose gate terminals are electrically connected, a second clamp circuit having third and fourth NMOS transistors whose gate terminals are electrically connected, a fifth NMOS transistor electrically connected to the variable-resistance memory cell array, a reference resistor, and a sixth NMOS transistor electrically connected to the reference resistor.
The first and third NMOS transistors are connected in series between the sense node and the fifth NMOS transistor, and the second and fourth NMOS transistors are connected in series between the sense node and the sixth NMOS transistor.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
A semiconductor device includes: a first electric-current generator circuit generating a first electric current having a positive temperature coefficient and not having dependency on a first power-supply voltage; a second electric-current generator circuit generating a second electric current having a negative temperature coefficient and not having dependency on the first power-supply voltage; and a third electric-current generator circuit generating a third electric current neither having dependency on the temperature nor the first power-supply voltage, based on the first electric current and the second electric current.
A data transfer device that divides and transfers the transfer target data in a burst manner from a transmission-side device to a reception-side device includes a storage device and a control device that controls the storage device to store one piece of the input transfer target data, controls the storage device so that data transfer is performed at a set burst length as a data length of divided data when the one piece of the data is divided by a division number until a last part of the data is sensed, and when the last part of the data is sensed, controls the storage device to adjust the burst length so that a data length of the data coincides with a total of data lengths of data to be transferred, and to transfer the data at the adjusted burst length.
Improve the reliability of semiconductor device. The protective cell ESD1a comprises a group of MISFETS 1QA constituted by a plurality of n-type MISFETs 1Q, and a pair of MISFET groups 2QA constituted by a plurality of p-type MISFETs 2Q. The group of MISFETs 1QA and the pair of MISFET groups 2QA are electrically connected to the power wiring and the ground wiring, respectively, to electrically short-circuit them. The pair of MISFET groups 2QA outputs a signal to turn on a plurality of MISFETs 10 to each gate electrode of the plurality of MISFETs 1Q. The group of MISFETs 1QA is provided between the pair of MISFET groups 2QA.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A resist pattern having an opening portion that exposes a part of a conductive film located on a gate insulating film is formed on the conductive film. Next, an anisotropic etching treatment is performed using the resist pattern as a mask to selectively remove the conductive film exposed from the resist pattern and to form a gate pattern and a dummy gate pattern from the remaining conductive film. Next, an oblique ion implantation is performed using the resist pattern as a mask to form a p-type body region in a semiconductor substrate.
The method for transporting the semiconductor wafer involves the steps of preparing the non-contact chuck provided with an optical sensor and the semiconductor wafer having a first main surface, positioning the non-contact chuck so that the optical sensor and the first main surface face each other with a predetermined interval therebetween, measuring a first intensity, which is the intensity of a reflected light from the first main surface, by illuminating the first main surface with a light from the optical sensor before bringing the non-contact chuck close to the first main surface, bringing the non-contact chuck close to the first main surface and maintaining the semiconductor wafer in a non-contact state by blowing gas to the first main surface from the non-contact chuck, and disengaging the non-contact chuck from the semiconductor wafer by moving the non-contact chuck away from the first main surface.
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
A debugging system includes first and second semiconductor devices and a log analysis apparatus. Each of the first and second semiconductor devices executes software to generate a trace log, a first execution log, and a second execution log. The first semiconductor device transfers the trace log and the first execution log to the log analysis apparatus. The second semiconductor device transfers the trace log and the second execution log to the log analysis apparatus. The log analysis apparatus identifies the processing order of the first execution log and the second execution log based on time stamps given to the trace logs, the first execution log, and the second execution log transferred from the first and second semiconductor devices, and generates analysis data by combining the first and second execution logs according to the identified processing order. The analysis data is used for analyzing a cause of an error.
A semiconductor device includes: a field plate electrode formed in an inner portion of a trench through a first insulating film, the trench being formed in a semiconductor substrate; and a gate electrode formed over the field plate electrode through a second insulating film. The first insulating film includes a stacked film made of a first oxide film in contact with the semiconductor substrate and a second oxide film in contact with the field plate electrode, and an inclination of an upper surface of the first insulating film changes at a boundary between the first oxide film and the second oxide film.
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
21.
TWO-STAGE BATTERY CHARGER WITH MIDPOINT VOLTAGE REGULATION
Apparatuses, devices, and methods for operating a battery charger are described. A semiconductor device can include a controller that can monitor at least one battery parameter of a battery connected to a secondary stage of a two-stage battery charger. The controller can determine a threshold voltage based on the at least one battery parameter. The controller can regulate a midpoint voltage at the threshold voltage. The midpoint voltage can be provided by a primary stage of the two-stage battery charger to the secondary stage of the two-stage battery charger. The controller can operate the secondary stage in a non-switching mode to directly provide the midpoint voltage regulated at the threshold voltage to the battery.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
22.
POWER-CONVERTER CONTROL USING PASS-THROUGH AND SWITCHING MODES
Systems and methods for operating a power converter of a device are described. A controller of the power converter may determine a battery voltage of a battery of the device and determine whether the battery voltage meets a threshold voltage. Responsive to determining that the battery voltage meets the threshold voltage, the controller may cause the power converter to operate in a pass-through mode where the power converter provides a load voltage to a load that is equal to the battery voltage. Alternatively, responsive to determining that that battery voltage does not meet the threshold voltage, the controller may cause the power converter to operate in a switching mode where the power converter provides the load voltage that is equal to the threshold voltage. By using the pass-through mode when the battery voltage meets the threshold voltage, a battery life of the device may be conserved.
A system and method for authenticating sound verbalized or otherwise generated by a live source within a monitored setting for voice-controlled or sound-controlled automation of a responsive process. One or more classifiers each generate a decision value according to values of predetermined signal features extracted from a received digital stream, and a sound type classification is computed according to an aggregate score of a predetermined number of decision values. The actuation of the responsive process is authenticated when the system discriminately indicates the captured sound signals to be verbalized or generated by a live source. The responsive process is thereby suppressed when the sound is instead determined to be reproduced or otherwise previously transduced, for example by a transmission or recording.
A Semiconductor device capable of performing efficient signal processing, to provide a control method and a program of the semiconductor device. The semiconductor device includes a first signal processing unit, a second signal processing unit, and a control unit. The control unit includes: a detection unit that detects the process amount of the second process in which the first signal processing unit or the second signal processing unit executes; a prediction unit that predicts the process amount of the second process to be executed next based on the process amount of the detected second process; and a distribution unit that distributes the first process to the first signal processing unit and the second signal processing unit according to the process amount of the predicted second process.
A semiconductor device includes, in a gate finger region, a gate potential trench formed on a main surface side of a semiconductor substrate, predetermined potential trenches formed so as to sandwich the gate potential trench on the main surface side of the semiconductor substrate, a drift region of a first conductivity type formed in a first region between the gate potential trench and the predetermined potential trench, and a well region of a second conductivity type, which is a region above the drift region and formed in a second region on a side of the predetermined potential trench opposite to a side where the gate potential trench is located.
Captured samples of a physical structure or other scene are mapped to a predetermined multi-dimensional coordinate space, and spatially-adjacent samples are organized into array cells representing subspaces thereof. Each cell is classified according to predetermined target-identifying criteria for the samples of the cell. A cluster of spatially-contiguous cells of common classification, peripherally bounded by cells of different classification, is constructed, and a boundary demarcation is defined from the peripheral contour of the cluster. The boundary demarcation is overlaid upon a visual display of the physical scene, thereby visually demarcating the boundaries of a detected target of interest.
G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
G06F 18/21 - Design or setup of recognition systems or techniquesExtraction of features in feature spaceBlind source separation
G06F 18/2131 - Feature extraction, e.g. by transforming the feature spaceSummarisationMappings, e.g. subspace methods based on a transform domain processing, e.g. wavelet transform
G06F 18/231 - Hierarchical techniques, i.e. dividing or merging pattern sets so as to obtain a dendrogram
G06F 18/2411 - Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches based on the proximity to a decision surface, e.g. support vector machines
G06F 18/2453 - Classification techniques relating to the decision surface non-linear, e.g. polynomial classifier
G06T 7/70 - Determining position or orientation of objects or cameras
G06T 7/90 - Determination of colour characteristics
G06T 11/60 - Editing figures and textCombining figures or text
G06V 10/26 - Segmentation of patterns in the image fieldCutting or merging of image elements to establish the pattern region, e.g. clustering-based techniquesDetection of occlusion
G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersectionsConnectivity analysis, e.g. of connected components
G06V 10/46 - Descriptors for shape, contour or point-related descriptors, e.g. scale invariant feature transform [SIFT] or bags of words [BoW]Salient regional features
G06V 10/80 - Fusion, i.e. combining data from various sources at the sensor level, preprocessing level, feature extraction level or classification level
The present invention suppresses an increase in manufacturing cost and reduces switching noise. A field-effect transistor having a gate electrode embedded in a trench in an upper surface of a semiconductor substrate, a source region formed in the semiconductor substrate, and a drain region formed on a lower surface of the semiconductor substrate is provided with a gate wiring formed on the semiconductor substrate and being electrically connected to the gate electrode, a gate pad formed on the semiconductor substrate, a first resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned ON, a second resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned OFF, and a rectifier diode included in the first resistor or the second resistor between the gate pad and the gate wiring.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Enhancing the performance of semiconductor devices by reducing the operating voltage of a ferroelectric memory equipped with a ferroelectric film. On a semiconductor substrate, forming a laminated body including a paraelectric film, which is an insulating film, and the ferroelectric film made of three or more layers of ferroelectric layers to on the insulating film, and forming a metal film and a gate electrode on the ferroelectric film. By discretely placing impurity particles between the ferroelectric layers that are in contact with each other, the crystallinity of the ferroelectric film is enhanced.
A plurality of wirings included in a wiring substrate includes: a plurality of first wirings for propagating a first clock signal and a first chip select signal to first and second memory devices mounted on a front surface; and a plurality of second wirings for propagating a second clock signal and a second chip select signal to third and fourth memory devices mounted on a back surface. The plurality of first wirings is provided in a wiring layer, which is closer to the front surface, of a plurality of wiring layers, and the plurality of second wirings is provided in a wiring layer, which is closer to the back surface, of the wiring layers.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
30.
COMPACT INJECTION MOLDED OPTICAL MODULE FOR GAS SENSING
An optical module component for a gas sensor may comprise a first housing portion and a second housing portion. The first housing portion and the second housing portion may be configured to be joined together and to form a substantially cylindrical optical cavity when joined together. The optical module component may further comprise: a first opening for receiving light from a light source; at least one second opening for passing light from the optical cavity to a detector; a first curved reflecting element configured to direct the light from the light source into the optical cavity; and a second curved reflecting element configured to direct the light from the optical cavity to the detector. In particular, optical axes of the first and second curved reflecting elements may be tilted with respect to a diametral plane of the optical cavity.
G01N 21/3504 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light for analysing gases, e.g. multi-gas analysis
31.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a ferroelectric memory cell, and the ferroelectric memory cell includes a select transistor and a memory transistor. A gate dielectric film of the select transistor includes a ferroelectric film, and a gate dielectric film of the memory transistor includes a ferroelectric film.
Methods and system for one-line synchronous interface are described. A timing device including a first buffer can be connected to a line card including a second buffer. The timing device can control the first buffer to output a synchronization pulse to the line card periodically at a time interval. For each output of the synchronization pulse, the timing device can switch the first buffer from a first output mode to a first input mode. Under the first input mode, the timing device listen for incoming data on the trace. The line card can receive the synchronization pulse periodically at the time interval. For each receipt of the synchronization pulse, the line card can switch the second buffer from a second input mode to a second output mode. Under the second output mode, the line card can transmit outgoing data on the trace.
H04L 7/06 - Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity, or frequency
Apparatuses, devices, and systems for time synchronization are described. A timing circuit can include an analog phase lock loop (APLL), a plurality of digital phase lock loops (DPLLs) and a plurality of fractional output dividers (FODs). The timing circuit can receive the plurality of reference clock signals. The timing circuit can use the plurality of reference clock signals to generate at least one fractional frequency offset signal. The timing circuit can apply at least one operand on the at least one fractional frequency offset signal. The timing circuit can sum results of the application of the at least one operand on the at least one fractional frequency offset signal to generate a plurality of signals that control frequencies of a plurality of output clock signals that can be synchronized with the plurality of reference clock signals.
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
H03L 7/195 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number in which the counter of the loop counts between two different non zero numbers, e.g. for generating an offset frequency
34.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device has: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type differing from the first conductivity type in the first semiconductor layer; a third semiconductor layer of the second conductivity type in the second semiconductor layer and having a higher impurity concentration than the second semiconductor layer; a fourth semiconductor layer of the first conductivity type on the third semiconductor layer; a fifth semiconductor layer of the first conductivity type on the fourth semiconductor layer and having a higher impurity concentration than the fourth semiconductor layer; a sixth semiconductor layer of the second conductivity type in the second semiconductor layer and having a higher impurity concentration than the third semiconductor layer; and a seventh semiconductor layer of the second conductivity type having the same impurity concentration distribution as the third semiconductor layer in a depth direction.
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
According to one embodiment, a semiconductor device includes: a semiconductor substrate having an upper surface and a lower surface; a first conductive layer formed above the semiconductor substrate; and a second conductive layer formed on the upper surface of the first conductive layer, in which, when viewed from above, the second conductive layer is formed in a region inside an end edge of the first conductive layer, the thickness of the second conductive layer is larger than the thickness of the first conductive layer, the thermal conductivity of the second conductive layer is larger than the thermal conductivity of the first conductive layer, and the resistivity of the second conductive layer is smaller than the resistivity of the first conductive layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
A semiconductor device includes a semiconductor substrate, a first semiconductor region formed in the semiconductor substrate, a second semiconductor region surrounding the first semiconductor region in plan view, a first conductive layer formed on the first semiconductor region, a first electrode formed on the first conductive layer, a cathode region connected to the first electrode via the first conductive layer, a second conductive layer in contact with the first semiconductor region, a second electrode formed on the second conductive layer, and a first region disposed between a region in contact with the first conductive layer of the first semiconductor region and the cathode region in a direction along the upper surface of the semiconductor substrate, and the first region is in contact with a lower surface of the second conductive layer. A depth of the first region is greater than a depth of the cathode region.
Apparatuses, devices, and systems for detecting open pins are described. A controller can control at least one power stage. The controller can include a first set of interface pins, a digital communication bus and a circuit configured to switch connections between a reference voltage and the first set of interface pins. The controller can read a pin status of the at least one power stage via the digital communication bus. The pin status can indicate whether the reference voltage is detected at a second set of interface pins of the at least one power stage. The controller can, based on the pin status, detect a presence or an absence of an open pin condition between the first set of interface pins and the second set of interface pins.
On a lower layer side of a temperature sensing diode, trenches are periodically formed in a semiconductor substrate. A source field plate is arranged in the trenches via an insulating film. A P type diffusion layer is formed between adjacent trenches. The source field plate and the P type diffusion layer are connected to a source potential.
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
A semiconductor device includes a processor including a first register set and a second register set. In a first period, the processor selects the second register set as an active register set, and executes a first virtual machine by use of second context data. In a second period, the processor selects the first register set as the active register set, and executes a hypervisor by use of first context data. In the second period, the processor performs a processing of saving the second context data and a processing of reading third context data. In a third period, the processor selects the second register set as the active register set, and executes a second virtual machine by use of the third context data.
A semiconductor device with high performance is provided. A semiconductor device according to the present disclosure includes a semiconductor substrate having a plurality of trenches provided along a first direction, a field plate electrode having a plurality of recess portions and a plurality of thinning-out portions which are alternately disposed in the first direction, and being provided in the trench, an oxide film provided on the field plate electrode, and a gate electrode formed on the oxide film and disposed in each of the recess portions. In the adjacent trenches, the gate electrodes are disposed to be shifted in the first direction.
A semiconductor device includes a first terminal, an oscillation circuit that generates a first clock signal and a second clock signal, an AD conversion circuit, a correction circuit that corrects the digital signal obtained by the AD conversion circuit based on a correction data stored in a memory circuit and outputs the digital signal, an averaging circuit, a sampling circuit, a current generation circuit, and a superposition circuit, the correction data is generated based on an output of the sampling circuit when a dispersion current is superposed on a detection current, and is stored in the memory circuit.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
42.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: a semiconductor chip having a source electrode pad and mounted on a die pad via a die bonding material; a wire electrically connected with the source electrode pad of the semiconductor chip; and a sealing body sealing the semiconductor chip and the wire. The wire and the source electrode pad are made of different types of metals to each other. A wire bonding layer made of sintered metal is interposed between the source electrode pad and the wire. The wire is electrically connected with the source electrode pad via the wire bonding layer.
An interrupt reception unit receives an interrupt request. In response to a received interrupt request, an interrupt processing unit performs an interrupt process of a first priority or an interrupt process of a second priority having a lower priority than the first priority. An interrupt suppression control unit controls the number of interrupt processes of the second priority processed by the interrupt processing unit in a cycle time according to a suppression condition. The suppression condition is set on the basis of a cycle in which the interrupt process of the second priority occurs and the total number of the interrupt processes of the second priority occurring within a period corresponding to the cycle.
Since an electrode formed on an insulating film may be separated from the insulating film in a semiconductor device, the present invention makes it possible to prevent the separation of the electrode from the insulating film. A semiconductor device includes a semiconductor substrate, an insulating film, and an electrode. The insulating film is formed on the semiconductor substrate. The electrode is formed on the insulating film. The semiconductor device also includes an anchor member. The anchor member is in contact with the insulating film and the electrode, at an outer peripheral portion of the electrode.
A semiconductor device includes a semiconductor substrate, a first semiconductor region formed in the semiconductor substrate, a buried region formed in the semiconductor substrate, a second semiconductor region disposed over the buried region, a third semiconductor region disposed over the buried region, a drain region formed in the second semiconductor region, a source region formed in the third semiconductor region, and a gate electrode layer formed on an upper surface of the semiconductor substrate. The first semiconductor region includes a first region formed between the third semiconductor region and the buried region, and a second region formed between the second semiconductor region and the buried region. The semiconductor substrate, the first semiconductor region, and the second semiconductor region each have a first conductivity type. The buried region and the third semiconductor region each have a second conductivity type opposite the first conductivity type.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device including: a semiconductor chip mounted on a wiring substrate such that a main surface of the semiconductor chip faces a front surface of an insulating film of the wiring substrate; and a bump electrically connecting a land and an electrode pad. Here, in cross-sectional view, a center of the land is shifted in a direction from a center of an opening portion, which exposes a part of the land, of the insulating film toward a center of the semiconductor chip is provided.
A semiconductor device includes three types of cells as a plurality of logic gates. A first cell includes a p-type MOSFET having a first threshold voltage and an n-type MOSFET having a second threshold voltage. A second cell includes a p-type MOSFET having a third threshold voltage and an n-type MOSFET having a fourth threshold voltage. A third cell includes a p-type MOSFET having the third threshold voltage and an n-type MOSFET having the second threshold voltage. An absolute value of the first threshold voltage is higher than an absolute value of the third threshold voltage, and an absolute value of the second threshold voltage is higher than an absolute value of the fourth threshold voltage.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
48.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A pad is formed on an interlayer insulating film, and an insulating film is formed to cover the interlayer insulating film and the pad. An opening is formed in the insulating film to expose a part of the pad. In the opening, a nickel plating film is formed on the pad, a first gold plating film is formed on the nickel plating film, and a second gold plating film is formed on the first gold plating film. A phosphorus concentration of the nickel plating film is 2% by mass or more and 7% by mass or less.
H01L 23/00 - Details of semiconductor or other solid state devices
C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
C23C 18/32 - Coating with one of iron, cobalt or nickelCoating with mixtures of phosphorus or boron with one of these metals
C23C 18/44 - Coating with noble metals using reducing agents
49.
VOLTAGE REGULATOR CONTROL WITH SCALABLE POWER STAGE
Apparatuses, devices, and systems for controlling power supply to a load are described. A system can include a power stage and a power management integrated circuit (PMIC). The PMIC can include a controller configured to determine a load is operating under a low power mode. The controller can, in response to the load operating under the low power mode, operate the PMIC to supply power to the load. The controller can determine the load is operating under a high power mode. The controller can, in response to the load operating under the high power mode, operate at least one of the PMIC and the power stage to supply power to the load.
In an embodiment, a semiconductor device is disclosed that includes a bidirectional unipolar-bipolar DC-DC circuit. The bidirectional unipolar-bipolar DC-DC circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor is connected between a reference ground connection and a first connection of a coil. The second transistor is connected between a positive bipolar input/output connection and the first connection of the coil. The third transistor is connected between a second connection of the coil and a negative bipolar input/output connection. The fourth transistor is connected between the second connection of the coil and a unipolar voltage input/output connection. The bidirectional DC-DC circuit is configured to concurrently activate the second and third transistors to cause a current flow through the coil between the positive bipolar input/output connection and the negative bipolar input/output connection.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Systems and devices for power multiplexing are described. A device can include a first power input circuit including a first power driver having a first gate that is configured to receive power from a first power input channel and output power to a power output channel. The device includes a second power input circuit including a second power driver having a second gate that is configured to receive power from a second power input channel and output power to the power output channel. The device includes a charge pump connected to the power output channel that generates an output having a voltage greater than a voltage on the power output channel. The device includes a switching circuit connected to the output of the charge pump that is configured to selectively control the first and second power input circuits to output power to the power output channel.
H03K 17/00 - Electronic switching or gating, i.e. not by contact-making and -breaking
H02J 50/00 - Circuit arrangements or systems for wireless supply or distribution of electric power
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
52.
BIDIRECTIONAL THREE-LEVEL BUCK-BOOST VOLTAGE CONVERTER WITH BATTERY CHARGING
Apparatuses, devices, and methods for operating a voltage converter are described. A semiconductor device can include a first switching circuit comprising four switches and a flying capacitor. The semiconductor device can further include a second switching circuit comprising two switches. The semiconductor device can further include an inductor connected between a first phase node of the first switching circuit to a second phase node of the second switching converter. The first switching circuit and the second switching circuit can be combined to implement a buck-boost voltage converter that performs voltage conversion in a first direction from the first phase node to the second phase node and in a second direction from the second phase node to the first phase node.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor device includes fuse circuits, and each of the fuse circuits includes fuse elements and cutting transistors. The fuse elements and the cutting transistors are arranged in a first direction of a first main surface of a semiconductor substrate, respectively, and each of the fuse elements is surrounded by each of deep trench isolation parts in plan view. In plan view, each of the cutting transistors is surrounded by each of power supply parts, and the power supply parts are integrally surrounded by the deep trench isolation part. The cutting transistors are formed in a well region, and each of the power supply parts has the same conductivity type as the well region and is formed in the well region.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
54.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An n-type drift region and a p-type well region are formed in a semiconductor substrate. An n-type first drain region and an n-type second drain region are formed in the n-type drift region, and an n-type source region and an n-type semiconductor region are formed in the p-type well region. An impurity concentration of the n-type semiconductor region is lower than an impurity concentration of the n-type source region. A gate electrode includes an n-type first gate electrode portion and an n-type second gate electrode portion extending in the Y direction, and a p-type gate connection portion connecting the first gate electrode portion and the second gate electrode portion. In plan view, the n-type source region is arranged between the first gate electrode portion and the second gate electrode portion.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes a CPU configured to execute an instruction, a first register configured to store an address of the instruction currently being executed, a second register configured to store a return address when a function branch occurs, and a generation circuit configured to generate and output function branch information indicating an address of a function branch destination when the function branch occurs. The generation circuit is configured to determine whether or not the function branch has occurred based on values of the first register and the second register before and after instruction execution by the CPU, and, when determining that the function branch has occurred, output the value of the first register after the instruction execution by the CPU as the function branch information.
A semiconductor device includes an insulating film, and a polysilicon film formed on the insulating film. The semiconductor device includes, in plan view, a first region including a first semiconductor element formed of the polysilicon film, and a second region including a second semiconductor element. A first contact hole formed in the first region extends through the polysilicon film. An ohmic contact is formed between a metal embedded in the first contact hole and the polysilicon film on a side surface of the first contact hole.
A non-transitory computer readable medium stores a program for causing a co-simulation apparatus including a first simulator, a second simulator, a first communication path, and a second communication path to execute a co-simulation method. The first simulator stores first data in a first shared memory via the first communication path. In addition, the first simulator divides information related to a first address of the first shared memory in which the first data is stored into pieces of a size defined by an FMI standard, and transmits the pieces of information to the second simulator via the second communication path. The second simulator reads the first data stored in the shared memory by using the first address via the first communication path.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
A semiconductor device includes a dummy field structure in a non-element forming region. The dummy field structure includes a deep n-type well, an n-type well, a trench, a conductor layer, a first n-type semiconductor region, a second n-type semiconductor region, and a third n-type semiconductor region. The semiconductor device includes not only a first parasitic bipolar transistor but also a second parasitic bipolar transistor.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
An IGBT includes a first trench gate electrode extending in a first width direction, and a second trench gate electrode facing the first trench gate electrode. A first position range in the first width direction of a first channel region formed by the first trench gate electrode and a second position range in the first width direction of a second channel region formed by the second trench gate electrode differ from each other.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
60.
BATTERY MANAGEMENT SYSTEM, BATTERY MANAGEMENT METHOD, AND PROGRAM
The battery management system includes a first communication connection checking unit, a second communication connection checking unit, and an estimating unit. The first communication connection checking unit checks the communication state of the first communication connection that connects the microcontroller and the battery managing unit that obtains the cell voltage and the pack temperature. The second communication connection checking unit checks the communication state of the second communication connection that connects the microcontroller and the measuring unit that measures the pack voltage and pack current. The estimating unit estimates the charge/discharge information for controlling the charge/discharge of the battery based on the information that the microcontroller MC1 can be obtained, in accordance with the communication state of the first communication connection and the second communication connection.
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
61.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor layer having an N type drift region, a P type body region on the N type drift region, and an N type source region on the P type body region; an insulating layer on the semiconductor layer; a first opening provided in the insulating layer; a second opening provided in the semiconductor layer and extending from the N type source region to the P type body region so as to overlap the first opening in plan view; an insulating film arranged on a sidewall of the second opening; a first metal layer provided on the insulating layer, on the semiconductor layer of the first opening, on the insulating film, and on the semiconductor layer of the second opening; and a second metal layer provided on the first metal layer.
Reliability of a semiconductor device is improved. An insulating film is formed in an inner portion of a trench and on an upper surface of a semiconductor substrate. A field plate electrode is formed on the insulating film to fill the inner portion of the trench. The field plate electrode is recessed toward a bottom portion of the trench by etching process. Etching process using mixed gas containing CF4 gas and O2 gas is performed to an upper surface of the field plate electrode. A silicon oxide film is formed on the upper surface of the field plate electrode by thermal oxidation process.
A semiconductor chip is mounted on a die pad via a solder material. The semiconductor chip includes a plurality of corners including a first corner. A recess portion is formed in the die pad at an upper surface of the die pad. The semiconductor chip is mounted on the die pad such that the first corner is located at an inside of the recess portion. The first corner is located farthest from a center of a sealing body, among the plurality of corners. The solder material has: a first portion that is located between the semiconductor chip and a bottom surface of the recess portion; and a second portion that is located between the semiconductor chip and the upper surface of the die pad. A thickness of the solder material in the first portion is greater than a thickness of the solder material in the second portion.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A controller for controlling a power stage having a plurality of phases is presented. The controller generates a control signal; sends the control signal to the plurality of phases via a first link; receives from each phase a feedback signal via a second link; sums the plurality of feedback signals and derives an average current per phase.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
65.
NON-LINEAR TRANSIENT IMPROVEMENTS IN CURRENT MODE CONTROLLERS
A method of increasing a transient response of a current mode controller and a current mode controller with an improved transient response are provided. The current mode controller is configured to control a high side switch and a low side switch. The current mode controller includes a pulse width modulation generator.
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
66.
RUNTIME ANTENNA MATCHING FOR NEAR FIELD COMMUNICATION WIRELESS POWER TRANSFER
Systems and methods for runtime antenna matching for wireless power devices are described. The integrated circuit can include a controller. The integrated circuit can further include a circuit configured to sense voltage in a switching converter. The circuit can be further configured to determine whether a negative voltage spike is present or absent in the sensed voltage. The controller can be configured to, based on the presence or the absence of the negative voltage spike in the sensed voltage, tune a capacitance of an antenna interface circuit between the switching converter and an antenna to perform impedance matching.
H04B 5/79 - Near-field transmission systems, e.g. inductive or capacitive transmission systems specially adapted for specific purposes for data transfer in combination with power transfer
H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
67.
BATTERY CHARGING CIRCUIT HAVING CURRENT OVERSHOOT PROTECTION
A method for operating a battery charging circuit is generally described. The method comprises obtaining a fault condition value and determining that a fault condition is present. The method further comprises setting a freeze signal to a first value based on the determination that the fault condition is present and outputting the freeze signal to a loop control circuit that is configured to inhibit a correction of a battery input current based on the freeze signal. The method further comprises re-obtaining the fault condition value and determining that the fault condition is not present. The method further comprises setting the freeze signal to a second value based on the determination that the fault condition is not present and outputting the freeze signal to the loop control circuit. The loop control circuit is configured to enable a correction of the battery input current based on the freeze signal.
Systems and methods for method for operating a switching converter are described. A controller can sense a load current associated with an output voltage of a power stage. The controller can, based on the sensed load current, define a gate voltage at one of a default voltage level and a modified voltage level. The gate voltage can be for driving the power stage.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
69.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A lower electrode is formed in a first wiring layer. In a second wiring layer located over the first wiring layer, two wirings having a thickness greater than that of the lower electrode are formed. Between the first wiring layer and the second wiring layer, a dielectric film and an upper electrode are formed over the lower electrode. A resistor element is formed over the two wirings. The lower electrode, the dielectric film, and the upper electrode function as a capacitor element.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
70.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Reliability of a semiconductor device is improved. A resistance element and a trench form a closed path in plan view.
Reliability of a semiconductor device is improved. A resistance element and a trench form a closed path in plan view.
The semiconductor device includes: first and second contact members each electrically connecting a gate pad and the resistance element; third and fourth contact members each electrically connecting a gate wiring and the resistance element; and fifth to eighth contact members each electrically connecting a first conductive member and the resistance element. A current path passing from the gate pad to the gate wiring through the first conductive member is made of the plurality of contact members and the resistance element. The first conductive member functions together with the fifth to eighth contact members to form a bypass path for reducing the current that flows through some sections of the closed path made of the resistance element.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A semiconductor device includes a semiconductor chip in which a plurality of circuit blocks is formed. The plurality of circuit blocks includes a plurality of logic circuits. Each of the plurality of logic circuits includes an inverter circuit. The inverter circuit outputs a signal according to the result of a logical operation of a first signal and a second signal after being precharged by a trigger signal.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
H03K 19/17704 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
H03K 19/17728 - Reconfigurable logic blocks, e.g. lookup tables
H03K 19/1776 - Structural details of configuration resources for memories
A semiconductor device includes a first power supply voltage line to which a power supply voltage is supplied, a second power supply voltage line, a first impedance element provided between the first power supply voltage line and the second power supply voltage line, a first reference voltage line to which a reference voltage is supplied, a second reference voltage line, a second impedance element provided between the first reference voltage line and the second reference voltage line, an electronic circuit provided between the second power supply voltage line and the second reference voltage line and performing a predetermined processing on an input signal, and provided in series between the second power supply voltage line and the second reference voltage line, and having gates connected to drains, a first transistor which is a P-channel MOS transistor, and a second transistor which is an N-channel MOS transistor.
A silicon film in amorphous state is formed on a semiconductor substrate located in first to fourth regions. The silicon film located in the first region and the fourth region is removed such that the silicon film located in the second region and the third region is left. A polycrystalline silicon film is formed by crystallizing the silicon film by a heat treatment.
Performance of a semiconductor device is improved. A semiconductor device includes a semiconductor chip, a sealing body having an upper surface and a lower surface, a plurality of leads, and a metal plate exposed from the sealing body at the upper surface of the sealing body. An outer lead portion of each of the plurality of leads includes a portion extending from the upper surface toward the lower surface in a thickness direction of the sealing body. The portion includes an end of the outer lead portion. When it is assumed that the lower surface is a reference surface in side view, in the thickness direction of the sealing body, a distance from the end of the outer lead portion to the reference surface is less than a distance from the upper surface to the reference surface.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
75.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor substrate includes a p-type substrate region, an n-type buried layer on the p-type substrate region, and a p-type semiconductor layer on the n-type buried layer. In the semiconductor layer, an n-type semiconductor region is formed so as to surround a transistor in plan view and to reach the n-type buried layer from a main surface of the semiconductor substrate. A DTI region is formed so as to penetrate through the n-type semiconductor region and the n-type buried layer and reach the p-type substrate region.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Gate drivers, systems and methods are described. A gate driver can generate a gate current for driving a power switch in a system. A circuit can define a waveform shape of the gate current. The defined waveform shape of the gate current can cause a current of the power switch to have a constant slew rate.
Apparatuses and circuits for overcurrent protection are described. A circuit can be connected to one of a first hybrid switching device and a second hybrid switching device in a half bridge circuit. The first hybrid switching device can include a first wide-bandgap (WBG) device and a first FET in a cascode arrangement. The first WBG device can have a higher breakdown voltage than the first FET and a larger band gap than the first FET. The second hybrid switching device can include a second hybrid switching device including a second WBG device and a second FET in a cascode arrangement. The second WBG device can have a higher breakdown voltage than the second FET and a larger band gap than the second FET. The circuit can monitor a drive current of the half bridge circuit for detecting an overcurrent condition of the half bridge circuit.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
78.
SEMICONDUCTOR DEVICE, SWITCHING METHOD AND PROGRAM
A semiconductor device, a switching method, and a program that can prevent an overcurrent from flowing through a winding inside the motor are provided. The semiconductor device 100a, based on at least one of the inductance value and the resistance value of the winding inside the motor 10, a determination unit 363 for determining whether the current value of the winding exceeds the threshold after a predetermined time, based on the determination result of the determination unit 363 comprising a switch unit 364 for switching the control mode of the motor 10.
H02P 29/024 - Detecting a fault condition, e.g. short circuit, locked rotor, open circuit or loss of load
H02P 23/14 - Estimation or adaptation of motor parameters, e.g. rotor time constant, flux, speed, current or voltage
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
79.
COMMUNICATION CONTROLLER AND COMMUNICATION CONTROL METHOD
A communications controller is disclosed. The communications controller includes a data transfer unit and a protocol engine. The communications controller further includes a circuit configured to control transfer of data from the data transfer unit to the protocol engine in dependence upon a process identifier which identifies a process entity requiring the protocol engine to transmit data for the process entity.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
80.
PROBE TESTING APPARATUS, PROBE TESTING SYSTEM AND PROBE CARD
A probe testing apparatus includes a wafer stage, a temperature sensor, a temperature adjustment mechanism, and a controller. The wafer stage includes a wafer mounting surface on which a semiconductor wafer is mounted. The temperature sensor includes a temperature observation point exposed on the wafer mounting surface, and directly measures a temperature of a rear surface of the semiconductor wafer mounted on the wafer mounting surface. The temperature adjustment mechanism adjusts a temperature of the wafer stage by heating or cooling the wafer stage. The controller controls the temperature adjustment mechanism in such a manner that a measured temperature by the temperature sensor becomes a target temperature.
A first conductive pattern is formed on a semiconductor substrate and formed from a first conductive film. A second conductive film having a first portion on the semiconductor substrate, a second portion on an upper surface of the first conductive pattern, and a third portion connecting the first portion and the second portion so as to cover a side surface of the first conductive pattern, is formed. The upper surface of the third portion is higher than the upper surface of the first portion. The second portion is patterned. The second portion and a part of the third portion are selectively removed. By patterning the first conductive pattern and the second conductive film, a first gate electrode is formed from a part of the first conductive pattern, and a second gate electrode is formed from a part of the first portion.
Systems and methods for calibrating a clock signal are described. A device can include a processer, a circuit and a system duty cycle control (DCC) circuit. The circuit can perform a first phase shift on a clock signal to generate a first phase-shifted signal. The circuit can perform a second phase shift on the clock signal to generate a second phase-shifted signal. The circuit can perform a fixed DCC on the first phase-shifted signal to generate a first voltage signal. The circuit can sweep the second phase-shifted signal at a range of duty cycles to generate a second voltage signal. The circuit can sample an output clock signal at a time where the first voltage signal and the second voltage signal overlaps. The processor can generate a digital code based on the output clock signal. The system DCC circuit can calibrate the clock signal using the digital code.
A semiconductor device includes a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip. One of the first semiconductor chip and the second semiconductor chip includes a first switch. The other of the first semiconductor chip and the second semiconductor chip includes a second switch. The third semiconductor chip includes a first transformer. A signal is transmitted from the first semiconductor chip to the second semiconductor chip by the first transformer when the first switch is turned off while the second switch is turned on. A signal is transmitted from the second semiconductor chip to the first semiconductor chip by the first transformer when the second switch is turned off while the first switch is turned on.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H02M 7/00 - Conversion of AC power input into DC power outputConversion of DC power input into AC power output
84.
SEMICONDUCTOR MEASUREMENT DEVICE AND SEMICONDUCTOR MEASUREMENT METHOD
According to an embodiment, a semiconductor measurement device includes a CBCM circuit having a first terminal and a connection terminal and a potential difference application circuit connected to the connection terminal, the potential difference application circuit having a second terminal and applying a predetermined potential difference with respect to an output of the first terminal. The semiconductor measurement device obtains the parasitic capacitance of a measurement system from a capacitance in a connected state in which the first terminal and the second terminal are connected to a transistor and a capacitance in a disconnected state in which the first terminal and the second terminal are disconnected from the transistor, and calculates the capacitance of the transistor.
G01R 27/26 - Measuring inductance or capacitanceMeasuring quality factor, e.g. by using the resonance methodMeasuring loss factorMeasuring dielectric constants
G01R 31/26 - Testing of individual semiconductor devices
A semiconductor device includes a semiconductor substrate, an insulating film, a first coil, a second coil, a third coil, a fourth coil, a first guard ring and a second guard ring. The first coil and the second coil are formed on the semiconductor substrate. The third coil faces the first coil through the insulating film. The fourth coil faces the second coil through the insulating film. The first guard ring is formed to surround the third coil in plan view. The second guard ring is formed to surround the fourth coil in plan view. The first guard ring and the second guard ring are adjacent to each other while being spaced apart from each other in plan view.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
86.
INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD AND PROGRAM
To appropriately estimate the amount and direction of movement of a moving object, an information processing apparatus has an acquisition unit that acquires each image captured at each point in time by a shooting device mounted on the moving object; a determination unit that determines the type of movement of the moving object based on the respective images; and an estimation unit that, based on a first image and a second image captured at a time interval corresponding to the type of movement from the first image, estimates the amount and direction of movement of the moving object from the first point in time when the first image was captured to the second point in time when the second image was captured.
A semiconductor device capable of verifying whether or not correct acquirement of image data from a sensor has been successful is provided. A semiconductor device includes: a reception interface circuit receiving a plurality of packets including a plurality of line data, respectively, and outputting an image composite signal generated by linking a line synchronization signal with each of the plurality of line data; and a capture circuit provided at a subsequent stage of the reception interface circuit. The capture circuit includes: a line counter receiving, as its input, the line synchronization signal included in the image composite signal, and counting the number of times of the input of the line synchronization signal; and a comparator comparing a count value counted by the line counter with a preset expected value of the number of lines, and outputting an error signal if the count value and the expected value do not match each other.
Systems and methods for wireless power transfer systems are described. A wireless power transmitter can be configured to perform a frequency sweep on a transmitter coil of the wireless power transmitter at a plurality of frequencies. The plurality of frequencies can include a resonant frequency of a detection capacitor parallel to a receiver coil in a wireless power receiver. The wireless power transmitter can be configured to determine whether the wireless power receiver is present or absent on a charging region connected to the wireless power transmitter based on a phase response of the frequency sweep.
To provide a semiconductor device and a memory module capable of correctly maintaining the phase relationship between a data signal and a data strobe signal that determines the latch timing of the data signal. A variable delay circuit VDLYs_A generates respective data strobe signals DQSin, DQSin_M by delaying an input data strobe signal MDQS by delay amounts ST1, ST2. A timing adjustment circuit TMCT adjusts the delay amount ST1 based on the determination of matching/mismatching between a data signal DQo from a main slicer SLr and a data signal DQo_M from a monitor slicer SLr_M, while changing the delay amount ST2,
A current sense circuit is provided. The circuit includes a current mirror circuit QN1, QN2, and diode-connected QP1, QP2, QP3, and QP4 with their bases connected together, stacking such that the diode-connected side (QN1, QP1, QP3) aligns and connecting the emitter of QP2 to the collector of QP4. Furthermore, the gates of MP1 and MP2 are connected to the collector of QN2 and QP2, respectively. Additionally, the source of MP1 is connected to the drain of MP3 via the source of MP2 and also connected to the source of a Sense MOS. Moreover, the emitter of QP4 is connected to the source of MP4 via R1, and the drain of MP4 is connected to the source (OUT terminal) of a Main MOS. Furthermore, the gates of MP3 and MP4 are connected to the emitters of QN1 and QN2.
A semiconductor device having a semiconductor chip with a first circuit, a second circuit, a third circuit, a first protection element, and a resistor circuit, the first circuit and the third circuit mutually input and output unidirectional or bidirectional signals via the second circuit, the first protection element is electrically connected to a first node which electrically connects a first terminal and the second circuit, and the resistor circuit is provided between the first node and a second node which electrically connects the first terminal, the first circuit, and the second circuit and is located upstream of the first node.
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
92.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device includes: a step of forming a sealing body, and a step of irradiating a laser light to a region, which is covering a part of each of the plurality of leads, of the sealing body. Each of the plurality of leads of a lead frame LF includes a first portion having a first upper surface and a first lower surface opposite the first upper surface, and a second portion having a thickness smaller than the first portion. The second portion has a second upper surface, and a second lower surface opposite the second upper surface. In the step of irradiating the laser light, the second lower surface is exposed from the sealing body by selectively irradiating the region with the laser light.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A semiconductor nonvolatile memory device or the like capable of narrowing a cell voltage distribution range while suppressing write delay is provided. The semiconductor nonvolatile memory device includes: a plurality of gate lines; a plurality of bit lines intersecting the plurality of gate lines; and a plurality of memory cells connected to respectively intersection points between the gate lines and the bit lines. The plurality of memory cells are connected to one gate line selected from among the plurality of gate lines respectively via the different bit lines, and the semiconductor nonvolatile memory device further includes a plurality of write bit line current or voltage control circuits respectively controlling bit line currents in order to simultaneously perform writing into the plurality of memory cells.
Apparatuses, devices, and methods for operating a voltage converter are described. A semiconductor device can include a switching circuit and a controller. The switching circuit can include a plurality of switching elements. The controller can determine an operation mode of the switching circuit. In response to the operation mode indicating a two-level operation mode, the controller can program the switching circuit to operate as a two-level voltage converter. In response to the operation mode indicating a three-level operation mode, the controller can program the switching circuit to operate as a three-level converter.
H02M 3/00 - Conversion of DC power input into DC power output
H02M 3/06 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor device includes a semiconductor chip having a plurality of layers formed on a surface. Here, a power supply wiring to which a power supply voltage is supplied, a ground wiring to which a ground voltage is supplied, MOS transistors connected to the power supply and ground wirings, and a trigger circuit, which is electrically connected to a gate electrode of the MOS transistor via a first wiring, are formed in the plurality of layers. The MOS transistors and the trigger circuit are formed in a first layer, the first wiring is formed in a second layer which is an upper layer of the first layer, and the first wiring includes a first portion extending in a first direction and a second portion which extends in a second direction intersecting the first direction and is electrically connected to the first portion.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
96.
SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SEMICONDUCTOR DEVICE, AND CONTROL PROGRAM
A semiconductor device according to this disclosure includes: a comparator circuit; a counter circuit; and a latch circuit that stores a count value of the counter circuit at a timing when an output signal of the comparator circuit changes, the counter circuit includes: a multiphase signal generator; and a plurality of flip-flop circuits including a first-stage flip-flop and second-stage and subsequent flip-flops, the first-stage flip-flop takes in an inverted signal of an output signal of a flip-flop in a final stage and each of the second-stage and subsequent flip-flops takes in an output signal of a flip-flop in a preceding stage in synchronization with each of the plurality of clock signals, and an output signal of each of the plurality of flip-flop circuits is output as a count signal of the count value.
H04N 25/633 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current by using optical black pixels
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H04N 25/40 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
Access time from a CPU to a register can be reduced while complication of software is prevented. A semiconductor device includes: a decoder circuit determining a write-source process; a write-enable setting storage circuit storing a write-enable setting that indicates a processor enabled to execute writing into each bit of a write-destination register; a masking/merging circuit generating a value to be written back into the write-destination register on the basis of the write-enable setting and the write-source processor; and a write-back circuit writing back the value to be written back into the write-destination register.
Systems and methods for operating a wireless power transfer device are described. A circuit can generate a first signal that indicates a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter falling below ground. The circuit can delay a gate-source voltage of a second LS transistor in the switching converter to generate a second signal. The circuit can merge the first signal and the second signal to generate a third signal. A controller can use the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time. The first LS transistor being turned on at the specific time reduces a diode conduction time of a body diode of the first LS transistor.
H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
H03K 17/13 - Modifications for switching at zero crossing
H03K 17/16 - Modifications for eliminating interference voltages or currents
H03K 17/296 - Modifications to provide a choice of time-intervals for executing more than one switching action and automatically terminating their operation after the programme is completed
A semiconductor device includes a non-volatile memory (NVM) capable of data-writing even after the semiconductor device is shipped. When a read request is made, the semiconductor reads and outputs the content stored in the area of the NVM in place of the replacement target data in the instruction codes stored in a read only memory. Therefore, after shipping of the semiconductor device, even if a defect such as fragility in the code used at the start of the semiconductor device is found, replacement data in place of 10 the data to be replaced it can be obtained. That is, the semiconductor device, replacement process using the modified patches of Boot ROM cord is enabled.
A method of manufacturing a semiconductor device includes, after a wire bonding step, a step of determining a quality as to whether or not a whole of an end portion of a wire is located within a bonding region. A semiconductor chip includes a plurality of position determining opening patterns arranged in a region located around a main opening portion including the bonding region in plan view. The bonding region has a rectangular shape having an area smaller than an opening area of the main opening portion in plan view. The bonding region is defined by the plurality of position determining opening patterns.
