Alpha and Omega Semiconductor (Cayman) Ltd.

United States of America

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IPC Class
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement 10
H01L 23/495 - Lead-frames 10
H01L 23/00 - Details of semiconductor or other solid state devices 7
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only 7
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings 6
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Found results for  patents

1.

Isolated coupling structure

      
Application Number 15887418
Grant Number 11170926
Status In Force
Filing Date 2018-02-02
First Publication Date 2019-06-06
Grant Date 2021-11-09
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Cheng, Jung-Pei
  • Chang, Hsiang-Chung
  • Chen, Yu-Ming
  • Cheng, Chieh-Wen
  • Ou, Tsung-Han
  • Doong, Lih-Ming

Abstract

An isolation coupling structure for transmitting a feedback signal between a secondary side and a primary side of a voltage conversion device includes a first dielectric layer including a first face and a second face opposite to the first face, a first coupling coil disposed on the first face enclosing to form an inner region; a second coupling coil configured to couple with the first coupling coil. The second coupling coil includes a first coil portion and a second coil portion, where the first coil portion is disposed on the second face, the second coil portion is disposed on the first face and located inside the inner region. The second coil portion is isolated from the first coupling coil, and the first coil portion and the second coil portion are electrically connected. The technical effect is that it can realize the electrical isolation and the coupling with low cost and small package size.

IPC Classes  ?

  • H01F 27/28 - CoilsWindingsConductive connections
  • H01F 19/04 - Transformers or mutual inductances suitable for handling frequencies considerably beyond the audio range
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01F 27/29 - TerminalsTapping arrangements
  • H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for

2.

Semiconductor device having one or more titanium interlayers and method of making the same

      
Application Number 15811417
Grant Number 10438813
Status In Force
Filing Date 2017-11-13
First Publication Date 2019-05-16
Grant Date 2019-10-08
Owner Alpha and Omega Semiconductor (Cayman) Ltd. (USA)
Inventor
  • He, Wei
  • Wiebe, Chris
  • Xue, Hongyong

Abstract

A semiconductor device comprising a substrate layer, an epitaxial layer, a dielectric layer, a first aluminum layer, a first titanium interlayer and a second aluminum layer. The first titanium interlayer is disposed between the first aluminum layer and the second aluminum layer. A process for fabricating a semiconductor device comprising the steps of: preparing a semiconductor wafer; depositing a first aluminum layer onto the semiconductor wafer; depositing a first titanium interlayer onto the first aluminum layer; depositing a second aluminum layer onto the first titanium interlayer; applying an etching process so that a plurality of trenches are formed so as to expose a plurality of top surfaces of a dielectric layer; and applying a singulation process so as to form a plurality of separated semiconductor devices.

IPC Classes  ?

  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 23/00 - Details of semiconductor or other solid state devices

3.

Converting apparatus and method thereof

      
Application Number 15879887
Grant Number 10289136
Status In Force
Filing Date 2018-01-25
First Publication Date 2019-05-14
Grant Date 2019-05-14
Owner ALPHA AND OMEGA SEMICONDUCTORE (CAYMAN) LTD. (USA)
Inventor Tu, Wei-Cheng

Abstract

A converting apparatus includes: a driving device arranged to charge a connecting terminal by a charging signal and to discharge the connecting terminal by a discharging signal for generating a driving signal; a filtering device coupled to the connecting terminal for generating an output voltage according to the driving signal; and a controlling device coupled to the connecting terminal, for receiving the driving signal to generate a control signal. The driving device is arranged to generate the charging signal and the discharging signal according to the control signal. A method of generating an output voltage includes the steps of generating a driving signal; filtering the driving signal to generate the output voltage; receiving the driving signal to generate a control signal; and generating the charging signal and the discharging signal according to the control signal.

IPC Classes  ?

  • G05F 1/445 - Regulating voltage or current wherein the variable is actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices semiconductor devices only being transistors in series with the load
  • H02M 1/00 - Details of apparatus for conversion
  • H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
  • H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/12 - Arrangements for reducing harmonics from AC input or output

4.

Molded power module having single in-line leads

      
Application Number 15294778
Grant Number 10056893
Status In Force
Filing Date 2016-10-16
First Publication Date 2018-04-19
Grant Date 2018-08-21
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Suh, Bum-Seok
  • Niu, Zhiqiang
  • Cho, Wonjin
  • Tran, Son
  • Bou, James Rachana

Abstract

A power module has a lead frame, a first power chip, a second power chip, a plurality of single in-line leads, a gate drive and protection integrated circuit (IC), a plurality of bonding wires and a molding encapsulation. The first and second power chips are attached to a top surface of the lead frame. The plurality of single in-line leads has a high voltage power lead, a low voltage power lead and a plurality of signal control leads. The low voltage power lead has a lead portion and an extension portion. The gate drive and protection IC is attached to the extension portion of the low voltage power lead. The molding encapsulation encloses the first and second power chips, the extension portion of the low voltage power lead, the gate drive and protection IC, the plurality of bonding wires and at least a majority portion of the lead frame.

IPC Classes  ?

  • H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts
  • H03K 17/041 - Modifications for accelerating switching without feedback from the output circuit to the control circuit
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
  • H01L 23/495 - Lead-frames
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
  • H03K 17/16 - Modifications for eliminating interference voltages or currents
  • H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage

5.

Molded intelligent power module

      
Application Number 15602002
Grant Number 10177080
Status In Force
Filing Date 2017-05-22
First Publication Date 2018-04-19
Grant Date 2019-01-08
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Niu, Zhiqiang
  • Suh, Bum-Seok
  • Lu, Jun
  • Cho, Wonjin

Abstract

An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, an IC, a plurality of leads and a molding encapsulation. The first MOSFET is attached to the first die paddle. The second MOSFET is attached to the second die paddle. The third MOSFET is attached to the third die paddle. The fourth, fifth and sixth MOSFETs are attached to the fourth die paddle. The IC is attached to the tie bar. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar and the IC. The IPM is a small-outline package. It reduces system design time and improves reliability. The IC includes boost diodes. It reduces a package size of the IPM.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H05K 1/14 - Structural association of two or more printed circuits
  • H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
  • H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor
  • H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
  • H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

6.

Molded intelligent power module and method of making the same

      
Application Number 15699985
Grant Number 10141249
Status In Force
Filing Date 2017-09-08
First Publication Date 2018-04-19
Grant Date 2018-11-27
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Niu, Zhiqiang
  • Suh, Bum-Seok
  • Cho, Wonjin
  • Lu, Jun

Abstract

An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, a metal slug, a plurality of spacers, a plurality of leads and a molding encapsulation. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar and the plurality of spacers. A bottom surface of the metal slug is exposed from the molding encapsulation. A process for fabricating the IPM comprises preparing the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar, the plurality of leads, the metal slug and the plurality of spacers and applying a molding process to form the molding encapsulation.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H02P 27/00 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

7.

Molded intelligent power module

      
Application Number 15600698
Grant Number 09881856
Status In Force
Filing Date 2017-05-19
First Publication Date 2018-01-30
Grant Date 2018-01-30
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Suh, Bum-Seok
  • Niu, Zhiqiang
  • Cho, Wonjin
  • Oh, Cheow Khoon
  • Tran, Son
  • Bou, James Rachana

Abstract

An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth transistors, a tie bar, a low voltage IC, a high voltage IC, a first, second and third boost diodes, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die paddle. The second transistor is attached to the second die paddle. The third transistor is attached to the third die paddle. The fourth, fifth and sixth transistor s are attached to the fourth die paddle. The low and high voltage ICs are attached to the tie bar. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth transistors, the tie bar, the low and high voltage ICs, and the first, second and third boost diodes. The IPM has a reduced top surface area and a reduced number of leads compared to a conventional IPM.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H02P 27/00 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

8.

Wafer level chip scale package structure and manufacturing method thereof

      
Application Number 15197609
Grant Number 10242926
Status In Force
Filing Date 2016-06-29
First Publication Date 2018-01-04
Grant Date 2019-03-26
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Oh, Cheow Khoon
  • Lu, Ming-Chen
  • Sui, Xiaoming
  • Chen, Bo
  • Xue, Vincent

Abstract

A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.

IPC Classes  ?

  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

9.

Power trench MOSFET with improved unclamped inductive switching (UIS) performance and preparation method thereof

      
Application Number 15646084
Grant Number 09997593
Status In Force
Filing Date 2017-07-10
First Publication Date 2017-12-28
Grant Date 2018-06-12
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Ding, Yongping
  • Yilmaz, Hamza
  • Wang, Xiaobin
  • Bobde, Madhur

Abstract

A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole. The method comprises the steps of providing a semiconductor substrate, etching an epitaxial layer, depositing a conductive material, depositing an insulation passivation layer and etching through the insulation passivation layer.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/40 - Electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/8234 - MIS technology

10.

Semiconductor power device having single in-line lead module and method of making the same

      
Application Number 15659587
Grant Number 09966328
Status In Force
Filing Date 2017-07-25
First Publication Date 2017-12-28
Grant Date 2018-05-08
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Xue, Yan Xun
  • Niu, Zhiqiang

Abstract

A semiconductor power device is disclosed. The semiconductor power device comprises a lead frame unit, two or more pluralities of single in-line leads, two or more semiconductor chip stacks, and a molding encapsulation. Each semiconductor chip stack includes a high-side semiconductor chip, a low-side semiconductor chip and a clip connecting a top surface of the high-side semiconductor chip to a bottom surface of the low-side semiconductor chip. This invention further discloses a method for fabricating semiconductor power devices. The method comprises the steps of providing a lead frame strip having a plurality of lead frame units; providing two or more pluralities of single in-line leads; attaching two or more high-side semiconductor chips to each lead frame unit; connecting each of the two or more high-side semiconductor chips to a respective lead by a respective clip of two or more first clips; attaching a respective low-side semiconductor chip of the two or more low-side semiconductor chips to each clip of the two or more first clips; molding an encapsulation; and singulating the lead frame strip and the encapsulation to form the semiconductor power devices.

IPC Classes  ?

  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/495 - Lead-frames
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

11.

Molded intelligent power module

      
Application Number 15294766
Grant Number 09704789
Status In Force
Filing Date 2016-10-16
First Publication Date 2017-07-11
Grant Date 2017-07-11
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Suh, Bum-Seok
  • Niu, Zhiqiang
  • Cho, Wonjin
  • Oh, Cheow Khoon
  • Tran, Son
  • Bou, James Rachana

Abstract

An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth transistors, a tie bar, a low voltage IC, a high voltage IC, a first, second and third boost diodes, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die paddle. The second transistor is attached to the second die paddle. The third transistor is attached to the third die paddle. The fourth, fifth and sixth transistor s are attached to the fourth die paddle. The low and high voltage ICs are attached to the tie bar. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth transistors, the tie bar, the low and high voltage ICs, and the first, second and third boost diodes. The IPM has a reduced top surface area and a reduced number of leads compared to a conventional IPM.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H02P 27/00 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage

12.

Power semiconductor device with small contact footprint and the preparation method

      
Application Number 15458797
Grant Number 10504823
Status In Force
Filing Date 2017-03-14
First Publication Date 2017-06-29
Grant Date 2019-12-10
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Gao, Hongtao
  • Lu, Jun
  • Lu, Ming-Chen
  • Ye, Jianxin
  • Huo, Yan
  • Pan, Hua

Abstract

A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor chips, and the conductive pads. Side surfaces of the conductive pads are exposed from a side surface of the plastic package body.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material

13.

Voltage detection circuit and a method of detecting voltage changes

      
Application Number 15348110
Grant Number 10298144
Status In Force
Filing Date 2016-11-10
First Publication Date 2017-03-02
Grant Date 2019-05-21
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Chen, Yu-Ming
  • Liu, Chih-Yuan
  • Huang, Pei-Lun

Abstract

A power conversion system and a method for voltage change detection, specifically, relates to a detection circuit implemented in the AC-DC power converter, detect the voltage change. The AC input voltage is rectified to convert into a DC input voltage transmitted to a detection unit generating a detection voltage signal at different logical states corresponding to the input voltage changes. A charge current source unit is used for charging the capacitor when the detection voltage signal is in a second state and a discharge current source unit is used for discharging the capacitor when the detection voltage signal is in a first state. A primary comparator compares the voltage changes of the capacitor in the alternating charge and discharge processes with a critical zero potential and outputs a detection signal identifying the changing trend of the input voltage.

IPC Classes  ?

  • H02M 7/217 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M 1/32 - Means for protecting converters other than by automatic disconnection
  • G01R 19/22 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using conversion of AC into DC
  • G01R 15/16 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using capacitive devices
  • G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
  • H02M 7/06 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
  • G01R 19/15 - Indicating the presence of current
  • H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
  • H02M 7/04 - Conversion of AC power input into DC power output without possibility of reversal by static converters
  • G01R 19/155 - Indicating the presence of voltage
  • G01R 19/145 - Indicating the presence of current or voltage

14.

Flyback converter output current evaluation circuit and evaluation method

      
Application Number 15343091
Grant Number 09954449
Status In Force
Filing Date 2016-11-03
First Publication Date 2017-02-16
Grant Date 2018-04-24
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Chen, Yu-Ming
  • Cheng, Jung-Pei
  • Huang, Pei-Lun

Abstract

LEB is transmitted through an output stage in a predetermined time ratio of a cycle with the duty cycle determined by a logic control unit, in which the logic control unit controls the output stage to receive the voltage converted from sum current in a predetermined time period of each cycle, and prevents the output stage to receive the voltage converted from sum current in the remaining time other than such predetermined time period of each cycle.

IPC Classes  ?

  • H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • G01R 19/10 - Measuring sum, difference, or ratio
  • G01R 19/15 - Indicating the presence of current
  • G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
  • H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
  • H02M 1/00 - Details of apparatus for conversion

15.

Dual-side exposed semiconductor package with ultra-thin die and manufacturing method thereof

      
Application Number 14862136
Grant Number 09437528
Status In Force
Filing Date 2015-09-22
First Publication Date 2016-09-06
Grant Date 2016-09-06
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Gong, Yuping
  • Sui, Xiaoming
  • Xue, Yan Yun
  • Lu, Jun

Abstract

A dual-side exposed semiconductor package with ultra-thin die and a manufacturing method are disclosed. A die having a source electrode and a gate electrode at top surface is flipped and attached to a die paddle of a lead frame and then is encapsulated with a first molding compound. The first molding compound and the die are ground to reduce the thickness. A mask is applied atop the lead frame with the back of the flipped die exposed and a metal layer is deposited on the exposed area at the back of the flipped die. A metal clip is attached to the back of the flipped die. A second molding compound is deposited on the lead frame with the top surface of the metal clip exposed from the top surface of the second molding compound and the bottom surface of the lead frame exposed from the bottom surface of the second plastic molding compound.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

16.

Flyback converter output current evaluation circuit and evaluation method

      
Application Number 14755951
Grant Number 09490712
Status In Force
Filing Date 2015-06-30
First Publication Date 2016-06-23
Grant Date 2016-11-08
Owner Alpha and Omega Semiconductor (Cayman) Ltd. (USA)
Inventor
  • Chen, Yu-Ming
  • Cheng, Jung-Pei
  • Huang, Pei-Lun

Abstract

LEB is transmitted through an output stage in a predetermined time ratio of a cycle with the duty cycle determined by a logic control unit, in which the logic control unit controls the output stage to receive the voltage converted from sum current in a predetermined time period of each cycle, and prevents the output stage to receive the voltage converted from sum current in the remaining time other than such predetermined time period of each cycle.

IPC Classes  ?

  • H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • G01R 19/10 - Measuring sum, difference, or ratio
  • G01R 19/15 - Indicating the presence of current

17.

Power semiconductor device and the preparation method

      
Application Number 14500982
Grant Number 09337131
Status In Force
Filing Date 2014-09-29
First Publication Date 2016-03-31
Grant Date 2016-05-10
Owner Alpha and Omega Semiconductor (Cayman) Ltd. (USA)
Inventor
  • Huo, Yan
  • Yilmaz, Hamza
  • Lu, Jun
  • Lu, Ming-Chen
  • Niu, Zhi Qiang
  • Xue, Yan Xun
  • Gong, Demei

Abstract

An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/3105 - After-treatment

18.

CONSTANT ON-TIME (COT) CONTROL IN ISOLATED CONVERTER

      
Application Number US2015050526
Publication Number 2016/044487
Status In Force
Filing Date 2015-09-16
Publication Date 2016-03-24
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Lin, Tien-Chi
  • Liu, Chih-Yuan
  • Hsu, Yung-Chuan
  • Huang, Pei-Lun

Abstract

A constant on-time isolated converter comprising a transformer is disclosed. The transformer primary side connects to an electronic switch and secondary-side connects to a load and a processor. The processor connects to a driver on primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal. The driver receives control signal through the coupling element and accordingly changes the electronic switch ON/OFF state, regulating output voltage and current via the transformer, where the electronic switch ON/OFF duration is determined between the moment control signal changes from negative to positive and the moment it changes from positive to negative to achieve a high-speed response to load transient.

IPC Classes  ?

  • H02M 1/10 - Arrangements incorporating converting means for enabling loads to be operated at will from different kinds of power supplies, e.g. from AC or DC
  • H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M 7/155 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
  • H02M 7/21 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
  • G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor

19.

CONSTANT ON-TIME (COT) CONTROL IN ISOLATED CONVERTER

      
Application Number US2015050529
Publication Number 2016/044490
Status In Force
Filing Date 2015-09-16
Publication Date 2016-03-24
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Lin, Tien-Chi
  • Liu, Chih-Yuan
  • Hsu, Yung-Chuan
  • Huang, Pei-Lun

Abstract

The present invention discloses a constant on-time isolated converter comprising a transformer with a primary side and a secondary side. The primary side is connected to an electronic switch and secondary-side is connected to a load and a processor. The processor is connected to a driver on primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal accordingly. The driver receives the control signal through the coupling element and accordingly changes the ON/OFF state of the electronic switch, regulating the output voltage and the output current via the transformer, where the duration of the ON/OFF state of the electronic switch is determined between the moment control signal changes from negative to positive and the moment it changes from positive to negative to achieve a high-speed load transient response.

IPC Classes  ?

  • H02M 1/10 - Arrangements incorporating converting means for enabling loads to be operated at will from different kinds of power supplies, e.g. from AC or DC
  • H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M 7/155 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
  • H02M 7/21 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
  • G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor

20.

CONSTANT ON-TIME (COT) CONTROL IN ISOLATED CONVERTER

      
Application Number US2015050535
Publication Number 2016/044496
Status In Force
Filing Date 2015-09-16
Publication Date 2016-03-24
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Lin, Tien-Chi
  • Liu, Chih-Yuan
  • Hsu, Yung-Chuan
  • Huang, Pei-Lun

Abstract

The present invention discloses a constant on-time isolated converter comprising a transformer with a primary side and a secondary side. The primary side is connected to an electronic switch and secondary-side is connected to a load and a processor. The processor is connected to a driver on primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal accordingly. The driver receives the control signal through the coupling element and accordingly changes the ON/OFF state of the electronic switch, regulating the output voltage and the output current via the transformer, where the duration of the ON/OFF state of the electronic switch is determined between the moment control signal changes from negative to positive and the moment it changes from positive to negative to achieve a high-speed load transient response.

IPC Classes  ?

  • H02M 7/00 - Conversion of AC power input into DC power outputConversion of DC power input into AC power output
  • H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

21.

CONSTANT ON-TIME (COT) CONTROL IN ISOLATED CONVERTER

      
Application Number US2015050528
Publication Number 2016/044489
Status In Force
Filing Date 2015-09-16
Publication Date 2016-03-24
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. (USA)
Inventor
  • Lin, Tien-Chi
  • Liu, Chih-Yuan
  • Yu, Yueh-Ping
  • Cheng, Jung-Pei
  • Huang, Pei-Lun

Abstract

The present invention discloses a constant on-time isolated converter comprising a transformer with a primary side and a secondary side. The primary side is connected to an electronic switch and secondary-side is connected to a load and a processor. The processor is connected to a driver on primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal accordingly. The driver receives the control signal through the coupling element and accordingly changes the ON/OFF state of the electronic switch, regulating the output voltage and the output current via the transformer, where the duration of the ON/OFF state of the electronic switch is determined between the moment control signal changes from negative to positive and the moment it changes from positive to negative to achieve a high-speed load transient response.

IPC Classes  ?

  • H02M 1/10 - Arrangements incorporating converting means for enabling loads to be operated at will from different kinds of power supplies, e.g. from AC or DC
  • H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M 7/155 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
  • H02M 7/21 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
  • G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor

22.

CONSTANT ON-TIME (COT) CONTROL IN ISOLATED CONVERTER

      
Application Number US2015050536
Publication Number 2016/044497
Status In Force
Filing Date 2015-09-17
Publication Date 2016-03-24
Owner ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN ) LTD. (USA)
Inventor
  • Lin, Tien-Chi
  • Liu, Chih-Yuan
  • Yu, Yueh-Ping
  • Huang, Pei-Lun

Abstract

The present invention discloses a constant on-time isolated converter comprising a transformer with a primary side and a secondary side. The primary side is connected to an electronic switch and secondary-side is connected to a load and a processor. The processor is connected to a driver on. primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal accordingly. The driver receives the control signal through the coupling element and accordingly changes the ON/OFF state of the electronic switch, regulating the output voltage and the output current via the transformer, where the duration of the ON/OFF state of the electronic switch is determined between the moment control signal changes from negative to positive and the moment it changes from positive to negative to achieve a high-speed load transient response.

IPC Classes  ?

  • H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M 7/217 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

23.

Constant on-time (COT) control in isolated converter

      
Application Number 14562733
Grant Number 09548667
Status In Force
Filing Date 2014-12-07
First Publication Date 2016-03-17
Grant Date 2017-01-17
Owner Alpha and Omega Semiconductor (Cayman) Ltd. (USA)
Inventor
  • Lin, Tien-Chi
  • Liu, Chih-Yuan
  • Hsu, Yung-Chuan
  • Huang, Pei-Lun

Abstract

The present invention discloses a constant on-time isolated converter comprising a transformer with a primary side and a secondary side. The primary side is connected to an electronic switch and secondary-side is connected to a load and a processor. The processor is connected to a driver on primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal accordingly. The driver receives the control signal through the coupling element and accordingly changes the ON/OFF state of the electronic switch, regulating the output voltage and the output current via the transformer, where the duration of the ON/OFF state of the electronic switch is determined between the moment control signal changes from negative to positive and the moment it changes from positive to negative to achieve a high-speed load transient response.

IPC Classes  ?

  • H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only

24.

Ultra-thin semiconductor device and preparation method thereof

      
Application Number 14805390
Grant Number 09337127
Status In Force
Filing Date 2015-07-21
First Publication Date 2015-11-12
Grant Date 2016-05-10
Owner Alpha and Omega Semiconductor (Cayman) Ltd. (USA)
Inventor Huo, Yan

Abstract

A small and ultra-thin power semiconductor device and a preparation method are disclosed. The device includes a chip mounting unit with a plurality of pads with a plate arranged on top surface of each pad; a semiconductor chip flipped and attached on the chip mounting unit, where the electrodes at the front of the chip are electrically connected to the pads; a plastic packaging body covering the chip mounting units and the chip, where the top surface of the plate and the back surface of the chip are exposed out from top surface of the plastic packaging body and the bottom surfaces of the pads are exposed out of the bottom surface of the plastic packaging body; a plurality of top metal segments arranged on the top surface of the plastic packaging body and electrically connected to the top surface of each plate and the back surface of the chip.

IPC Classes  ?

  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/492 - Bases or plates
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/053 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/495 - Lead-frames
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

25.

Alternating current injection for constant-on time buck converter—a regulator control method

      
Application Number 14458464
Grant Number 09154034
Status In Force
Filing Date 2014-08-13
First Publication Date 2015-08-27
Grant Date 2015-10-06
Owner Alpha and Omega Semiconductor (Cayman), Ltd. (USA)
Inventor
  • Ng, Kong Soon
  • Huang, Wei-Chi
  • Wu, Jean-Shin

Abstract

The present invention discloses a voltage control method. At first, the load voltage of the load is divided to generate a feedback voltage. The feedback voltage and a triangular wave of a triangular wave periodic signal, including the positive voltage and negative voltage, are combined to generate a sum signal. The sum signal is compared with a target voltage, and when the sum signal is less than the target voltage signal, a control signal is generated to control the switches to turn on or off. Finally, the switch receives the control signal and accordingly providing an input voltage to update and stabilize the load voltage.

IPC Classes  ?

  • H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

26.

Input line selector system for battery chargers

      
Application Number 13711614
Grant Number 09385530
Status In Force
Filing Date 2012-12-12
First Publication Date 2014-06-12
Grant Date 2016-07-05
Owner Alpha and Omega Semiconductor (Cayman), Ltd. (USA)
Inventor Lee, Gilbert S.

Abstract

An input line selector system provided to selectively connect one of two input power lines is configured with a single switch provided in series with each of the input power lines, the connection between the switches being made such that it prevents reverse flow of current in the event that the switches are OFF. A smart, simple and precisely operating automatic line selector is provided to control the operation of the two switches. The line selector system configuration is simple and implements only two switches and can be applied to a linear charger or switching charger application with addition of one or two switches respectively, thereby providing a simple, efficient and cost effective system.

IPC Classes  ?

  • H02J 4/00 - Circuit arrangements for mains or distribution networks not specified as ac or dc
  • H02J 1/10 - Parallel operation of dc sources