A graphics processor includes a texel unit and an execution unit. The texel unit includes a loading module. The execution unit includes an im2col module to execute an im2col algorithm to expand an original matrix to obtain an expansion matrix according to the size of a kernel. The execution unit multiplies the expansion matrix and the kernel to obtain a feature map matrix. The loading module calculates feature coordinates of each element of the feature map matrix according to the coordinates of the expansion matrix, and obtains the original coordinates of each element of the original matrix according to the feature coordinates, the size of the kernel, a stride, and padding. The loading module reads at least one of the memory blocks covered by the original coordinates of each element of the original matrix, and outputs data corresponding to the original coordinates in the memory blocks.
A model simplification method is provided. The model simplification method includes: constructing a surrounding body to surround a model, wherein the model includes at least one primitive and a plurality of vertexes; drawing the model and the surrounding body to at least one rendering surface by respectively taking each of the plurality of vertexes as an eye-position; determining whether the surrounding body drawn on the rendering surface by taking a current vertex of the plurality of vertexes as the eye-position is occluded to decide whether to mark the current vertex as an invisible vertex; and eliminating a current primitive from the model when all vertexes of the current primitive of the at least one primitive are marked as the invisible vertex.
A graphics processing unit includes a sparse matrix detection unit, a register file, an assertion register, and a matrix calculation unit. The sparse matrix detection unit reads a plurality of matrices from a storage device and determines whether the matrices are zero matrices or non-zero matrices to output a determination result. The register file stores the plurality of matrices from the sparse matrix detection unit. The assertion register marks up the matrices according to the determination result, and outputs a mark result. The matrix calculation unit receives a matrix calculation instruction, reads the non-zero matrices in the plurality of matrices from the register file according to the mark result, and calculates the non-zero matrices.
A neural network computing device and a cache management method thereof are provided. The neural network computing device includes a computing circuit, a cache circuit and a main memory. The computing circuit performs a neural network calculation including a first layer calculation and a second layer calculation. After the computing circuit completes the first layer calculation and generates a first calculation result required for the second layer calculation, the cache circuit retains the first calculation result in the cache circuit until the second layer calculation is completed. After the second layer calculation is completed, the cache circuit invalidates the first calculation result retained in the cache circuit to prevent the first calculation result from being written into the main memory.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
An integrated circuit is provided. The integrated circuit includes a first volatile memory, a second volatile memory, and a video decoder. In response to the video decoder starting video decoding on a current frame of a video stream, the video decoder reads an initial probability table for the current frame from a memory unit external to the integrated circuit, and stores the initial probability table in the first volatile memory. When a decoding phase of the current tile is completed, the video decoder complements the probability table corresponding to each row of the second volatile memory according to control flags corresponding to the rows of the first volatile memory and the second volatile memory to obtain a complete probability table, and writes the complete probability table to the memory unit.
H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
G06N 7/00 - Computing arrangements based on specific mathematical models
6.
Data transferring apparatus and method for transferring data with overlap
A data transferring apparatus and a method for transferring data with overlap are provided. The data transferring apparatus includes a command splitter circuit and a plurality of tile processing circuits. The command splitter circuit splits a block level transfer command into a plurality of tile transfer tasks. The command splitter circuit may issue the tile transfer tasks to the tile processing circuits in a plurality of batches. The tile processing circuits may execute the tile transfer tasks in a current batch, so as to read data of a plurality of corresponding tiles among a plurality of source tiles of a source block to the tile processing circuits. After all the tile transfer tasks in the current batch have been executed by the tile processing circuits, the command splitter circuit issues the tile transfer tasks in a next batch of the batches to the tile processing circuits.
A sub-pixel rendering method for generating a target image according to a source image is provided. The method includes: obtaining the source image; determining a target pixel to be rendered in the target image; calculating an edge code of the source pixel corresponding to a sub-pixel of the target pixel to be rendered in the source image; determining texture information around the sub-pixel of the target pixel to be rendered according to the edge code; and calculating a pixel value for the sub-pixel of the target pixel to be rendered according to the texture information and based on area when the edge code is not a specific pattern.
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G06T 7/49 - Analysis of texture based on structural texture description, e.g. using primitives or placement rules
A graphics processing apparatus includes a tessellation circuit and a post-processing circuit. The tessellation circuit performs tessellation processing to subdivide a patch in an image frame into a plurality of triangles. The tessellation circuit further performs triangle striping processing to convert data of the plurality of triangles into data of a triangle strip. The post-processing circuit performs subsequent processing on the data of the triangle strip.
An artificial intelligence integrated circuit is provided. The artificial intelligence integrated circuit includes a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory is configured to store a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping (G2P) tables. The memory controller includes a first processing core and a second processing core. The first processing core receives a host access command from a host. When a specific G2P table corresponding to a specific logical address in the host access command is not stored in the DRAM, the first processing core determines whether the second processing core has loaded the specific G2P table from the flash memory to the DRAM according to the values in a first column in a first bit map and in a second column of a second bit map.
An image fusion method for removing ghost artifacts is provided. The method includes: determining a first fusion weight of a reference pixel in a reference frame, wherein the coordinates of the reference pixel are the same as the coordinates of one of input pixels included in an input frame; determining a reference brightness parameter according to values of all channels of the reference pixel; determining an input brightness parameter according to values of all channels of the input pixel; determining a ghost weight according to an amount that the brightness parameter ratio of the input brightness parameter and the reference brightness parameter deviates from a reasonable range; determining a fusion weight according to the first fusion weight and the ghost weight; and fusing the reference pixel with the input pixel according to the fusion weight to generate a fused pixel in a fused frame.
An image anti-aliasing method comprises following steps: receiving an aliasing image; wherein the aliasing image includes a plurality of source pixels; generating a plurality of hash values corresponding to the plurality of source pixels respectively; and performing a filtering processing or a filter generating procedure on the aliasing image according to the plurality of hash values. Each of the plurality of hash values is generated by the following steps: selecting one source pixel from the aliasing image and selecting a window containing the selected source pixel; determining an aliasing strength according to the grayscale values of all the source pixels of a row and a column at which the selected source pixel is located in the window; and determining a hash value of the selected source pixel according to the aliasing strength.
The disclosure provides an image processing method and an image processing device. The method includes: obtaining a specific block from a specific block group of a specific image, wherein the specific block group includes blocks; compressing the specific block as a specific stream based on a predetermined compression ratio; when a length of the specific stream is not shorter than a predetermined block length, dividing the specific stream into a first sub-stream and a second sub-stream; storing the first sub-stream into a specific private block of a plurality of private blocks; finding an idle chunk out of shared chunks shared by the blocks; if the idle chunk is enough for storing the second sub-stream, storing the second sub-stream into the idle chunk and using a chunk usage information to record a number of the idle chunk.
H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
13.
Image processing method and image processing device
An image processing method and an image processing device are provided. The method includes: retrieving a first and second blocks and compressing the first and second blocks into a first and second streams; in response to determining performing a dynamic memory allocation mechanism to the first and second blocks, respectively allocating a first and second private storage spaces to the first and second blocks, and allocating a shared storage space shared by the first and second blocks and divided into multiple segments; when the first private storage space is insufficient to store the first stream, using the first private storage space and a first part of the segments to cooperatively store the first stream; when the second private storage space is insufficient to store the second stream, using the second private storage space and a second part of the segments to cooperatively store the second stream.
H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
G06F 3/06 - Digital input from, or digital output to, record carriers
A sub-pixel rendering method for generating a target image according to a source image is provided. The method includes: obtaining the source image; determining a target pixel to be rendered in the target image; calculating an edge code of the source pixel corresponding to a sub-pixel of the target pixel to be rendered in the source image; determining texture information around the sub-pixel of the target pixel to be rendered according to the edge code; and calculating a pixel value for the sub-pixel of the target pixel to be rendered according to the texture information and based on distance when the edge code is not a specific pattern.
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G06T 7/49 - Analysis of texture based on structural texture description, e.g. using primitives or placement rules
15.
Method for compressing image and device using the same
The disclosure provides a method for image compression and a device using the same method. The method includes: retrieving an image block including pixels, wherein each pixel include a plurality of channel data; defining root nodes according to an image compressing ratio of the image block; categorizing each channel data of each pixel into groups corresponding to the root nodes, wherein a structure of each group is a binary tree; if an empty tree exists in the aforementioned groups, dividing an non-empty tree of the groups into sub-trees and replacing the empty tree and the non-empty tree with the sub-trees to update the groups and the root nodes; building a center value of each group and determining a group index of each channel data of each group; encoding the center value of each group and characterizing each channel data as the corresponding center value and the group index to compress each channel data.
An image compression method is provided. The image compression method includes steps of receiving, by a tile division generator, an input image; by the tile division generator, determining whether the input image corresponds to a partial updated region and whether the partial updated region coincides with one tile or a combination of tiles of a current frame and generating a determination result; and by the tile division generator, determining whether to re-perform tile division and compressing and encoding one portion of the current frame according to the determination result.
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
17.
Computer systems that are able to reduce memory data flow and graphics processing methods thereof
A graphics processing method is provided, adapted to a graphic processing unit, the steps including: receiving, via a CSP, a first command associated with all render targets from a display driver; determining, via the display driver, sizes and areas of a plurality of tiles in each frame; repeatedly controlling, via a scissor pool unit, a graphics processing unit to perform drawing processing for each tile according to the first command; comparing, via a signature comparing unit of a cache memory, a signature of a current tile of a current frame and a signature of a tile corresponding to the same position of a previous frame and generating a comparison result; and determining whether to flush the dirty data of the current tile stored in the cache memory from the cache memory to a memory access unit according to the comparison result.
G09G 5/36 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory
18.
Computer system, graphics processing unit, and graphics processing method thereof that are capable of switching different rendering modes
A graphics processing unit (GPU) is provided. The GPU includes a command stream parser (CSP). The CSP receives a command list from a display driver and parses commands in the command list to determine a rendering mode of the GPU and perform a graphics rendering pipeline for graphics processing according to the rendering mode. When the CSP determines that at least a specific CSP command is not included in the command list, the CSP determines that the rendering mode is a first rendering mode. When the CSP determines that the specific CSP command is included in the command list, the CSP determines that the rendering mode is a second rendering mode. In the second rendering mode, the CSP divides a rendering target into tiles, obtains first drawing commands from the command list according to the specific CSP command, and executes the first drawing commands for each tile.
A graphics processing unit (GPU) is provided. The GPU includes a command stream parser (CSP) including a profiling unit used to provide performance statistics data for the GPU to determine a rendering mode of the GPU, wherein the rendering mode includes a first rendering mode and a second rendering mode for performing a graphics rendering pipeline for graphics processing. The profiling unit calculates drawing time of frames and the number of objects in the frames when the GPU operates in the first rendering mode, and determines whether the operation of the GPU is switched to the second rendering mode according to the calculated drawing time and the number of objects; when determining that the calculated drawing time and the number of objects are less than their respective thresholds, the CSP causes the operation of the GPU to switch from the first rendering mode to the second rendering mode.
An apparatus integrates arithmetic with logic operations. The apparatus includes a calculation device that calculates source data to generate and output first destination data. The apparatus further includes a normalization unit, coupled to the calculation device, that normalizes the first destination data to generate second destination data of a first type when receiving a signal indicating an output of first-type data, and normalizing the first destination data to generate the second destination data of a second type when receiving the signal indicating an output of second-type data.
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
G06F 7/57 - Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups or for performing logical operations
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
H04N 19/85 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
G06F 7/74 - Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders
21.
Apparatuses for enqueuing kernels on a device-side
An apparatus for enqueuing kernels on a device-side is introduced to incorporate with at least a MXU (Memory Access Unit) and a CSP (Command Stream Processor): The CSP, after receiving a first command from the MXU, executes commands of a ring buffer, thereby enabling an EU (Execution Unit) to direct the MXU to allocate space of the ring buffer for a first hardware thread and subsequently write second commands of the first hardware thread into the allocated space of the ring buffer according to an instruction of a kernel.
A method provides data synchronization between a sensor hub and an application processor, which contains at least the following steps: generating and adding a plurality of absolute time stamps in a sensor-data stream; and generating and adding a plurality of pieces of sensor data and a plurality of relative time stamps in the sensor-data stream between the moments of generating each two adjacent absolute time stamps, wherein each relative time stamp is associated with one piece of sensor data.
G01D 9/28 - Producing one or more recordings, each recording being of the values of two or more different variables
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H04Q 9/00 - Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
23.
Methods for rate control in an MB (macroblock) layer and apparatuses using the same
The invention introduces a method for rate control in an MB (macroblock) layer, including: calculating a prediction MAD (Mean Absolute Difference) of a current MB of a current frame according to a real MAD of a previous MB of a previous frame; calculating a real MAD of the current MB of the current frame; performing an adjustment procedure to adjust the prediction MAD of the current MB of the current frame according to the real MAD of the current MB of the current frame to obtain a final MAD of the current MB of the current frame; calculating a quantization parameter of the current MB of the current frame according to the final MAD of the current MB of the current frame; and outputting the quantization parameter of the current MB of the current frame to a quantizer.
H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
H04N 11/02 - Colour television systems with bandwidth reduction
H04N 11/04 - Colour television systems using pulse code modulation
H04N 19/25 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video object coding with scene description coding, e.g. binary format for scenes [BIFS] compression
H04N 19/593 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques
H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
24.
Graphics processing device and graphics processing method
A technique for graphics processing which processes an image in units of blocks is disclosed. A graphics processing device has a buffer, an indicator register and an arithmetic logic unit (ALU). The buffer is provided to buffer a plurality of source blocks. The indicator register includes at least one instruction pointer. The ALU uses the instruction pointer to read source pixels in a first source block of the plurality of source blocks and adjacent source pixels in at least an adjacent source block with respect to the first source block from the buffer, to generate a first target block.
A method for controlling STB game, a remote control system and a handheld electronic apparatus are provided. After the handheld electronic apparatus is connected to the STB, when a gamepad mode is enabled, a virtual gamepad interface is displayed through a touch display panel of the handheld electronic apparatus, so as to simulate an operation method of a real gamepad. When the screen capturing mode is enabled, a game image of the display is captured and displayed on the touch display panel of the handheld electronic apparatus, and a specific function set in the game image is controlled through the touch display panel.
A63F 13/2145 - Input arrangements for video game devices characterised by their sensors, purposes or types for locating contacts on a surface, e.g. floor mats or touch pads the surface being also a display device, e.g. touch screens
A63F 13/235 - Input arrangements for video game devices for interfacing with the game device, e.g. specific interfaces between game controller and console using a wireless connection, e.g. infrared or piconet
G06F 3/0488 - Interaction techniques based on graphical user interfaces [GUI] using specific features provided by the input device, e.g. functions controlled by the rotation of a mouse with dual sensing arrangements, or of the nature of the input device, e.g. tap gestures based on pressure sensed by a digitiser using a touch-screen or digitiser, e.g. input of commands through traced gestures
A63F 13/26 - Output arrangements for video game devices having at least one additional display device, e.g. on the game controller or outside a game booth
A63F 13/24 - Constructional details thereof, e.g. game controllers with detachable joystick handles
26.
Mobile devices and methods for determining orientation information thereof
A mobile device including an acceleration sensor, a magneto sensor, a gyroscope sensor, and a processor is provided. The acceleration sensor, the magneto sensor, and the gyroscope sensor generate acceleration data, magnetic field data, and angular velocity data, respectively. The processor determines a pitch angle and a roll angle according to the acceleration data, determines a yaw angle according to the magnetic field data, and determines a quaternion according to the pitch angle, the roll angle, and the yaw angle. Also, the processor determines orientation information of the mobile device according to the quaternion and the angular velocity data, and adjusts the orientation information according to the acceleration data and the magnetic field data.
G01B 21/22 - Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring angles or tapersMeasuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for testing the alignment of axes
G01C 21/16 - NavigationNavigational instruments not provided for in groups by using measurement of speed or acceleration executed aboard the object being navigatedDead reckoning by integrating acceleration or speed, i.e. inertial navigation
patents