Utica Leaseco, LLC Assignee

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H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof 39
H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds 23
H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells 23
H01L 31/0224 - Electrodes 18
H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof 13
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Registered / In Force 102
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1.

Systems and methods for high-rate electrochemical arsine generation

      
Application Number 17472075
Grant Number 12139804
Status In Force
Filing Date 2021-09-10
First Publication Date 2022-03-24
Grant Date 2024-11-12
Owner Utica Leaseco, LLC (USA)
Inventor
  • Khater, Nabil A.
  • Gong, Kuanping
  • Wang, Chaowei
  • Dobkin, Daniel Mark

Abstract

A system and method for generating arsine are disclosed. The system may include a shell having a top interior surface. The system may also include a cathode-anode assembly positioned in the shell and forming an elongated structure substantially parallel to the top surface. The cathode-anode assembly may include a first electrode and a second electrode surrounding the first electrode and forming a gap therebetween. The second electrode may include a plurality of channels along a length of the second electrode. The plurality of channels may allow circulation of electrolyte within and around at least a portion of the cathode-anode assembly and allow gases generated in response to current applied to the cathode-anode assembly to escape from the cathode-anode assembly. Such gases may be used as precursor gases for a high-volume metal-organic chemical vapor deposition (MOCVD) operation.

IPC Classes  ?

  • C25B 9/30 - Cells comprising movable electrodes, e.g. rotary electrodes; Assemblies of constructional parts thereof
  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
  • C25B 1/01 - Products
  • C25B 11/034 - Rotary electrodes
  • C25B 11/061 - Metal or alloy
  • C25B 11/075 - Electrodes formed of electrocatalysts on a substrate or carrier characterised by the electrocatalysts material consisting of a single catalytic element or catalytic compound
  • C25B 15/08 - Supplying or removing reactants or electrolytes; Regeneration of electrolytes

2.

SYSTEMS AND METHODS FOR LARGE SCALE GAS GENERATION

      
Application Number 17472106
Status Pending
Filing Date 2021-09-10
First Publication Date 2022-03-10
Owner Utica Leaseco, LLC (USA)
Inventor
  • Salim, Sateria
  • Gong, Kuanping
  • Dobkin, Daniel Mark
  • Khater, Nabil A.

Abstract

A system and method for generating gas are disclosed. The system may include one or more current sources to generate an electrical current. The system may also include one or more cathode-anode assemblies electrically coupled with the one or more current sources. The one or more cathode-anode assemblies may generate a gas in response to receiving the electrical current from the one or more current sources. Each of the one or more cathode-anode assemblies may include a first electrode and a second electrode forming a concentric cylindrical structure, wherein the second electrode surrounds the first electrode and forms a gap between the second electrode and the first electrode. The system may also include electrolyte provided in the gap.

IPC Classes  ?

  • C25B 1/01 - Products
  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
  • C25B 1/50 - Processes
  • C25B 15/08 - Supplying or removing reactants or electrolytes; Regeneration of electrolytes
  • C25B 11/04 - Electrodes; Manufacture thereof not otherwise provided for characterised by the material
  • C25B 11/02 - Electrodes; Manufacture thereof not otherwise provided for characterised by shape or form

3.

Self-bypass diode function for gallium arsenide photovoltaic devices

      
Application Number 17455346
Grant Number 11695088
Status In Force
Filing Date 2021-11-17
First Publication Date 2022-03-10
Grant Date 2023-07-04
Owner Utica Leaseco, LLC (USA)
Inventor
  • Nie, Hui
  • Kayes, Brendan M.
  • Kizilyalli, Isik C.

Abstract

Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect.

IPC Classes  ?

  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/0443 - PV modules or arrays of single PV cells including bypass diodes comprising bypass diodes integrated or directly associated with the devices, e.g. bypass diodes integrated or formed in or on the same substrate as the photovoltaic cells
  • H01L 27/142 - Energy conversion devices

4.

Sputtered then evaporated back metal process for increased throughput

      
Application Number 17459611
Grant Number 12021164
Status In Force
Filing Date 2021-08-27
First Publication Date 2021-12-16
Grant Date 2024-06-25
Owner UTICA LEASECO, LLC (USA)
Inventor
  • Semonin, Octavi Santiago Escala
  • Furler, Reto Adrian
  • Majidi, Hasti
  • Hessler, Kristen Sydney

Abstract

A method is described that includes sputtering multiple layers on a back surface of the photovoltaic structure, the photovoltaic structure being made of at least one group III-V semiconductor material, and evaporating, over the multiple layers, one or more additional layers including a metal layer, the back metal structure being formed by the multiple layers and the additional layers. A photovoltaic device is also described that includes a back metal structure disposed over a back surface of a photovoltaic structure made of a group III-V semiconductor material, the back metal structure including one or more evaporated layers disposed over multiple sputtered layers, the one or more evaporated layers including a metal layer. By allowing evaporation along with sputtering, tool size and costs can be reduced, including minimizing a number of vacuum breaks. Moreover, good yield and reliability, such as reducing dark line defects (DLDs), can also be achieved.

IPC Classes  ?

  • H01L 31/0216 - Coatings
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/054 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means
  • H01L 31/056 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means the light-reflecting means being of the back surface reflector [BSR] type
  • H01L 31/0687 - Multiple junction or tandem solar cells
  • H01L 31/0725 - Multiple junction or tandem solar cells
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

5.

Thin-film semiconductor optoelectronic device with textured front and/or back surface prepared from etching

      
Application Number 17347314
Grant Number 11942566
Status In Force
Filing Date 2021-06-14
First Publication Date 2021-09-30
Grant Date 2024-03-26
Owner UTICA LEASECO, LLC (USA)
Inventor
  • Zhu, Yan
  • Sweetnam, Sean
  • Kayes, Brendan M.
  • Archer, Melissa J.
  • He, Gang

Abstract

A method is provided for preparing at least one textured layer in an optoelectronic device. The method includes epitaxially growing a semiconductor layer of the optoelectronic device over a growth substrate; exposing the semiconductor layer to an etching process to create the at least one textured surface on the semiconductor layer; and lifting the optoelectronic device from the growth substrate.

IPC Classes  ?

  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 31/0216 - Coatings
  • H01L 31/0236 - Special surface textures
  • H01L 31/056 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means the light-reflecting means being of the back surface reflector [BSR] type
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 33/22 - Roughened surfaces, e.g. at the interface between epitaxial layers
  • H01L 33/30 - Materials of the light emitting region containing only elements of group III and group V of the periodic system
  • H01L 33/42 - Transparent materials
  • H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
  • H01L 33/46 - Reflective coating, e.g. dielectric Bragg reflector

6.

Methods and systems for identifying features

      
Application Number 16657271
Grant Number 11199501
Status In Force
Filing Date 2019-10-18
First Publication Date 2021-04-22
Grant Date 2021-12-14
Owner UTICA LEASECO, LLC (USA)
Inventor
  • Kumar, Vineet
  • Zand, Katayoun
  • Woo, Howard
  • Gibbs, Markelle L.
  • Bravo Mora, Enrique
  • France, Christopher E.
  • Kayes, Brendan M.

Abstract

Aspects of the present disclosure include methods, apparatuses, and computer readable media for transmitting a light such that it is incident on a multi-layer stack, wherein the multi-layer stack includes the feature and a region without the feature, detecting a narrow-band light from the feature and the region without the feature, wherein the feature has a first optical response in response to a wavelength of the narrow-band light and the region without the feature has a second optical response in response to the wavelength of the narrow-band light, and generating, based on the narrow-band light, an image indicative of where the first optical response and the second optical response occur on the multi-layer stack.

IPC Classes  ?

  • G01N 21/64 - Fluorescence; Phosphorescence
  • G01N 21/33 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using ultraviolet light
  • G01N 21/47 - Scattering, i.e. diffuse reflection
  • G02B 6/42 - Coupling light guides with opto-electronic elements
  • H04N 5/33 - Transforming infrared radiation
  • H01S 3/00 - Lasers, i.e. devices using stimulated emission of electromagnetic radiation in the infrared, visible or ultraviolet wave range
  • G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means

7.

Gas trap system having a conical inlet condensation region

      
Application Number 16595939
Grant Number 11583793
Status In Force
Filing Date 2019-10-08
First Publication Date 2021-04-08
Grant Date 2023-02-21
Owner UTICA LEASECO, LLC (USA)
Inventor Wang, Chaowei

Abstract

A gas trap system for metal organic chemical vapor deposition (MOCVD) exhaust abatement operations is provided. The gas trap system may include a housing including an inlet configured to receive exhaust gas and an outlet. The gas trap system may also include a conical inlet shield positioned within the housing. The conical inlet shield may form a first path between the housing and the conical inlet shield, wherein the first path receives the exhaust gas from the inlet. The conical inlet shield may also cool the exhaust gas and cause the exhaust gas to be uniformly distributed in the first path. The gas trap system may also include a filter configured to receive the exhaust gas from the first path and to filter the exhaust gas, wherein the filtered gas exhaust is provided to the outlet.

IPC Classes  ?

  • B01D 8/00 - Cold traps; Cold baffles
  • B01D 35/30 - Filter housing constructions
  • B01D 53/00 - Separation of gases or vapours; Recovering vapours of volatile solvents from gases; Chemical or biological purification of waste gases, e.g. engine exhaust gases, smoke, fumes, flue gases or aerosols
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating

8.

Modules incorporating encapsulation layers

      
Application Number 16592124
Grant Number 11075128
Status In Force
Filing Date 2019-10-03
First Publication Date 2021-04-08
Grant Date 2021-07-27
Owner UTICA LEASECO, LLC (USA)
Inventor Vijh, Aarohi Surya

Abstract

Aspects of the present disclosure include a packaged product including a product, a first encapsulation disposed on top of the product, wherein the first encapsulation is configured to protect the product during an operation of the product, a second encapsulation disposed on top of the first encapsulation, wherein the second encapsulation is configured to protect the product during a testing of the product, and a third encapsulation disposed on top of the second encapsulation, wherein the third encapsulation is configured to protect the product during a transport of the product, wherein at least one of the first encapsulation, the second encapsulation, or the third encapsulation is detachably coupled with the product.

IPC Classes  ?

9.

Systems and methods for measuring electrical characteristics of a material using a non-destructive multi-point probe

      
Application Number 16460432
Grant Number 11442090
Status In Force
Filing Date 2019-07-02
First Publication Date 2021-01-07
Grant Date 2022-09-13
Owner Utica Leaseco, LLC (USA)
Inventor
  • Limpinsel, Jan Moritz
  • Semonin, Octavi Santiago Escala
  • Rodriguez, Edwin J.
  • Kayes, Brendan M.
  • Faifer, Vladimir N.

Abstract

This disclosure describes an elastic multi-contact probe that includes conductive strips each of which comprises a conductive elastomer; dielectric strips formed on a back surface of a respective conductive strip; and a layer of a thermoplastic formed on back surfaces of the dielectric strips. The disclosure also describes a method that includes measuring a first I-V curve between a pair of inner probes of the an elastic multi-contact probe based on a first current applied to a pair of outer probes; determining a first slope of a linear region of the first I-V curve; measuring a second I-V curve between the pair of inner probes based on a second current applied to the pair of inner probes; determining a second slope of a linear region of the second I-V curve; and calculating a sheet resistance and a contact resistivity of the semiconductor material based on the first and second slopes.

IPC Classes  ?

  • G01R 27/08 - Measuring resistance by measuring both voltage and current
  • G01R 1/073 - Multiple probes
  • G01R 31/26 - Testing of individual semiconductor devices

10.

Sputtered then evaporated back metal process for increased throughput

      
Application Number 16399012
Grant Number 11107942
Status In Force
Filing Date 2019-04-30
First Publication Date 2020-11-05
Grant Date 2021-08-31
Owner UTICA LEASECO, LLC (USA)
Inventor
  • Semonin, Octavi Santiago Escala
  • Furler, Reto Adrian
  • Majidi, Hasti
  • Hessler, Kirsten Sydney

Abstract

A method is described that includes sputtering multiple layers on a back surface of the photovoltaic structure, the photovoltaic structure being made of at least one group III-V semiconductor material, and evaporating, over the multiple layers, one or more additional layers including a metal layer, the back metal structure being formed by the multiple layers and the additional layers. A photovoltaic device is also described that includes a back metal structure disposed over a back surface of a photovoltaic structure made of a group III-V semiconductor material, the back metal structure including one or more evaporated layers disposed over multiple sputtered layers, the one or more evaporated layers including a metal layer. By allowing evaporation along with sputtering, tool size and costs can be reduced, including minimizing a number of vacuum breaks. Moreover, good yield and reliability, such as reducing dark line defects (DLDs), can also be achieved.

IPC Classes  ?

  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/0216 - Coatings
  • H01L 31/054 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/0725 - Multiple junction or tandem solar cells
  • H01L 31/056 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means the light-reflecting means being of the back surface reflector [BSR] type
  • H01L 31/0687 - Multiple junction or tandem solar cells

11.

Laser-textured thin-film semiconductors by melting and ablation

      
Application Number 16373305
Grant Number 11393938
Status In Force
Filing Date 2019-04-02
First Publication Date 2020-10-08
Grant Date 2022-07-19
Owner UTICA LEASECO, LLC (USA)
Inventor
  • Semonin, Octavi Santiago Escala
  • Patterson, Daniel Guilford
  • Furler, Reto Adrian
  • Ritenour, Andrew James

Abstract

A photovoltaic device and a method of making the photovoltaic device are disclosed. The photovoltaic device may include a semiconductor layer epitaxially grown using a compound semiconductor material, such as a group III-V semiconductor material, wherein a surface of the semiconductor layer is textured via one or more laser pulses of a laser. The photovoltaic device may also include a dielectric layer deposited over the textured surface of the semiconductor layer, and a back metal reflector provided on the dielectric layer. The textured surface extends a path of light traveling through the photovoltaic device to increase absorption of the light within the photovoltaic device.

IPC Classes  ?

  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H01L 31/0236 - Special surface textures
  • H01L 31/056 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means the light-reflecting means being of the back surface reflector [BSR] type
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

12.

Front metal contact stack

      
Application Number 16370473
Grant Number 11257978
Status In Force
Filing Date 2019-03-29
First Publication Date 2020-10-01
Grant Date 2022-02-22
Owner UTICA LEASECO, LLC (USA)
Inventor
  • Saldivar-Valdes, Abraham
  • Semonin, Octavi Santiago Escala

Abstract

A photovoltaic device and a method of forming a contact stack of the photovoltaic device are disclosed. The photovoltaic device may include a first layer deposited on a semiconductor layer including a compound semiconductor material. The photovoltaic device may also include a dopant layer comprising tin (Sn) deposited on the first layer. The photovoltaic device may further include a conductive layer deposited or provided over the dopant layer to form a contact stack with the first layer and the dopant layer.

IPC Classes  ?

  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/06 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H01L 31/0224 - Electrodes
  • H01L 31/0693 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells
  • H01L 31/20 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor material
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells

13.

Energy device for use in electronic devices

      
Application Number 16264324
Grant Number 11356052
Status In Force
Filing Date 2019-01-31
First Publication Date 2020-08-06
Grant Date 2022-06-07
Owner UTICA LEASECO, LLC (USA)
Inventor Vijh, Aarohi Surya

Abstract

The present disclosure describes an energy device with a solar module having a form factor configured to be inserted into and to match an inner portion of a coin-type cell holder of an electronic device. The solar module includes one or more photovoltaic cells to capture energy from ambient light and a pair of electrodes. The energy device may be configured to provide, to the electronic device via contact with the coin-type cell holder, electric energy produced from the ambient light energy. The solar module may include a converter module to convert the ambient light energy into the electric energy. The energy device may also include an energy storage module and/or a power management module that are stackable below the solar module with electrical connectivity to the solar module, and that combined with the solar module have the appropriate form factor for the coin-type cell holder.

IPC Classes  ?

  • H02S 30/00 - Structural details of PV modules other than those related to light conversion
  • H02S 40/30 - Electrical components
  • H02S 10/20 - Systems characterised by their energy storage means

14.

Systems and methods for shingling cells using an adhesive film

      
Application Number 16257569
Grant Number 11107939
Status In Force
Filing Date 2019-01-25
First Publication Date 2020-07-30
Grant Date 2021-08-31
Owner UTICA LEASECO, LLC (USA)
Inventor
  • Krajewski, Todd Allen
  • Tolentino, Jason

Abstract

This disclosure describes various structures, devices, and arrangements that replace a PSA used to hold shingled cells together with an adhesive film. For example, in an aspect, the present disclosure is directed to a shingled arrangement of photovoltaic (PV) cells. In some aspects, the shingled arrangement of PV cells may include a first PV cell, a second PV cell, and an adhesive film placed between a backside the first PV cell and a front side of the second PV cell. The adhesive film may be thermally bonded to the first PV cell and to the second PV cell after the application of localized heat and pressure and holds the first PV cell and the second PV cell together. Additionally, a bus bar of the second PV cell may be electrically connected to the first PV cell by a conductive via formed through the adhesive film.

IPC Classes  ?

  • H02N 6/00 - Generators in which light radiation is directly converted into electrical energy (solar cells or assemblies thereof H01L 25/00, H01L 31/00)
  • H01L 31/042 - PV modules or arrays of single PV cells
  • H01L 31/048 - Encapsulation of modules
  • H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • C09J 7/38 - Pressure-sensitive adhesives [PSA]
  • C09J 7/29 - Laminated material
  • B32B 7/12 - Interconnection of layers using interposed adhesives or interposed materials with bonding properties

15.

Optoelectronic devices manufactured using different growth substrates

      
Application Number 16657765
Grant Number 11075313
Status In Force
Filing Date 2019-10-18
First Publication Date 2020-04-16
Grant Date 2021-07-27
Owner UTICA LEASECO, LLC (USA)
Inventor
  • Jain, Nikhil
  • Ritenour, Andrew J.
  • Rau, Ileana
  • Canizares, Claudio
  • Washington, Lori D.
  • He, Gang
  • Kayes, Brendan M.

Abstract

A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L 31/0725 - Multiple junction or tandem solar cells
  • H01L 31/0687 - Multiple junction or tandem solar cells
  • H01L 31/076 - Multiple junction or tandem solar cells
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/0236 - Special surface textures
  • H01L 31/056 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means the light-reflecting means being of the back surface reflector [BSR] type
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/054 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means

16.

Methods of manufacturing optoelectronic devices using different growth substrates

      
Application Number 16657802
Grant Number 10873001
Status In Force
Filing Date 2019-10-18
First Publication Date 2020-04-16
Grant Date 2020-12-22
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Jain, Nikhil
  • Ritenour, Andrew J.
  • Rau, Ileana
  • Canizares, Claudio
  • Washington, Lori D.
  • He, Gang
  • Kayes, Brendan M.

Abstract

A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

17.

Versatile flexible circuit interconnection for connecting two flexible solar cells

      
Application Number 16570882
Grant Number 11205993
Status In Force
Filing Date 2019-09-13
First Publication Date 2020-01-23
Grant Date 2021-12-21
Owner UTICA LEASECO, LLC (USA)
Inventor
  • France, Christopher Earl
  • Yang, Linlin
  • Lan, Liguang

Abstract

A flexible circuit that allows a standardized connection interface to connect flexible solar cell(s) for easy integration into electronics devices. This interconnection scheme does not limit the intrinsic solar cell flexibility and may conform to standard design practices in electronic device manufacturing. In an aspect, a solar module is described that includes one or more solar panels and a flexible trace or interconnect having conductive wires inside an insulation material. In another aspect, an electronic device is described that includes a circuit board, one or more solar panels and a flexible trace or interconnect having conductive wires inside an insulation material. The electronic device may be an internet-of-things (IoT) device or an unmanned aerial vehicle (UAV), for example. In yet another aspect, a lighting module is described that includes one or more lighting panels and a flexible trace or interconnect having conductive wires inside an insulation material.

IPC Classes  ?

  • H01L 31/042 - PV modules or arrays of single PV cells
  • H02N 6/00 - Generators in which light radiation is directly converted into electrical energy (solar cells or assemblies thereof H01L 25/00, H01L 31/00)
  • H02S 40/36 - Electrical components characterised by special electrical interconnection means between two or more PV modules, e.g. electrical module-to-module connection
  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
  • H01L 51/00 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
  • H01L 51/44 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation - Details of devices
  • H01L 31/046 - PV modules composed of a plurality of thin film solar cells deposited on the same substrate
  • H02S 40/32 - Electrical components comprising DC/AC inverter means associated with the PV module itself, e.g. AC modules
  • H02S 40/38 - Energy storage means, e.g. batteries, structurally associated with PV modules
  • H01L 31/0224 - Electrodes
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/0392 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

18.

Planarization of photovoltaics

      
Application Number 16585436
Grant Number 11616154
Status In Force
Filing Date 2019-09-27
First Publication Date 2020-01-23
Grant Date 2023-03-28
Owner UTICA LEASECO, LLC (USA)
Inventor Krajewski, Todd

Abstract

Various processes can apply pressure and/or heat to a photovoltaic (PV) layer, including processes that integrate solar cells into different types of industrial glass such as an autoclave lamination process. The disclosure describes a planarization technique that can be used on the PV layer to eliminate point loads caused by such processes. In an aspect, a method for producing a component is described that includes disposing or placing a planarization material on a PV layer, modifying a physical form of the planarization material to provide a planar surface made of the planarization material on one side of the PV layer having surface irregularities, and forming a stack of layers (e.g., as part of an autoclave lamination process) for the component by disposing a first layer over the planar surface on the one side of the PV layer and a second layer over the other, opposite side of the PV layer.

IPC Classes  ?

  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/0475 - PV cell arrays made by cells in a planar, e.g. repetitive, configuration on a single semiconductor substrate; PV cell microarrays
  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H01L 31/0256 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by the material
  • H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells

19.

Versatile flexible circuit interconnection for flexible solar modules

      
Application Number 16570927
Grant Number 11201585
Status In Force
Filing Date 2019-09-13
First Publication Date 2020-01-16
Grant Date 2021-12-14
Owner UTICA LEASECO, LLC (USA)
Inventor
  • France, Christopher Earl
  • Yang, Linlin
  • Lan, Liguang

Abstract

A flexible circuit that allows a standardized connection interface to connect flexible solar cell(s) for easy integration into electronics devices. This interconnection scheme does not limit the intrinsic solar cell flexibility and may conform to standard design practices in electronic device manufacturing. In an aspect, a solar module is described that includes one or more solar panels and a flexible trace or interconnect having conductive wires inside an insulation material. In another aspect, an electronic device is described that includes a circuit board, one or more solar panels and a flexible trace or interconnect having conductive wires inside an insulation material. The electronic device may be an internet-of-things (IoT) device or an unmanned aerial vehicle (UAV), for example. In yet another aspect, a lighting module is described that includes one or more lighting panels and a flexible trace or interconnect having conductive wires inside an insulation material.

IPC Classes  ?

  • H01L 31/042 - PV modules or arrays of single PV cells
  • H02N 6/00 - Generators in which light radiation is directly converted into electrical energy (solar cells or assemblies thereof H01L 25/00, H01L 31/00)
  • H02S 40/36 - Electrical components characterised by special electrical interconnection means between two or more PV modules, e.g. electrical module-to-module connection
  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
  • H01L 51/00 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
  • H01L 51/44 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation - Details of devices
  • H01L 31/046 - PV modules composed of a plurality of thin film solar cells deposited on the same substrate
  • H02S 40/32 - Electrical components comprising DC/AC inverter means associated with the PV module itself, e.g. AC modules
  • H02S 40/38 - Energy storage means, e.g. batteries, structurally associated with PV modules
  • H01L 31/0224 - Electrodes
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/0392 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

20.

Thin-film, flexible optoelectronic devices incorporating a single lattice-matched dilute nitride junction and methods of fabrication

      
Application Number 16011531
Grant Number 10797197
Status In Force
Filing Date 2018-06-18
First Publication Date 2019-12-19
Grant Date 2020-10-06
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Jain, Nikhil
  • Kayes, Brendan M.
  • He, Gang

Abstract

A thin film, flexible optoelectronic device is described. In an aspect, a method for fabricating a single junction optoelectronic device includes forming a p-n structure on a substrate, the p-n structure including a semiconductor having a lattice constant that matches a lattice constant of substrate, the semiconductor including a dilute nitride, and the single-junction optoelectronic device including the p-n structure; and separating the single-junction optoelectronic device from the substrate. The dilute nitride includes one or more of GaInNAs, GaInNAsSb, alloys thereof, or derivatives thereof.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/0216 - Coatings
  • H01L 31/0232 - Optical elements or arrangements associated with the device
  • H01L 31/0687 - Multiple junction or tandem solar cells
  • H01L 31/0725 - Multiple junction or tandem solar cells
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/20 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor material
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

21.

Forming front metal contact on solar cell with enhanced resistance to stress

      
Application Number 16427142
Grant Number 11257965
Status In Force
Filing Date 2019-05-30
First Publication Date 2019-09-19
Grant Date 2022-02-22
Owner UTICA LEASECO, LLC (USA)
Inventor
  • Yang, Linlin
  • Lan, Liguang
  • France, Chris
  • He, Gang
  • Li, Erhong
  • Corbacho, Jose

Abstract

System and method of providing a photovoltaic (PV) cell having a cushion layer to alleviate stress impact between a front metal contact and a thin film PV layer. A cushion layer is disposed between an extraction electrode and a photovoltaic (PV) surface. The cushion layer is made of a nonconductive material and has a plurality of vias filled with a conductive material to provide electrical continuity between the bus bar and the PV layer. The cushion layer may be made of a flexible material preferably with rigidity that matches the substrate. Thus, the cushion layer can effectively protect the PV layer from physical damage due to tactile contact with the front metal contact.

IPC Classes  ?

  • H01L 31/0224 - Electrodes
  • H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
  • H01L 31/0693 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells
  • H01L 31/0445 - PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/048 - Encapsulation of modules
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

22.

Photovoltaic device

      
Application Number 16404602
Grant Number 10505058
Status In Force
Filing Date 2019-05-06
First Publication Date 2019-08-22
Grant Date 2019-12-10
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Archer, Melissa J.
  • Gmitter, Thomas J.
  • He, Gang
  • Higashi, Gregg

Abstract

Methods and apparatus are provided for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells. One embodiment of the present invention provides a photovoltaic (PV) device. The PV device comprises an absorber layer made of a compound semiconductor; and an emitter layer located closer than the absorber layer to a first side of the device. The PV device includes a p-n junction formed between the emitter layer and the absorber layer, the p-n junction causing a voltage to be generated in the device in response to the device being exposed to light at a second side of the device. Such innovations may allow for greater efficiency and flexibility in PV devices when compared to conventional solar cells.

IPC Classes  ?

  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/068 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
  • H01L 31/065 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the graded gap type
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/0236 - Special surface textures
  • H01L 31/0224 - Electrodes
  • H01L 31/0693 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells
  • H01L 31/056 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means the light-reflecting means being of the back surface reflector [BSR] type

23.

Self-bypass diode function for gallium arsenide photovoltaic devices

      
Application Number 16277749
Grant Number 11121272
Status In Force
Filing Date 2019-02-15
First Publication Date 2019-06-13
Grant Date 2021-09-14
Owner UTICA LEASECO, LLC (USA)
Inventor
  • Ritenour, Andrew J.
  • Kayes, Brendan M.
  • Nie, Hui
  • Kizilyalli, Isik

Abstract

Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide and an emitter layer. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect. The absorber or base layer has a grading in doping concentration from a first doping level closest to the emitter layer to a second doping level away from the emitter layer, the second doping level being greater than the first doping level.

IPC Classes  ?

  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/0443 - PV modules or arrays of single PV cells including bypass diodes comprising bypass diodes integrated or directly associated with the devices, e.g. bypass diodes integrated or formed in or on the same substrate as the photovoltaic cells
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 27/142 - Energy conversion devices

24.

Growth structure under a release layer for manufacturing of optoelectronic devices

      
Application Number 16008919
Grant Number 10811557
Status In Force
Filing Date 2018-06-14
First Publication Date 2018-12-20
Grant Date 2020-10-20
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Ritenour, Andrew J.
  • Rau, Ileana
  • Canizares, Claudio
  • Washington, Lori D.
  • Kayes, Brendan M.
  • He, Gang

Abstract

A growth structure having a lattice transition under a release layer is used as a seed crystal for growth of optoelectronic devices. The optoelectronic device can be a single- or multi-junction photovoltaic device. The release layer can be selectively removed in an epitaxial lift-off (ELO) process to separate the optoelectronic device from the growth structure and leave the region with the lattice transition intact to reuse the growth structure to grow additional devices. A manufacturing method is described that includes providing a growth structure having a substrate and a lattice transition from a first lattice constant to a second lattice constant, depositing a release layer on the growth structure, depositing on the release layer an epitaxial layer having a lattice constant that matches the second lattice and including an optoelectronic device, and removing the release layer to separate the epitaxial layer and the optoelectronic device from the growth structure.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/0687 - Multiple junction or tandem solar cells
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

25.

Methods for chemical vapor deposition (CVD) in a movable liner assembly

      
Application Number 15971571
Grant Number 10718051
Status In Force
Filing Date 2018-05-04
First Publication Date 2018-09-06
Grant Date 2020-07-21
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Higashi, Gregg
  • Sorabji, Khurshed
  • Washington, Lori D.

Abstract

An example method for chemical vapor deposition (CVD) of thin films includes providing a deposition zone in a reaction chamber having a fixed showerhead assembly that introduces CVD reactive gases under positive pressure into the deposition zone. The example method also includes moving a substrate carrier beneath the showerhead assembly in the reaction chamber, the substrate carrier supports and transports at least one substrate within the reaction chamber so as to be subjected to a CVD process by the CVD reactive gases. The example method also includes providing a liner assembly shrouding the deposition zone and including at least one partial enclosure around the deposition zone isolating the deposition zone and the substrate carrier, whereby solid reaction byproducts are plated onto material in the liner assembly and gaseous reaction byproducts flow radially outward, the liner assembly being mounted on the substrate carrier for motion with the substrate carrier.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/48 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation

26.

Multi-junction optoelectronic device with group IV semiconductor as a bottom junction

      
Application Number 15957446
Grant Number 11271133
Status In Force
Filing Date 2018-04-19
First Publication Date 2018-08-30
Grant Date 2022-03-08
Owner UTICA LEASECO, LLC (USA)
Inventor
  • Kayes, Brendan M.
  • He, Gang

Abstract

A multi-junction optoelectronic device and method of manufacture are disclosed. The method comprises providing a first p-n structure on a substrate, wherein the first p-n structure comprises a first base layer of a first semiconductor with a first bandgap such that a lattice constant of the first semiconductor matches a lattice constant of the substrate, and wherein the first semiconductor comprises a Group III-V semiconductor. The method includes providing a second p-n structure, wherein the second p-n structure comprises a second base layer of a second semiconductor with a second bandgap, wherein a lattice constant of the second semiconductor matches a lattice constant of the first semiconductor, and wherein the second semiconductor comprises a Group IV semiconductor. The method also includes lifting off the substrate the multi-junction optoelectronic device having the first p-n structure and the second p-n structure, wherein the multi-junction optoelectronic device is a flexible device.

IPC Classes  ?

  • H01L 31/0687 - Multiple junction or tandem solar cells
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/028 - Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 33/04 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
  • H01L 33/30 - Materials of the light emitting region containing only elements of group III and group V of the periodic system

27.

Optoelectronic devices including heterojunction and intermediate layer

      
Application Number 15958844
Grant Number 10916676
Status In Force
Filing Date 2018-04-20
First Publication Date 2018-08-23
Grant Date 2021-02-09
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Kayes, Brendan M.
  • Nie, Hui
  • Kizilyalli, Isik C.

Abstract

Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device and is made of a different material and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. An intermediate layer is located between the absorber layer and the emitter layer and provides the offset of the p-n junction from the heterojunction, and includes a graded layer and an ungraded back window layer.

IPC Classes  ?

  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/0224 - Electrodes
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

28.

High throughput polishing system for workpieces

      
Application Number 15953064
Grant Number 11267095
Status In Force
Filing Date 2018-04-13
First Publication Date 2018-08-16
Grant Date 2022-03-08
Owner UTICA LEASECO, LLC (USA)
Inventor
  • Fisher, Stephen M.
  • Banerjee, Robindranath
  • Beaudry, Christopher L.
  • Brown, Brian J.

Abstract

A method and system for polishing a plurality of workpieces is disclosed. The method and system comprises providing a polishing tool with multiple polishing heads; and providing a substrate tray that can hold the plurality of work pieces in a fixed position on a tray underneath the polishing heads. The system and method includes moving the tray within the polisher. Finally, the method and system includes configuring the multiple polishing heads with the appropriate pad/slurry combinations to polish the workpieces and to create a finished polished surface on the plurality of work pieces.

IPC Classes  ?

  • B24B 7/22 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
  • B24B 37/10 - Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping
  • B24B 41/00 - Component parts of grinding machines or devices, such as frames, beds, carriages or headstocks
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • B24B 27/00 - Other grinding machines or devices
  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • B24B 37/34 - Accessories
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

29.

Pressurized heated rolling press for manufacture and method of use

      
Application Number 15934380
Grant Number 11211517
Status In Force
Filing Date 2018-03-23
First Publication Date 2018-07-26
Grant Date 2021-12-28
Owner UTICA LEASECO, LLC (USA)
Inventor
  • Sorabji, Khurshed
  • Yoshida, Steven
  • Sanford, Eric

Abstract

A system for connecting photovoltaic cells is disclosed. The system comprises a flexible component feeder source for feeding the photovoltaic cells to a process that couples them together; a vacuum conveyor for receiving at a first location the coupled photovoltaic cells and including openings through which a vacuum is applied to hold the coupled photovoltaic cells in place; a moving belt above the vacuum conveyor at a second location, where the vacuum conveyor and the moving belt are driven in a predetermined relation to one another for conveying the coupled photovoltaic cells from the first location to the second location; a vacuum source for applying a vacuum through the openings to cause the moving belt to apply a pressure to an upper surface of the coupled photovoltaic cells to compress the coupled photovoltaic cells; and a curing source at the second location for curing the compressed coupled photovoltaic cells.

IPC Classes  ?

  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • B65G 15/16 - Conveyors having endless load-conveying surfaces, i.e. belts and like continuous members, to which tractive effort is transmitted by means other than endless driving elements of similar configuration comprising two or more co-operating endless surfaces with parallel longitudinal axes, or a multiplicity of parallel elements, e.g. ropes defining an endless surface with two or more endless belts the load being conveyed between the belts between an auxiliary belt and a main belt
  • B65G 21/20 - Means incorporated in, or attached to, framework or housings for guiding load-carriers, traction elements or loads supported on moving surfaces
  • F16B 47/00 - Suction cups for attaching purposes; Equivalent means using adhesives

30.

Off-axis epitaxial lift off process

      
Application Number 15876001
Grant Number 10337087
Status In Force
Filing Date 2018-01-19
First Publication Date 2018-06-07
Grant Date 2019-07-02
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Gmitter, Thomas
  • He, Gang
  • Archer, Melissa
  • Neo, Siew

Abstract

Embodiments described herein provide processes for forming and removing epitaxial films and materials from growth wafers by epitaxial lift off (ELO) processes. In some embodiments, the growth wafer has edge surfaces with an off-axis orientation which is utilized during the ELO process. The off-axis orientation of the edge surface provides an additional variable for controlling the etch rate during the ELO process and therefore the etch front may be modulated to prevent the formation of high stress points which reduces or prevents stressing and cracking the epitaxial film stack. In one embodiment, the growth wafer is rectangular and has an edge surface with an off-axis orientation rotated by an angle greater than 0° and up to 90° relative to an edge orientation of <110> at 0°.

IPC Classes  ?

  • C22C 29/00 - Alloys based on carbides, oxides, borides, nitrides or silicides, e.g. cermets, or other metal compounds, e. g. oxynitrides, sulfides
  • C30B 33/06 - Joining of crystals
  • C30B 29/42 - Gallium arsenide
  • C30B 29/40 - AIIIBV compounds
  • C30B 33/08 - Etching
  • C30B 29/00 - Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B 33/10 - Etching in solutions or melts

31.

High throughput polishing system for workpieces

      
Application Number 13434726
Grant Number 09950404
Status In Force
Filing Date 2012-03-29
First Publication Date 2018-04-24
Grant Date 2018-04-24
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Fisher, Stephen M.
  • Banerjee, Robindranath
  • Beaudry, Christopher L.
  • Brown, Brian J.

Abstract

A method and system for polishing a plurality of workpieces is disclosed. The method and system comprises providing a polishing tool with multiple polishing heads; and providing a substrate tray that can hold the plurality of work pieces in a fixed position on a tray underneath the polishing heads. The system and method includes moving the tray within the polisher. Finally, the method and system includes configuring the multiple polishing heads with the appropriate pad/slurry combinations to polish the workpieces and to create a finished polished surface on the plurality of work pieces.

IPC Classes  ?

  • B24B 37/04 - Lapping machines or devices; Accessories designed for working plane surfaces
  • B24B 7/22 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain

32.

Charging station for mobile device with solar panel

      
Application Number 15809576
Grant Number 11387681
Status In Force
Filing Date 2017-11-10
First Publication Date 2018-03-15
Grant Date 2022-07-12
Owner UTICA LEASECO, LLC (USA)
Inventor
  • He, Gang
  • Kayes, Brendan
  • France, Christopher

Abstract

A charging device configured to charge a mobile device through the solar cells integrated on the mobile device. The charging device converts wall power to light energy which can be absorbed by the solar cells and then converted to electricity for storage in the rechargeable battery of the mobile device. The charging device includes a light source configured to emit a light beam having a spectrum tuned to the spectral response of the solar cells. The charging device includes a proximity sensor for detecting the presence of a mobile device within the charging device housing and responsively signaling the activation of the light source. The charging device includes logic for wirelessly communicating with the mobile device as well as controlling the charging process in various stages and aspects. The light source may be LEDs that also serve to transmit light communication signals to the mobile device.

IPC Classes  ?

  • H02J 50/30 - Circuit arrangements or systems for wireless supply or distribution of electric power using light, e.g. lasers
  • H02J 7/35 - Parallel operation in networks using both storage and other dc sources, e.g. providing buffering with light sensitive cells
  • H02J 50/90 - Circuit arrangements or systems for wireless supply or distribution of electric power involving detection or optimisation of position, e.g. alignment
  • H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
  • H02J 7/02 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from ac mains by converters

33.

Methods for high growth rate deposition for forming different cells on a wafer

      
Application Number 15717694
Grant Number 11393683
Status In Force
Filing Date 2017-09-27
First Publication Date 2018-01-18
Grant Date 2022-07-19
Owner UTICA LEASECO, LLC (USA)
Inventor
  • Washington, Lori D.
  • Bour, David P.
  • Higashi, Gregg
  • He, Gang

Abstract

Aspects of the disclosure relate to processes for epitaxial growth of Group III/V materials at high rates, such as about 30 μm/hr or greater, for example, about 40 μm/hr, about 50 μm/hr, about 55 μm/hr, about 60 μm/hr, about 70 μm/hr, about 80 μm/hr, and about 90-120 μm/hr deposition rates. The Group III/V materials or films may be utilized in solar, semiconductor, or other electronic device applications. The Group III/V materials may be formed or grown on a sacrificial layer disposed on or over the support substrate during a vapor deposition process. Subsequently, the Group III/V materials may be removed from the support substrate during an epitaxial lift off (ELO) process. The Group III/V materials are thin films of epitaxially grown layers containing gallium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium arsenide nitride, gallium aluminum indium phosphide, phosphides thereof, nitrides thereof, derivatives thereof, alloys thereof, or combinations thereof.

IPC Classes  ?

34.

Multi-junction optoelectronic device

      
Application Number 13705064
Grant Number 09768329
Status In Force
Filing Date 2012-12-04
First Publication Date 2017-09-19
Grant Date 2017-09-19
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Kayes, Brendan M.
  • He, Gang
  • Spruytte, Sylvia
  • Ding, I-Kang
  • Higashi, Gregg

Abstract

An optoelectronic semiconductor device is disclosed. The optoelectronic device comprises a plurality of stacked p-n junctions. The optoelectronic semiconductor device includes a n-doped layer disposed below the p-doped layer to form a p-n layer such that electric energy is created when photons are absorbed by the p-n layer. Recesses are formed on top of the p-doped layer at the top of the plurality of stacked p-n junctions. The junctions create an offset and an interface layer is formed on top of the p-doped layer at the top of the plurality stacked p-n junctions. The optoelectronic semiconductor device also includes a window layer disposed below the plurality stacked p-n junctions. In another aspect, one or more optical filters are inserted into a multi-junction photovoltaic device to enhance its efficiency through photon recycling.

IPC Classes  ?

  • H01L 31/109 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN heterojunction type
  • H01L 31/0232 - Optical elements or arrangements associated with the device
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells

35.

Versatile flexible circuit interconnection for flexible solar cells

      
Application Number 15372085
Grant Number 10418933
Status In Force
Filing Date 2016-12-07
First Publication Date 2017-06-08
Grant Date 2019-09-17
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • France, Christopher Earl
  • Yang, Linlin
  • Lan, Liguang

Abstract

A flexible circuit that allows a standardized connection interface to connect flexible solar cell(s) for easy integration into electronics devices. This interconnection scheme does not limit the intrinsic solar cell flexibility and may conform to standard design practices in electronic device manufacturing. In an aspect, a solar module is described that includes one or more solar panels and a flexible trace or interconnect having conductive wires inside an insulation material. In another aspect, an electronic device is described that includes a circuit board, one or more solar panels and a flexible trace or interconnect having conductive wires inside an insulation material. The electronic device may be an internet-of-things (IoT) device or an unmanned aerial vehicle (UAV), for example. In yet another aspect, a lighting module is described that includes one or more lighting panels and a flexible trace or interconnect having conductive wires inside an insulation material.

IPC Classes  ?

  • H02N 6/00 - Generators in which light radiation is directly converted into electrical energy (solar cells or assemblies thereof H01L 25/00, H01L 31/00)
  • H01L 31/042 - PV modules or arrays of single PV cells
  • H02S 40/36 - Electrical components characterised by special electrical interconnection means between two or more PV modules, e.g. electrical module-to-module connection
  • H01L 31/046 - PV modules composed of a plurality of thin film solar cells deposited on the same substrate
  • H02S 40/32 - Electrical components comprising DC/AC inverter means associated with the PV module itself, e.g. AC modules
  • H02S 40/38 - Energy storage means, e.g. batteries, structurally associated with PV modules
  • H01L 31/0224 - Electrodes
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/0392 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H01L 51/44 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation - Details of devices
  • H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
  • H01L 51/00 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof

36.

Thin-film semiconductor optoelectronic device with textured front and/or back surface prepared from etching

      
Application Number 15422218
Grant Number 11038080
Status In Force
Filing Date 2017-02-01
First Publication Date 2017-05-25
Grant Date 2021-06-15
Owner UTICA LEASECO, LLC (USA)
Inventor
  • Zhu, Yan
  • Sweetnam, Sean
  • Kayes, Brendan M.
  • Archer, Melissa J.
  • He, Gang

Abstract

An optoelectronic device having a textured layer is described. In an aspect, a method may be used to produce the optoelectronic device, where the method includes epitaxially growing a semiconductor layer of the optoelectronic device on a growth substrate, and exposing the semiconductor layer to an etching process to create at least one textured surface in the semiconductor layer. The textured semiconductor layer can be referred to as a textured layer. The etching process is performed without the use of a template layer, or similar layer, configured as a mask to generate the texturing. The etching process can be done by one or more of a liquid or solution-based chemical etchant, gas etching, laser etching, plasma etching, or ion etching. The method can also include lifting the semiconductor layer of the optoelectronic device from the growth substrate by, for example, the use of an epitaxial lift off (ELO) process.

IPC Classes  ?

  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 31/0216 - Coatings
  • H01L 33/22 - Roughened surfaces, e.g. at the interface between epitaxial layers
  • H01L 33/30 - Materials of the light emitting region containing only elements of group III and group V of the periodic system
  • H01L 33/42 - Transparent materials
  • H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
  • H01L 33/46 - Reflective coating, e.g. dielectric Bragg reflector
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/056 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means the light-reflecting means being of the back surface reflector [BSR] type
  • H01L 31/0236 - Special surface textures

37.

Forming front metal contact on solar cell with enhanced resistance to stress

      
Application Number 14918043
Grant Number 10483410
Status In Force
Filing Date 2015-10-20
First Publication Date 2017-04-20
Grant Date 2019-11-19
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Yang, Linlin
  • Lan, Liguang
  • France, Chris
  • He, Gang
  • Li, Erhong
  • Corbacho, Jose

Abstract

System and method of providing a photovoltaic (PV) cell having a cushion layer to alleviate stress impact between a front metal contact and a thin film PV layer. A cushion layer is disposed between an extraction electrode and a photovoltaic (PV) surface. The cushion layer is made of a nonconductive material and has a plurality of vias filled with a conductive material to provide electrical continuity between the bus bar and the PV layer. The cushion layer may be made of a flexible material preferably with rigidity that matches the substrate. Thus, the cushion layer can effectively protect the PV layer from physical damage due to tactile contact with the front metal contact.

IPC Classes  ?

  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/048 - Encapsulation of modules
  • H01L 31/0224 - Electrodes
  • H01L 31/0445 - PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
  • H01L 31/0693 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells

38.

Via structures for solar cell interconnection in solar module

      
Application Number 14858808
Grant Number 09711671
Status In Force
Filing Date 2015-09-18
First Publication Date 2017-03-23
Grant Date 2017-07-18
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Yang, Linlin
  • He, Gang
  • Patterson, Dan
  • Goddu, Paul
  • Lan, Liguang
  • Higashi, Gregg

Abstract

System and method of providing a photovoltaic (PV) cell with a complex via structure in the substrate that has a primary via for containing a conductive material and an overflow capture region for capturing an overflow of the conductive material from the primary via. The conductive filling in the primary via may serve as an electrical contact between the PV cell and another PV cell. The overflow capture region includes one or more recesses formed on the substrate back surface. When the conductive material overflows from the primary via, the one or more recesses can capture and confine the overflow within the boundary of the complex via structure. A recess may be a rectangular or circular trench proximate to or overlaying the primary via. The recesses may also be depressions formed by roughening the substrate back surface.

IPC Classes  ?

  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells

39.

Thin-film semiconductor optoelectronic device with textured front and/or back surface prepared from template layer and etching

      
Application Number 15340560
Grant Number 10008628
Status In Force
Filing Date 2016-11-01
First Publication Date 2017-02-16
Grant Date 2018-06-26
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Ding, I-Kang
  • Kayes, Brendan M.
  • Twist, Rose
  • Spruytte, Sylvia
  • Liu, Feng
  • Higashi, Gregg
  • Archer, Melissa J.
  • He, Gang

Abstract

A method for providing a textured layer in an optoelectronic device is disclosed. The method includes depositing a template layer on a first layer. The template layer has significant inhomogeneity either in thickness or in composition, or both, including the possibility of forming one or more islands to provide at least one textured surface of the island layer. The method also includes exposing the template layer and the first layer to an etching process to create or alter at least one textured surface. The altered at least one textured surface is operative to cause scattering of light.

IPC Classes  ?

  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/0236 - Special surface textures
  • H01L 31/0224 - Electrodes
  • H01L 31/056 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means the light-reflecting means being of the back surface reflector [BSR] type
  • H01L 31/0216 - Coatings

40.

Reflector and susceptor assembly for chemical vapor deposition reactor

      
Application Number 14817037
Grant Number 10932323
Status In Force
Filing Date 2015-08-03
First Publication Date 2017-02-09
Grant Date 2021-02-23
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Burrows, Brian
  • Cabreros, Abril
  • Ishikawa, David M.
  • Brown, Brian
  • Lerner, Alexander

Abstract

A reactor for chemical vapor deposition is equipped with an IR radiation compensating susceptor assembly that supports one or more semiconductor substrates above linear IR heater lamps arranged in a parallel array. A set of primary IR radiation reflectors beneath the lamps directs IR radiation back toward the susceptor in a pattern selected to provide uniform IR irradiation of the susceptor assembly to thereby uniformly heat the substrates. Secondary IR shield reflectors may be provided in selected patterns on the underside of the susceptor assembly as a fine tuning measure to direct IR radiation away from the assembly in a controlled pattern. The combined IR radiation reflectors have an IR signature that compensates for any non-uniform heating profile created by the linear IR heater lamp array. The heating profile of the lamp array might also be tailored in order to reduce the amount of compensation required to be supplied by the IR reflectors.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • H05B 3/00 - Ohmic-resistance heating
  • C23C 16/48 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation

41.

Texturing a layer in an optoelectronic device for improved angle randomization of light

      
Application Number 14696106
Grant Number 09537025
Status In Force
Filing Date 2015-04-24
First Publication Date 2017-01-03
Grant Date 2017-01-03
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Kayes, Brendan M.
  • Higashi, Gregg S.
  • Reinhardt, Frank
  • Spruytte, Sylvia

Abstract

Embodiments generally relate to optoelectronic devices and more specifically, to textured layers in optoelectronic devices. In one embodiment, a method for providing a textured layer in an optoelectronic device includes depositing a first layer of a first material and depositing an island layer of a second material on the first layer. Depositing the island layer includes forming one or more islands of the second material to provide at least one textured surface of the island layer, where the textured surface is operative to cause scattering of light.

IPC Classes  ?

  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H01L 31/0236 - Special surface textures
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

42.

Pressurized heated rolling press for manufacture and method of use

      
Application Number 15191410
Grant Number 10076896
Status In Force
Filing Date 2016-06-23
First Publication Date 2016-12-29
Grant Date 2018-09-18
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor Sorabji, Khurshed

Abstract

A method and system for connecting a plurality of materials using pressure and curing is disclosed. The method provides for: a) receiving the plurality of materials on the vacuum conveyor; b) conveying the received plurality of materials from the first location to a second location along the vacuum conveyor; c) applying a predetermined vacuum pressure; and d) curing the compressed plurality of materials. The system comprises a vacuum conveyor for receiving the plurality of materials at a first location, a moving belt adaptively positioned above the vacuum conveyor at a second location and the vacuum conveyor and the moving belt are arranged to be driven in a predetermined relation to one another, a vacuum pressure source for applying a predetermined vacuum pressure creating a force compressing the plurality of materials; and a curing source at a second location for curing the compressed plurality of materials.

IPC Classes  ?

  • B32B 37/10 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the pressing technique, e.g. using direct action of vacuum or fluid pressure
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • B32B 37/06 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the heating method
  • B32B 37/14 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
  • B32B 38/18 - Handling of layers or the laminate

43.

Charging station for mobile device with solar panel

      
Application Number 14989659
Grant Number 09853489
Status In Force
Filing Date 2016-01-06
First Publication Date 2016-07-28
Grant Date 2017-12-26
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • He, Gang
  • Kayes, Brendan
  • France, Christopher

Abstract

A charging device configured to charge a mobile device through the solar cells integrated on the mobile device. The charging device converts wall power to light energy which can be absorbed by the solar cells and then converted to electricity for storage in the rechargeable battery of the mobile device. The charging device includes a light source configured to emit a light beam having a spectrum tuned to the spectral response of the solar cells. The charging device includes a proximity sensor for detecting the presence of a mobile device within the charging device housing and responsively signaling the activation of the light source. The charging device includes logic for wirelessly communicating with the mobile device as well as controlling the charging process in various stages and aspects. The light source may be LEDs that also serve to transmit light communication signals to the mobile device.

IPC Classes  ?

  • H01M 10/44 - Methods for charging or discharging
  • H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
  • H02J 7/35 - Parallel operation in networks using both storage and other dc sources, e.g. providing buffering with light sensitive cells
  • H02J 7/02 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from ac mains by converters
  • H02J 50/30 - Circuit arrangements or systems for wireless supply or distribution of electric power using light, e.g. lasers
  • H02J 50/90 - Circuit arrangements or systems for wireless supply or distribution of electric power involving detection or optimisation of position, e.g. alignment

44.

Perforation of films for separation

      
Application Number 14663683
Grant Number 09859162
Status In Force
Filing Date 2015-03-20
First Publication Date 2016-03-17
Grant Date 2018-01-02
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Sorabji, Khurshed
  • Patterson, Daniel G.

Abstract

A method for separation of semiconductor device cell units from fabricated large-area cell units, together with a corresponding tile unit structure, are provided in which the tile unit is cut along cell unit boundaries while leaving intact a set of specified tab sections distributed along the cell unit boundaries. The tile unit may be a multi-layer composite of a semiconductor layer with a conductive metallic base supported upon a polymer layer and adhered thereto by an adhesive film, wherein tab sections are cut completely through the semiconductor layer and its metallic base from above and may also be cut partially through the polymer layer from below, leaving at least a portion of the polymer layer in place at tab sections. Tile units can be handled such that component cell units are held together by the tab sections, until a physical final separation of selected cell units.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

45.

Tape-based epitaxial lift off apparatuses and methods

      
Application Number 14861821
Grant Number 10204831
Status In Force
Filing Date 2015-09-22
First Publication Date 2016-02-18
Grant Date 2019-02-12
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Gmitter, Thomas
  • He, Gang
  • Archer, Melissa
  • Hegedus, Andreas

Abstract

Embodiments of the invention generally relate to apparatuses and methods for producing epitaxial thin films and devices by epitaxial lift off (ELO) processes. In one embodiment, a method for forming thin film devices during an ELO process is provided which includes coupling a plurality of substrates to an elongated support tape, wherein each substrate contains an epitaxial film disposed over a sacrificial layer disposed over a wafer, exposing the substrates to an etchant during an etching process while moving the elongated support tape, and etching the sacrificial layers and peeling the epitaxial films from the wafers while moving the elongated support tape. Embodiments also include several apparatuses, continuous-type as well as a batch-type apparatuses, for forming the epitaxial thin films and devices, including an apparatus for removing the support tape and epitaxial films from the wafers on which the epitaxial films were grown.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

46.

Tiled showerhead for a semiconductor chemical vapor deposition reactor

      
Application Number 14924488
Grant Number 10066297
Status In Force
Filing Date 2015-10-27
First Publication Date 2016-02-18
Grant Date 2018-09-04
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Higashi, Gregg
  • Lerner, Alexander
  • Sorabji, Khurshed
  • Washington, Lori D.
  • Hegedus, Andreas

Abstract

A showerhead for a semiconductor processing reactor formed by an array of showerhead tiles. Each showerhead tile has a plurality of process gas apertures, which may be in a central area of the tile or may extend over the entire tile. Each showerhead tile can be dimensioned for processing a respective substrate or a plurality of substrates or the array can be dimensioned for processing a substrate. An exhaust region surrounds the process gas apertures. The exhaust region has at least one exhaust aperture, and may include an exhaust slot, a plurality of connected exhaust slots or a plurality of exhaust apertures. The exhaust region surrounds the array of showerhead tiles, or a respective portion of the exhaust region surrounds the plurality of process gas apertures in each showerhead tile or group of showerhead tiles. A gas curtain aperture may be between the exhaust region and the process gas apertures of one of the showerhead tiles or adjacent to the central area of the tile.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations

47.

Thin-film semiconductor optoelectronic device with textured front and/or back surface prepared from template layer and etching

      
Application Number 14452393
Grant Number 09502594
Status In Force
Filing Date 2014-08-05
First Publication Date 2015-11-26
Grant Date 2016-11-22
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Ding, I-Kang
  • Kayes, Brendan M.
  • Twist, Rose
  • Spruytte, Sylvia
  • Liu, Feng
  • Higashi, Gregg
  • Archer, Melissa J.
  • He, Gang

Abstract

A method for providing a textured layer in an optoelectronic device is disclosed. The method includes depositing a template layer on a first layer. The template layer has significant inhomogeneity either in thickness or in composition, or both, including the possibility of forming one or more islands to provide at least one textured surface of the island layer. The method also includes exposing the template layer and the first layer to an etching process to create or alter at least one textured surface. The altered at least one textured surface is operative to cause scattering of light.

IPC Classes  ?

  • H01L 31/0224 - Electrodes
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/0236 - Special surface textures
  • H01L 31/056 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means the light-reflecting means being of the back surface reflector [BSR] type
  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

48.

Tiled showerhead for a semiconductor chemical vapor deposition reactor

      
Application Number 13222890
Grant Number 09175393
Status In Force
Filing Date 2011-08-31
First Publication Date 2015-11-03
Grant Date 2015-11-03
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Higashi, Gregg
  • Sorabji, Khurshed
  • Washington, Lori D.
  • Hegedus, Andreas

Abstract

A showerhead for a semiconductor-processing reactor formed by an array of showerhead tiles. Each showerhead tile has a plurality of process gas apertures, which may be in a central area of the tile or may extend over the entire tile. Each showerhead tile can be dimensioned for processing a respective substrate or the array can be dimensioned for processing a substrate. An exhaust region surrounds the process gas apertures. The exhaust region has at least one exhaust aperture, and may include an exhaust slot, a plurality of connected exhaust slots or a plurality of exhaust apertures. The exhaust region surrounds the array of showerhead tiles, or a respective portion of the exhaust region surrounds the plurality of process gas apertures in each showerhead tile or group of showerhead tiles. A gas curtain aperture may be between the exhaust region and the process gas apertures of one of the showerhead tiles or adjacent to the central area of the tile.

IPC Classes  ?

  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • C23F 1/00 - Etching metallic material by chemical means
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

49.

Epitaxial lift off stack having a pre-curved handle and methods thereof

      
Application Number 14723223
Grant Number 09679814
Status In Force
Filing Date 2015-05-27
First Publication Date 2015-10-01
Grant Date 2017-06-13
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Archer, Melissa
  • Atwater, Harry
  • Gmitter, Thomas
  • He, Gang
  • Hegedus, Andreas
  • Higashi, Gregg
  • Sonnenfeldt, Stewart

Abstract

Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming an ELO thin film is provided which includes depositing an epitaxial material over a sacrificial layer on a substrate, adhering a flattened, pre-curved support handle onto the epitaxial material, and removing the sacrificial layer during an etching process. The etching process includes bending the pre-curved support handle to have substantial curvature while peeling the epitaxial material from the substrate and forming an etch crevice therebetween. Compression is maintained within the epitaxial material during the etching process. The flattened, pre-curved support handle may be formed by flattening a pre-curved support material.

IPC Classes  ?

  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching

50.

Texturing a layer in an optoelectronic device for improved angle randomization of light

      
Application Number 13354175
Grant Number 09136422
Status In Force
Filing Date 2012-01-19
First Publication Date 2015-09-15
Grant Date 2015-09-15
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Higashi, Gregg
  • Kayes, Brendan M.
  • Reinhardt, Frank
  • Spruytte, Sylvia

Abstract

Embodiments generally relate to optoelectronic devices and more specifically, to textured layers in optoelectronic devices. In one embodiment, a method for providing a textured layer in an optoelectronic device includes depositing a first layer of a first material and depositing an island layer of a second material on the first layer. Depositing the island layer includes forming one or more islands of the second material to provide at least one textured surface of the island layer, where the textured surface is operative to cause scattering of light.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

51.

Photovoltaic device with back side contacts

      
Application Number 14706704
Grant Number 10797187
Status In Force
Filing Date 2015-05-07
First Publication Date 2015-08-27
Grant Date 2020-10-06
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • He, Gang
  • Kizilyalli, Isik C.
  • Archer, Melissa J.
  • Atwater, Harry A.
  • Gmitter, Thomas J.
  • Hegedus, Andreas G.
  • Higashi, Gregg S.

Abstract

Methods and apparatus for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells are provided. A photovoltaic (PV) device generally includes a window layer; an absorber layer disposed below the window layer such that electrons are generated when photons travel through the window layer and are absorbed by the absorber layer; and a plurality of contacts for external connection coupled to the absorber layer, such that all of the contacts for external connection are disposed below the absorber layer and do not block any of the photons from reaching the absorber layer through the window layer. Locating all the contacts on the back side of the PV device avoids solar shadows caused by front side contacts, typically found in conventional solar cells. Therefore, PV devices described herein with back side contacts may allow for increased efficiency when compared to conventional solar cells.

IPC Classes  ?

  • H01L 31/0224 - Electrodes
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/0216 - Coatings

52.

Fixture for substrate cutting

      
Application Number 13420414
Grant Number 09114464
Status In Force
Filing Date 2012-03-14
First Publication Date 2015-08-25
Grant Date 2015-08-25
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Ishikawa, David
  • Mattos, Laila

Abstract

A fixture for cutting thin substrates, such as films, wafers, semiconductor layers and the like, using a blade holder assembly joined to a substrate clamp assembly. Each assembly has a plurality of members with the substrate clamp having a base plate that introduces a vacuum environment and a substrate support plate that uses the vacuum to secure the substrate in place. The blade holder assembly has interlocking projections in interleaving sheet members sandwiched between two bracket members that define slots for supporting a knife. Multiple slots allow the blade to be positioned in different positions and different orientations for cutting thin substrates held with vacuum pressure in the substrate clamp assembly.

IPC Classes  ?

  • B26F 1/02 - Perforating by punching, e.g. with relatively-reciprocating punch and bed
  • B21D 22/00 - Shaping without cutting, by stamping, spinning, or deep-drawing
  • H05K 13/02 - Feeding of components
  • B23D 23/00 - Machines or devices for shearing or cutting profiled stock
  • B26D 7/32 - Means for performing other operations combined with cutting for conveying or stacking cut product

53.

Optoelectronic devices including heterojunction and intermediate layer

      
Application Number 14692647
Grant Number 09954131
Status In Force
Filing Date 2015-04-21
First Publication Date 2015-08-13
Grant Date 2018-04-24
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Kayes, Brendan M.
  • Nie, Hui
  • Kizilyalli, Isik C.

Abstract

Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device and is made of a different material and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. An intermediate layer is located between the absorber layer and the emitter layer and provides the offset of the p-n junction from the heterojunction, and includes a graded layer and an ungraded back window layer.

IPC Classes  ?

  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/0224 - Electrodes
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

54.

Device for individual finger isolation in an optoelectronic device

      
Application Number 14480147
Grant Number 09647148
Status In Force
Filing Date 2014-09-08
First Publication Date 2015-01-15
Grant Date 2017-05-09
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor Hegedus, Andreas

Abstract

An optoelectronic device including at least one of a solar device, a semiconductor device, and an electronic device. The device includes a semiconductor unit. A plurality of metal fingers is disposed on a surface of the semiconductor unit for electrical conduction. Each of the metal fingers includes a pad area for forming an electrical contact. The optoelectronic device includes a plurality of pad areas that is available for connection to a bus bar, wherein each of the metal fingers is connected to a corresponding pad area for forming an electrical contact.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 31/0224 - Electrodes
  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 21/66 - Testing or measuring during manufacture or treatment

55.

System and method for improved epitaxial lift off

      
Application Number 14183349
Grant Number 09142707
Status In Force
Filing Date 2014-02-18
First Publication Date 2014-06-12
Grant Date 2015-09-22
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Burrows, Brian
  • Brown, Brian
  • Gmitter, Thomas
  • He, Gang

Abstract

An apparatus, system and method for performing ELO are disclosed. Device assemblies are contemporaneously etched in a stacked arrangement. Each device assembly may be placed in a respective tray, where the trays are overlapped and spaced apart from one another. In this manner, more device assemblies can be etched per unit area compared to conventional systems. Further, by stacking device assemblies during etching, the yield can be improved and/or the cost of the etch tank and associated hardware can be reduced.

IPC Classes  ?

  • B32B 38/10 - Removing layers, or parts of layers, mechanically or chemically
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • B32B 43/00 - Operations specially adapted for layered products and not otherwise provided for, e.g. repairing; Apparatus therefor

56.

Laser cutting through two dissimilar materials separated by a metal foil

      
Application Number 13222686
Grant Number 08728849
Status In Force
Filing Date 2011-08-31
First Publication Date 2014-05-20
Grant Date 2014-05-20
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Mattos, Laila
  • Patterson, Daniel G.

Abstract

A method of laser cutting through dissimilar materials separated by a metal foil. A material stack includes a semiconductor layer or film, with a metal foil layer attached to the back surface. The metal foil layer is attached to an insulative support material layer. A laser parameter is selected and optimized for the material stack. A laser beam creates a kerf in the material stack down to the metal foil layer. The laser beam removes metal through the kerf primarily by gasification rather than melting. Kerf formation continues after optimization of the laser parameter for removal of material from the remaining layers. A debris field resulting from the laser cutting of the metal layer is reduced and/or a portion of the debris is removed in an assisted manner as the beam cuts. The materials are diced by cutting the kerf through all materials.

IPC Classes  ?

  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting

57.

Laser cutting and chemical edge clean for thin-film solar cells

      
Application Number 13223133
Grant Number 08728933
Status In Force
Filing Date 2011-08-31
First Publication Date 2014-05-20
Grant Date 2014-05-20
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Andres, Michael
  • Mattos, Laila
  • Patterson, Daniel G.
  • He, Gang

Abstract

A method of kerf formation and treatment for solar cells and semiconductor films and a system therefor are described. A semiconductor film is backed by a first metal layer and topped by a second metal layer. A reference feature is defined on the film. An ultraviolet laser beam is aligned to the reference feature. A kerf is cut along the reference feature, using the ultraviolet laser beam. The beam cuts through the second metal layer, through the film and through the first metal layer. Cutting leaves debris deposited on walls of the kerf. The debris is cleaned off of the walls, using an acid-based solvent. In the case of solar cells, respective first terminals of the solar cells are electrically isolated by the cleaned kerf, and respective negative terminals of the solar cells are electrically isolated by the cleaned kerf.

IPC Classes  ?

  • H01L 21/4763 - Deposition of non-insulating-, e.g. conductive-, resistive-, layers on insulating layers; After-treatment of these layers

58.

Photovoltaic module containing shingled photovoltaic tiles and fabrication processes thereof

      
Application Number 13397487
Grant Number 10741712
Status In Force
Filing Date 2012-02-15
First Publication Date 2013-08-15
Grant Date 2020-08-11
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • He, Gang
  • Mattos, Laila S.
  • Scully, Shawn

Abstract

A photovoltaic module is disclosed. The photovoltaic module comprises an array of shingled tiles disposed between a transparent front substrate and a back substrate, wherein the array of shingled tiles comprises a plurality of photovoltaic tiles in electrically contact with each other and positioned in overlapping rows. Each photovoltaic tile comprises a front metallic contact layer disposed on an epitaxial film stack disposed on a back metallic contact layer disposed on a support carrier layer. The photovoltaic module includes at least one busbar in electrical contact with the array of shingled tiles and disposed between the front and back glass substrates. The photovoltaic module also includes an encapsulation layer between the front and back glass substrates.

IPC Classes  ?

  • H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H01L 31/048 - Encapsulation of modules
  • H01L 31/0465 - PV modules composed of a plurality of thin film solar cells deposited on the same substrate comprising particular structures for the electrical interconnection of adjacent PV cells in the module
  • H01L 31/042 - PV modules or arrays of single PV cells

59.

Photovoltaic device

      
Application Number 13772043
Grant Number 10326033
Status In Force
Filing Date 2013-02-20
First Publication Date 2013-06-20
Grant Date 2019-06-18
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Archer, Melissa J.
  • Gmitter, Thomas J.
  • He, Gang
  • Higashi, Gregg

Abstract

Methods and apparatus are provided for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells. One embodiment of the present invention provides a photovoltaic (PV) device. The PV device comprises an absorber layer made of a compound semiconductor; and an emitter layer located closer than the absorber layer to a first side of the device. The PV device includes a p-n junction formed between the emitter layer and the absorber layer, the p-n junction causing a voltage to be generated in the device in response to the device being exposed to light at a second side of the device. Such innovations may allow for greater efficiency and flexibility in PV devices when compared to conventional solar cells.

IPC Classes  ?

  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/068 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
  • H01L 31/0224 - Electrodes
  • H01L 31/065 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the graded gap type
  • H01L 31/0693 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells
  • H01L 31/0236 - Special surface textures
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells

60.

Two beam backside laser dicing of semiconductor films

      
Application Number 13222617
Grant Number 08399281
Status In Force
Filing Date 2011-08-31
First Publication Date 2013-03-19
Grant Date 2013-03-19
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Patterson, Daniel G.
  • Mattos, Laila

Abstract

A method and system for dicing semiconductor devices from a semiconductor film. A semiconductor film, backed by a metal layer, is bonded by an adhesive layer to a flexible translucent substrate. Reference features on the film are used to describe a cutting path like a scribe line. An infrared laser beam is aligned to the scribe lines from the back surface of the flexible substrate. The infrared laser beam cuts through the flexible substrate and the majority of the thickness of the adhesive layer, cutting a first trough of a backside street along a scribe line defined by the reference features. An ultraviolet laser beam is aligned to the backside street, or to the scribe line as mapped to the back surface of the flexible substrate. The ultraviolet laser cuts through the metal layer and the semiconductor film, cutting a second trough along the scribe line. The second trough extends from the bottom of and deepens the first trough, cutting through the semiconductor film.

IPC Classes  ?

  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

61.

CVD reactor with gas flow virtual walls

      
Application Number 13222840
Grant Number 09212422
Status In Force
Filing Date 2011-08-31
First Publication Date 2013-02-28
Grant Date 2015-12-15
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Higashi, Gregg
  • Lerner, Alexander
  • Sorabji, Khurshed
  • Washington, Lori D.

Abstract

A chemical vapor deposition reactor has one or more deposition zones bounded by gas flow virtual walls, within a housing having closed walls. Each deposition zone supports chemical vapor deposition onto a substrate. Virtual walls formed of gas flows laterally surround the deposition zone, including a first gas flow of reactant gas from within the deposition zone and a second gas flow of non-reactant gas from a region laterally external to the deposition zone. The first and second gas flows are mutually pressure balanced to form the virtual walls. The virtual walls are formed by merging of gas flows at the boundary of each deposition zone. The housing has an exhaust valve to prevent pressure differences or pressure build up that would destabilize the virtual walls. Cross-contamination is reduced, between the deposition zones and the closed walls of the housing or an interior region of the housing outside the gas flow virtual walls.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

62.

Method and apparatus for assembling photovoltaic cells

      
Application Number 13223242
Grant Number 09130093
Status In Force
Filing Date 2011-08-31
First Publication Date 2013-02-28
Grant Date 2015-09-08
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Deangelo, Joseph O.
  • Lesperance, Sara Kieu
  • Krishnan, Kasiraman

Abstract

A method of assembling a matrix of photovoltaic cells includes positioning photovoltaic cells in a desired orientation, aligning the row of photovoltaic cells relative to each other, and enabling a homogeneous downward pressure on the row of photovoltaic cells to facilitate electrical and mechanical connectivity between the photovoltaic cells.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

63.

Device and method for individual finger isolation in an optoelectronic device

      
Application Number 13222310
Grant Number 08846417
Status In Force
Filing Date 2011-08-31
First Publication Date 2013-02-28
Grant Date 2014-09-30
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor Hegedus, Andreas

Abstract

An optoelectronic device including at least one of a solar device, a semiconductor device, and an electronic device. The device includes a semiconductor unit. A plurality of metal fingers is disposed on a surface of the semiconductor unit for electrical conduction. Each of the metal fingers includes a pad area for forming an electrical contact. The optoelectronic device includes a plurality of pad areas that is available for connection to a bus bar, wherein each of the metal fingers is connected to a corresponding pad area for forming an electrical contact.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

64.

Individual finger isolation through spot application of a dielectric in an optoelectronic device

      
Application Number 13222393
Grant Number 09698284
Status In Force
Filing Date 2011-08-31
First Publication Date 2013-02-28
Grant Date 2017-07-04
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor Hegedus, Andreas

Abstract

An optoelectronic device including at least one of a solar device, a semiconductor device, and an electronic device. The device includes a semiconductor unit. A plurality of metal fingers is disposed on a surface of the semiconductor unit for electrical conduction. Each of the metal fingers corresponds to a section of the optoelectronic device. A plurality of pad areas is available for connection to a bus bar, wherein each of the metal fingers is connected to a corresponding pad area for forming an electrical contact. The optoelectronic device includes a bad section, wherein the bad section is associated with a compromised metal finger and a compromised pad area. A dielectric spot coating is disposed above the compromised pad area to electrically isolate the bad section.

IPC Classes  ?

  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H02S 50/10 - Testing of PV devices, e.g. of PV modules or single PV cells
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 31/0224 - Electrodes
  • H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
  • H01L 31/0216 - Coatings

65.

Movable liner assembly for a deposition zone in a CVD reactor

      
Application Number 13222881
Grant Number 09982346
Status In Force
Filing Date 2011-08-31
First Publication Date 2013-02-28
Grant Date 2018-05-29
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Higashi, Gregg
  • Sorabji, Khurshed
  • Washington, Lori D.

Abstract

A chemical vapor deposition (CVD) reactor comprises a deposition zone, a substrate carrier and a liner assembly. The deposition zone is constructed so as to have a positive pressure reactant gases fixed showerhead introducing reactant gas supporting thin film CVD deposition. The substrate carrier movably supports a substrate and the liner assembly within the deposition zone and is heated so as to be subjected to a CVD process. The liner assembly partly encloses selected portions of the deposition zone, particularly portions of the substrate carrier and thereby enclose a hot zone surrounding a substrate to be processed so as to retain heat in that zone but allows gas flow radially outwardly toward walls of a surrounding cold-wall reactor with exhaust ports surrounding the deposition zone that exhaust spent reactant gases. The liner assembly is a sink for solid reaction byproducts while gaseous reaction byproducts are pumped out at the exhaust ports. The liner assembly is linearly movable away from the fixed showerhead.

IPC Classes  ?

  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/48 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation

66.

Thermal bridge for chemical vapor deposition reactors

      
Application Number 13222984
Grant Number 09644268
Status In Force
Filing Date 2011-08-31
First Publication Date 2013-02-28
Grant Date 2017-05-09
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Higashi, Gregg
  • Sorabji, Khurshed
  • Hegedus, Andreas

Abstract

A thermal bridge connecting first and second processing zones and a method for transferring a work piece from a first to a second processing zone by way of the thermal bridge are disclosed. A work piece, transportable from the first to the second processing zone on or above the thermal bridge, is maintained at a temperature between the temperatures of the processing zones. The thermal bridge member features a thermally conductive transport member for the work piece supported over an infrared transmissive member that is insulative to heat conduction and convection. The bridge insulative member extends between the first and second processing zones or between reactors. An infrared radiation beam source emits infrared radiation which passes through the bridge insulative member to the transport member, heating the member. In an alternate embodiment, the transport member may be heated directly. A liner member may be mounted above the bridge member to retain heat.

IPC Classes  ?

  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for heating the substrate
  • F27D 11/12 - Arrangement of elements for electric heating in or on furnaces with electromagnetic fields acting directly on the material being heated
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/48 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
  • C23C 16/54 - Apparatus specially adapted for continuous coating
  • F27B 17/00 - Furnaces of a kind not covered by any of groups
  • F27D 11/06 - Induction heating, i.e. in which the material being heated, or its container or elements embodied therein, form the secondary of a transformer
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations

67.

Off-axis epitaxial lift off process

      
Application Number 13210138
Grant Number 09994936
Status In Force
Filing Date 2011-08-15
First Publication Date 2013-02-21
Grant Date 2018-06-12
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Gmitter, Thomas
  • He, Gang
  • Archer, Melissa
  • Neo, Siew

Abstract

Embodiments described herein provide processes for forming and removing epitaxial films and materials from growth wafers by epitaxial lift off (ELO) processes. In some embodiments, the growth wafer has edge surfaces with an off-axis orientation which is utilized during the ELO process. The off-axis orientation of the edge surface provides an additional variable for controlling the etch rate during the ELO process- and therefore the etch front may be modulated to prevent the formation of high stress points which reduces or prevents stressing and cracking the epitaxial film stack. In one embodiment, the growth wafer is rectangular and has an edge surface with an off-axis orientation rotated by an angle greater than 0° and up to 90° relative to an edge orientation of <110> at 0°.

IPC Classes  ?

  • C30B 19/00 - Liquid-phase epitaxial-layer growth
  • C22C 29/00 - Alloys based on carbides, oxides, borides, nitrides or silicides, e.g. cermets, or other metal compounds, e. g. oxynitrides, sulfides
  • C30B 33/06 - Joining of crystals
  • C30B 29/42 - Gallium arsenide
  • C30B 29/40 - AIIIBV compounds
  • C30B 33/08 - Etching
  • C30B 29/00 - Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B 33/10 - Etching in solutions or melts

68.

Aligned frontside backside laser dicing of semiconductor films

      
Application Number 13222750
Grant Number 08361828
Status In Force
Filing Date 2011-08-31
First Publication Date 2013-01-29
Grant Date 2013-01-29
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Patterson, Daniel G.
  • Mattos, Laila
  • He, Gang

Abstract

A method and system for dicing semiconductor devices from semiconductor thin films. A semiconductor film, backed by a metal layer, is bonded by an adhesive layer to a flexible translucent substrate. Reference features define device boundaries. An ultraviolet laser beam is aligned to the reference features and cuts through the semiconductor film, the metal layer and partially into the adhesive layer, cutting a frontside street along a real or imaginary scribe line on the cutting path. An infrared laser beam is aligned to the trough of the frontside street from the back surface of the flexible substrate, or the scribe lines are mapped to the back surface of the flexible substrate. The infrared laser beam cuts through the flexible substrate and the majority of the thickness of the adhesive layer, cutting a backside street along the scribe line. The backside street overlaps or cuts through to the frontside street, thereby separating the semiconductor devices.

IPC Classes  ?

  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

69.

Epitaxial lift off stack having a non-uniform handle and methods thereof

      
Application Number 13536043
Grant Number 08716107
Status In Force
Filing Date 2012-06-28
First Publication Date 2012-10-18
Grant Date 2014-05-06
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Gmitter, Thomas
  • He, Gang
  • Hegedus, Andreas

Abstract

Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming a thin film material during an epitaxial lift off process is provided which includes forming an epitaxial material over a sacrificial layer on a substrate, adhering a non-uniform support handle onto the epitaxial material, and removing the sacrificial layer during an etching process. The etching process further includes peeling the epitaxial material from the substrate while forming an etch crevice therebetween and bending the support handle to form compression in the epitaxial material during the etching process. In one example, the non-uniform support handle contains a wax film having a varying thickness.

IPC Classes  ?

  • H01L 21/46 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups

70.

Film transfer frame

      
Application Number 13077353
Grant Number 08403315
Status In Force
Filing Date 2011-03-31
First Publication Date 2012-10-04
Grant Date 2013-03-26
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor Frankel, Jonathan Stuart

Abstract

A system for retaining a film on a single-piece frame includes a frame having a shape with a center open area larger than the film, the frame comprising a plurality of fingers on the frame extending into the open area, and a barb positioned on an end of each of the plurality of fingers, wherein the barbs retain the film. The system also includes an end effecter comprising a first and second plurality of vacuum line openings, wherein the end effecter holds onto the film with the first plurality of vacuum line openings and holds onto the frame with the second plurality of vacuum line openings, wherein the end effecter picks up the film with the first plurality of vacuum line openings and presses the film onto the frame, wherein pressing the film onto the frame will retain the film on the barbs.

IPC Classes  ?

  • B65H 9/08 - Holding devices, e.g. finger, needle, suction, for retaining articles in registered position
  • B25B 11/00 - Work holders or positioners not covered by groups , e.g. magnetic work holders, vacuum work holders

71.

Methods for forming optoelectronic devices including heterojunction

      
Application Number 13451439
Grant Number 09178099
Status In Force
Filing Date 2012-04-19
First Publication Date 2012-10-04
Grant Date 2015-11-03
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Nie, Hui
  • Kayes, Brendan M.
  • Kizilyalli, Isik C.

Abstract

Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.

IPC Classes  ?

  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/0224 - Electrodes
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

72.

Self-bypass diode function for gallium arsenide photovoltaic devices

      
Application Number 13023733
Grant Number 09716196
Status In Force
Filing Date 2011-02-09
First Publication Date 2012-08-09
Grant Date 2017-07-25
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Nie, Hui
  • Kayes, Brendan M.
  • Kizilyalli, Isik C.

Abstract

Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect.

IPC Classes  ?

  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 27/142 - Energy conversion devices
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/0443 - PV modules or arrays of single PV cells including bypass diodes comprising bypass diodes integrated or directly associated with the devices, e.g. bypass diodes integrated or formed in or on the same substrate as the photovoltaic cells

73.

Wafer carrier track

      
Application Number 13257269
Grant Number 08985911
Status In Force
Filing Date 2010-03-16
First Publication Date 2012-04-19
Grant Date 2015-03-24
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • He, Gang
  • Higashi, Gregg
  • Sorabji, Khurshed
  • Hamamjy, Roger
  • Hegedus, Andreas G.

Abstract

Embodiments of the invention generally relate to apparatuses for chemical vapor deposition (CVD) processes. In one embodiment, a wafer carrier track for levitating and traversing a wafer carrier within a vapor deposition reactor system is provided which includes upper and lower sections of a track assembly having a gas cavity formed therebetween. A guide path extends along an upper surface of the upper section and between two side surfaces which extend along and above the guide path and parallel to each other. A plurality of gas holes along the guide path extends from the upper surface of the upper section, through the upper section, and into the gas cavity. In some examples, the upper and lower sections of the track assembly may independently contain quartz, and in some examples, may be fused together.

IPC Classes  ?

  • B65G 53/00 - Conveying materials in bulk through troughs, pipes or tubes by floating the materials or by flow of gas, liquid or foam
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/54 - Apparatus specially adapted for continuous coating

74.

Reactor clean

      
Application Number 12913688
Grant Number 09127364
Status In Force
Filing Date 2010-10-27
First Publication Date 2011-11-03
Grant Date 2015-09-08
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor Bour, David P.

Abstract

A method and apparatus for performing chemical vapor deposition (CVD) processes is provided. In one embodiment, the apparatus comprises a reactor body having a processing region, comprising a wafer carrier track having a wafer carrier disposed thereon, at least one sidewall having an exhaust assembly for exhausting gases from the processing region, a lid assembly disposed on the reactor body, comprising a lid support comprising a first showerhead assembly for supplying reactant gases to the processing region, a first isolator assembly for supplying isolation gases to the processing region, a second showerhead assembly for supplying reactant gases to the processing region, and a second isolator assembly for supplying isolation gases to the processing region, wherein the first showerhead assembly, the first isolator assembly, the second showerhead assembly, and the second isolator assembly are consecutively and linearly disposed next to each other.

IPC Classes  ?

  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes
  • C23C 16/54 - Apparatus specially adapted for continuous coating
  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations

75.

Epitaxial lift off systems and methods

      
Application Number 13039307
Grant Number 10259206
Status In Force
Filing Date 2011-03-02
First Publication Date 2011-09-08
Grant Date 2019-04-16
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Brown, Brian
  • Burrows, Brian
  • Berkstressor, David
  • He, Gang
  • Gmitter, Thomas J

Abstract

Epitaxial lift off systems and methods are presented. In one embodiment a tape is disposed on the opposite side of the epitaxial material than the substrate is used to hold the epitaxial material during the etching and removal steps of the ELO process. In various embodiments, the apparatus for removing the ELO film from the substrates without damaging the ELO film may include an etchant reservoir, substrate handling and tape handling mechanisms, including mechanisms to manipulate (e.g., cause tension, peel, widen the etch gap, etc.) the lift off component during the lift off process.

IPC Classes  ?

  • B32B 38/10 - Removing layers, or parts of layers, mechanically or chemically
  • B32B 37/14 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
  • B32B 43/00 - Operations specially adapted for layered products and not otherwise provided for, e.g. repairing; Apparatus therefor
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

76.

Substrate clean solution for copper contamination removal

      
Application Number 13042379
Grant Number 09028620
Status In Force
Filing Date 2011-03-07
First Publication Date 2011-09-08
Grant Date 2015-05-12
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor Archer, Melissa

Abstract

Embodiments of the invention generally relate to a method for selectively etching or otherwise removing copper or other metallic contaminants from a substrate, such as a gallium arsenide wafer. In one embodiment, a method for selectively removing metallic contaminants from a substrate surface is provided which includes exposing a substrate to a peroxide clean solution, exposing the substrate to a hydroxide clean solution, and exposing the substrate to a selective etch solution containing potassium iodide, iodine, sulfuric acid, and water during a selective etch process. The substrate generally contains gallium arsenide material, such as crystalline gallium arsenide, and is usually a growth substrate for an epitaxial lift off (ELO) process. The copper or other metallic contaminants disposed on the substrate may be selectively etched at a rate of about 500 times, about 1,000 times, about 2,000 times, or about 4,000 times or greater than the gallium arsenide material.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

77.

Textured metallic back reflector

      
Application Number 12904047
Grant Number 09691921
Status In Force
Filing Date 2010-10-13
First Publication Date 2011-04-14
Grant Date 2017-06-27
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Atwater, Harry
  • Kayes, Brendan
  • Kizilyalli, Isik C.
  • Nie, Hui

Abstract

Embodiments of the invention generally relate to device fabrication of thin films used as solar devices or other electronic devices, and include textured back reflectors utilized in solar applications. In one embodiment, a method for forming a textured metallic back reflector which includes depositing a metallic layer on a gallium arsenide material within a thin film stack, forming an array of metallic islands from the metallic layer during an annealing process, removing or etching material from the gallium arsenide material to form apertures between the metallic islands, and depositing a metallic reflector layer to fill the apertures and cover the metallic islands. In another embodiment, a textured metallic back reflector includes an array of metallic islands disposed on a gallium arsenide material, a plurality of apertures disposed between the metallic islands and extending into the gallium arsenide material, a metallic reflector layer disposed over the metallic islands, and a plurality of reflector protrusions formed between the metallic islands and extending from the metallic reflector layer and into the apertures formed in the gallium arsenide material.

IPC Classes  ?

  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L 31/0232 - Optical elements or arrangements associated with the device
  • H01L 31/056 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means the light-reflecting means being of the back surface reflector [BSR] type
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/0236 - Special surface textures
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/20 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor material
  • H01L 31/0693 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells

78.

Method of high growth rate deposition for group III/V materials

      
Application Number 12904090
Grant Number 09834860
Status In Force
Filing Date 2010-10-13
First Publication Date 2011-04-14
Grant Date 2017-12-05
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Washington, Lori D.
  • Bour, David P.
  • Higashi, Gregg
  • He, Gang

Abstract

Embodiments of the invention generally relate processes for epitaxial growing Group III/V materials at high growth rates, such as about 30 μm/hr or greater, for example, about 40 μm/hr, about 50 μm/hr, about 55 μm/hr, about 60 μm/hr, or greater. The deposited Group III/V materials or films may be utilized in solar, semiconductor, or other electronic device applications. In some embodiments, the Group III/V materials may be formed or grown on a sacrificial layer disposed on or over the support substrate during a vapor deposition process. Subsequently, the Group III/V materials may be removed from the support substrate during an epitaxial lift off (ELO) process. The Group III/V materials are thin films of epitaxially grown layers which contain gallium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium arsenide nitride, gallium aluminum indium phosphide, phosphides thereof, nitrides thereof, derivatives thereof, alloys thereof, or combinations thereof.

IPC Classes  ?

79.

Photovoltaic device

      
Application Number 12940861
Grant Number 08895845
Status In Force
Filing Date 2010-11-05
First Publication Date 2011-03-10
Grant Date 2014-11-25
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Kizilyalli, Isik C.
  • Archer, Melissa
  • Atwater, Harry
  • Gmitter, Thomas J.
  • He, Gang
  • Hegedus, Andreas
  • Higashi, Gregg

Abstract

Methods and apparatus are provided for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells. A photovoltaic (PV) unit, according to embodiments of the invention, may have a very thin absorber layer produced by epitaxial lift-off (ELO), all electrical contacts positioned on the back side of the PV device to avoid shadowing, and/or front side and back side light trapping employing a diffuser and a reflector to increase absorption of the photons impinging on the front side of the PV unit. Several PV units may be combined into PV banks, and an array of PV banks may be connected to form a PV module with thin strips of metal or conductive polymer applied at low temperature. Such innovations may allow for greater efficiency and flexibility in PV devices when compared to conventional solar cells.

IPC Classes  ?

  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/0236 - Special surface textures
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells

80.

Photovoltaic device including an intermediate layer

      
Application Number 12940955
Grant Number 08912432
Status In Force
Filing Date 2010-11-05
First Publication Date 2011-03-10
Grant Date 2014-12-16
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Kizilyalli, Isik C.
  • Archer, Melissa J.
  • Atwater, Harry
  • Gmitter, Thomas J.
  • He, Gang
  • Hegedus, Andreas G.
  • Higashi, Gregg

Abstract

+-doped layer may compose an absorber layer having a thickness less than 500 nm. Such a thin absorber layer may allow for greater efficiency and flexibility in PV devices when compared to conventional solar cells.

IPC Classes  ?

  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells

81.

Photovoltaic device

      
Application Number 12940876
Grant Number 08895846
Status In Force
Filing Date 2010-11-05
First Publication Date 2011-03-03
Grant Date 2014-11-25
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Kizilyalli, Isik C.
  • Archer, Melissa
  • Atwater, Harry
  • Gmitter, Thomas J.
  • He, Gang
  • Hegedus, Andreas
  • Higashi, Gregg

Abstract

Methods and apparatus are provided for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells. A photovoltaic (PV) unit, according to embodiments of the invention, may have a very thin absorber layer produced by epitaxial lift-off (ELO), all electrical contacts positioned on the back side of the PV device to avoid shadowing, and/or front side and back side light trapping employing a diffuser and a reflector to increase absorption of the photons impinging on the front side of the PV unit. Several PV units may be combined into PV banks, and an array of PV banks may be connected to form a PV module with thin strips of metal or conductive polymer applied at low temperature. Such innovations may allow for greater efficiency and flexibility in PV devices when compared to conventional solar cells.

IPC Classes  ?

  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/0236 - Special surface textures
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds

82.

Photovoltaic device with increased light trapping

      
Application Number 12940966
Grant Number 08895847
Status In Force
Filing Date 2010-11-05
First Publication Date 2011-03-03
Grant Date 2014-11-25
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Kizilyalli, Isik C.
  • Archer, Melissa J.
  • Atwater, Harry
  • Gmitter, Thomas J.
  • He, Gang
  • Hegedus, Andreas G.
  • Higashi, Gregg

Abstract

Methods and apparatus are provided for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells. A photovoltaic (PV) device may incorporate front side and/or back side light trapping techniques in an effort to absorb as many of the photons incident on the front side of the PV device as possible in the absorber layer. The light trapping techniques may include a front side antireflective coating, multiple window layers, roughening or texturing on the front and/or the back sides, a back side diffuser for scattering the light, and/or a back side reflector for redirecting the light into the interior of the PV device. With such light trapping techniques, more light may be absorbed by the absorber layer for a given amount of incident light, thereby increasing the efficiency of the PV device.

IPC Classes  ?

  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/0216 - Coatings

83.

Thin absorber layer of a photovoltaic device

      
Application Number 12940918
Grant Number 08669467
Status In Force
Filing Date 2010-11-05
First Publication Date 2011-02-24
Grant Date 2014-03-11
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Kizilyalli, Isik C.
  • Archer, Melissa J.
  • Atwater, Harry
  • Gmitter, Thomas J.
  • He, Gang
  • Hegedus, Andreas G.
  • Higashi, Gregg

Abstract

+-doped layer may compose an absorber layer having a thickness less than 500 nm. Such a thin absorber layer may allow for greater efficiency and flexibility in PV devices when compared to conventional solar cells.

IPC Classes  ?

  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

84.

Tiled substrates for deposition and epitaxial lift off processes

      
Application Number 12715243
Grant Number 08362592
Status In Force
Filing Date 2010-03-01
First Publication Date 2010-09-02
Grant Date 2013-01-29
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • He, Gang
  • Hegedus, Andreas

Abstract

−1.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

85.

Method for vapor deposition

      
Application Number 12725296
Grant Number 08852696
Status In Force
Filing Date 2010-03-16
First Publication Date 2010-08-19
Grant Date 2014-10-07
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • He, Gang
  • Higashi, Gregg
  • Sorabji, Khurshed
  • Hamamjy, Roger
  • Hegedus, Andreas

Abstract

Chemical vapor deposition (CVD) processes include, in one embodiment, a method for processing a wafer within a vapor deposition reactor comprising heating at least one wafer disposed on a wafer carrier by exposing a lower surface of the wafer carrier to radiation emitted from a lamp assembly and flowing a liquid through a passageway extending throughout the reactor to maintain the reactor lid assembly at a predetermined temperature, such as within a range from about 275° C. to about 325° C. The method further includes traversing the wafer carrier along a wafer carrier track through at least a chamber containing a showerhead assembly and an isolator assembly and another chamber containing a showerhead assembly and an exhaust assembly, and removing gases from the reactor through the exhaust assembly.

IPC Classes  ?

  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes
  • C30B 25/12 - Substrate holders or susceptors
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • C30B 29/40 - AIIIBV compounds
  • C23C 16/54 - Apparatus specially adapted for continuous coating
  • C30B 29/42 - Gallium arsenide
  • C30B 25/02 - Epitaxial-layer growth
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/48 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating

86.

Methods for heating with lamps

      
Application Number 12725318
Grant Number 08859042
Status In Force
Filing Date 2010-03-16
First Publication Date 2010-08-19
Grant Date 2014-10-14
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • He, Gang
  • Higashi, Gregg
  • Sorabji, Khurshed
  • Hamamjy, Roger
  • Hegedus, Andreas

Abstract

Embodiments of the invention generally relate to methods for chemical vapor deposition (CVD) processes. In one embodiment, a method for heating a substrate or a substrate susceptor within a vapor deposition reactor system includes exposing a lower surface of a substrate susceptor, such as a wafer carrier, to energy emitted from a heating lamp assembly, and heating the substrate susceptor to a predetermined temperature. The heating lamp assembly generally contains a lamp housing disposed on an upper surface of a support base and contains at least one lamp holder, a plurality of lamps extending from the lamp holder, and a reflector disposed on the upper surface of the support base, next to the lamp holder, and below the lamps. The plurality of lamps may have split filament lamps and/or non-split filament lamps for heating inner and outer portions of the substrate susceptor.

IPC Classes  ?

  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C30B 29/42 - Gallium arsenide
  • C30B 25/10 - Heating of the reaction chamber or the substrate
  • C23C 16/48 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
  • C30B 29/40 - AIIIBV compounds
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/54 - Apparatus specially adapted for continuous coating
  • C30B 25/02 - Epitaxial-layer growth
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

87.

Wafer carrier track

      
Application Number 12725308
Grant Number 09169554
Status In Force
Filing Date 2010-03-16
First Publication Date 2010-08-19
Grant Date 2015-10-27
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • He, Gang
  • Higashi, Gregg
  • Sorabji, Khurshed
  • Hamamjy, Roger
  • Hegedus, Andreas

Abstract

Embodiments of the invention generally relate to apparatuses for chemical vapor deposition (CVD) processes. In one embodiment, a wafer carrier track for levitating and traversing a wafer carrier within a vapor deposition reactor system is provided which includes upper and lower sections of a track assembly having a gas cavity formed therebetween. A guide path extends along an upper surface of the upper section and between two side surfaces which extend along and above the guide path and parallel to each other. A plurality of gas holes along the guide path extends from the upper surface of the upper section, through the upper section, and into the gas cavity. In some examples, the upper and lower sections of the track assembly may independently contain quartz, and in some examples, may be fused together.

IPC Classes  ?

  • C23C 16/54 - Apparatus specially adapted for continuous coating
  • C23C 14/56 - Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/48 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
  • C30B 25/02 - Epitaxial-layer growth
  • C30B 25/12 - Substrate holders or susceptors
  • C30B 29/40 - AIIIBV compounds
  • C30B 29/42 - Gallium arsenide
  • C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

88.

Tape-based epitaxial lift off apparatuses and methods

      
Application Number 12640796
Grant Number 09165805
Status In Force
Filing Date 2009-12-17
First Publication Date 2010-06-17
Grant Date 2015-10-20
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Gmitter, Thomas
  • He, Gang
  • Archer, Melissa
  • Hegedus, Andreas

Abstract

An apparatus or method for forming a tape-based, epitaxial lift-off film. The epitaxial lift-off film can be for at least one of a solar device, a semiconductor device, and an electronic device. The apparatus can comprise: a tape supply section, the tape supply section providing an unloaded support tape; a lamination section for receiving the unloaded support tape and a plurality of substrates, each substrate containing an epitaxial film thereon, the lamination section adhering the substrates to the unloaded support tape to form a loaded support tape; and an ELO etch section comprising a pressure system for applying pressure on said loaded support tape such that pressure is applied progressively downward and progressively towards a center-line of said loaded support tape when passing through said ELO etch section, the ELO etch section removing the substrates from the loaded support tape, while leaving the epitaxial film on the loaded support tape.

IPC Classes  ?

  • C23F 1/08 - Apparatus, e.g. for photomechanical printing surfaces
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

89.

Multiple stack deposition for epitaxial lift off

      
Application Number 12632565
Grant Number 09068278
Status In Force
Filing Date 2009-12-07
First Publication Date 2010-06-17
Grant Date 2015-06-30
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • He, Gang
  • Hegedus, Andreas

Abstract

Embodiments of the invention are provided for a thin film stack containing a plurality of epitaxial stacks disposed on a substrate and a method for forming such a thin film stack. In one embodiment, the epitaxial stack contains a first sacrificial layer disposed over the substrate, a first epitaxial film disposed over the first sacrificial layer, a second sacrificial layer disposed over the first epitaxial film, and a second epitaxial film disposed over the second sacrificial layer. The thin film stack may further contain additional epitaxial films disposed over sacrificial layers. Generally, the epitaxial films contain gallium arsenide alloys and the sacrificial layers contain aluminum arsenide alloys. Methods provide the removal of the epitaxial films from the substrate by etching away the sacrificial layers during an epitaxial lift off (ELO) process. The epitaxial films are useful as photovoltaic cells, laser diodes, or other devices or materials.

IPC Classes  ?

  • C30B 21/02 - Unidirectional solidification of eutectic materials by normal casting or gradient freezing
  • C30B 29/42 - Gallium arsenide
  • C30B 29/40 - AIIIBV compounds
  • C30B 33/06 - Joining of crystals
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/0725 - Multiple junction or tandem solar cells
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

90.

Photovoltaic device

      
Application Number 12605108
Grant Number 08937244
Status In Force
Filing Date 2009-10-23
First Publication Date 2010-06-03
Grant Date 2015-01-20
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Kizilyalli, Isik C.
  • Archer, Melissa
  • Atwater, Harry
  • Gmitter, Thomas J.
  • He, Gang
  • Hegedus, Andreas
  • Higashi, Gregg

Abstract

Methods and apparatus are provided for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells. A photovoltaic (PV) unit, according to embodiments of the invention, may have a very thin absorber layer produced by epitaxial lift-off (ELO), all electrical contacts positioned on the back side of the PV device to avoid shadowing, and/or front side and back side light trapping employing a diffuser and a reflector to increase absorption of the photons impinging on the front side of the PV unit. Several PV units may be combined into PV banks, and an array of PV banks may be connected to form a PV module with thin strips of metal or conductive polymer applied at low temperature. Such innovations may allow for greater efficiency and flexibility in PV devices when compared to conventional solar cells.

IPC Classes  ?

  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/0236 - Special surface textures
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells

91.

Thin absorber layer of a photovoltaic device

      
Application Number 12605129
Grant Number 08674214
Status In Force
Filing Date 2009-10-23
First Publication Date 2010-05-27
Grant Date 2014-03-18
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Kizilyalli, Isik C.
  • Archer, Melissa
  • Atwater, Harry
  • Gmitter, Thomas J.
  • He, Gang
  • Hegedus, Andreas
  • Higashi, Gregg

Abstract

+-doped layer may compose an absorber layer having a thickness less than 500 nm. Such a thin absorber layer may allow for greater efficiency and flexibility in PV devices when compared to conventional solar cells.

IPC Classes  ?

  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

92.

Photovoltaic device with increased light trapping

      
Application Number 12605140
Grant Number 08686284
Status In Force
Filing Date 2009-10-23
First Publication Date 2010-05-27
Grant Date 2014-04-01
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Kizilyalli, Isik C.
  • Archer, Melissa
  • Atwater, Harry
  • Gmitter, Thomas J.
  • He, Gang
  • Hegedus, Andreas
  • Higashi, Gregg

Abstract

Methods and apparatus are provided for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells. A photovoltaic (PV) device may incorporate front side and/or back side light trapping techniques in an effort to absorb as many of the photons incident on the front side of the PV device as possible in the absorber layer. The light trapping techniques may include a front side antireflective coating, multiple window layers, roughening or texturing on the front and/or the back sides, a back side diffuser for scattering the light, and/or a back side reflector for redirecting the light into the interior of the PV device. With such light trapping techniques, more light may be absorbed by the absorber layer for a given amount of incident light, thereby increasing the efficiency of the PV device.

IPC Classes  ?

  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

93.

Integration of a photovoltaic device

      
Application Number 12605163
Grant Number 09029680
Status In Force
Filing Date 2009-10-23
First Publication Date 2010-05-27
Grant Date 2015-05-12
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Kizilyalli, Isik C.
  • Archer, Melissa
  • Atwater, Harry
  • Gmitter, Thomas J.
  • He, Gang
  • Hegedus, Andreas
  • Higashi, Gregg

Abstract

Methods and apparatus are provided for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells. A photovoltaic (PV) unit may have all electrical contacts positioned on the back side of the PV device to avoid shadowing and increase absorption of the photons impinging on the front side of the PV unit. Several PV units may be combined into PV banks, and an array of PV banks may be connected to form a PV module with thin strips of metal or conductive polymer formed at low temperature. Such innovations may allow for greater efficiency and flexibility in PV devices when compared to conventional solar cells.

IPC Classes  ?

  • H01L 31/042 - PV modules or arrays of single PV cells
  • H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/0224 - Electrodes
  • H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds

94.

Photovoltaic device with back side contacts

      
Application Number 12605151
Grant Number 09029687
Status In Force
Filing Date 2009-10-23
First Publication Date 2010-05-27
Grant Date 2015-05-12
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Kizilyalli, Isik C.
  • Archer, Melissa
  • Atwater, Harry
  • Gmitter, Thomas J.
  • He, Gang
  • Hegedus, Andreas
  • Higashi, Gregg

Abstract

Methods and apparatus for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells are provided. A photovoltaic (PV) device generally includes a window layer; an absorber layer disposed below the window layer such that electrons are generated when photons travel through the window layer and are absorbed by the absorber layer; and a plurality of contacts for external connection coupled to the absorber layer, such that all of the contacts for external connection are disposed below the absorber layer and do not block any of the photons from reaching the absorber layer through the window layer. Locating all the contacts on the back side of the PV device avoids solar shadows caused by front side contacts, typically found in conventional solar cells. Therefore, PV devices described herein with back side contacts may allow for increased efficiency when compared to conventional solar cells.

IPC Classes  ?

  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 31/0224 - Electrodes
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

95.

Mesa etch method and composition for epitaxial lift off

      
Application Number 12577645
Grant Number 09064810
Status In Force
Filing Date 2009-10-12
First Publication Date 2010-05-13
Grant Date 2015-06-23
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor Archer, Melissa

Abstract

Embodiments of the invention generally relate to compositions of mesa etch solutions and methods for mesa etching materials on a wafer during an epitaxial lift off (ELO) process. The wafer usually contains an etch stop layer disposed thereon and a laminated epitaxial material disposed on the etch stop layer. In one embodiment, an etch process includes exposing the wafer to a non-selective etch solution and subsequently exposing the wafer to a selective etch solution while peeling the laminated epitaxial material from the wafer. The selective etch solution may contain succinic acid, an ammonium hydroxide compound, and an oxidizing agent, such as hydrogen peroxide. The selective etch solution may have a GaAs/AlAs selectivity of about 600, about 1,000, about 1,400, or greater. The non-selective etch solution may be an aqueous solution containing sulfuric acid and hydrogen peroxide.

IPC Classes  ?

  • B44C 1/22 - Removing surface-material, e.g. by engraving, by etching
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

96.

Continuous feed chemical vapor deposition

      
Application Number 12577641
Grant Number 08008174
Status In Force
Filing Date 2009-10-12
First Publication Date 2010-05-13
Grant Date 2011-08-30
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • He, Gang
  • Higashi, Gregg

Abstract

Embodiments of the invention generally relate to a method for forming a multi-layered material during a continuous chemical vapor deposition (CVD) process. In one embodiment, a method for forming a multi-layered material during a continuous CVD process is provided which includes continuously advancing a plurality of wafers through a deposition system having at least four deposition zones. Multiple layers of materials are deposited on each wafer, such that one layer is deposited at each deposition zone. The methods provide advancing each wafer through each deposition zone while depositing a first layer from the first deposition zone, a second layer from the second deposition zone, a third layer from the third deposition zone, and a fourth layer from the fourth deposition zone. Embodiments described herein may be utilized to form an assortment of materials on wafers or substrates, especially for forming Group III/V materials on GaAs wafers.

IPC Classes  ?

  • H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
  • H01L 21/36 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes

97.

Concentric showerhead for vapor deposition

      
Application Number 12576797
Grant Number 09121096
Status In Force
Filing Date 2009-10-09
First Publication Date 2010-04-15
Grant Date 2015-09-01
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor Hegedus, Andreas

Abstract

Embodiments of the invention generally relate to a concentric gas manifold assembly used in deposition reactor or system during a vapor deposition process. In one embodiment, the manifold assembly has an upper section coupled to a middle section coupled to a lower section. The middle section contains an inlet, a manifold extending from the inlet to a passageway, and a tube extending along a central axis and containing a channel along the central axis and in fluid communication with the passageway. The lower section of the manifold assembly contains a second manifold extending from a second inlet to a second passageway and an opening concentric with the central axis. The tube extends to the opening to form a second channel between the tube and an edge of the opening. The second channel is concentric with the central axis and is in fluid communication with the second passageway.

IPC Classes  ?

  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes
  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/48 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
  • C23C 16/54 - Apparatus specially adapted for continuous coating

98.

Epitaxial lift off stack having a multi-layered handle and methods thereof

      
Application Number 12475420
Grant Number 08367518
Status In Force
Filing Date 2009-05-29
First Publication Date 2010-01-07
Grant Date 2013-02-05
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Gmitter, Thomas
  • He, Gang

Abstract

Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods for forming such films and devices. In one embodiment, a method for forming an ELO thin film includes depositing an epitaxial material over a sacrificial layer on a substrate, adhering a multi-layered support handle onto the epitaxial material, and removing the sacrificial layer during an etching process. The etching process further includes peeling the epitaxial material from the substrate and forming an etch crevice therebetween while maintaining compression in the epitaxial material. The method further provides that the multi-layered support handle contains a stiff support layer adhered to the epitaxial material, a soft support layer adhered to the stiff support layer, and a handle plate adhered to the soft support layer. In one example, the stiff support layer may contain multiple inorganic layers, such as metal layers, dielectric layers, or combinations thereof.

IPC Classes  ?

  • H01L 21/30 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 21/46 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups

99.

Epitaxial lift off stack having a non-uniform handle and methods thereof

      
Application Number 12475418
Grant Number 08314011
Status In Force
Filing Date 2009-05-29
First Publication Date 2010-01-07
Grant Date 2012-11-20
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • Gmitter, Thomas
  • He, Gang
  • Hegedus, Andreas

Abstract

Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming a thin film material during an epitaxial lift off process is provided which includes forming an epitaxial material over a sacrificial layer on a substrate, adhering a non-uniform support handle onto the epitaxial material, and removing the sacrificial layer during an etching process. The etching process further includes peeling the epitaxial material from the substrate while forming an etch crevice therebetween and bending the support handle to form compression in the epitaxial material during the etching process. In one example, the non-uniform support handle contains a wax film having a varying thickness.

IPC Classes  ?

  • H01L 21/46 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups

100.

Methods and apparatus for a chemical vapor deposition reactor

      
Application Number 12475169
Grant Number 08602707
Status In Force
Filing Date 2009-05-29
First Publication Date 2009-12-31
Grant Date 2013-12-10
Owner
  • UTICA LEASECO, LLC ASSIGNEE (USA)
  • UTICA LEASECO, LLC ASSIGNEE (USA)
Inventor
  • He, Gang
  • Higashi, Gregg
  • Sorabji, Khurshed
  • Hamamjy, Roger
  • Hegedus, Andreas
  • Archer, Melissa
  • Atwater, Harry
  • Sonnenfeldt, Stewart

Abstract

Embodiments of the invention generally relate to a levitating substrate carrier or support. In one embodiment, a substrate carrier for supporting and carrying at least one substrate or wafer is provided which includes a substrate carrier body containing an upper surface and a lower surface, and at least one indentation pocket disposed within the lower surface. In another embodiment, the substrate carrier includes at least open indentation area within the upper surface, and at least two indentation pockets disposed within the lower surface. Each indentation pocket may be rectangular and have four side walls extending substantially perpendicular to the lower surface. In another embodiment, a method for levitating substrates disposed on a substrate carrier is provided which includes exposing the lower surface of a substrate carrier to a gas stream, forming a gas cushion under the substrate carrier, levitating the substrate carrier within a processing chamber, and moving the substrate carrier along a path within the processing chamber.

IPC Classes  ?

  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
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