Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.
Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.
A method of activating scheduling instructions within a parallel processing unit includes checking if an ALU targeted by a decoded instruction is full by checking a value of an ALU work fullness counter stored in the instruction controller and associated with the targeted ALU. If the targeted ALU is not full, the decoded instruction is sent to the targeted ALU for execution and the ALU work fullness counter associated with the targeted ALU is updated. If, however, the targeted ALU is full, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state. When an ALU changes from being full to not being full, the scheduler is triggered to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the non-active state.
G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
G06F 7/575 - Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
4.
Processing Instructions at a Processing Unit Configured to Perform Parallel Processing
A method of processing instructions at a processing unit having a parallel processing engine. During a mission cycle, a first set of mission operand values is processed in accordance with a mission instruction at a first processing instance to generate a first mission output. In parallel, a second set of mission operand values is processed in accordance with the mission instruction at a second processing instance to generate a second mission output. During a test cycle, a first set of test operand values is processed in accordance with a test instruction at the first processing instance to generate a first test output, and in parallel, a second set of test operand values is processed in accordance with the test instruction at the second processing instance to generate a second test output, where the first set of test operand values is the same as the second set of test operand values. The first test output and the second test output are compared and a fault signal is raised if the compared test outputs do not match.
A block of sub-primitive presence indications for use in intersection testing in a rendering system is compressed into a block of compressed data. Spatial decorrelation is performed to determine spatially decorrelated presence indications by (i) determining a predicted value for the presence indication based on one or more other presence indications in the line, and (ii) replacing the presence indication with a value of a difference between the presence indication and the determined predicted value for the presence indication. For each line of presence indications in a second dimension within the block, for one or more of the presence indications in the line: (i) a predicted value for the presence indication is determined based on one or more other presence indications in the line, and (ii) the presence indication is replaced with a value of a difference between the presence indication and the determined predicted value for the presence indication.
A method of compressing meshlet topology data includes selecting a starting vertex in a meshlet and creating an encoding comprising data identifying a glue type of the starting vertex and data indicating a number of connected vertices. A next glue vertex in the meshlet is then selected and for the next glue vertex, the method comprises appending to the encoding, one or more of: data identifying the next glue vertex; data identifying a glue type of the next glue vertex and data indicating a number of new connected vertices, wherein each new connected vertex is connected to the new glue vertex by an edge. The method continues to select a next glue vertex and append one or more bits to the encoding until all the vertices and edges of the meshlet are included in the encoding. Methods and apparatus for decompression are also described.
Methods and coarse depth test logic perform coarse depth testing in a graphics processing system in which a rendering space is divided into a plurality of tiles. A depth range for a tile identifies a depth range based on primitives previously processed. A determination is made based on the depth range for the tile as to whether all or a portion of a primitive is hidden in the tile. If at least a portion of the primitive is not hidden in the tile, a determination is made as to whether the primitive or a primitive fragment thereof has better depth than the primitives previously processed for the tile. If so, the primitive or the primitive fragment is identified as not requiring a read of a depth buffer to perform full resolution depth testing, such that a determination that at least a portion of the primitive is hidden in the tile causes full resolution depth testing not to be performed on at least that portion of the primitive.
G06F 7/24 - Sorting, i.e. extracting data from one or more carriers, re-arranging the data in numerical or other ordered sequence, and re-recording the sorted data on the original carrier or on a different carrier or set of carriers
G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
A computer implemented method converts ray data for a ray into a ray representative, wherein the ray representative is a compressed representation of the ray data, and wherein the ray data comprises three direction components and three position components for the ray. The method comprises identifying which of the three direction components of the ray data has the greatest magnitude, and defining the axis of the identified direction component as the major axis of the ray. The method further comprises determining a translated position on the ray at which the position component along the major axis is zero, and rescaling the three direction components of the ray so that the magnitude of the direction component along the major axis is one. The ray representative comprises: (i) the two position components of the translated position along the axes which are not the major axis, and (ii) the two rescaled direction components along the axes which are not the major axis.
A system and method for performing intersection testing of rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes, each identifying one or more elements able to be intersected by a ray. The system makes use of a serial-mode ray intersection process, in which, when a ray intersects a bounding volume, a limited number of new ray requests are generated.
A sparse matrix and a dense matrix are multiplied to determine an output matrix. A cache stores portions of rows of the dense matrix. The sparse matrix comprises non-zero elements and elements which are zero. The rows and columns of the dense matrix and the output matrix are ordered in accordance the rows and columns of the sparse matrix. The threads of a workgroup access data representing non-zero elements of a corresponding row of the sparse matrix. For each of the non-zero elements of the corresponding row of the sparse matrix, a portion of a related row of the dense matrix is accessed from the cache, and the non-zero element is multiplied with the related row of the dense matrix. A row-position of the related row in the dense matrix matches a column-position of the non-zero element in the sparse matrix. A column-position of the portion of the related row of the dense matrix matches a column-position of the portion of the row of the output matrix of the section to which the thread is allocated.
A structured language for use in a language model is tokenised. Each segment of the structured language includes a plurality of words formed using a predetermined syntax. A segment structure embedding of a received segment is determined by identifying, based on the predetermined syntax, a word-category for each word in the segment, thereby obtaining a sequence of word-categories; determining a category-token value for the sequence of word-categories; and encoding the category-token value as a vector defining the segment structure embedding. Word embeddings are determined by, for each word in the segment: determining a word-token value for the word; and encoding the word-token value as a vector. A unique vector embedding is determined by combining i) the vector defining the segment structure embedding and ii) each vector defining each word embedding of the word embeddings, wherein the unique vector embedding uniquely defines the received segment and is arranged to be input into language model.
A computer-implemented method of compressing a set of values, the method comprising: determining a matrix comprising the set of values; assessing a similarity between pairs of rows and/or pairs of columns of the matrix; reordering the rows and/or columns of the matrix in dependence on the similarity between the pairs of rows and/or pairs of columns so as to form a plurality of groups of values of the set of values; and compressing at least one group of values of the plurality of groups of values so as to compress the set of values.
A method of compiling a shader which uses burst scheduling includes analysing a control flow graph for a shader to create a plurality of bursts, each burst comprising an instruction from the shader. The bursts are then analysed to group them together to form one or more new, larger, bursts using pre-defined grouping rules. The resultant bursts are then ordered using pre-defined ordering rules before a modified version of the shader is output. This modified version of the shader comprises instructions in an order according to the ordered bursts where this order is different from that of the original shader.
A mechanism for processing, on a hardware accelerator comprising fixed-function circuitry, data according to a neural network process that comprises a neural network with an associated argmax or argmin function. The argmax or argmin function is mapped to a set of elementary neural network operations available to the fixed-function circuitry. The neural network process is then executed using the fixed-function circuitry. The data processed using the neural network process comprises image and/or audio data.
A hardware unit for manipulating data stored in a memory comprises an internal buffer, a memory reading block, configured to read the data from the memory and write the data to the internal buffer. a memory writing block, configured to read the data from the internal buffer and write the data to the memory. The hardware unit optionally also comprises a control channel between the memory reading block and the memory writing block, wherein the memory reading block and the memory writing block are configured to communicate via the control channel to maintain synchronisation between them when writing the data to the internal buffer and reading the data from the internal buffer, respectively. The hardware unit may be configured to apply one or more transformations to multidimensional data in the memory. The hardware unit may be configured to traverse the multidimensional array using a plurality of nested loops.
The operation of a GPU is controlled based on one or more deadlines by which one or more GPU tasks must be completed and estimates of the time required to complete the execution of a first GPU task (which is currently being executed) and the time required to execute one or more other GPU tasks (which are not currently being executed). Based on a comparison between the deadline(s) and the estimates, context switching may or may not be triggered.
A method of verifying processing logic of a graphics processing unit receives a test task including a predefined set of instructions for execution on the graphics processing unit, the predefined set of instructions being configured to perform a predetermined set of operations on the graphics processing unit when executed for predefined input data. In a test phase, the test task is processed by executing the predefined set of instructions for the predefined input data first and second times at the graphics processing unit so as to, respectively, generate first and second outputs. A fault signal is raised if the first and second outputs do not match.
A graphics processing system for performing tile-based rendering of a scene that includes safety-critical elements. A geometry engine identifies protected tiles that include safety-critical elements in a geometry processing phase. A fragment processing engine processes each of the protected tiles first and second times so as to respectively generate first and second fragment-processed outputs in a fragment processing phase. A check unit compares the first and second fragment-processed outputs for each of the protected tiles and raises a fault signal if the first and second fragment-processed outputs do not match.
A method of compressing data is described in which the compressed data is generated by either or both of a primary compression unit or a reserve compression unit in order that a target compression threshold is satisfied. If a compressed data block generated by the primary compression unit satisfies the compression threshold, that block is output. However, if the compressed data block generated by the primary compression unit is too large, such that the compression threshold is not satisfied, a compressed data block generated by the reserve compression unit using a lossy compression technique, is output.
A method of configuring a graphics processing unit (GPU) provides an instruction to the GPU, comprising configuration data for the GPU and a request for a response from the GPU. A timer configured to expire after a time period is initialised, and the response from the GPU is monitored during the time period. The GPU is configured in accordance with the configuration data, and it is determined whether the GPU is correctly configured in accordance with the configuration data, by determining whether an error has occurred in response to determining that: (i) the GPU is not correctly configured in accordance with the configuration data; or (ii) the response is not received from the GPU before the timer expires.
Ray tracing systems and methods are described for processing rays. A parent shader is executed for a ray. The parent shader includes a shader recursion instruction which invokes a child shader. The execution of the parent shader for the ray is suspended. Intermediate data for the parent shader is stored in a heap of memory, wherein the intermediate data comprises state data and payload data. Storing intermediate data comprises allocating a first set of registers in the heap of memory for storing payload data, and allocating a second set of registers in the heap of memory for storing state data. When the parent shader is ready to resume, intermediate data for the parent shader is read from the heap of memory, and the execution of the parent shader for the ray is resumed.
A processor has a processing module a ray engine. The ray engine comprises a ray store and ray-tracing circuitry. The ray-engine comprises control logic which: receives a plurality of batches of ray descriptors supplied from the processing module, each batch comprising respective ray descriptors of a plurality of modelled rays; and allocates ray descriptors to address space of the ray store in blocks of ray descriptors, each block being a subset of the ray descriptors in the batch, and stores each block in the allocated address space. For each batch of ray descriptors, the ray-tracing circuitry processes each of the rays of the batch based on the respective ray descriptors stored in the ray store. For each block, the control logic deallocates the memory allocated to the block in response to the processing of all the rays in the block being finished by the ray-tracing engine.
A tiling unit assigning primitives to tiles in a graphics processing system which has rendering space subdivided into a plurality of tiles. Each tile can comprise one or more polygonal region. Mesh logic of the tiling unit can determine that a plurality of primitives form a mesh and can determine whether the mesh entirely covers a region. If the mesh entirely covers the region then a depth threshold for the region can be updated so that subsequent primitives which lie behind the depth threshold are culled (i.e. not included in the display list for a tile). This helps to reduce the number of primitive IDs included in a display list for a tile which reduces the amount of memory used by the display list and reduces the number of primitives which a hidden surface removal (HSR) module needs to fetch to perform HSR on the tile.
Frames are rendered in a graphics processing unit representing views of a scene in a rendering space subdivided into a plurality of tiles. Tiles of a group of frames are rendered in an interspersed order such that the frame from which a tile is rendered switches back and forth between the frames of the group of frames, wherein the view represented by each frame in the group of frames is a view of the scene at a different time instance, wherein at least one transformation indicates tiles which are likely to be similar in different frames of the group of frames, wherein the interspersed order is based on the at least one transformation such that said rendering comprises rendering similar tiles from the frames of the group of frames sequentially.
A method and system for processing a set of k floating point numbers to perform addition and/or subtraction is disclosed. Each floating-point number comprises a mantissa (mi) and an exponent (ei). The method comprises receiving the set of k floating point numbers in a first format, each floating-point number in the first format comprising a mantissa (mi) with a bit-length of b bits. The method further comprises creating a set of k numbers (yi) based on the mantissas of the k floating-point numbers, the numbers having a bit-length of n bits obtained by adding both extra most-significant bits and extra least-significant bits to the bit length b of the mantissa (mi). The method includes identifying a maximum exponent (emax) among the exponents ei, aligning the magnitude bits of the numbers (yi) based on the maximum exponent (emax) and processing the set of k numbers concurrently.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
A master unit in a core of a plurality of cores in a graphics processing unit receives a set of image rendering tasks, assigns a first subset of the image rendering tasks to a first core and assigns a second subset of the image rendering tasks to a second core. The master unit transmits the first subset of image rendering tasks to a slave unit of the first core and transmits the second subset of image rendering tasks to a slave unit of the second core. The master unit stores a credit number for each of the first and second cores and adjusts the credit number of the first and second cores by a first amount for each task in the first and second subset of the image rendering tasks. The slave units transmit credit notifications when tasks have been processed and the master unit adjusts the credit numbers when it receives the notifications.
G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
Methods and compression units for compressing a two-dimensional block of image element values. A block of image element values is compressed using a fixed-length compression scheme to form a block of compressed image element values, which are divided into a plurality of sub-blocks of compressed image element values. A pattern of a plurality of patterns formed by the compressed image element values of a first sub-block of the plurality of sub-blocks is identified, and a compressed block of compressed image element values is formed by encoding the first sub-block in the compressed block of compressed image element values with: (i) information identifying the identified pattern, and (ii) the compressed image element values of the first sub-block forming the identified pattern.
H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
H04N 19/136 - Incoming video signal characteristics or properties
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
28.
Ray Tracing Using Indications Of Re-Entry Points In A Hierarchical Acceleration Structure
A computer-implemented method of performing intersection testing in a ray tracing system performs intersection testing for each of a plurality of rays against nodes of a hierarchical acceleration structure. The intersection testing for each of the rays comprises, in response to identifying, in a memory, an indication of a re-entry point associated with a ray identifier that is associated with the ray, fetching from the memory the indication of the re-entry point that is associated with the ray identifier, the re-entry point being a node of the hierarchical acceleration structure for which an intersection has been identified for a previously tested ray associated with the ray identifier. The intersection testing for each of the rays further comprises performing intersection testing of the ray against a set of nodes of the hierarchical acceleration structure starting from the re-entry point.
Coarse depth testing is performed in a graphics processing system having a rendering space divided into a plurality of tiles. A depth range for a tile identifies a depth range based on primitives previously processed. A determination is made based on the depth range as to whether all or a portion of a primitive is hidden in the tile. If at least a portion is not hidden in the tile, a determination is made as to whether the primitive or a primitive fragment thereof has better depth than the primitives previously processed. If so, the primitive or primitive fragment is identified as not requiring a read of a depth buffer to perform full resolution depth testing, such that a determination that at least a portion of the primitive is hidden in the tile causes full resolution depth testing not to be performed on at least that portion of the primitive.
G06F 7/24 - Sorting, i.e. extracting data from one or more carriers, re-arranging the data in numerical or other ordered sequence, and re-recording the sorted data on the original carrier or on a different carrier or set of carriers
G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. The graphics processing system includes a plurality of depth buffers, thereby allowing a processing module to process primitives of one tile by accessing one of the depth buffers while primitive identifiers of another, partially processed tile are stored in another one of the depth buffers. This allows the graphics processing system to have “multiple tiles in flight”, which can increase the efficiency of the graphics processing system.
Weights of a neural network in a first number format are converted to a second number format. For at least a portion of the weights, a total quantisation error associated with quantising the weights to the second number format is computed in accordance with a first quantisation method. A subset of the weights to be quantised to the second number format is identified in accordance with a second quantisation method based on the total quantisation error. A set of quantised weights is generated by converting the weights to the second number format, wherein each weight in the subset is converted in accordance with the second quantisation method and each of the remaining weights is converted in accordance with the first quantisation method.
When an instruction is received, the instruction checks against older “in-flight” instructions for hazards, and stores a hazard flag in a control storage entry. An instruction will not start executing while the hazard flag is set. When the older instruction executes and produces a result to a register, it clears the hazard for the current instruction. The current instruction can start executing when no hazards remain.
A vector processing unit contains an operation cache and a separate micro-op cache. The operation cache tracks state and logic of instructions, and is responsible for splitting instructions into micro-ops. The micro-op cache tracks state and logic of micro-ops. Having a separate micro-op cache provides power and area benefits, as well as allowing instructions to be split out of order.
A handshaking protocol is implemented between a control unit, a vector processing unit (VPU) and a load-store unit (LSU). Micro-ops of an instruction will only be executed by the LSU if it is guaranteed not to generate an exception and no earlier micro-ops will generate an exception. The handshaking protocol guarantees this using signals passed between the control unit, VPU and LSU.
A method of rasterizing a line in computer graphics determines whether the line's start and/or end is inside a diamond test area within the pixel. If the end is not inside and the start is inside, the pixel is drawn as part of the line. If neither the start nor the end of the line are inside, it is determined whether the line crosses more than one extended diamond edge and if so, it is further determined (i) whether an extended line passing through the start and end is substantially vertical and touches the right point of the diamond area, (ii) if the extended line touches the bottom point of the diamond area, and (iii) whether the extended line is on a same side of each point of the diamond area. If any of (i), (ii) and (iii) is positive, the pixel is drawn as part of the line.
Each core of a multi-core processor is capable of running both safety-critical and non-safety-critical applications. The first core is configured to send a request to the second core to enter into a lock mode to execute the safety-critical application in parallel with the first core. A comparator receives inputs from the first core and the second core and compares the inputs. The second core drives the comparator into a transition state; stops execution of a first application running on the second core; saves data from the second core to memory associated with the second core; and sends an acknowledgment back to the first core in response to the request. The first core, in response to receiving the acknowledgement signal, is further configured to enable the execution of the safety-critical application by both cores in lock mode by configuring the memory and the comparator.
A processor includes a data buffer, the data buffer being configured as a write-combine buffer. The processor further includes logic circuitry which is configured to perform: receiving, from a further entity, an input data stream for a write operation, wherein the input data stream is received in blocks of data, and partitioning the data buffer into partitions, wherein the partitioning is based on a size of the blocks of data that are received. The logic circuitry is further configured to perform: writing each of the blocks of data to one of the partitions, each block of data being written to a partition of the data buffer based on an address associated with the respective block of data, and for each of the partitions, determining whether to initiate a draining of the respective partition to further memory based on the data that is stored in the respective partition.
A processor is able to re-encode a normal value of a first floating point format to a normalized floating point format, and re-encode a subnormal value of the first floating point format to the normalized floating point format. A subset of the exponent bits of the exponent field of a normalized floating point format is used to encode a predetermined indication of being an exceptional value, wherein a combination of bit values used to encode this predetermined indication does not occur within a range of the exponent field of the normalized floating point format used to represent any possible non-exceptional, normal and subnormal values.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
A processor can re-encode from an unnormalized wider floating point format to a normalized wider floating point format, and re-encode from an unnormalized narrower floating point format to a normalized narrower floating point format. According to the disclosure, when performing a wider-format sign injection operation on a NaN-boxed value of the normalized narrower floating point format held in a source register of a set of normalized-format registers, a bit manipulation is performed on a bit in the respective source register at a most-significant bit-position of the normalized wider floating point format. When de-normalizing the NaN-boxed value of the normalized narrower floating point format from the respective source register, the bit at the most-significant bit-position of the normalized wider floating point format is ignored in detecting NaN-boxing.
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
40.
Systems and Methods For 3-D Scene Acceleration Structure Creation and Updating
Systems and methods for producing an acceleration structure provide for subdividing a 3-D scene into a plurality of volumetric portions, which have different sizes, each being addressable using a multipart address indicating a location and a relative size of each volumetric portion. A stream of primitives is processed by characterizing each according to one or more criteria, selecting a relative size of volumetric portions for use in bounding the primitive, and finding a set of volumetric portions of that relative size which bound the primitive. A primitive ID is stored in each location of a cache associated with each volumetric portion of the set of volumetric portions. A cache location is selected for eviction, responsive to each cache eviction decision made during the processing. An element of an acceleration structure according to the contents of the evicted cache location is generated, responsive to the evicted cache location.
A method and data processing system using a processor implement a neural network containing at least one matrix multiplication operation. A set of operations to which the matrix multiplication operations are mapped is evaluated, the set of operations including at least one convolution operation, to thereby evaluate the matrix multiplication operation, whereby the processor is adapted to multiply the same set of weights simultaneously by multiple sets of input data elements in parallel at multiple processing elements.
A method and an intersection testing module for performing intersection testing in a ray tracing system determines a first offset intersection distance which is equal to a sum of an intersection distance at which a ray intersects a first primitive and a first offset which is dependent upon the orientation of the first primitive. A second offset intersection distance is determined which is equal to a sum of an intersection distance at which the ray intersects a second primitive and a second offset which is dependent upon the orientation of the second primitive. The determined first and second offset intersection distances are compared to select the intersection of the ray with one of the first and second primitives.
A processor includes a hardware pipeline comprising fixed-function hardware, a register bank to which software can write task descriptors, and a blocking circuit disposed between an upstream section and a downstream section of the hardware pipeline, wherein the blocking circuit has an open state in which data passes from the upstream section to the downstream section, and a closed state that blocks data passing from the upstream section to the downstream section. Control circuitry triggers the upstream section to start processing a second task while the downstream section is still processing the first task, and switches the blocking circuit to the closed state, in response to detecting that the upstream section has finished processing a first task.
A converter module handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.
G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
A first input and a second input are added in hardware logic to determine an output value. receiving The first input comprises a first number of bits and the second input comprises a second number of bits, the second input being wider than the first input. The first input is added to the first number of least significant bits of the second input to determine a carry value. Using a third number of most significant bits of the second input, it is determined whether there is a risk of integer overflow, the third number being equal to the first number subtracted from the second number. The determined carry value and the determined risk of overflow are used to determine whether the addition of the first input and the second input will cause integer overflow. In response to determining that the addition will cause integer overflow, the output value is determined.
Multidimensional data mapped into one-dimensional data using a Z-ordering function is parsed to identify work packets to be processed. Dimensions of the multidimensional data and information identifying a valid region of the multidimensional data are obtained, where the valid region identifies work packets. At least part of a sequence within the one-dimensional data is determined, corresponding to positions within the multidimensional data lying in the valid region, by determining whether a position defined by a first value lies within the valid region. If the position does not lie within the valid region, an overflow value is calculated which causes a least significant bit that is a 1 in a binary representation of the first value to flip to a 0. The first value and the overflow value are summed to obtain a trial value which if lying within the valid region forms part of the sequence, wherein the sequence identifies work packets to be processed.
A method and processing system for applying upsampling to input pixel values of frames of a sequence of frames to determine upsampled pixel values at upsampled pixel locations. A jitter pattern is used over the sequence such that different frames of the sequence have input pixel values at locations corresponding to different upsampled pixel locations. An initial block of upsampled pixel values is determined for a current frame. An aligned block of upsampled pixel values for the current frame is determined based on the initial block in accordance with the jitter pattern. A block of refinement values for the initial block of upsampled pixel values is determined for the current frame, and is applied to the initial block to determine a refined block of upsampled pixel values.
G06T 3/4053 - Scaling of whole images or parts thereof, e.g. expanding or contracting based on super-resolution, i.e. the output image resolution being higher than the sensor resolution
G06T 3/4023 - Scaling of whole images or parts thereof, e.g. expanding or contracting based on decimating pixels or lines of pixelsScaling of whole images or parts thereof, e.g. expanding or contracting based on inserting pixels or lines of pixels
G06T 3/4046 - Scaling of whole images or parts thereof, e.g. expanding or contracting using neural networks
A graphics processing unit (GPU) using a rendering space which is sub-divided into a plurality of tiles comprises a plurality of tile pipelines and a tile arbiter. The tile arbiter receives tile-primitive indications, each of which indicates an association between a tile and a set of primitives. The tile arbiter determines which of the tile pipelines to send each of the tile-primitive indications to in accordance with a dynamic allocation scheme. The tile arbiter sends each of the tile-primitive indications to the tile pipeline determined for that tile-primitive indication. Each of the tile pipelines is configured to: receive the tile-primitive indications that are sent to that tile pipeline by the tile arbiter; and use the received tile-primitive indications to, for each of the tiles for which a tile-primitive indication is received at the tile pipeline, include in a control stream for that tile, indications of primitives that are present within that tile.
Fast matrix multiplication in a multithreaded processing system having one or more processing units, each processing unit operates a plurality of threads grouped into a plurality of workgroups. At least a portion of a first matrix input is stored in a cache dedicated to a first processing unit as a first matrix subunit. At least a portion of a second matrix input is stored in a local memory dedicated to the first processing unit as a second matrix subunit. A plurality of output matrix subunits is generated by launching a plurality of workgroups. A subset of one or more second matrix subunits is assigned to a workgroup. Each of the first matrix subunits is multiplied with a corresponding second matrix subunit to obtain an output matrix subunit. During the generation of the plurality of output matrix subunits, the first matrix subunits are concurrently accessed by each launched workgroup from a cache dedicated to the first processing unit.
A system for controlling memory buffer reservation comprising a transmitter, a receiver and buffer control logic is provided. The transmitter is configured to transmit a plurality of memory requests on two or more request channels, the plurality of memory requests comprising at least one priority request transmitted on a first request channel. The receiver comprises a plurality of buffers, each buffer having an associated credit, wherein each request channel is provided with a credit value based on the number of buffers allocated to receive memory requests from the corresponding request channel, where at least one credit is provided to the first request channel. The buffer control logic enables the first request channel to use a buffer allocated to a second request channel by utilizing a credit provided to the second request channel for transmitting the priority request to the receiver when a credit provided to first request channel is unavailable.
Methods for selecting fixed point number formats for representing values input to and/or output from layers of a Deep Neural Network (DNN) which take into account the impact of the fixed point number formats for a particular layer in the DNN. The fixed point number format(s) used to represent sets of values input to and/or output from a layer are selected one layer at a time in a predetermined sequence wherein any layer is preceded in the sequence by the layer(s) from which it depends. The fixed point number format(s) for each layer is/are selected based on the error in the output of the DNN associated with the fixed point number formats. Once the fixed point number format(s) for a layer has/have been selected any calculation of the error in the output of the DNN for a subsequent layer in the sequence is based on that layer being configured to use the selected fixed point number formats.
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
G06N 3/04 - Architecture, e.g. interconnection topology
During tracing of a primary ray in a 3-D space (e.g., a 3-D scene in graphics rendering), a ray is found to intersect a primitive (e.g., a triangle) located in the 3-D space. Secondary ray(s) may be generated for a variety of purposes. For example, occlusion rays may be generated to test occlusion of a point of intersection between the primary ray and primitive is illuminated by any of the light(s). An origin for each secondary ray can be modified from the intersection point based on characteristics of the primitive intersected. For example, an offset from the intersection point can be calculated using barycentric coordinates of the intersection point and interpolation of one or more parameters associated with vertices defining the primitive. These parameters may include a size of the primitive and differences between a geometric normal for the primitive and a respective additional vector supplied with each vertex.
Hierarchical methods for selecting fixed point number formats with reduced mantissa bit lengths for representing values input to, and/or output, from, the layers of a DNN. The methods begin with one or more initial fixed point number formats for each layer. The layers are divided into subsets of layers and the mantissa bit lengths of the fixed point number formats are iteratively reduced from the initial fixed point number formats on a per subset basis. If a reduction causes the output error of the DNN to exceed an error threshold, then the reduction is discarded, and no more reductions are made to the layers of the subset. Otherwise a further reduction is made to the fixed point number formats for the layers in that subset. Once no further reductions can be made to any of the subsets the method is repeated for continually increasing numbers of subsets until a predetermined number of layers per subset is achieved.
G06N 3/04 - Architecture, e.g. interconnection topology
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
G06F 17/11 - Complex mathematical operations for solving equations
Hierarchical methods for selecting fixed point number formats with reduced mantissa bit lengths for representing values input to, and/or output, from, the layers of a DNN. The methods begin with one or more initial fixed point number formats for each layer. The layers are divided into subsets of layers and the mantissa bit lengths of the fixed point number formats are iteratively reduced from the initial fixed point number formats on a per subset basis. If a reduction causes the output error of the DNN to exceed an error threshold, then the reduction is discarded, and no more reductions are made to the layers of the subset. Otherwise a further reduction is made to the fixed point number formats for the layers in that subset. Once no further reductions can be made to any of the subsets the method is repeated for continually increasing numbers of subsets until a predetermined number of layers per subset is achieved.
G06N 3/04 - Architecture, e.g. interconnection topology
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
G06F 17/11 - Complex mathematical operations for solving equations
A graphics processing system is configured to perform ray tracing. Rays are bundled together and processed together into a ray bundle using a programmable chip. Intersection testing is performed on the rays of the ray bundle in the scene using fixed function hardware. Results of the intersection testing are used to determine whether the rays are to be maintained in the ray bundle. A plurality of instances of a shader program, each corresponding to a ray of the ray bundle, are executed, wherein the shader program utilizes data determined by the execution of an instance of the shader program corresponding to a first ray of the ray bundle in the execution of an instance of the shader program for a further ray of the ray bundle.
A set of image rendering tasks and state information are distributed in a graphics processing unit (GPU) having a plurality of cores. A first master unit in one of the cores receives the set of image rendering tasks and the state information, and stores the state information in a memory. The first master unit splits the set of image rendering tasks into a first subset of tasks and a second subset of tasks, wherein the first subset of tasks is assigned to the first core, and the second subset of tasks is assigned to the second core. At least a first portion of the state information is transmitted to the first core, and at least a second portion of the state information is transmitted to the second core. The first subset of tasks is transmitted to the first core, and the second subset of tasks is transmitted to the second core.
G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
An application sends primitives to a graphics processing system so that an image of a 3D scene can be rendered. The primitives are placed into primitive blocks for storage and retrieval from a parameter memory. Rather than simply placing the first primitives into a primitive block until the primitive block is full and then placing further primitives into the next primitive block, multiple primitive blocks can be “open” such that a primitive block allocation module can allocate primitives to one of the open primitive blocks to thereby sort the primitives into primitive blocks according to their spatial positions. By grouping primitives together into primitive blocks in accordance with their spatial positions, the performance of a rasterization module can be improved. For example, in a tile-based rendering system this may mean that fewer primitive blocks need to be fetched by a hidden surface removal module in order to process a tile.
A graphics processing system is configured to perform ray tracing. Rays are bundled together and processed together into a ray bundle using a programmable chip. Intersection testing is performed on the rays of the ray bundle in the scene using fixed function hardware. Results of the intersection testing are used to determine whether the rays are to be maintained in the ray bundle. Shader programs are executed on the rays in the ray bundle by determining differential data for a particular ray of the ray bundle using data for another ray of the ray bundle.
A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by
A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by
1
/
d
i
.
A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by
1
/
d
i
.
The hardware logic comprises a plurality of multipliers and adders arranged to implement a mth-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.
G06F 7/57 - Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups or for performing logical operations
A method performed by a graphics processor searches for a candidate reinsertion for each of a plurality of input nodes of a current bounding volume hierarchy (BVH) which would move the input node from an old parent to a new parent, and which would reduce an expected computational cost of searching the BVH for a ray intersection; and performs a first update to update the current BVH with one or more selected reinsertions from among the candidates. The selection comprises a conflict check to determine whether any group of the candidates would affect a same part of the current BVH, and if so selecting only one of the group to include in the first update. At least one of the iterations further comprises, after the first update, performing a second update within the same iteration to update the current BVH with another of said group.
A method and intersection testing module are provided in a ray tracing system for determining whether a ray intersects a 3D axis-aligned volume. The volume is defined by a front-facing plane and a back-facing plane for each of the dimensions of the three-dimensional axis-aligned volume. Scaled ray components are determined, wherein a third scaled ray component equals 1. A scaled minimum culling distance and a scaled maximum culling distance are determined. Determined cross-multiplication values are used to identify which of the front-facing planes intersects the ray furthest along the ray and identify which of the back-facing planes intersects the ray least far along the ray. It is determined whether the ray intersects the identified front-facing plane of the volume at a position that is no further along the ray than the position at which the ray intersects the identified back-facing plane.
Power consumption of read/write operations of a processor is reduced by encoding data values. An input value of a plurality of input values with a uniformly distributed random probability is mapped to one of a predefined set of codes, wherein the input value is mapped to a code that comprises more bits than the input value. The codes corresponding to the input value are outputted, wherein compared to an input value having a relatively low value, an input value having a relatively high value is mapped to a code of the pre-defined set of codes which either: (i) is closer to a target Hamming Weight, or (ii) has closer to a target number of bit flips within the code.
H03M 7/02 - Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
63.
Compression and Decompression of Sub-Primitive Presence Indications for Use in a Rendering System
Compressed data is decompressed to determine one or more sub-primitive presence indications for use in a rendering system. It is determined whether child-level data is included in a hierarchical representation for a parent region in a block of compressed data for a block of sub-primitive presence indications subdivided into a plurality of parent regions, each subdivided into a plurality of child regions, where the block comprises the hierarchical representation of the block of sub-primitive presence indications, wherein for each of parent regions whose child regions all have the same presence state, parent-level data is included in the hierarchical representation to represent the presence state of the parent region without child-level data for the child regions within the parent region being included in the hierarchical representation. Where child-level data is not included in the hierarchical representation for the parent region, parent-level data for the parent region is used without child-level data, to determine one or more sub-primitive presence indications in the parent region.
A multicore graphics rendering system includes a plurality of cores configured to implement tile-based rendering of a stream of primitives. First cores are configured to process groups of primitives, to produce transformed geometry data. The graphics rendering system uses at least one virtualised memory space. At least one virtualised memory space is segmented such that the first cores are allocated respective non-overlapping virtual address ranges in the space, the virtual address ranges being associated with different entries in a top level of the index. The top level of the hierarchical index is pre-allocated, and each core is primed by providing it with said top level of the hierarchical index.
A system and method for coherency gathering for rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes including upper level nodes and lower level nodes. For each instance where one of the lower level nodes is a child of one of the upper level nodes, an instance transform is defined, specifying the relationship between a first coordinate system of the upper level node and the second coordinate system for that instance of the lower level node. The system provides an instance transform cache for storing a plurality of these instance transforms while conducting intersection testing.
A method and apparatus are provided for allocating memory for geometry processing in a 3-D graphics rendering system comprising multiple cores. Geometry processing work is divided up into discrete work-packages, which form an ordered sequence. Cores are assigned different work-packages to process, and make memory allocation requests to enable them to store the results of the processing. Memory allocation requests relating to the current earliest uncompleted work-package in the sequence are treated differently to other requests, and may be prioritised.
A method for generating an augmented reality image from first and second images, wherein at least a portion of at least one of the first and the second image is captured from a real scene, identifies a confidence region in which a confident determination as to which of the first and second image to render in that region of the augmented reality image can be made, and identifies an uncertainty region in which it is uncertain as to which of the first and second image to render in that region of the augmented reality image. At least one blending factor value in the uncertainty region is determined based upon a similarity between a first colour value in the uncertainty region and a second colour value in the confidence region, and an augmented reality image is generated by combining, in the uncertainty region, the first and second images using the at least one blending factor value.
A multicore graphics rendering system includes a plurality of cores configured to implement tile-based rendering of a stream of primitives. The graphics rendering system uses at least one virtualised memory space. A hierarchical index is provided, to index the physical memory portions associated with virtual memory portions in the at least one virtualised memory space. The portions of memory allocated for the hierarchical index are recorded in an MMU (memory management unit) list (MLIST). The MLIST comprises a plurality of entries, each entry being associated with a respective portion of the hierarchical index, wherein each entry includes an indication of the portion of virtual memory that is indexed by that portion of the hierarchical index. The MLIST is used to identify, and free, portions of memory associated with indexing virtual memory that has been fully consumed in a partial render.
A binary logic circuit for converting a number in floating point format into a fixed point format. An inverting hardware circuit inverts bit values of an exponent. A shifter coupled to the inverting hardware circuit receives a significand input comprising a contiguous set of the most significant bits of the significand and right-shifts the significand input by a number of bits equal to the value represented by p least significant bits of the inverted exponent to generate a shifter output, wherein p is dependent on an integer width iw or a fractional width fw. A multiplexer coupled to the shifter receives an input comprising a contiguous set of bits of the shifter output, and outputs the input if the most significant bit of the exponent is equal to zero.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
G06F 7/48 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices
H03M 7/24 - Conversion to or from floating-point codes
A method of rendering primitives is described. Vertex coordinates are converted from floating-point to fixed-point format and triangle primitives having non-zero area prior to the conversion and zero area after the conversion and primitives that have changed from line primitives to point primitives as a consequence of the conversion are identified. A flag is set for each identified primitive and triangle or line primitives that have changed to point primitives as a consequence of the conversion are marked as small objects. Tile lists for each tile in the rendering space are then generated by: for any primitive that is not flagged as a degenerate primitive, using one or more edge calculations to determine whether the primitive overlaps a tile; and for any primitive that is both marked as a small object and flagged as a degenerate primitive, using a conservative bounding box to determine whether the primitive overlaps a tile.
G06V 10/25 - Determination of region of interest [ROI] or a volume of interest [VOI]
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
In an aspect, an update unit can evaluate condition(s) in an update request and update one or more memory locations based on the condition evaluation. The update unit can operate atomically to determine whether to effect the update and to make the update. Updates can include one or more of incrementing and swapping values. An update request may specify one of a pre-determined set of update types. Some update types may be conditional and others unconditional. The update unit can be coupled to receive update requests from a plurality of computation units. The computation units may not have privileges to directly generate write requests to be effected on at least some of the locations in memory. The computation units can be fixed function circuitry operating on inputs received from programmable computation elements. The update unit may include a buffer to hold received update requests.
G06T 15/00 - 3D [Three Dimensional] image rendering
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/126 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
Hardware units and methods for performing matrix multiplication via a multi-stage pipeline wherein the storage elements associated with one or more stages of the pipeline are clock gated based on the data elements and/or portions thereof that known to have a zero value (or can be treated as having a zero value). In some cases, the storage elements may be clock gated on a per data element basis based on whether the data element has a zero value (or can be treated as having a zero value). In other cases, the storage elements may be clock gated on a partial element basis based on the bit width of the data elements. For example, if bit width of the data elements is less than a maximum bit width for the data elements then a portion of the bits related to that data element can be treated as having a zero value and a portion of the storage elements associated with that data element may not be clocked. In yet other cases the storage elements may be clock gated on both a per element and a partial element basis.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
A method and system for generating and shading a computer graphics image in a tile based computer graphics system is provided. Geometry data is supplied and a plurality of primitives are derived from the geometry data. One or more modified primitives are then derived from at least one of the plurality of primitives. For each of a plurality of tiles, an object list is derived including data identifying the primitive from which each modified primitive located at least partially within that tile is derived. Alternatively, the object list may include data identifying each modified primitive located at least partially within that tile. Each tile is then shaded for display using its respective object list.
Data hazards are avoided by stalling from execution a received secondary instruction determined to be dependent on a primary instruction by an associated instruction pipeline if a counter of a plurality of counters associated with the primary instruction indicates that there is a hazard related to the primary instruction. In response to detecting that a hazard related to a primary instruction has been resolved by an instruction pipeline of a plurality of instruction pipelines, an adjustment signal is transmitted to a counter block that causes the value of the counter of the plurality of counters of the counter block associated with the primary instruction to be adjusted to indicate that the hazard related to the primary instruction has been resolved.
Blocks of a video frame to be excluded from a motion-compensated operation are identified, by processing pixel values of a first frame to characterize blocks of the pixels as representing a portion of an object. Difference values between blocks of the first frame and blocks of a second frame are determined, processed difference values characterizing blocks of the first frame as representing an image component that is static between the first and second frames. A score is generated for each block of the first frame indicating a confidence level that the block represents a static image component. Blocks of the first frame are identified as protected blocks which (i) represent a portion of an object; and (ii) represent an image component that is static between the first and second frames. A dilating kernel is applied to blocks with a score indicating a low confidence level and characterizing each block within the kernel as not representing a static image component.
G06V 10/98 - Detection or correction of errors, e.g. by rescanning the pattern or by human interventionEvaluation of the quality of the acquired patterns
G06V 20/40 - ScenesScene-specific elements in video content
76.
Processing Fragments Which Have A Shader-Dependent Property In A Graphics Processing System
A graphics processing system includes hidden surface removal logic and processing logic for processing fragments. An early depth test is performed on a first fragment with the hidden surface removal logic using a depth buffer, the first fragment having a shader-dependent property. In response to the first fragment passing the early depth test, the processing logic determines the property of the first fragment. After the determination of the property of the first fragment, a late depth test is performed on the first fragment with the hidden surface removal logic using the depth buffer. After performing the early depth test on the first fragment but before the late depth test is performed on the first fragment, an early depth test is performed on a second fragment with the hidden surface removal logic, wherein the second fragment does not have a shader-dependent property.
A decoder for decoding a texel according to the Adaptive Scalable Texture Compression (ASTC) format, is configured to select a colour endpoint mode (CEM) of a plurality of different CEMs and generate a plurality of input values for inputting to multiple inputs of a logic circuit. The input values are generated such that the logic circuit will generate an intermediate output value for calculating colour endpoints in accordance with the selected CEM. For different CEMs, the decoder generates a different plurality of input values for inputting to the same inputs of the multiple inputs of the logic circuit. The logic circuit is configured to operate on the plurality of input values so as to generate the at least one intermediate output value; determine a colour endpoint pair in accordance with the selected CEM in dependence on the at least one intermediate output value; and decode the texel in dependence on the colour endpoint pair.
H04N 19/597 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding specially adapted for multi-view video sequence encoding
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
A method of preventing unauthorized access to uninitialized memory. Registers are grouped into blocks, each of which has a corresponding validity bit. When data is written to a block of memory the validity bit is set to valid. A read function reads both the register data and the validity bit but if the validity bit is set to invalid dummy values are output. Once a program is complete, or before a fresh program the validity bits are reset to invalid.
A graphics processing unit (GPU) comprises a plurality of geometry pipelines and a tiling back-end module. The geometry pipelines receive batches of primitives of a sequence of primitives. Each pipeline has geometry processing modules configured to perform geometry processing functions on the primitives of a batch. A tiling front-end module determines, for each tile of a set of tiles, tile-primitive indications indicating which of the primitives of the batch of primitives received at the geometry pipeline are present within that tile. The tiling back-end module is configured to: receive the tile-primitive indications determined by the plurality of geometry pipelines; and for each of the tiles for which a tile-primitive indication is received, include indications of the primitives that are present within that tile in a control stream for that tile in an order in accordance with an order of the primitives within the sequence of primitives.
A method for compressing work item coordinate data for work items in a work group and sending the data across an interface between a computation requesting unit and a computation sequencing unit. A work item valid mask is created in dependence on the number and positions of work items in the work group, the work item valid mask indicating valid work items in the work group. A first swizzle mask indicates which bits of a swizzle index for each work item in the work group correspond to the value of a first coordinate for that work item. A second swizzle mask indicates which bits of the swizzle index for each work item in the work group correspond to the value of a second coordinate for that work item.
Compressed work item coordinate data for work items in a work group across an interface between a computation requesting unit and a computation sequencing unit is decompressed. A work item valid mask indicates valid work items in the work group. A swizzle index is computed for each valid work item in the work group. A first swizzle mask indicates which bits of the swizzle index for each work item correspond to the value of a first coordinate for that work item. A second swizzle mask indicates which bits of the swizzle index for each work item correspond to the value of a second coordinate for that work item. First coordinates for each valid work item in dependence on the first swizzle mask and the swizzle index for that item, and second coordinates for each valid work item in dependence on the second swizzle mask and the swizzle index computed for that item are computed.
A filtering unit of a processing unit applies filtering to sequences of input values to determine output values. A control block allocates each of the sequences to a sequencer defining a sequence of operations of a filtering process to be performed on the sequence of input values allocated to that sequencer. A datapath block processes values for the operations to generate results of the operations as part of the filtering process. An arbiter controls access to the datapath block according to prioritization rules, where each operation has a priority in accordance with those rules. Operations of a first set of operations have a high priority, operations of a second set of intermediate operations which do not involve input values and which determine intermediate result values rather than determining output values have a medium priority, and operations of a third set of operations have a low priority, wherein the third set of operations comprises output operations which determine output values.
A filtering unit applies filtering methods to input values to determine output values. A plurality of inputs receive input values, signal values, and filter coefficients. The signal values define a filtering mode and the filter coefficients correspond to a filtering method. A computation pipeline receives two input values and a corresponding filter coefficient, and performs an interpolation using the input values and the filter coefficient. Registers store intermediate output values generated by the computation pipeline. Signal values, a volumetric filter coefficient, and an input value are received, and it is determined i) that a filtering mode defined by the received signal values comprises volumetric filtering and at least one other filtering method and ii) that the volumetric filter coefficient is equal to zero. In response to determining i) and ii) the filtering unit stores the received input value in a register of the plurality of registers.
A hardware module for performing dot product operations includes receiver circuitry receiving a first vector and a second vector, each comprising at least two elements of a binary encoded integer. Logic generates an array of partial products of N rows of bits for a dot product operation between the first vector and the second vector. Grouping circuitry groups bits of the elements of the second vector into a binary number, wherein each binary number is associated with a respective row of the N rows of bits, and selector circuitry selects a partial product value for each of the N rows of bits based on the binary number that is associated with the respective row, such that one partial product is generated per binary number. The hardware module also comprises adder circuitry configured to perform adding the N rows of bits together to compute an output associated with the dot product operation between the first and second vectors.
A contained region facilitating determining whether a ray intersects an object of a scene in a ray tracing system is generated, wherein the object is contained within finite bounding regions forming an object partitioning hierarchy. The volume inside the finite bounding regions is partitioned into voxels categorised by identifying a subset of boundary voxels that lie within extents of a geometry defined by the object and which intersect with the object's contiguous surface. An occlusion utility metric comprises a component quantifying a maximum number of boundary voxels lying in a contiguous chain that intersect the contiguous surface of the object. A boundary voxel is selected to be a candidate voxel for transformation into a contained region. An expanded volume of the candidate voxel is generated through at least one dimension to obtain an expanded voxel contained within, and smaller than, the extents of the geometry defined by the object. The expanded voxel is allocated as a contained region.
A contained region for use in a ray tracing system is generated, the contained region facilitating determining whether a ray intersects an object of a scene, the object being contained within finite bounding regions which form part of an object partitioning hierarchy. The volume inside the finite bounding regions is partitioned into voxels, which are categorised by identifying a subset of internal voxels that are contained within extents of a geometry defined by the object, and determining an occlusion utility metric for each of the internal voxels which quantifies an estimate of a potential surface area of an expanded version of each internal voxel. In dependence on the occlusion utility metric, an internal voxel is selected from the subset of internal voxels to be a candidate voxel for transformation into a contained region, and a volume of the candidate voxel is expanded through at least one dimension to obtain an expanded voxel and is allocated as a contained region.
A computer-implemented method of compiling a program includes analysing the program to identify at least one group of instructions within the program that can be executed atomically. In response to identifying a group of instructions that can be executed atomically, the group of instructions is extracted from the program to form a burst; a modified program is created by inserting an instruction into the program in place of the extracted group of instructions. The instruction is configured to trigger execution of the burst, and the burst and the modified program are saved separately.
An image of a 3-D scene is rendered by rendering a noisy image at a first resolution; obtaining initial guide channels at the first resolution, and obtaining corresponding initial guide channels at a second resolution. When the two resolutions are the same, the initial guide channels at the first resolution and the corresponding initial guide channels at the second resolution may be provided by a single set of initial guide channels. Enhanced guide channels are derived from the initial guide channels using machine learning models. For each of a plurality of local neighbourhoods, the parameters of a denoising model that approximates the noisy image (in the local neighbourhood) are calculated as a function of the enhanced guide channels (at the first resolution), and the calculated parameters are applied to the one or more enhanced guide channels (at the second resolution), to produce a denoised image at the second resolution.
G06T 3/4053 - Scaling of whole images or parts thereof, e.g. expanding or contracting based on super-resolution, i.e. the output image resolution being higher than the sensor resolution
G06T 5/20 - Image enhancement or restoration using local operators
G06T 5/60 - Image enhancement or restoration using machine learning, e.g. neural networks
Shuffle accelerators for shuffling data on a shader core of a graphics processing unit include routing logic, slave logic and master logic. The routing logic selectively connects data input ports to a plurality of data output ports. The slave logic selectively provides data from a first set of instances to the plurality of data input ports and receives data from the plurality of data output ports for a second set of instances. The master logic is configured to, in response to receiving a shuffle instruction that identifies a shuffle of data between the plurality of instances, cause the routing logic and the slave logic to perform the identified shuffle of data in a plurality of phases, wherein in each phase of the plurality of phases a subset of the instances of the plurality of instances receive data from a subset of the instances of the plurality of instances.
Contained regions are selected for a ray tracing system, the contained regions facilitating determining whether a ray intersects an object of a scene contained within finite bounding regions of an object partitioning hierarchy. A target contained region is selected from candidate contained regions within extents of a geometry defined by the object. Occluded contained regions of the contained regions are identified, which the target contained region at least partially occludes. It is determined whether a surface area metric of the target contained region meets surface area utility criteria defined based on i) a surface area defined by the occluded contained regions; and ii) a surface area defined by the object. When the surface area metric does not meet the surface area utility criteria, the geometry data defining the target contained region is discarded to obtain a refined set of contained regions facilitating determining whether a ray intersects the object in dependence on determining that the ray intersects at least one contained region of the refined set of contained regions.
Processing logic of a processing system processes protected tasks first and second times to generate first and second processed outputs. A first fault detection unit compares the first and second processed outputs for a respective protected task and generates a first signal indicative of whether they match. A second fault detection unit compares the first and second processed outputs for the respective protected task and generates a second signal indicative of whether they match. The processing system is operable in a first protected mode in which the first fault detection unit and the second fault detection unit operate, concurrently, in respective mission modes, and the first signal and the second signal for the respective protected task are provided to a fault assessment unit for comparison in order to assess whether a fault existed at the first fault detection unit and/or the second fault detection unit when generating the first and second signals.
G06F 11/18 - Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits, e.g. by quadding or by majority decision circuits
G06F 11/16 - Error detection or correction of the data by redundancy in hardware
A hierarchy is a multi-level linked structure of nodes, wherein the hierarchy represents data relating to a set of one or more items to be processed. Where there are multiple input hierarchies, it may improve the efficiency of the processing of the items to merge the input hierarchies to form a merged hierarchy. The hierarchies are merged by identifying two or more sub-hierarchies within the input hierarchies which are to be merged, and determining one or more nodes of the merged hierarchy which reference nodes of the identified sub-hierarchies. The determined nodes of the merged hierarchy are stored and indications of the references between the determined nodes of the merged hierarchy and the referenced nodes of the identified sub-hierarchies are also stored. In this way, the merged hierarchy is formed for use in processing the items.
G06F 7/14 - Merging, i.e. combining at least two sets of record carriers each arranged in the same ordered sequence to produce a single set having the same ordered sequence
A method of performing safety-critical rendering at a graphics processing unit within a graphics processing system, the method comprising: receiving, at the graphics processing system, graphical data for safety-critical rendering at the graphics processing unit; scheduling at a safety controller, in accordance with a reset frequency, a plurality of resets of the graphics processing unit; rendering the graphical data at the graphics processing unit; and the safety controller causing the plurality of resets of the graphics processing unit to be performed commensurate with the reset frequency.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
G06T 15/00 - 3D [Three Dimensional] image rendering
94.
Texture Address Generation Using Fragment Pair Differences
Methods and hardware for texture address generation receive fragment coordinates for an input block of fragments and texture instructions for the fragments and calculating gradients for at least one pair of fragments. Based on the gradients, the method determines whether a first mode or a second mode of texture address generation is to be used and then uses the determined mode and the gradients to perform texture address generation. The first mode of texture address generation performs calculations at a first precision for a subset of the fragments and calculations for remaining fragments at a second, lower, precision. The second mode of texture address generation performs calculations for all fragments at the first precision and if the second mode is used and more than half of the fragments in the input block are valid, the texture address generation is performed over two clock cycles.
Object intersection testing in a ray tracing system determines whether a ray intersects an object of a scene, wherein the object is contained within a bounding region that is finite and forms part of an object partitioning hierarchy. Upon determining that the ray intersects the bounding region, at least one contained region is obtained, wherein the contained region is contained within, and smaller than, extents of a geometry defined by the object. Upon determining that the ray intersects a contained region of the at least one contained region, it is determined whether the ray intersects the object in dependence on at least determining that the ray intersects the contained region.
A computer-implemented method for compressing, an input group of m data values compresses the two least significant bits of each of the data values by mapping the two least significant bits of each of the data values in the input group of m data values collectively onto an m-bit encoding and storing the m-bit encoding, the m-bit encoding being selected from 2m m-bit encodings, the 2m m-bit encodings comprising a first group of encodings comprising (2m−4) m-bit encodings and a second group of encodings comprising four m-bit encodings, wherein if the selected encoding is an encoding from the first group of encodings then the selected encoding represents the two least significant bits for a representative group of m data values in which the second least significant bit of each of the data values is the same as a respective bit of the m-bit encoding, and wherein if the selected encoding is an encoding from the second group of encodings then the selected encoding represents the two least significant bits for a representative group of m data values in which the two least significant bits for each of the data values in the representative group are equal to the two least significant bits of the other data values in the representative group.
A method of generating identifiers (IDs) for primitives and optionally vertices during tessellation. The IDs include a binary sequence of bits that represents the sub-division steps taken during the tessellation process and so encodes the way in which tessellation has been performed. Such an ID may subsequently be used to generate a random primitive or vertex and hence recalculate vertex data for that primitive or vertex.
A method of performing anisotropic texture filtering involves performing isotropic filtering at each sampling point of a set of sampling points in an ellipse to produce isotropic filter results. Weights of an anisotropic filter are selected that minimize a cost function that penalises high frequencies in the filter response of the anisotropic filter under a constraint that the variance of the anisotropic filter is related to an anisotropic ratio squared, the anisotropic ratio being the ratio of a major radius of the ellipse to be sampled and a minor radius of the ellipse to be sampled. The plurality of isotropic filter results are combined using the selected weights of the anisotropic filter to generate at least a portion of a filter result.
A block of sub-primitive presence indications for use in a rendering system are compressed into a block of compressed data. The block of sub-primitive presence indications is subdivided into a plurality of parent regions, each of the parent regions being subdivided into a plurality of child regions. A hierarchical representation of the block of sub-primitive presence indications is determined, wherein for each of one or more parent regions whose child regions all have the same presence state according to the sub-primitive presence indications in the block of sub-primitive presence indications, parent-level data is included in the hierarchical representation to represent the presence state of the parent region without child-level data for the child regions within the parent region being included in the hierarchical representation. The determined hierarchical representation of the block of sub-primitive presence indications is then stored in the block of compressed data.
A tessellation method uses both vertex tessellation factors and displacement factors defined for each vertex of a patch, which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves calculating a vertex tessellation factor for each corner vertex in one or more input patches. Tessellation is then performed on the plurality of input patches using the vertex tessellation factors. The tessellation operation involves adding one or more new vertices and calculating a displacement factor for each newly added vertex. A world space parameter for each vertex is subsequently determined by calculating a target world space parameter for each vertex and then modifying the target world space parameter for a vertex using the displacement factor for that vertex.
