Methods of encoding and decoding are described which use a variable number of instruction words to encode instructions from an instruction set, such that different instructions within the instruction set may be encoded using different numbers of instruction words. To encode an instruction, the bits within the instruction are re-ordered and formed into instruction words based upon their variance as determined using empirical or simulation data. The bits in the instruction words are compared to corresponding predicted values and some or all of the instruction words that match the predicted values are omitted from the encoded instruction.
Adder circuits and associated methods for processing a set of at least three floating-point numbers to be added together include identifying, from among the at least three numbers, at least two numbers that have the same sign—that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together using one or more same-sign floating-point adders. A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.
G06F 7/24 - Sorting, i.e. extracting data from one or more carriers, re-arranging the data in numerical or other ordered sequence, and re-recording the sorted data on the original carrier or on a different carrier or set of carriers
G06F 7/501 - Half or full adders, i.e. basic adder cells for one denomination
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A method of filtering a target pixel in an image forms, for a kernel of pixels comprising the target pixel and its neighbouring pixels, a data model to model pixel values within the kernel; calculates a weight for each pixel of the kernel comprising: (i) a geometric term dependent on a difference in position between that pixel and the target pixel; and (ii) a data term dependent on a difference between a pixel value of that pixel and its predicted pixel value according to the data model; and uses the calculated weights to form a filtered pixel value for the target pixel, e.g. by updating the data model with a weighted regression analysis technique using the calculated weights for the pixels of the kernel; and evaluating the updated data model at the target pixel position so as to form the filtered pixel value for the target pixel.
Processing of commands at a graphics processor are controlled by receiving input data and generating a command for processing at the graphics processor from the input data, wherein the command will cause the graphics processor to write out at least one buffer of data to an external memory, and submitting the command to a queue for later processing at the graphics processor. Subsequent to submitting the command, but before the write to external memory has been completed, further input data is received and it is determined that the buffer of data does not need to be written to external memory. The graphics processor is then signalled to prevent at least a portion of the write to external memory from being performed for the command.
A method of GPU virtualization comprises allocating each virtual machine (or operating system running on a VM) an identifier by the hypervisor and then this identifier is used to tag every transaction deriving from a GPU workload operating within a given VM context (i.e. every GPU transaction on the system bus which interconnects the CPU, GPU and other peripherals). Additionally, dedicated portions of a memory resource (which may be GPU registers or RAM) are provided for each VM and whilst each VM can only see their allocated portion of the memory, a microprocessor within the GPU can see all of the memory. Access control is achieved using root memory management units which are configured by the hypervisor and which map guest physical addresses to actual memory addresses based on the identifier associated with the transaction.
Neural network accelerators with one or more neural network accelerator cores. Each neural network accelerator core has hardware accelerators configured to accelerate neural network operations, an embedded processor, a command decoder, and a hardware feedback path between the embedded processor and the command decoder. The command decoder is configured to control the hardware accelerators and the embedded processor of that core in accordance with commands of a command stream, and when the command stream comprises a set of one or more branch commands that indicate a conditional branch is to be performed, cause the embedded processor to determine a next command stream, and in response to receiving information from the embedded processor identifying the next command stream via the hardware feedback path, control the one or more hardware accelerators and the embedded processor in accordance with commands of the next command stream.
Shader processing units for a graphics processing unit execute ray tracing shaders that generate ray data associated with rays. The ray data includes a plurality of ray data elements. Store logic receives, as part of a ray tracing shader, a ray store instruction that includes: (i) information identifying a store group of a plurality of store groups, each store group comprising one or more ray data elements of the plurality of ray data elements, and (ii) information identifying one or more ray data elements of the identified store group to be stored in an external unit. In response to receiving the ray store instruction, the store logic retrieves the identified ray data elements for one or more rays from the storage. The store logic then sends one or more store requests to an external unit which cause the external unit to store the identified ray data elements for the one or more rays.
Methods and intersection testing modules are provided for determining, in a ray tracing system, whether a ray intersects a 3D axis-aligned box representing a volume defined by a front-facing plane and a back-facing plane for each dimension. The front-facing plane of the box which intersects the ray furthest along the ray is identified. It is determined whether the ray intersects the identified front-facing plane at a position that is no further along the ray than positions at which the ray intersects the back-facing planes in a subset of the dimensions, and this determination is used to determine whether the ray intersects the axis-aligned box. The subset of dimensions comprises the two dimensions for which the front-facing plane was not identified, but does not comprise the dimension for which the front-facing plane was identified. It is determined whether the ray intersects the box without performing a test to determine whether the ray intersects the identified front-facing plane at a position that is no further along the ray than a position at which the ray intersects the back-facing plane in the dimension for which the front-facing plane was identified.
A graphics processing system with a data store includes processing units for processing tasks. A check unit forms a signature which is characteristic of an output from processing a task on a processing unit, and a fault detection unit compares signatures formed at the check unit. Each task is processed first and second times at the processing units to generate first and second processed outputs. The graphics processing system write outs the first processed output to the data store, reads back the first processed output from the data store and forms at the check unit a first signature characteristic of the first processed output as read back from the data store; forms at the check unit a second signature characteristic of the second processed output, compares the first and second signatures at the fault detection unit, and raises a fault signal if the signatures do not match.
G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/16 - Error detection or correction of the data by redundancy in hardware
G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
G06F 21/64 - Protecting data integrity, e.g. using checksums, certificates or signatures
A graphics processing system for performing tile-based rendering of a scene that comprises safety-related primitives. The system comprises a plurality of graphics processing units (GPUs), each configured to i) receive tile data identifying one or more protected tiles comprising at least part of a safety-related primitive, ii) process two respective sets of protected tiles, and iii) based on said processing, generate two respective checksums for each respective set of protected tiles. The two respective sets of protected tiles are mutually exclusive, and each respective set and each protected tile being processed by two different GPUs. The system comprises a comparison unit configured to compare one or more pairs of checksums, each pair comprising a respective checksum generated based on a same respective set of protected tiles and generated by different GPUs. The graphics processing system is configured to perform one or more actions based on an outcome of said comparison.
A computer-implemented method of compressing one or more data values, uses a first number of bits to determine a second number of bits, wherein the first number of bits is for representing a maximum difference value of one or more difference values representing one or more differences between the one or more data values and an origin value; and forms compressed data, wherein the compressed data comprises one or more representations of the one or more difference values, wherein each of the one or more representations of the one or more difference values uses said determined second number of bits.
G06F 7/72 - Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radixComputing devices using combinations of denominational and non-denominational quantity representations using residue arithmetic
G06T 3/40 - Scaling of whole images or parts thereof, e.g. expanding or contracting
12.
CPU FOR IMPLEMENTING A GRAPHICS PROCESSING PIPELINE
A central processing unit for implementing a graphics processing pipeline which comprises a plurality of graphics processing tasks, the central processing unit comprising: one or more distinct graphics processing modules configured in dedicated hardware, wherein each of the one or more distinct graphics processing modules is configured to perform one of the graphics processing tasks of the graphics processing pipeline; and an execution unit configured to execute instructions of an instruction set for implementing the graphics processing pipeline, wherein the execution unit is configured to call each of the one or more distinct graphics processing modules using a respective instruction of the instruction set to perform its respective graphics processing task of the graphics processing pipeline.
A hierarchical acceleration structure for use in a ray tracing system. When generating a node for the hierarchical acceleration structure, the primitives in a particular portion of the 3D scene may be alternatively bounded by different shaped volumes. These bounding volumes or ‘bounding regions’ can be Axis Aligned Bounding Boxes (AABBs), although other bounding volumes can be used. The ray tracing system may use sets of two or more bounding volumes in a 3D scene to bound all the primitives within that portion. The choice of how to create sets of multiple bounding volumes within a portion of the 3D scene may be done by using a binary space partition (BSP). Different sets of bounding regions may present different amounts of surface area for a hypothetical ray entering the portion of the 3D scene dependent upon the expected ray direction or angle.
A graphics processing system is configured to render primitives using a rendering space that is sub-divided into sections, wherein the graphics processing system includes assessment logic configured to make an assessment regarding the presence of primitive edges in a section, and determination logic configured to determine an anti-aliasing setting for the section based on the assessment.
A computer implemented method of training a neural network configured to combine a set of coefficients with respective input data values. So as to train a test implementation of the neural network, sparsity is applied to one or more of the coefficients according to a sparsity parameter, the sparsity parameter indicating a level of sparsity to be applied to the set of coefficients; the test implementation of the neural network is operated on training input data using the coefficients so as to form training output data; in dependence on the training output data, assessing the accuracy of the neural network; the sparsity parameter is updated in dependence on the accuracy of the neural network; and a runtime implementation of the neural network is configured in dependence on the updated sparsity parameter.
G06N 3/084 - Backpropagation, e.g. using gradient descent
G06F 18/2136 - Feature extraction, e.g. by transforming the feature spaceSummarisationMappings, e.g. subspace methods based on sparsity criteria, e.g. with an overcomplete basis
G06N 3/082 - Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections
16.
Unified Rasterization and Ray Tracing Rendering Environments
A graphics processor architecture provides for scan conversion and ray tracing approaches to visible surface determination as concurrent and separate processes. Surfaces can be identified for shading by scan conversion and ray tracing. Data produced by each can be normalized, so that instances of shaders, being executed on a unified shading computation resource, can shade surfaces originating from both ray tracing and rasterization. Such resource also may execute geometry shaders. The shaders can emit rays to be tested for intersection by the ray tracing process. Such shaders can complete, without waiting for those emitted rays to complete. Where scan conversion operates on tiles of 2-D screen pixels, the ray tracing can be tile aware, and controlled to prioritize testing of rays based on scan conversion status. Ray population can be controlled by feedback to any of scan conversion, and shading.
A hardware-implemented method of indexing data elements in a source array in a memory, generates a number of shifted copy arrays based on the source array, each shifted copy array comprising the data elements of the source array at a respective shifted position. A plurality of indices for indexing the source array are received, each index of the plurality of indices indicating a target location in the source array, and for each index of the plurality of indices, a data element is retrieved from each of the shifted copy arrays. The retrieved elements are gated based on the index, to thereby select a data element.
G06F 17/11 - Complex mathematical operations for solving equations
18.
PROCESSOR HAVING FIRST AND SECOND PIPELINES AND BLOCKING CIRCUIT ENABLING SECOND PIPELINE TO PROCESS TASKS DURING DEALLOCATION OF MEMORY ALLOCATED TO FIRST PIPELINE
A processor includes a first processing pipeline, a second processing pipeline and a memory management that allocates memory regions from memory for the first processing pipeline to write the data of each of a first of a sequence of tasks, and deallocates each of the memory regions after the data therein has been processed by the second processing pipeline. A blocking circuit enables the second processing pipeline to start processing a second sequence of tasks while the memory management circuit is still deallocating some of the memory regions allocated to the data portions of the first of said sequence of tasks, the blocking circuit preventing identifiers of the data portions of the second task being passed to the memory management circuit until the memory management circuit indicates that it has completed deallocating the memory regions allocated to all the data portions of the first task.
A method for generating an augmented reality image from first and second images, wherein at least a portion of at least one of the first and the second image is captured from a real scene, identifies a confidence region in which a confident determination as to which of the first and second image to render in that region of the augmented reality image can be made, and identifies an uncertainty region in which it is uncertain as to which of the first and second image to render in that region of the augmented reality image. At least one blending factor value in the uncertainty region is determined based upon a similarity between a first colour value in the uncertainty region and a second colour value in the confidence region, and an augmented reality image is generated by combining, in the uncertainty region, the first and second images using the at least one blending factor value.
Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods include receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.
A ray tracing system determines whether a ray intersects a three-dimensional axis-aligned box by determining whether a minimum distance condition and a maximum distance condition are satisfied, wherein the determining comprises determining whether a single distance condition is satisfied. The determination is used to determine whether the ray intersects the axis-aligned box. A point on the ray is at a position O+Dt where O is a vector which represents an origin of the ray, and t represents a distance along the ray from the origin of the ray, and wherein D is a 3D vector defining a direction vector of the ray.
A ray tracing unit and method for processing a ray in a ray tracing system performs intersection testing for the ray by performing one or more intersection testing iterations. Each intersection testing iteration includes: (i) traversing an acceleration structure to identify the nearest intersection of the ray with a primitive that has not been identified as the nearest intersection in any previous intersection testing iterations for the ray; and (ii) if, based on a characteristic of the primitive, a traverse shader is to be executed in respect of the identified intersection: executing the traverse shader in respect of the identified intersection; and if the execution of the traverse shader determines that the ray does not intersect the primitive at the identified intersection, causing another intersection testing iteration to be performed. When the intersection testing for the ray is complete, an output shader is executed to process a result of the intersection testing for the ray.
A method of performing intersection testing in a ray tracing system, for a ray with respect to a set of two or more primitives. Each primitive is defined by an ordered set of edges, and each edge is defined by a respective pair of vertices. A set of distinct edges is determined for the set of primitives, each distinct edge being part of at least one primitive of the set of primitives and being defined by a different pair of vertices to the other distinct edges in the set, wherein every edge in the ordered sets of edges that define the set of primitives is represented by a distinct edge of the set of distinct edges. For each distinct edge in the set of distinct edges, an edge test is performed to determine which side of the distinct edge the ray passes on. For each primitive in the set of primitives, a result of the edge test is used for each distinct edge that defines that primitive to determine whether or not the ray intersects that primitive.
A method of processing a primitive as part of intersection testing in a ray tracing system, the primitive being defined by an ordered set of vertices. Data defining a direction and an origin of a ray to be tested against the primitive, and coordinate data for a set of vertices are received. The coordinate data for the set of vertices is projected into ray space using the ray data, wherein the ray space has two non-parallel axes that are transverse to the direction of the ray, wherein a ray-space frame of reference associated with the axes is centered at a point on the ray such that the ray is represented as that point on the axes in the ray space, and wherein the point is an origin of the ray space. Then, the signs of the coordinate data for the set of vertices are analysed to determine whether a non-intersection condition is fulfilled, wherein fulfilment of the non-intersection condition indicates that the ray does not intersect the primitive. In response to determining that the non-intersection condition is fulfilled, it is determined that the ray does not intersect the primitive.
An image of a 3-D scene is rendered by first rendering a noisy image at a first resolution. One or more guide channels at the first resolution and one or more corresponding guide channels at a second resolution are obtained. When the two resolutions are the same, the guide channels at the first resolution and the corresponding guide channels at the second resolution may be provided by a single set of guide channels. For each of a plurality of local neighborhoods, the parameters of a model that approximates the noisy image as a function of the one or more guide channels (at the first resolution) are calculated, and the calculated parameters are applied to the one or more guide channels (at the second resolution), to produce a denoised image at the second resolution. The one or more guide channels include at least one guide channel characterizing a spatial dependency of incident light on global lighting over the surface of one or more 3-D models in the scene.
A processing unit configured to perform parallel processing includes a parallel processing engine, the parallel processing engine including a plurality of processing instances configured to process instructions in parallel. Test instruction insertion logic identifies an idle cycle of the parallel processing engine and inserts a test instruction for processing during the idle cycle by each of the plurality of processing instances so as to generate a respective plurality of test outputs. Check logic compares a test output generated during the idle cycle by a first processing instance of the plurality of processing instances with a test output generated during the idle cycle by a second processing instance of the plurality of processing instances, and raises a fault signal if the compared test outputs do not match.
A first pixel in a first group of neighbouring pixels classified as acceptable or not acceptable with respect to a second pixel in a second group of neighbouring pixels. It is determined whether a difference between the first pixel and the second pixel is greater than a threshold difference, and in response to determining that the difference between the first pixel and the second pixel is greater than the threshold difference, the pixels in at least one of the first and second groups of neighbouring pixels are analysed to determine whether the difference is indicative of the first pixel being erroneous. The first pixel is classified as acceptable or not acceptable based on whether the difference is determined to be indicative of the first pixel being erroneous, and the classification of the first pixel is outputted.
A decoder for decoding texels of a p by q sub-block from a block of ASTC encoded texture data representing an n by m block of texels, where p≤n and q≤m. The decoder determines a position of a first texel of the sub-block with respect to the rows and/or columns of a weight grid comprising a first plurality of weights in a first plane; determines a position of a second texel of the sub-block with respect to the rows and/or columns of the weight grid; compares the positions of the first and second texels; extracts fewer than (p+1)(q+1) weights in response to determining that the positions of the first and second texels are between the upper-most and lower-most rows of a predetermined number of adjacent rows of the weight grid and/or the left-most and right-most columns of a predetermined number of adjacent columns of the weight grid; and decodes the texels in dependence on the extracted weights.
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
H04N 19/167 - Position within a video image, e.g. region of interest [ROI]
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
29.
Reduced Acceleration Structures for Ray Tracing Systems
Ray tracing units, processing modules and methods are described for generating one or more reduced acceleration structures to be used for intersection testing in a ray tracing system for processing a 3D scene. Nodes of the reduced acceleration structure(s) are determined, wherein a reduced acceleration structure represents a subset of the 3D scene. The reduced acceleration structure(s) are stored for use in intersection testing. Since the reduced acceleration structures represent a subset of the scene (rather than the whole scene) the memory usage for storing the acceleration structure is reduced, and the latency in the traversal of the acceleration structure is reduced.
A computer-implemented method and a processing module for identifying that a fault has occurred in a finite-state machine (FSM). It is determined whether a set of one or more transitions that have occurred between states of the FSM is allowable. In response to determining that the set of one or more transitions is not allowable, it is identified that a fault has occurred in the FSM.
A method of processing instructions at a processing unit having a parallel processing engine. During a mission cycle, a first set of mission operand values is processed in accordance with a mission instruction at a first processing instance to generate a first mission output. In parallel, a second set of mission operand values is processed in accordance with the mission instruction at a second processing instance to generate a second mission output. During a test cycle, a first set of test operand values is processed in accordance with a test instruction at the first processing instance to generate a first test output, and in parallel, a second set of test operand values is processed in accordance with the test instruction at the second processing instance to generate a second test output, where the first set of test operand values is the same as the second set of test operand values. The first test output and the second test output are compared and a fault signal is raised if the compared test outputs do not match.
A method of rounding a floating-point number in an Extended Exponent Range (EER), that would be a denormal floating-point number represented in an Unextended Exponent Range (UER) includes the steps of receiving, at an arithmetic unit, a plurality of input numbers in the EER representation, each input number comprising a sign bit (si), exponent bits (ei) and mantissa bits (mi); performing an arithmetic operation to produce an output number in the EER representation comprising a sign bit (sa), an exponent bits (ea) and mantissa bits (ma); constructing a rounding mask based on the exponent bits (ea) computed by the arithmetic operation; and applying the rounding mask to the output number in the EER representation to round the output number to correct position as if rounding in the UER representation.
A graphics processing unit for graphics data in a tile-based rendering space includes a plurality of processing cores, cost indication logic which obtains a cost indication parameter from a set of tiles, similarity indication logic which obtains similarity indications between sets of tiles of the rendering space, and scheduling logic that assigns the sets of tiles to the processing cores for rendering in dependence on the cost indications and the similarity indications. The similarity indication logic is configured to assign a single similarity indication to each of a plurality of sets of one or more tiles, the similarity indication assigned to each set of one or more tiles being indicative of a level of similarity between that set of one or more tiles and another set of one or more tiles specified according to a spatial order of the tiles within the rendering space.
A method of scheduling tasks in a processor comprises receiving a plurality of tasks that are ready to be executed, i.e. all their dependencies have been met and all the resources required to execute the task are available, and adding the received tasks to a task queue (or “task pool”). The number of tasks that are executing is monitored and in response to determining that an additional task can be executed by the processor, a task is selected from the task pool based at least in part on a comparison of indications of resources used by tasks being executed and indications of resources used by individual tasks in the task pool and the selected task is then sent for execution.
A graphics processing system for generating a rendering output includes geometry processing logic having first transformation logic configured to transform a plurality of untransformed primitives into a plurality of transformed primitives, the first transformation logic configured to implement one or more expansion transformation stages which generate one or more sub-primitives; a primitive block generator configured to divide the plurality of transformed primitives into a plurality of groups; and generate an untransformed primitive block for each group comprising (i) information identifying the untransformed primitives related to the transformed primitives in the group; and (ii) an expansion transformation stage mask for at least one or more expansion transformation stages that indicates the sub-primitives generated for the untransformed primitives in that untransformed primitive block used in generating the rendering output. Rasterization logic includes second transformation logic configured to re-transform the plurality of untransformed primitives into the plurality of transformed primitives on an untransformed primitive block-basis in accordance with the expansion transformation stage mask for the one or more expansion transformation stages; and logic configured to render the transformed primitives to generate the rendering output.
A control stream decoder decodes a control stream for a tile group comprising at least two tiles of a rendering space. A primitive block entry analyser received a primitive block entry of the control stream and identifies a location in memory of a control data block for a corresponding primitive block. For the received primitive block entry, in response to determining that a current tile is a valid tile for the corresponding primitive block, the control data block for the corresponding primitive block is retrieved from the identified location in memory. An address of the corresponding primitive block in memory is identified from the control data block and primitives of that primitive block relevant for rendering the current tile, and information identifying the address of the corresponding primitive block and the primitives of that primitive block relevant for rendering the current tile is outputted.
An image processing method and an image processing unit for performing image processing determines a set of one or more filtered pixel values, wherein the one or more filtered pixel values represent a result of processing image data using a set of one or more filtering functions. A total covariance of the set of one or more filtering functions is identified. A refinement filtering function is applied to the set of one or more filtered pixel values to determine a set of one or more refined pixel values, wherein the refinement filtering function has a covariance that is determined based on the total covariance of the set of one or more filtering functions.
In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., Newton-Raphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementation-dependent processing) forms an initial approximation of a value, with a number of bits of precision. A limited-precision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor. The full-precision multiplier circuit requires a first number of clock cycles to complete, and both the small multiplier and the initial approximation circuitry complete within the first number of clock cycles.
Aspects relate to tracing rays in 3-D scenes that comprise objects that are defined by or with implicit geometry. In an example, a trapping element defines a portion of 3-D space in which implicit geometry exist. When a ray is found to intersect a trapping element, a trapping element procedure is executed. The trapping element procedure may comprise marching a ray through a 3-D volume and evaluating a function that defines the implicit geometry for each current 3-D position of the ray. An intersection detected with the implicit geometry may be found concurrently with intersections for the same ray with explicitly-defined geometry, and data describing these intersections may be stored with the ray and resolved.
3-D rendering systems include a rasterization section that can fetch untransformed geometry, transform geometry and cache data for transformed geometry in a memory. As an example, the rasterization section can transform the geometry into screen space. The geometry can include one or more of static geometry and dynamic geometry. The rasterization section can query the cache for presence of data pertaining to a specific element or elements of geometry, and use that data from the cache, if present, and otherwise perform the transformation again, for actions such as hidden surface removal. The rasterization section can receive, from a geometry processing section, tiled geometry lists and perform the hidden surface removal for pixels within respective tiles to which those lists pertain.
Graphics processing system configured to perform ray tracing. Rays are bundled together and processed together. When differential data is needed by a shader, the data of a true ray in the bundle can be used rather than processing separate tracker rays.
A binary logic circuit for determining y=x mod (2m−1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer β and a second m-bit integer γ; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by β; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by γ; and the binary value 1.
G06F 7/72 - Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radixComputing devices using combinations of denominational and non-denominational quantity representations using residue arithmetic
43.
Synchronising Devices Using Clock Signal Delay Comparison
A time difference between an occurrence of a first event and an occurrence of a second event is estimated. A first time marker indicating the occurrence of the first event and a second time marker indicating the occurrence of the second event are received, wherein at least one event is one of playing a media frame or receiving a beacon. A plurality of delayed versions of the first time marker are provided, each being delayed by a different amount of delay to the other delayed versions. Each of the delayed versions of the first time marker are compared with the second time marker to identify which of the delayed versions of the first time marker is the closest temporally matching time marker to the second time marker. The time difference between the first and second time markers is estimated in dependence on the identified delayed version.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03K 5/15 - Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
H04L 7/00 - Arrangements for synchronising receiver with transmitter
44.
IMMERSIVE VIRTUAL REALITY SYSTEM USING RAY TRACING
Ray tracing, and more generally, graphics operations taking place in a 3-D scene, involve a plurality of constituent graphics operations. Responsibility for executing these operations can be distributed among different sets of computation units. The sets of computation units each can execute a set of instructions on a parallelized set of input data elements and produce results. These results can be that the data elements can be categorized into different subsets, where each subset requires different processing as a next step. The data elements of these different subsets can be coalesced so that they are contiguous in a results set. The results set can be used to schedule additional computation, and if there are empty locations of a scheduling vector (after accounting for the members of a given subset), then those empty locations can be filled with other data elements that require the same further processing as that subset.
Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.
Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing a non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a selection of bits of the binary classification dataset and sort its received selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset. Output generating logic selects between bits belonging to different intermediary binary strings to generate a binary output identifying a set of output memory addresses containing at least one address in the identified subset.
A memory interface for interfacing between a memory bus and a cache memory. A plurality of bus interfaces are configured to transfer data between the memory bus and the cache memory, and a plurality of snoop processors are configured to receive snoop requests from the memory bus. Each snoop processor is associated with a respective bus interface and each snoop processor is configured, on receiving a snoop request, to determine whether the snoop request relates to the bus interface associated with that snoop processor and to process the snoop request in dependence on that determination.
Graphics processing systems can include lighting effects when rendering images. “Light probes” are directional representations of lighting at particular probe positions in the space of a scene which is being rendered. Light probes can be determined iteratively, which can allow them to be determined dynamically, in real-time over a sequence of frames. Once the light probes have been determined for a frame then the lighting at a pixel can be determined based on the lighting at the nearby light probe positions. Pixels can then be shaded based on the lighting determined for the pixel positions.
Input data for a convolutional neural network (CNN) is stored in a buffer comprising a plurality of banks, by receiving input data comprising input data values to be processed in the CNN, determining addresses in the buffer in which the received input data values are to be stored, keeping a cursor for one or more salient positions to reduce arithmetic performed to determine the addresses in the buffer in which the received input data values are to be stored, and storing the received input data values at the determined addresses in the buffer.
Out-of-bounds recovery circuits are configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G06F 21/52 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure
Rendering systems that can use combinations of rasterization rendering processes and ray tracing rendering processes are disclosed. In some implementations, these systems perform a rasterization pass to identify visible surfaces of pixels in an image. Some implementations may begin shading processes for visible surfaces, before the geometry is entirely processed, in which rays are emitted. Rays can be culled at various points during processing, based on determining whether the surface from which the ray was emitted is still visible. Rendering systems may implement rendering effects as disclosed.
Systems and methods of geometry processing, for rasterization and ray tracing processes provide for pre-processing of source geometry, such as by tessellating or other procedural modification of source geometry, to produce final geometry on which a rendering will be based. An acceleration structure (or portion thereof) for use during ray tracing is defined based on the final geometry. Only coarse-grained elements of the acceleration structure may be produced or retained, and a fine-grained structure within a particular coarse-grained element may be Produced in response to a collection of rays being ready for traversal within the coarse grained element. Final geometry can be recreated in response to demand from a rasterization engine, and from ray intersection units that require such geometry for intersection testing with primitives. Geometry at different resolutions can be generated to respond to demands from different rendering components.
A windowed operation is implemented in at least three traversed dimensions. The windowed operation applies a window having at least three dimensions to data having at least three traversed dimensions, with shifts of the window in all three traversed dimensions. Two dimensions of the at least three traversed dimensions are selected, and the windowed operation is mapped to a plurality of constituent 2-D windowed operations in the selected two dimensions, the 2-D windowed operations applying a slice of the window to a slice of the data, with shifts of the slice of the window in only two dimensions. Each of the plurality of 2-D windowed operations is implemented by at least one hardware accelerator, each 2-D windowed operation producing a respective partial result, and the partial results are assembled to produce the result of the windowed operation.
Graphics processing systems and methods provide soft shadowing effects into rendered images. This is achieved in a simple manner which can be implemented in real-time without incurring high processing costs so it is suitable for implementation in low-cost devices. Rays are cast from positions on visible surfaces corresponding to pixel positions towards the center of a light, and occlusions of the rays are determined. The results of these determinations are used to apply soft shadows to the rendered pixel values.
A method of synchronizing a group of scheduled tasks within a parallel processing unit into a known state is described. The method uses a synchronization instruction in a scheduled task which triggers, in response to decoding of the instruction, an instruction decoder to place the scheduled task into a non-active state and forward the decoded synchronization instruction to an atomic ALU for execution. When the atomic ALU executes the decoded synchronization instruction, the atomic ALU performs an operation and check on data assigned to the group ID of the scheduled task and if the check is passed, all scheduled tasks having the particular group ID are removed from the non-active state.
G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
G06F 7/575 - Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/52 - Program synchronisationMutual exclusion, e.g. by means of semaphores
G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake
G06F 15/76 - Architectures of general purpose stored program computers
56.
Graphics Processor with Non-Blocking Concurrent Architecture
In some aspects, systems and methods provide for forming groupings of a plurality of independently-specified computation workloads, such as graphics processing workloads, and in a specific example, ray tracing workloads. The workloads include a scheduling key, which is one basis on which the groupings can be formed. Workloads grouped together can all execute from the same source of instructions, on one or more different private data elements. Such workloads can recursively instantiate other workloads that reference the same private data elements. In some examples, the scheduling key can be used to identify a data element to be used by all the workloads of a grouping. Memory conflicts to private data elements are handled through scheduling of non-conflicted workloads or specific instructions and/or deferring conflicted workloads instead of locking memory locations.
G06T 15/00 - 3D [Three Dimensional] image rendering
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
G06F 9/52 - Program synchronisationMutual exclusion, e.g. by means of semaphores
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
Aspects comprise systems implementing 3-D graphics processing functionality in a multiprocessing system. Control flow structures are used in scheduling instances of computation in the multiprocessing system, where different points in the control flow structure serve as points where deferral of some instances of computation can be performed in favor of scheduling other instances of computation. In some examples, the control flow structure identifies particular tasks, such as intersection testing of a particular portion of an acceleration structure, and a particular element of shading code. In some examples, the aspects are used in 3-D graphics processing systems that can perform ray tracing based rendering.
During tracing of a primary ray in a 3-D space (e.g., a 3-D scene in graphics rendering), a ray is found to intersect a primitive (e.g., a triangle) located in the 3-D space. Secondary ray(s) may be generated for a variety of purposes. For example, occlusion rays may be generated to test occlusion of a point of intersection between the primary ray and primitive is illuminated by any of the light(s). An origin for each secondary ray can be modified from the intersection point based on characteristics of the primitive intersected. For example, an offset from the intersection point can be calculated using barycentric coordinates of the intersection point and interpolation of one or more parameters associated with vertices defining the primitive. These parameters may include a size of the primitive and differences between a geometric normal for the primitive and a respective additional vector supplied with each vertex.
A method and apparatus are provided for tessellating patches of surfaces in a tile based three dimensional computer graphics rendering system. For each tile in an image a per tile list of primitive indices is derived for tessellated primitives which make up a patch. Hidden surface removal is then performed on the patch and any domain points which remain after hidden surface removal are derived. The primitives are then shaded for display.
A method of processing rays in a ray tracing system allocates a block of memory for a task on a per-task basis. Processing rays in the task causes at least one child ray to be emitted such that intermediate data for the task is written to the block of memory, the intermediate data being written to and read from the block of memory in one or more finite-sized data bursts. Processing of the task is suspended, and when the task is ready to resume, the intermediate data or updated intermediate data for the task is read from the block of memory, and the processing of the task is resumed.
A method of configuring a hardware implementation of a Convolutional Neural Network (CNN), the method comprising: determining, for each of a plurality of layers of the CNN, a first number format for representing weight values in the layer based upon a distribution of weight values for the layer, the first number format comprising a first integer of a first predetermined bit-length and a first exponent value that is fixed for the layer; determining, for each of a plurality of layers of the CNN, a second number format for representing data values in the layer based upon a distribution of expected data values for the layer, the second number format comprising a second integer of a second predetermined bit-length and a second exponent value that is fixed for the layer; and storing the determined number formats for use in configuring the hardware implementation of a CNN.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G06F 7/00 - Methods or arrangements for processing data by operating upon the order or content of the data handled
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06N 3/04 - Architecture, e.g. interconnection topology
A graphics processing system renders primitives using a rendering space which is sub-divided into a plurality of regions. Geometry processing logic performs a geometry processing phase for a current render wherein for each region in the plurality of regions it is determined, for each of a plurality of primitives which are present in the region, whether the primitive totally covers the region, and total coverage data is stored indicating which of the primitives which are present in the region totally cover the region. Rendering logic performs, after the geometry processing logic has completed the geometry processing phase for the current render, a rendering phase for each of the regions of the plurality of regions on a region-by-region basis for the current render using the total coverage data for the region.
A plurality of work items are processed through a processing pipeline comprising a plurality of stages in processing logic. The processing of a work item includes: (i) reading data in accordance with a memory address associated with the work item, (ii) updating the read data, and (iii) writing the updated data in accordance with the memory address associated with the work item. The method includes processing a first work item and a second work item through the processing pipeline, wherein the processing of the first work item through the pipeline is initiated earlier than the processing of the second work item, and where it is determined that the first and second work items are associated with the same memory address, first updated data of the first work item is written to a register in the processing logic, and the processing of the second work item comprises reading the first updated data from the register instead of reading data from the memory.
Apparatus includes hardware logic arranged to normalise an n-bit input number. The hardware logic comprises at least a first hardware logic stage, an intermediate hardware logic stage and a final hardware logic stage. Each stage comprises a left shifting logic element, the first and intermediate stages each also comprise a plurality of OR-reduction logic elements and the intermediate and final stages each also comprise one or more multiplexers. The OR-reduction logic elements operate on different subsets of bits from the number input to the particular stage. In the intermediate and final hardware logic stages, a first of the multiplexers selects an OR-reduction result received from a previous hardware logic stage and the left shifting logic element is arranged to perform left shifting on the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
65.
ASSESSING PERFORMANCE OF A HARDWARE DESIGN USING FORMAL EVALUATION LOGIC
A formal verification tool is used to assess the performance of a hardware design for an integrated circuit to complete a set of tasks. The tool monitors one or more control signals and/or data signals of an instantiation of the hardware design to identify start and completion of a symbolic task by the instantiation of the hardware design, the symbolic task representing the set of tasks. A number of cycles between the start and the completion of the symbolic task is counted, and it is verified that one or more formal properties related to the counted number of cycles are true for the hardware design. An indication of whether or not each of the one or more formal properties was successfully verified is outputted, the indication providing an exhaustive assessment of the performance of the instantiation of the hardware design in completing the set of tasks.
A reduced noise image can be formed from a set of images. One of the images of the set can be selected to be a reference image and other images of the set are transformed such that they are better aligned with the reference image. A measure of the alignment of each image with the reference image is determined. At least some of the transformed images can then be combined using weights which depend on the alignment of the transformed image with the reference image to thereby form the reduced noise image. By weighting the images according to their alignment with the reference image the effects of misalignment between the images in the combined image are reduced. Furthermore, motion correction may be applied to the reduced noise image.
Ray tracing systems have computation units (“RACs”) adapted to perform ray tracing operations (e.g. intersection testing). There are multiple RACs. A centralized packet unit controls the allocation and testing of rays by the RACs. This allows RACs to be implemented without Content Addressable Memories (CAMs) which are expensive to implement, but the functionality of CAMs can still be achieved by implemented them in the centralized controller.
A method of improving texture fetching by a texturing/shading unit in a GPU pipeline by performing efficient convolution operations, includes receiving a shader and determining whether the shader is a kernel shader. In response to receiving a kernel shader, the kernel shader is modified to perform a collective fetch of all texels for a group of output pixels instead of performing independent fetches of texels for each output pixel in the group of output pixels.
Task building logic builds a plurality of tasks each comprising a group of rays. When a new ray is received into ray storage, if an existing task exists for the new ray, the new ray is added to an existing respective list. The task building logic indicates when any of the tasks is ready for scheduling, and task scheduling logic identifies a task ready for scheduling based on the indication from the task building logic, and in response traverses the respective list in order to schedule at least some of the rays of the respective task for processing in parallel.
Rendering systems that can use combinations of rasterization rendering processes and ray tracing rendering processes are disclosed. In some implementations, these systems perform a rasterization pass to identify visible surfaces of pixels in an image. Some implementations may begin shading processes for visible surfaces, before the geometry is entirely processed, in which rays are emitted. Rays can be culled at various points during processing, based on determining whether the surface from which the ray was emitted is still visible. Rendering systems may implement rendering effects as disclosed.
G09G 5/36 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory
Methods and graphics processing modules for rendering a stereoscopic image including left and right images of a three-dimensional scene. Geometry is processed in the scene to generate left data for use in displaying the left image and right data for use in displaying the right image. Disparity is determined between the left and right data by comparing the generated left data and the generated right data used in displaying the stereoscopic image. In response to identifying at least a portion of the left data and the right data as non-disparate, a corresponding portion of the left image and the right image is commonly processed (e.g. commonly rendered or commonly stored). In response to identifying at least a portion of the left data and the right data as disparate, a corresponding portion of the left image and the right image is separately processed (e.g. separately rendered or separately stored).
A texture filtering unit applies anisotropic filtering using a filter kernel which can be adapted to apply different amounts of anisotropy up to a maximum amount of anisotropy. If it is determined that a received input amount of anisotropy is not above the maximum amount of anisotropy, the filter kernel applies the input amount of anisotropy, and texels of a texture are sampled using the filter kernel to determine a filtered texture value. If it is determined that the input amount of anisotropy is above the maximum amount of anisotropy, the filter kernel applies an amount of anisotropy that is not above the maximum amount of anisotropy, a plurality of sampling operations are performed to sample texels of the texture using the filter kernel to determine a respective plurality of intermediate filtered texture values, and the plurality of intermediate filtered texture values are combined to determine a filtered texture value which has been filtered in accordance with the input amount of anisotropy and the input direction of anisotropy.
Texture filtering in computer graphics calculates first and second pairs of texture-space basis vectors that correspond to first and second pairs of screen-space basis vectors transformed to texture space under a local approximation of a mapping between screen space and texture space. Based on differences in magnitudes of the vectors of the pairs of texture-space basis vectors, an angular displacement is determined between a selected pair of the first and second pairs of screen-space basis vectors and screen-space principal axes of the local approximation of the mapping that indicate maximum and minimum scale factors of the mapping. The determined angular displacement and the selected pair of screen-space basis vectors are used to generate texture-space principal axes, with a major axis associated with the maximum scale factor of the mapping and a minor axis associated with the minimum scale factor of the mapping. A texture is filtered using the major and minor axes.
A tessellation method uses vertex tessellation factors. For a quad patch, the method involves comparing the vertex tessellation factors for each vertex of the quad patch to a threshold value and if none exceed the threshold, the quad is sub-divided into two or four triangles. If at least one of the four vertex tessellation factors exceeds the threshold, a recursive or iterative method is used which considers each vertex of the quad patch and determines how to further tessellate the patch dependent upon the value of the vertex tessellation factor of the selected vertex or dependent upon values of the vertex tessellation factors of the selected vertex and a neighbor vertex. A similar method is described for a triangle patch.
Compressed image data is received in substantially in raster scan order, and for each group of pixels in a row of the compressed image data, a block-based decoding scheme for the group of pixels is identified and the compressed data corresponding to the group of pixels is decoded at decoding hardware using the identified scheme.
H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/184 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being bits, e.g. of the compressed video stream
76.
COMPUTER SYSTEM AND METHOD USING A FIRST PAGE TABLE AND A SECOND PAGE TABLE
A computer system includes a physical memory having a first page table and a second page table, and an address translation module. The first page table includes primary page table entries, where each page table entry among the primary page table entries is configured to store a mapping of a virtual memory address to a physical memory address and auxiliary information. The second page table includes secondary page table entries each storing at least one further auxiliary information, where each secondary page table entry corresponds to a primary page table entry in the first page table. The address translation module is configured to, in response to receiving a request from a processor, walk through the first page table to identify a primary page table entry and consecutively identify a location of a corresponding secondary page table entry based on a location of the primary page table entry.
Methods and systems for wirelessly transmitting data between Wi-Fi stations without requiring the Wi-Fi stations to be fully connected to the Wi-Fi network. A first Wi-Fi station generates the data to be transmitted. The data comprises status data and/or wake-up data. The first Wi-Fi station then inserts the data in a vendor-specific information element of a probe request frame and wirelessly transmits the probe request frame. The probe request frame is then received by a second Wi-Fi station. If the probe request frame contains wake-up data and the second Wi-Fi station is operating in a low-power mode when it receives the probe request frame, the second Wi-Fi station will wake-up from the low-power mode. If the probe request frame contains status data then the second Wi-Fi station may process the probe request frame and/or forward at least a portion of the received probe request frame to another device.
G08B 25/00 - Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems
G08B 25/10 - Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems characterised by the transmission medium using wireless transmission systems
A memory attribute structure comprises one or more memory address entries. Each memory address entry comprising a respective memory address range mapped to a respective priority level. The memory attribute table is used when processing a memory access transaction through an execution path of a processing system. During said processing, a memory address of the memory access transaction is determined. The memory attribute structure is used to determine a priority level mapped to the determined memory address, and the memory access transaction is processed based on the determined priority level.
A memory attribute structure, which is configurable, is used when processing memory access transactions through an execution path of a processing system. The memory attribute structure includes one or more memory address entries. The entries are configurable. Each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels. A central processing unit is configured to use the memory attribute structure to determine respective priority levels mapped to respective memory addresses of respective memory access transaction, and process the respective memory access transactions based on the respective priority levels.
Interpolation logic described herein provides a good approximation to a bicubic interpolation, which is generally smoother than bilinear interpolation, without performing all the calculations normally needed for a bicubic interpolation. This allows an approximation of smooth bicubic interpolation to be performed on devices (e.g. mobile devices) which have limited processing resources. At each of a set of predetermined interpolation positions within an array of data points, a set of predetermined weights represent a bicubic interpolation which can be applied to the data points. For a plurality of the predetermined interpolation positions which surround the sampling position, the corresponding sets of predetermined weights and the data points are used to determine a plurality of surrounding interpolated values which represent results of performing the bicubic interpolation at the surrounding predetermined interpolation positions. A linear interpolation is then performed on the surrounding interpolated values to determine an interpolated value at the sampling position.
A graphics processing system renders a scene in a rendering space sub-divided into a plurality of tiles, each tile being sub-divided into a plurality of microtiles. A plurality of first hardware elements calculate a respective first output based on coordinates for a pixel of a microtile. A plurality of second hardware elements calculate a respective second output based on coordinates for a subsample within the pixel. Hardware logic generates an edge test output value or depth calculation value based on at least one of the second outputs, and the scene is rendered in the rendering space using the generated edge test output values or depth calculation values.
A graphics processing unit (GPU) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The GPU comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. The cost indication for a set of tile(s) is suggestive of a cost of processing the set of one or more tiles. The GPU controls a rendering complexity with which primitives are rendered in tiles based on the cost indication for those tiles. This allows tiles to be rendered in a manner that is suitable based on the complexity of the graphics data within the tiles. In turn, this allows the rendering to satisfy constraints such as timing constraints even when the complexity of different tiles may vary significantly within an image.
Hardware for implementing a Deep Neural Network (DNN) having a convolution layer, the hardware comprising an input buffer configured to provide data windows to a plurality of convolution engines, each data window comprising a single input plane; and each of the plurality of convolution engines being operable to perform a convolution operation by applying a filter to a data window, each filter comprising a set of weights for combination with respective data values of a data window, and each of the plurality of convolution engines comprising: multiplication logic operable to combine a weight of the filter with a respective data value of the data window provided by the input buffer; and accumulation logic configured to accumulate the results of a plurality of combinations performed by the multiplication logic so as to form an output for a respective convolution operation.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
Methods of rendering a scene in a graphics system identify a draw call within a current render and analyse the last shader in the series of shaders used by the draw call to identify any buffers that are sampled by the last shader and that are to be written by a previous render that has not yet been sent for execution on the GPU. If any such buffers are identified, further analysis is performed to determine whether the last shader samples from the identified buffers using screen space coordinates that correspond to a current fragment location and if this determination is positive, the draw call is added to data relating to the previous render and the last shader is recompiled to replace an instruction that reads data from an identified buffer with an instruction that reads data from an on-chip register.
G09G 5/36 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory
85.
HIERARCHICAL MANTISSA BIT LENGTH SELECTION FOR HARDWARE IMPLEMENTATION OF DEEP NEURAL NETWORK
Hierarchical methods for selecting fixed point number formats with reduced mantissa bit lengths for representing values input to, and/or output, from, the layers of a DNN. The methods begin with one or more initial fixed point number formats for each layer. The layers are divided into subsets of layers and the mantissa bit lengths of the fixed point number formats are iteratively reduced from the initial fixed point number formats on a per subset basis. If a reduction causes the output error of the DNN to exceed an error threshold, then the reduction is discarded, and no more reductions are made to the layers of the subset. Otherwise a further reduction is made to the fixed point number formats for the layers in that subset. Once no further reductions can be made to any of the subsets the method is repeated for continually increasing numbers of subsets until a predetermined number of layers per subset is achieved.
G06N 3/04 - Architecture, e.g. interconnection topology
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
G06F 17/11 - Complex mathematical operations for solving equations
Methods and systems for performing a convolution transpose operation between an input tensor having a plurality of input elements and a filter comprising a plurality of filter weights. The method includes: dividing the filter into a plurality of sub-filters; performing, using hardware logic, a convolution operation between the input tensor and each of the plurality of sub-filters to generate a plurality of sub-output tensors, each sub-output tensor comprising a plurality of output elements; and interleaving, using hardware logic, the output elements of the plurality of sub-output tensors to form a final output tensor for the convolution transpose.
A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.
G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
A method and system for generating two or three dimensional computer graphics images using multisample antialiasing (MSAA) is provided, which enables memory bandwidth to be conserved. For each of one or more pixels it is determined whether all of a plurality of sample areas of that pixel are located within a particular primitive. For those pixels where it is determined that all the sample areas of that pixel are located within that primitive, a value is stored in a multisample memory for a smaller number of the sample areas of that pixel than the total number of the sample areas of that pixel and data is stored indicating that all the sample areas of that pixel are located within that primitive.
Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.
A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived. 0
G06F 7/38 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
A method of data compression in which the total size of the compressed data is determined and based on that determination, the bit depth of the input data may be reduced before the data is compressed. The bit depth that is used may be determined by comparing the calculated total size to one or more pre-defined threshold values to generate a mapping parameter. The mapping parameter is then input to a remapping element that is arranged to perform the conversion of the input data and then output the converted data to a data compression element. The value of the mapping parameter may be encoded into the compressed data so that it can be extracted and used when subsequently decompressing the data.
H03M 7/30 - CompressionExpansionSuppression of unnecessary data, e.g. redundancy reduction
H04N 19/13 - Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
H04N 19/132 - Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
92.
ACTIVATION ACCELERATOR FOR NEURAL NETWORK ACCELERATOR
An activation accelerator for use in a neural network accelerator includes a look-up table and activation pipelines. The look-up table stores values representing a non-linear activation function. Each activation pipeline comprises a range conversion unit which receives an input value and generates a converted value from the input value, an index generation unit which receives information identifying a first subset of bits of the converted value and a second subset of bits of the converted value, generates an index from the first subset of bits of the converted value, and generates an interpolation value from the second subset of bits of the converted value, a look-up table interface unit which retrieves multiple values from the look-up table based on the index, and an interpolation unit which generates an estimated result of the non-linear activation function for the input value by interpolating between the multiple values retrieved from the look-up table based on the interpolation value.
An activation accelerator for a neural network accelerator includes a look-up table and activation pipelines. The look-up table stores values representing a non-linear activation function. Each activation pipeline comprises a range conversion unit that receives an input value, an input offset, and an absolute value flag, and generates a converted value from the input value by combining the input value and the input offset, and when an absolute value flag is set, generates an absolute value of the combination of the input value and the input offset. An index generation unit generates an index and an interpolation value from the converted value. A look-up table interface retrieves multiple values from the look-up table based on the index. An interpolation unit generates an estimate of a result of the non-linear activation function for the input value from an interpolation output generated by interpolating between the multiple values retrieved from the look-up table based on the interpolation value.
An activation accelerator for a neural network accelerator includes a look-up table that stores a plurality of values representing a non-linear activation function, and activation pipelines. Each activation pipeline comprises a range conversion unit that receives an input value and generates a converted value from the input value, an index generation unit that generates an index and an interpolation value from the converted value, a look-up table interface unit that retrieves multiple values from the look-up table based on the index, and an interpolation unit that receives information identifying a rounding mode of a plurality of rounding modes, and generates an estimate of a result of the non-linear activation function for the input value from an interpolation output generated by interpolating between the multiple values retrieved from the look-up table using the interpolation value and rounding in accordance with the identified rounding mode.
A method of enabling synchronisation of a second clock at a second device with a first clock at a first device further comprising a third clock. A first message comprising an identifier generated in dependence on the third clock is transmitted to the second device. A timestamp is generated in dependence on the time at which the first message is transmitted from the first device according to the first clock, and a second message comprising the identifier and the generated timestamp is generated. The second message is then transmitted to the second device.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 69/00 - Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
H04N 21/00 - Selective content distribution, e.g. interactive television or video on demand [VOD]
H04N 21/43 - Processing of content or additional data, e.g. demultiplexing additional data from a digital video streamElementary client operations, e.g. monitoring of home network or synchronizing decoder's clockClient middleware
H04N 21/8547 - Content authoring involving timestamps for synchronizing content
H04W 4/70 - Services for machine-to-machine communication [M2M] or machine type communication [MTC]
A computer-implemented method for generating a feature descriptor for a location in an image for use in performing descriptor matching in analysing the image, the method comprising determining a set of samples characterising a location in an image by sampling scale-space data representative of the image, the scale-space data comprising data representative of the image at a plurality of length scales; and generating a feature descriptor in dependence on the determined set of samples.
G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersectionsConnectivity analysis, e.g. of connected components
G06V 10/46 - Descriptors for shape, contour or point-related descriptors, e.g. scale invariant feature transform [SIFT] or bags of words [BoW]Salient regional features
G06V 10/52 - Scale-space analysis, e.g. wavelet analysis
H04N 19/117 - Filters, e.g. for pre-processing or post-processing
H04N 19/132 - Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
97.
METHODS AND SYSTEMS FOR STORING VARIABLE LENGTH DATA BLOCKS IN MEMORY
A set of two or more variable length data blocks is stored in memory. Each variable length data block has a maximum size of N*B, wherein N is an integer greater than or equal to two, and B is a maximum data size that can be written to the memory using a single memory access request. For each variable length data block of the set, the first P non-overlapping portions of size B of the variable length data block are stored in a chunk of the memory allocated to that variable length data block, wherein P is a minimum of (i) a number of non-overlapping portions of size B of the variable length data block and (ii) X which is an integer less than N. Any remaining portions of the variable length data blocks are stored in a remainder section of the memory shared between the variable length data blocks of the set. Information indicating the size of each of the variable length data blocks in the set is stored in a header.
A method of scheduling a plurality of active GPU drivers in a GPU includes, for one or more of the plurality of active GPU drivers, allocating a portion of a scheduling interval to the active GPU driver and selecting an active GPU driver for execution according to a priority-based scheduling algorithm. In response to an active GPU driver executing within its allocated portion, the priority level of the active GPU driver is increased, in response to the active GPU driver completing its workload within its allocated portion the priority level of the active GPU driver is reset and in response to the active GPU driver executing for its whole allocated portion, the priority level of the active GPU driver is reduced. The priority levels of each active GPU driver are reset to their initial priority levels at the start of each scheduling interval.
Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.
Methods and apparatus for compressing image data are described along with corresponding methods and apparatus for decompressing the compressed image data. A decoder unit samples compressed image data including interleaved blocks of data encoding a first image and blocks of data encoding differences between the first image and a second image, the second image being twice the width and the height of the first image. A difference decoder decodes a fetched encoded sub-block of the differences between the first and second images and output a difference quad and a prediction value for a pixel, and a filter sub-unit generates a reconstruction of the image at a sample position using decoded blocks of the first image, the difference quad and the prediction value.
H04N 19/17 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 19/34 - Scalability techniques involving progressive bit-plane based encoding of the enhancement layer, e.g. fine granular scalability [FGS]
H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
H04N 19/59 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
H04N 19/82 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation involving filtering within a prediction loop
