A method for calibrating an image sensor begins by illuminating a portion of the image sensor with an input light spectrum, where the input light spectrum includes light of known wavelength and intensity. The method continues by sampling an output for each optical sensor of the image sensor, where each optical sensor is associated with one or more optical filters and where each optical filter being associated with a group of optical filters of a plurality of groups of optical filters. Each optical filter of a group of optical filters is configured to pass light in a different wavelength range and at least some optical filters in different groups of the plurality of groups of optical filters are configured to pass light in substantially a same wavelength range. The method then continues by comparing a sampled output for each optical sensor of the plurality of optical sensors with an expected output and generating a calibration factor for each of at least a subset of the plurality of optical sensors and storing the generated calibration factors in memory.
H04N 23/11 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from different wavelengths for generating image signals from visible and infrared light wavelengths
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
G01J 3/26 - Generating the spectrumMonochromators using multiple reflection, e.g. Fabry-Perot interferometer, variable interference filter
An integrated circuit for an imaging system is disclosed. In one aspect, an integrated circuit has an array of optical sensors, an array of optical filters integrated with the sensors and configured to pass a band of wavelengths onto one or more of the sensors, and read out circuitry to read out pixel values from the sensors to represent an image. Different ones of the optical filters are configured to have a different thickness, to pass different bands of wavelengths by means of interference, and to allow detection of a spectrum of wavelengths. The read out circuitry can enable multiple pixels under one optical filter to be read out in parallel. The thicknesses may vary non-monotonically across the array. The read out, or later image processing, may involve selection or interpolation between wavelengths, to carry out spectral sampling or shifting, to compensate for thickness errors.
An integrated circuit for an imaging system is disclosed. In one aspect, an integrated circuit has an array of optical sensors, an array of optical filters integrated with the sensors and configured to pass a band of wavelengths onto one or more of the sensors, and read out circuitry to read out pixel values from the sensors to represent an image. Different ones of the optical filters are configured to have a different thickness, to pass different bands of wavelengths by means of interference, and to allow detection of a spectrum of wavelengths. The read out circuitry can enable multiple pixels under one optical filter to be read out in parallel. The thicknesses may vary non-monotonically across the array. The read out, or later image processing, may involve selection or interpolation between wavelengths, to carry out spectral sampling or shifting, to compensate for thickness errors.
09 - Scientific and electric apparatus and instruments
10 - Medical apparatus and instruments
41 - Education, entertainment, sporting and cultural services
42 - Scientific, technological and industrial services, research and design
44 - Medical, veterinary, hygienic and cosmetic services; agriculture, horticulture and forestry services
Goods & Services
Software; mobile applications; computer programs whether or not for the benefit of an online platform; smart bracelets; electronic chips; sensors. Testing apparatus for medical purposes; electronic equipment for medical purposes; medical apparatus and instruments for measuring, recording and displaying physiological data. Education; organization and conducting workshops, conferences and seminars; publication (online and electronic) of books and periodicals; publication and development of learning materials; the provision of online electronic publications; education and training on detection and use of physiological data to promote health; advice, consultancy and information relating to the aforesaid services, also to be provided via electronic networks such as the Internet. Scientific and technological services, as well as associated research and design services; scientific and technological services for medical purposes; services in the field of industrial analysis and industrial research; designing and developing computers and software; graphic design, especially making volume drawings for the design of prototypes; technical drawing; design of prototypes; product development and product design; consultancy in the field of new technologies by experts; software as a service for the design, creation and analysis of data, including physiological data, measurement data and reports in the field of health and motivation; advice, consultancy and information relating to the aforesaid services, also to be provided via electronic networks such as the internet. Healthcare; medical research services; providing information in the context of medical treatment with respect to surgical, medical, dental and veterinary apparatus and instruments; preparing medical advice; advice, consultancy and information relating to the aforesaid services, also to be provided via electronic networks such as the internet.
5.
Method and device to reduce leakage and dynamic energy consumption in high-speed memories
A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
The disclosed technology relates generally to a semiconductor device package comprising a metal-insulator-metal capacitor (MIMCAP). In one aspect, the MIMCAP comprises portions of a first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers formed by single damascene processes. The MIMCAP comprises a bottom plate formed in the first metallization layer, a first conductive layer on and in electrical contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, a second conductive layer on and in contact with the dielectric layer, and a top plate formed in the second metallization layer, on and in electrical contact with the second metal plate. The electrical contacts to the bottom and top plates of the MIMCAP formed in the first and second metallization layer are thereby established without forming separate vias between the plates and the metallization layers. In addition, the first conductive layer of the MIMCAP may extend beyond the surface of the dielectric and the second layer for forming other structures.
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 27/01 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
Katholieke Universiteit Leuven, KU Leuven R&D (Belgium)
Inventor
Lagae, Liesbet
Peumans, Peter
Verstreken, Kris
Vercruysse, Dries
Liu, Chengxun
Abstract
A device and method for sorting objects immersed in a flowing medium are disclosed. An example device comprises a holographic imaging unit comprising one or more holographic imaging elements, a fluid handling unit comprising one or more microfluidic channels configured to conduct flowing medium along a corresponding holographic imaging element and at least one microfluidic switch arranged downstream of an imaging region in the microfluidic channel configured to direct objects in the flowing medium into a one of a plurality of outlets. The example device also comprises a processor configured to determine real-time characterizations of holographic diffraction images obtained for the moving objects. The processing unit is further configured to control the at least one microfluidic switch in response to the real-time characterizations.
G03H 1/00 - Holographic processes or apparatus using light, infrared, or ultraviolet waves for obtaining holograms or for obtaining an image from themDetails peculiar thereto
G03H 1/04 - Processes or apparatus for producing holograms
8.
Methods and mask structures for substantially defect-free epitaxial growth
Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, mask structure includes a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a semiconductor substrate, and a second level on top of the first level, wherein the second level defines a plurality of second trenches positioned at a non-zero angle with respect to the first trench.
An integrated circuit for an imaging system is disclosed. In one aspect, an integrated circuit has an array of optical sensors, an array of optical filters integrated with the sensors and configured to pass a band of wavelengths onto one or more of the sensors, and read out circuitry to read out pixel values from the sensors to represent an image. Different ones of the optical filters are configured to have a different thickness, to pass different bands of wavelengths by means of interference, and to allow detection of a spectrum of wavelengths. The read out circuitry can enable multiple pixels under one optical filter to be read out in parallel. The thicknesses may vary non-monotonically across the array. The read out, or later image processing, may involve selection or interpolation between wavelengths, to carry out spectral sampling or shifting, to compensate for thickness errors.
An integrated circuit for an imaging system is disclosed. In one aspect, an integrated circuit has an array of optical sensors, an array of optical filters integrated with the sensors and configured to pass a band of wavelengths onto one or more of the sensors, and read out circuitry to read out pixel values from the sensors to represent an image. Different ones of the optical filters are configured to have a different thickness, to pass different bands of wavelengths by means of interference, and to allow detection of a spectrum of wavelengths. The read out circuitry can enable multiple pixels under one optical filter to be read out in parallel. The thicknesses may vary non-monotonically across the array. The read out, or later image processing, may involve selection or interpolation between wavelengths, to carry out spectral sampling or shifting, to compensate for thickness errors.
A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
12.
Apparatus for fluid guided self-assembly of microcomponents
A method and apparatus is provided for self-assembly of micro-components such as microchips onto a carrier substrate, provided with assembly locations for the components. The components are supplied to the carrier by a liquid flow, while a template substrate is arranged facing the carrier. The template is a substrate provided with openings aligned to the assembly locations. The carrier and template are submerged into a tank filled with the liquid, while the liquid flow is supplied to the template side together with the components, so that the components are guided towards the openings by the flow of liquid. Once a component is trapped into an opening of the template, substantially no further liquid flow through the opening is possible, so that following components are guided towards the remaining openings, thereby establishing a fast and reliable self-assembly process.
B23P 19/00 - Machines for simply fitting together or separating metal parts or objects, or metal and non-metal parts, whether or not involving some deformationTools or devices therefor so far as not provided for in other classes
H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor
H01L 23/00 - Details of semiconductor or other solid state devices
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
13.
Enhancement mode III-nitride device and method for manufacturing thereof
Enhancement mode III-nitride HEMT and method for manufacturing an enhancement mode III-nitride HEMT are disclosed. In one aspect, the method includes providing a substrate having a stack of layers on the substrate, each layer including a III-nitride material, and a passivation layer having high temperature silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by MOCVD or LPCVD or any equivalent technique at a temperature higher than about 450° C. The method also includes forming a recessed gate region by removing the passivation layer only in the gate region, thereby exposing the underlying upper layer. The method also includes forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region, and forming a gate contact and source/drain contacts.
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.
A method for manufacturing a III-nitride HEMT having a gate electrode and source and drain ohmic contacts is provided, comprising providing a substrate; forming a stack of III-nitride layers on the substrate; forming a first passivation layer comprising silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the first passivation layer is deposited in-situ with the stack of III-nitride layers; forming a dielectric layer overlying and in contact with the first passivation layer; forming a second passivation layer comprising silicon nitride overlying and in contact with the dielectric layer wherein the second passivation layer is deposited at a temperature higher than 450° C. by LPCVD or MOCVD or any equivalent technique; and thereafter forming the source and drain ohmic contacts and the gate electrode.
H01L 29/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor bodies or of electrodes thereof
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
16.
Spectral camera with mirrors for projecting multiple adjacent image copies onto sensor array
A spectral camera for producing a spectral output is disclosed. The spectral camera has an objective lens for producing an image, an array of mirrors, an array of filters for passing a different passband of the optical spectrum for different ones of the optical channels arranged so as to project multiple of the optical channels onto different parts of the same focal plane, and a sensor array at the focal plane to detect the filtered image copies simultaneously. By using mirrors, there may be less optical degradation and the trade off of cost with optical quality can be better. By projecting the optical channels onto different parts of the same focal plane a single sensor or coplanar multiple sensors can to be used to detect the different optical channels simultaneously which promotes simpler alignment and manufacturing.
A spectral camera for producing a spectral output is disclosed. The spectral camera has an objective lens for producing an image, a mosaic of filters for passing different bands of the optical spectrum, and a sensor array arranged to detect pixels of the image at the different bands passed by the filters, wherein for each of the pixels, the sensor array has a cluster of sensor elements for detecting the different bands, and the mosaic has a corresponding cluster of filters of different bands, integrated on the sensor element so that the image can be detected simultaneously at the different bands. Further, the filters are first order Fabry-Perot filters, which can give any desired passband to give high spectral definition. Cross talk can be reduced since there is no longer a parasitic cavity.
A method an system is disclosed for the detection and/or allocation of at least one point mutation in target DNA and/or RNA duplexes. The method comprises obtaining a functionalized surface which is coated with probe DNA and/or RNA whereto target DNA and/or RNA duplexes are attached, contacting said functionalized surface to an electrolytic solution having a neutral pH in a flow cell and measuring a first impedance value within said electrolytic solution, and then adding a chemical to the electrolytic solution which is able to achieve denaturation of the target DNA and/or RNA. The method further comprises measuring a second impedance value within the flow cell after completion of the denaturation of the DNA and/or RNA target, and then obtaining a value representative for the impact of the chemical on the impedance of the electrolytic solution. The amount and/or allocation of point mutation(s) within the target DNA and/or RNA is then determined by calculating the denaturation-time constant based on the difference between the first and second impedance value and taking into account the impact of the chemical by third impedance value.
A semiconductor device includes a Schottky diode and a High Electron Mobility Transistor (HEMT) formed on a III-nitride stack. The III-nitride stack includes at least a lower and an upper III-nitride layer forming a heterojunction therebetween, so that a 2-dimensional electron gas (2DEG) layer may be formed in the lower layer. The 2DEG layer serves as a charge carrier for the diode and the HEMT. A doped III-nitride layer may be present between a portion of the anode of the diode and the III-nitride stack, and the portion may be located between the diode's Schottky junction and the cathode. A further layer of doped III-nitride material may be present between the gate electrode of the HEMT and the III-nitride stack. The thickness of the III-nitride layers is not equal, so that the turn-on voltage of the diode and the threshold voltage of the HEMT may be tuned according to specific requirements. The disclosure also involves a method of producing such a semiconductor device.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
20.
Probe configuration and method of fabrication thereof
The disclosed technology relates generally to probe configurations, and more particularly to probe configurations and methods of making probe configurations that have a diamond body and a diamond layer covering at least an apex region of the diamond body. In one aspect, a method of fabricating a probe configuration includes forming a probe tip. Forming the probe tip includes providing a substrate and forming a recessed mold into the substrate on a first side of the substrate, wherein the recessed mold is shaped to form a probe body having an apex region. Forming the probe tip additionally includes forming a first diamond layer on the substrate on the first side, wherein forming the first diamond layer includes at least partially filling the recessed mold with the first diamond layer such that a probe body having an apex region is formed in the recessed mold. Forming the probe tip additionally includes patterning to remove at least partially the first diamond layer which surrounds the probe body, removing a substrate material surrounding at least the apex region of the probe body, and forming a second diamond layer covering at least the apex region of the probe body. The method additionally includes attaching the probe tip to a first end of a cantilever and attaching the second end of the cantilever to a holder.
A method for manufacturing a three-dimensional resistive memory array is disclosed. The method comprises forming a repetitive sequence comprising an isolating layer, a semiconductor layer, a gate insulating layer, and a conductive layer. By performing a plurality of processing steps on the repetitive sequence a three-dimensional resistive memory array is obtained. A three-dimensional resistive memory array is further disclosed.
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
22.
Method of manufacturing a semiconductor device and a semiconductor device
A method of manufacturing a semiconductor device and the device resulted thereof is disclosed. In one aspect, the device has a heterogeneous layer stack of one or more III-V type materials, at least one transmission layer of the layer stack having a roughened or textured surface for enhancement of light transmission. The method includes (a) growing the transmission layer of a III-V type material, (b) providing a mask layer on the transmission layer, the mask layer leaving first portions of the transmission layer exposed, and (c) partially decomposing the first exposed portions of the transmission layer. Suitably redeposition occurs in a single step with decomposition, so as to obtain a textured surface based on crystal facets of a plurality of grown crystals. The resulting device has a light-emitting element. The transmission layer hereof is suitably present at the top side.
H01L 33/22 - Roughened surfaces, e.g. at the interface between epitaxial layers
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 33/18 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
The disclosed technology relates to pillar-type microbumps formed on a semiconductor component, such as an integrated circuit chip or an interposer substrate, and a method of forming the pillar-type microbumps. In one aspect, a method of forming the pillar-type microbump on a semiconductor component includes providing the semiconductor component, where the semiconductor component has an upper metallization layer, and the metallization layer has a contact area. The method additionally includes forming a passivation layer over the metallization layer. The method additionally includes forming a plurality of openings through the passivation layer such that the contact area is exposed at a bottom of the openings. The method further includes forming the microbump over the contact area, where the microbump forms an electrical connection with the contact area through the openings.
Katholieke Universiteit Leuven, KU Leuven R&D (Belgium)
Universiteit Hasselt (Belgium)
Inventor
Buffiere, Marie
Meuris, Marc
Brammertz, Guy
Abstract
A method for chemically cleaning and passivating a chalcogenide layer is provided, wherein the method comprises bringing the chalcogenide layer into contact with an ammonium sulfide containing ambient, such as an ammonium sulfide liquid solution or an ammonium sulfide containing vapor. Further, a method for fabricating photovoltaic cells with a chalcogenide absorber layer is provided, wherein the method comprises: providing a chalcogenide semiconductor layer on a substrate; bringing the chalcogenide semiconductor layer into contact with an ammonium sulfide containing ambient, thereby removing impurities and passivating the chalcogenide semiconductor layer; and afterwards providing a buffer layer on the chalcogenide semiconductor layer.
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 31/0749 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type including a AIBIIICVI compound, e.g. CdS/CuInSe2 [CIS] heterojunction solar cells
H01L 31/032 - Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups
H01L 31/072 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
25.
Semiconductor device having through-substrate vias
A semiconductor device having through-substrate vias is disclosed. In one aspect, the device includes a substrate having at least one front-end-of-line (FEOL) device and a back-end-of-line (BEOL) comprising a metal pad. The device additionally includes at least one first contact plug contacting the at least one FEOL device and at least one second contact plug underneath the metal pad and in electrical contact therewith. At least one second contact plug has one end contacting the metal pad and has other end contacting a material that is not part of a FEOL device.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
The disclosed technology generally relates to semiconductor devices, and more particularly spin transfer torque magnetic random access memory (STTMRAM) elements having perpendicular magnetic anisotropy (PMA). In one aspect, a magnetic element comprises a metal underlayer and a seed layer on the underlayer, the seed layer comprising alternating layers of a first metal and a second metal. The alternating layers of a first metal and a second metal are repeated n times with, 2<=n<=20. Also a spin transfer torque magnetic random access memory element is disclosed having a perpendicular magnetic orientation comprising a metal underlayer on a substrate, a seed layer on the metal underlayer; the seed layer comprising alternating layers of a first metal and a second metal, a magnetic tunnel junction (MTJ) element with a perpendicular orientation including: a reference layer formed on the seed layer, a tunnel barrier layer formed on the reference layer, a storage layer formed on the tunnel barrier layer and a top electrode and a bottom electrode.
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
Katholieke Universiteit Leuven, KU LEUVEN R&D (Belgium)
Inventor
Lagae, Liesbet
Peumans, Peter
Verstreken, Kris
Vercruysse, Dries
Liu, Chengxun
Abstract
A device and method for sorting objects immersed in a flowing medium are described. An example device comprises a holographic imaging unit comprising a plurality of holographic imaging elements, a fluid handling unit comprising a plurality of microfluidic channels for conducting flowing medium along a corresponding holographic imaging element and a microfluidic switch arranged downstream of an imaging region in the microfluidic channel for directing each object in the flowing medium into a one of a plurality of outlets. The example device also comprises a processing unit configured to determine real-time characterizations of holographic diffraction images obtained for each of the moving objects, with each real-time characterization accounting for at least one predetermined object-type signature. The processing unit is further adapted for controlling the microfluidic switches in response to the real-time characterizations.
G01N 15/14 - Optical investigation techniques, e.g. flow cytometry
G03H 1/22 - Processes or apparatus for obtaining an optical image from holograms
G03H 1/00 - Holographic processes or apparatus using light, infrared, or ultraviolet waves for obtaining holograms or for obtaining an image from themDetails peculiar thereto
28.
Method and system for measuring capacitance difference between capacitive elements
Methods and systems for measuring capacitance difference are disclosed. In one aspect, first and second capacitive elements are connected between voltage receiving nodes for receiving first and second DC voltages and nodes connectable to a third DC voltage via a first, resp. second switch. Further, in a first phase, a voltage difference is applied to charge the capacitive elements and the switches are alternately closed. First resulting currents are measured. Further, in a second phase, the first and second DC voltages are applied alternatingly and the switches are alternately closed. Second resulting currents are measured. The capacitance difference can be determined from the first and second resulting currents.
G01R 27/00 - Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
G01R 27/26 - Measuring inductance or capacitanceMeasuring quality factor, e.g. by using the resonance methodMeasuring loss factorMeasuring dielectric constants
G01B 7/00 - Measuring arrangements characterised by the use of electric or magnetic techniques
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
A photonic integrated device comprises a waveguide embedded in a photonic substrate. The waveguide has a waveguide radiation exit surface and the waveguide is optically connected to a two dimensional grating. The photonic integrated device also comprises a two dimensional grating having a plurality of curved elongate scattering elements. The two dimensional grating is adapted for diffracting radiation received from the waveguide toward a direction out of the photonic substrate and the curved elongate scattering elements are oriented with respect to the waveguide such that, for points of the scattering elements which can be irradiated by radiations stemming from the waveguide, normal lines to at least the curved elongate scattering element closest to the waveguide radiation exit surface do not substantially intersect with the waveguide radiation exit surface of the waveguide.
G02B 6/34 - Optical coupling means utilising prism or grating
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/124 - Geodesic lenses or integrated gratings
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
G02B 6/30 - Optical coupling means for use between fibre and thin-film device
30.
Method for reducing second order distortion in harmonic rejection mixer
The present disclosure relates to a method for reducing second order intermodulation distortion in a harmonic rejection mixer arranged for down-converting a radio frequency signal to an in-phase and a quadrature baseband signal. The method includes adjusting an output current of a first mixer, to reduce the second order intermodulation distortion in the quadrature baseband signal to a first value, and adjusting an output current of a second mixer, to reduce the second order intermodulation distortion in the in-phase baseband signal to a second value.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference
KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D (Belgium)
Inventor
Hoffman, Luis Diego Leon
Braeken, Dries
Musa, Silke
Abstract
In an aspect of the disclosure, a stimulation device includes a probe attached to a first support. The probe includes at least one grating coupler for coupling light into the probe. The device further includes at least one optical source for providing an optical stimulation signal mounted on a second support, and at least one means for detachably attaching the first support to the second support. The position of the at least one optical source is aligned with the position of the at least one grating coupler to allow light emitted from the at least one optical source to be received by the at least one grating coupler.
The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
33.
Non-volatile memory semiconductor devices and method for making thereof
The disclosed technology generally relates to memory devices, and more particularly to memory devices having an intergate dielectric stack comprising multiple high k dielectric materials. In one aspect, a planar non-volatile memory device comprises a hybrid floating gate structure separated from an inter-gate dielectric structure by a first interfacial layer which is designed to be electrically transparent so as not to affect the program saturation of the device. The inter-gate structure comprises a stack of three layers having a high-k/low-k/high-k configuration and the interfacial layer has a higher k-value than its adjacent high-k layer in the inter-gate dielectric structure. A method of making such a non-volatile memory device is also described.
The disclosure relates to a method for manufacturing a III-V device and the III-V device obtained therefrom. The method comprises providing a semiconductor substrate including at least a recess area and forming a buffer layer overlying the semiconductor substrate in the recess area. The buffer layer includes a binary III-V compound formed at a first growth temperature by selective epitaxial growth from a group III precursor and a group V precursor in the presence of a carrier gas. The first growth temperature is equal or slightly higher than a cracking temperature of each of the group III precursor and of the group V precursor.
H01L 21/4763 - Deposition of non-insulating-, e.g. conductive-, resistive-, layers on insulating layersAfter-treatment of these layers
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 31/0336 - Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups in different semiconductor regions, e.g. Cu2X/CdX hetero-junctions, X being an element of Group VI of the Periodic System
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
An example micro-fluidic device includes a micro-fluidic channel having an inner surface and a plurality of pillars positioned along the inner surface. The device further includes a plurality of power supplies connected to the pillars. Another example micro-fluidic device includes a micro-fluidic channel having an inner surface and a plurality of pillars positioned along the inner surface. The device further includes a power supply. The pillars are grouped into at least two groups of pillars, each group of pillars including at least two pillars, and all pillars of at least one group of pillars are connected to the power supply. In another example, a sensing system for detecting bioparticles includes a micro-fluidic device, wherein a surface of each pillar comprises functionalized plasmonic nanoparticles or functionalized SERS nanoparticles, a radiation source for radiating the micro-fluidic device, and a detector for detecting SERS signals or surface plasmon resonance.
A method includes providing a dummy gate structure on a substrate. The dummy gate structure includes a gate dielectric layer and a dummy gate electrode layer, and is laterally defined by inner sidewalls of a set of spacers. The method also includes laterally embedding the dummy gate structure, removing the dummy gate electrode, and providing a final gate electrode layer in between the inner sidewalls of the set of spacers. Providing the final gate electrode layer further includes providing a diffusion layer that extends on top of the gate dielectric layer, on inner sidewalls of the spacers, and on a portion of a front surface of embedding layers for the dummy gate structure. Providing the final gate electrode also includes providing a metal on top of the diffusion layer, applying an anneal step, and filling the area in between the inner sidewalls of the set of spacers with a final gate metal filling layer. The present disclosure also relates to an associated transistor.
2 and with a laser pulse duration in the range between 1 ns and 10 ms. Then, the method includes converting at least part of the metal layer into a metal silicide layer. In addition, the present invention is related to the use of such a method in a process for fabricating a photovoltaic cell, wherein the dielectric layer is a surface passivation layer, or wherein the dielectric layer is an antireflection coating.
An optical fluorescence-based sensor comprising at least one sensing element is disclosed. In one aspect, the at least one sensing element comprises a waveguide comprising a waveguide core, a light source optically coupled to an input part of the waveguide core, and a photodetector optically coupled to an output part of the waveguide core, the waveguide core being made of a material comprising a mixture of an optical material and a fluorescent dye.
G01N 21/77 - Systems in which material is subjected to a chemical reaction, the progress or the result of the reaction being investigated by observing the effect on a chemical indicator
The invention relates to the manufacturing process of a solar cell (1) with back contact and passivated emitter, comprising a dielectric stack (10) of at least two layers consisting of at least a first dielectric layer (11) made of AlOx in contact with a p-type silicon layer (3), and a second dielectric layer (13) deposited on the first dielectric layer (11). Besides, the method of manufacturing comprising a formation step of at least one partial opening (15) preferably by laser ablation into the dielectric stack (10), sparing at least partially the aforementioned first dielectric layer.
H01L 31/061 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being of the point-contact type
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
A semiconductor device includes a Schottky diode and a High Electron Mobility Transistor (HEMT) formed on a III-nitride stack. The III-nitride stack includes at least a lower and an upper III-nitride layer forming a heterojunction therebetween, so that a 2-dimensional electron gas (2DEG) layer may be formed in the lower layer. The 2DEG layer serves as a charge carrier for the diode and the HEMT. A doped III-nitride layer may be present between a portion of the anode of the diode and the III-nitride stack, and the portion may be located between the diode's Schottky junction and the cathode. A further layer of doped III-nitride material may be present between the gate electrode of the HEMT and the III-nitride stack. The thickness of the III-nitride layers is not equal, so that the turn-on voltage of the diode and the threshold voltage of the HEMT may be tuned according to specific requirements. The disclosure also involves a method of producing such a semiconductor device.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
41.
Two-step interconnect testing of semiconductor dies
The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.
G01R 31/20 - Preparation of articles or specimens to facilitate testing
G01R 31/26 - Testing of individual semiconductor devices
H01L 21/66 - Testing or measuring during manufacture or treatment
G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A semiconductor device comprising a graphene layer, a graphene oxide layer overlaying the graphene layer, and a high-k dielectric layer overlaying the graphene oxide layer is provided, as well as a method for producing the same. The method results in a graphene chemical functionalization that efficiently and uniformly seeds ALD growth, preserves the underlying graphene structure, and achieves desirable dielectric properties such as low leakage current and high capacitance.
H01L 21/24 - Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
King Abulaziz City for Science and Technology (Saudi Arabia)
IMEC (Belgium)
Inventor
Farghaly, Mahmoud A.
Rochus, Veronique
Rottenberg, Xavier
Tilmans, Hendrikus
Abstract
A two-axes MEMS magnetometer includes, in one plane, a freestanding rectangular frame having inner walls and four torsion springs, wherein opposing inner walls of the frame are contacted by one end of only two torsion springs, each torsion spring being anchored by its other end, towards the center of the frame, to a substrate. In operation, the magnetometer measures the magnetic field in two orthogonal sensing modes using differential capacitance measurements.
G01V 3/08 - Electric or magnetic prospecting or detectingMeasuring magnetic field characteristics of the earth, e.g. declination or deviation operating with magnetic or electric fields produced or modified by objects or geological structures or by detecting devices
G01V 3/40 - Electric or magnetic prospecting or detectingMeasuring magnetic field characteristics of the earth, e.g. declination or deviation specially adapted for measuring magnetic field characteristics of the earth
44.
Method and device to reduce leakage and dynamic energy consumption in high-speed memories
A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
G06F 12/0893 - Caches characterised by their organisation or structure
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
The present invention provides a method to analyze or identify a cell. The method comprises: providing a cell, stimulating the cell with a stimulant thereby modifying a cell membrane impedance of the cell, monitoring the cell membrane impedance of the cell and identifying the cell based on the monitored cell membrane impedance. A corresponding device is also provided.
C12Q 1/04 - Determining presence or kind of microorganismUse of selective media for testing antibiotics or bacteriocidesCompositions containing a chemical indicator therefor
A spectral camera for producing a spectral output is disclosed. The spectral camera has an objective lens for producing an image, an optical duplicator, an array of filters, and a sensor array arranged to detect the filtered image copies simultaneously on different parts of the sensor array. Further, a field stop defines an outline of the image copies projected on the sensor array. The filters are integrated on the sensor array, which has a planar structure without perpendicular physical barriers for preventing cross talk between each of the adjacent optical channels. The field stop enables adjacent image copies to fit together without gaps for such barriers. The integrated filters mean there is no parasitic cavity causing crosstalk between the adjacent image copies. This means there is no longer a need for barriers between adjacent projected image copies, and thus sensor area can be better utilized.
H04N 3/14 - Scanning details of television systemsCombination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, and a coating overlaying the core. The coating includes one or more metal oxide layers, at least one of which is aluminium. The device also includes a recess surrounding the at least one coated fin and being defined between two coated fins when more than one fin is present. The recess is filled up with a dielectric material so as to cover the coating on the side walls of the at least one fin up to a certain height h′, which is less than the height h. The present disclosure also relates to a method for producing the semiconductor device.
A bio-sensing device suitable for the detection and/or characterization of target bioparticles and corresponding method is described. The bio-sensing technique is based on the impact on the heat transfer resistivity value of bioparticles binding in binding cavities of a structured substrate. By sensing temperatures and determining a heat transfer resistivity value based thereon, a characteristic of the target bioparticles can be derived.
In one aspect, a method is disclosed that includes providing a substrate having a topography that comprises a relief and providing an anti-reflective film conformally over the substrate using a molecular layer deposition step. The anti-reflective film may be formed of a compound selected from the group consisting of: (i) an organic compound chemically bound to an inorganic compound, where one of the organic compound and the inorganic compound is bound to the substrate and where the organic compound absorbs light at at least one wavelength selected in the range 150-500 nm, or (ii) a monodisperse organic compound absorbing light at at least one wavelength selected in the range 150-500 nm. The method further includes providing a photoresist layer on the anti-reflective film.
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
G03F 7/09 - Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
The disclosed technology relates generally to electromechanical devices, and relates more specifically to a nanoelectromechanical switch device and a method for manufacturing the same. In one aspect, an electromechanical device includes a first electrode stack and a second electrode stack, both electrode stacks extending in a vertical direction relative to a substrate surface and being spaced apart by a gap. The electromechanical device additionally includes a third electrode stack comprising a beam extending in a vertical direction in the electrode gap and being spaced apart from the first electrode stack by a first gap, from the second electrode stack by a second gap, and from the substrate by a third gap; and a connector portion overlapping the first and second electrode stacks, wherein, in operation, the beam is movable in a first direction so as to electrically connect with the first electrode stack or in a second direction so as to electrically connect with the second electrode stack, and, in a rest position, the beam is isolated from the first and the second electrode stacks. Additionally, at least one of the first or second electrode stacks comprises two electrodes including a top electrode stacked over a bottom electrode, wherein the top and bottom electrodes are separated by an electrical insulator.
A method for tuning the effective work function of a gate structure in a semiconductor device is described. The semiconductor device is part of an integrated circuit and the gate structure has a metal layer and a high-k dielectric layer separating the metal layer from an active layer of the semiconductor device. The method includes providing an interconnect structure of the integrated circuit on top of the gate structure, the interconnect structure comprising a layer stack comprising at least a pre-metal dielectric layer comprising a metal filled connecting via connected to the gate structure through the pre-metal dielectric layer, and the interconnect structure having an upper exposed metal portion; and, thereafter, exposing at least a portion of the upper exposed metal portion to a plasma under predetermined exposure conditions, to tune the effective work function of the gate structure.
In the present invention, a molecular analysis device comprises a substrate, and a waveguide with a planar integrating element and filter or reflector element adjacent thereto is disposed on the substrate. The waveguide comprises a coupling means configured for coupling a predetermined frequency range of laser radiation into the waveguide. At least one metallic nanostructure is disposed on or adjacent to the planar integrating element, at least one metallic nanostructure is configured such that the field intensity and the gradient of the laser radiation, that is coupled into the waveguide, are enhanced over a sufficiently large volume around the nanostructure to simultaneously cause plasmonic based optical trapping of analyte(s) in a medium, and plasmonic based excitation of the particles to produce Raman scattered radiation. A Raman scattered radiation collection means is disposed on the substrate for collecting said Raman scattered radiation produced by the particles.
A tunable impedance network and a method for tuning the tunable impedance network are disclosed. In one aspect, the tunable impedance network comprises a plurality of transformers connected in series. Each transformer has a primary winding and a secondary winding. The transformers have a voltage transformation ratio of N:1 with N>1. An impedance structure, acting as a resonant circuit together with the inductance of the secondary winding, is connected at the secondary winding of each transformer. A control circuit or processor is configured to tune the imaginary part of at least one of the impedance structures so as to change its resonance frequency to mimic a reference impedance. The control circuit is further configured to tune the real part of at least one of the impedance structures so as to change its Q-factor to mimic the reference impedance.
A current generator is disclosed. An example current generator includes a plurality of current cells connected in parallel, each current cell being connected to a switch. The current generator further includes a first summer configured to sum the output of each current cell of a first subset of the plurality of current cells and a second summer configured to sum the output of each current cell of a second subset of the plurality of current cells. The current generator also includes a combiner configured to combine the outputs of the first and second summers. Further, each switch is switchable according to a sequence to generate a summed output of the current cells at a plurality of quantization levels to generate positive and/or negative alternations of a pseudo-sinusoidal, alternating current.
The disclosed technology generally relates to photovoltaic devices and methods of fabricating photovoltaic devices, and more particularly relates to interdigitated back contact photovoltaic cells and methods of fabricating the same. In one aspect, a method of forming first and second interdigitated electrodes on a semiconductor substrate comprises providing a dielectric layer on the rear surface of the semiconductor substrate. The method additionally comprises providing a metal seed layer on the dielectric layer. The method additionally comprises patterning the metal seed layer by laser ablation, thereby separating it into a first seed layer and a second seed layer with a separation region interposed therebetween, wherein the first seed layer and the second seed layer are interdigitated and electrically isolated from each other. The method further comprises thickening the first seed layer and the second seed layer by plating, thereby forming the first electrode and the second electrode.
H01L 31/068 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
57.
Method for bonding of group III-nitride device-on-silicon and devices obtained thereof
A method for flip chip bonding a GaN device formed on a silicon substrate is described. The method includes providing a silicon substrate having a GaN device thereon, the GaN device comprising at least one gallium-nitride layer near the silicon substrate and remote from the silicon substrate a dielectric layer comprising at least one via configured to electrically contact the at least one gallium-nitride layer, forming a stiffener layer over the GaN device leaving the at least one via exposed, flip chip bonding the GaN device to a submount, wherein the stiffener layer physically contacts the submount and the submount is electrically connected to the at least gallium-nitride layer through the via, and completely removing the silicon substrate exposing the GaN device. Preferably, the material of the stiffener layer comprises silicon, such as silicon, silicon-germanium, or silicon-carbide.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 21/44 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
58.
Spectral imaging device and method to calibrate the same
A solid-state spectral imaging device is described. The device includes an image sensor and a plurality of optical filters directly processed on top of the image sensor. Each optical filter includes a first mirror and a second mirror defining an optical filter cavity having a fixed height. Each optical filter also includes a first electrode and a second electrode having a fixed position located opposite to each other and positioned to measure the height of the optical filter cavity. Further, a method to calibrate spectral data of light and a computer program for calibrating light is described.
G01J 3/36 - Investigating two or more bands of a spectrum by separate detectors
G01B 7/06 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width, or thickness for measuring thickness
59.
Method for forming patterns of differently doped regions
The disclosed technology generally relates to forming patterns of doped semiconductor regions, and more particularly to methods of forming such patterns in fabricating photovoltaic devices. In one aspect, a method of forming a pattern of different doped regions at the same side of a semiconductor substrate comprises providing a patterned doped layer on a surface of the semiconductor substrate at predetermined locations where at least one first doped region is to be formed. The method additionally includes selectively growing at least one second doped region epitaxially at the same side of the semiconductor substrate using the patterned doped layer as an epitaxial growth mask. Furthermore, selectively growing comprises driving dopants from the patterned doped layer into the semiconductor substrate to form the first doped region at the predetermined locations.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 31/068 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
60.
Micro-fluidic device for sorting particles, and methods for sorting particles
A method and device for the sorting and focusing of suspended particles is disclosed. The device has a micro-fluidic channel, at least one inlet and a number of outlets for providing, sorting and receiving particles. A patterned array of grooves is present inside the micro-fluidic channel. The inlets and outlets are connected to the micro-fluidic channel. The particles are sorted by the array of grooves. The method consists of providing particles in a flow-focused manner to one end of the micro-fluidic channel using at least one inlet. The particles are sorted by the array of grooves present in the micro-fluidic channel. Particles are collected by a number of outlets which are connected to the other end of the micro-fluidic channel.
A circuit for reducing counter-intermodulation in a modulated signal caused by an oscillator frequency and harmonics of a baseband signal is disclosed. The circuit comprises a first and a second baseband section arranged for generating a first and a second version of a baseband signal, the second version being phase shifted with respect to the first version. The circuit further comprises three signal paths comprising mixers for multiplication of the first and second version of the baseband signal with a local oscillator signal, so that three upconverted signals with rotated phase with respect to each other are obtained, and arranged for applying a scaling with a scaling factor corresponding to the rotated phases. The circuit further comprises a combination unit arranged for combining the three upconverted signals.
Thermally stabilized resonant electro-optic modulator (1), wherein the temperature control unit (8) is provided for separately determining the first and the second intensities measured by the light sensor (6) at the first voltages and the second voltages respectively in function of time.
G02F 1/29 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the position or the direction of light beams, i.e. deflection
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
G02F 1/03 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect
G02F 1/313 - Digital deflection devices in an optical waveguide structure
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.
H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
Hu, Yu-Hsiang
Liu, Chung-Shi
Abstract
A method is provided for bonding a first semiconductor substrate to a second semiconductor substrate using low temperature thermo-compression. The bonding method comprises the step of in-situ mechanically scrubbing the metal contact structure surfaces prior to thermo-compression bonding step, thereby planarizing the removing the oxides and/or contaminants from the metal contact structure surfaces. The thermo-compression bonding step is followed by a thermal annealing step for creating interface diffusion between the metal contact structure of the first and second semiconductor substrates
A photonic device having a wavelength-dependent transmission or filter characteristic, comprising: a Splitter Polarization Rotator (SPR) configured to receive an input wave having a first polarization and outputting a first wave having the first polarization and a second wave having a second polarization different from the first polarization; first and second waveguide arms connected to the SPR configured to propagate the first and second waves respectively; and a Polarization Rotator and Combiner for combining the propagated first and second waves; wherein the dimensions of the first waveguide arm and the second waveguide arm are selected to cancel the influence of an external effect on the wavelength-dependent characteristic. Another aspect of the invention relates to a method for reducing the sensitivity of said integrated photonic device, comprising splitting a polarized light beam, propagating light waves of different through two waveguide arms of specific dimensions, and recombining them.
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference
66.
III-nitride transistor with source-connected heat spreading plate
Disclosed are semiconductor devices and methods for manufacturing them. An example device may include a III-nitride stack having a front side surface and a back side surface. The III-nitride stack may be formed of at least a first layer and a second layer, between which a heterojunction may be formed, such that a two-dimensional electron gas layer is formed in the second layer. A source electrode, a drain electrode, and a gate electrode positioned between the source and drain electrodes may be formed on the front side surface, and an insulation layer may be formed over the electrodes on the front side surface. A carrier substrate may be attached to the insulation layer. An electrically conductive back plate may be formed on the back side surface. The back plate may directly face the source electrode and the gate electrode, but not the drain electrode.
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/283 - Deposition of conductive or insulating materials for electrodes
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
67.
Semiconductor heterostructure field effect transistor and method for making thereof
A heterostructure field effect transistor is provided comprising a semiconductor wire comprising in its longitudinal direction a source and a drain region, a channel region in between the source and drain region and in its transversal direction for the source region, a source core region and a source shell region disposed around the source core region, the source shell region having in its transversal direction for the drain region, a drain core region and a drain shell region disposed around the drain core region, the drain shell region having in its transversal direction for the channel region, a channel core region and a channel shell region disposed around the channel core region; wherein the thickness of the channel shell region is smaller than the thickness of the source shell region and is smaller than the thickness of the drain shell region.
H01L 31/0336 - Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups in different semiconductor regions, e.g. Cu2X/CdX hetero-junctions, X being an element of Group VI of the Periodic System
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
A spin transfer torque magnetic memory device is disclosed. In one aspect, the spin transfer torque magnetic memory device comprises a first layered structure stacked in a vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device additionally includes a second layered structure stacked in the vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device further includes a magnetic material interposing the first and second layered structures in a horizontal direction different from the vertical direction such that the magnetic material is in contact with a first side surface of the first layered structure and in contact with a first side surface of the second layered structure. Additionally, the magnetic material is configured to have a magnetization direction that can change in response to a current flowing through the magnetic material.
H01L 29/82 - Types of semiconductor device controllable by variation of the magnetic field applied to the device
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H01L 43/12 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
H01L 21/336 - Field-effect transistors with an insulated gate
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
69.
FinFET device with dual-strained channels and method for manufacturing thereof
A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.
H01L 21/77 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
An avalanche photodetector element is disclosed for converting an optical signal to an electrical signal, comprising an input waveguide and a photodetector region, the photodetector region comprising at least one intrinsic region, at least one p-doped region and at least one n-doped region, the doped regions and the at least one intrinsic region forming at least one PIN-junction avalanche photodiode, the input waveguide and the photodetector region being arranged with respect to each other such that the optical signal conducted by the input waveguide is substantially conducted into the photodetector region to the PIN-junction avalanche photodiode, the PIN-junction avalanche photodiode converting the optical signal to an electrical signal, characterized in that the photodetector region comprises more than one p-doped region and/or n-doped region, whereby these p-doped regions and/or n-doped regions are physically arranged as an array.
H01L 31/0232 - Optical elements or arrangements associated with the device
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
H01L 31/028 - Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System
H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 51/00 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
B82Y 40/00 - Manufacture or treatment of nanostructures
72.
Semiconductor device comprising a diode and a method for producing such a device
The disclosed technology relates to a semiconductor device comprising a diode junction between two semiconductor regions of different doping types. In one aspect, the diode comprises a junction formed between an upper portion of an active area and a remainder of the active area, where the active area is defined in a substrate between two field dielectric regions. The upper portion is a portion of the active area that has a width smaller than a width of the active area itself. In another aspect, the semiconductor device is an electrostatic discharge protection device (ESD) comprising such a diode. In addition, the active area has a doping profile that exhibits a maximum value at the surface of the active area, and changes to a minimum value at a first depth, where the first depth can be greater in value than half of a depth of the upper portion. In another aspect, a method of fabrication the device does not require a separate ESD implant for lowering the holding voltage and can allow for a reduction in the number of processing steps as well as other devices comprising a diode junction.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
Kumar Goel, Sandeep
Marinissen, Erik Jan
Abstract
A test circuitry is configured to test for transition delay defects in a first inter-die interconnect connecting a first die and a second die. A test data value is initially received and temporarily stored in a data storage element. The test data is subsequently looped between the storage element and the second die through a feedback loop including the first inter-die interconnect and a second inter-die interconnect. A data conditioner conditions the test data value received from the second die so as to make it distinguishable from the test data value sent to the second die. A clock pulse generator generates a delayed clock pulse. A selection logic applies the generated delayed clock pulse and the conditioned fed back test data value to the data storage element. A readout unit for reading out a test data value stored in the data storage element.
The disclosed technology relates to a device including a diode. In one aspect, the device includes a lower group III metal nitride layer and an upper group III metal nitride layer and a heterojunction formed therebetween, where the heterojunction extends horizontally and is configured to form a two-dimensional electron gas (2DEG) that is substantially confined in a vertical direction and within the lower group III metal nitride layer. The device additionally includes a cathode forming an ohmic contact with the upper group III metal nitride layer. The device additionally includes an anode, which includes a first portion that forms a Schottky barrier contact with the upper group III metal nitride layer, and a second portion that is separated vertically from the upper group III metal nitride layer by a layer of dielectric material. The anode is configured such that the second portion is horizontally located between the anode and the cathode and the dielectric material is configured to pinch off the 2DEG layer in a reverse biased configuration of the device. The device further includes a passivation area formed between the anode and the cathode to horizontally separate the anode and the cathode from each other.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types. The method additionally includes forming a dielectric layer on the substrate, which extends to cover at least parts of the first and second areas. The method additionally includes forming a first metal layer/stack on the dielectric layer in the first area, where the first metal layer/stack comprises a first work function-shifting element. The method additionally includes forming a second metal layer/stack on the first metal layer in the first area and on the dielectric layer in the second area, where the second metal layer/stack comprises a second work function-shifting element. The method additionally includes annealing to diffuse the first work function-shifting element and the second work function-shifting element into the dielectric layer, and subsequently removing the first metal layer/stack and the second metal layer/stack. The method further includes forming a third metal layer/stack in the first and second predetermined areas.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Disclosed are methods for forming fins. In an example embodiment, a method includes providing a substrate that includes at least two elongated structures separated by an isolation region. Each elongated structure comprises a semiconductor alloy of a first semiconductor material and a second semiconductor material, and a relaxed portion of the elongated structure includes the semiconductor alloy in a relaxed and substantially defect-free condition. The method further includes subjecting the substrate to a condensation-oxidation, such that each elongated structure forms a fin and an oxide layer. The fin includes a fin base portion formed of the semiconductor alloy and a fin top portion of the first semiconductor material in a strained condition. The fin top portion is formed by condensation of the first semiconductor material. The oxide layer includes an oxide of the second semiconductor material. The method further includes removing at least some of the oxide layer.
H01L 21/479 - Application of electric currents or fields, e.g. for electroforming
H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group
The present disclosure relates to a method (10) for block-copolymer lithography. This method comprises the step of obtaining (12) a self-organizing block-copolymer layer comprising at least two polymer components having mutually different etching resistances, and the steps of applying at least once each of first plasma etching (14) of said self-organizing block-copolymer layer using a plasma formed from a substantially ashing gas, and second plasma etching (16) of said self-organizing block-copolymer layer using plasma formed from a pure inert gas or mixture of inert gases in order to selectively remove a first polymer phase. A corresponding intermediate product also is described.
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H01L 21/461 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
H01L 21/4763 - Deposition of non-insulating-, e.g. conductive-, resistive-, layers on insulating layersAfter-treatment of these layers
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01L 21/36 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines. The memory device further comprises a memory controller connected to and configured to apply voltages to the bit lines, the word lines, the source lines and the form lines. In addition, each of the memory cells comprises a cell selecting transistor and a resistive memory element serially connected to a drain-source path of the cell selecting transistor. Furthermore, each of the memory cells comprises a boosting capacitor configured to provide a boosting a voltage to an internal node formed at a connection point between the resistive memory element and the cell selecting transistor.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
Katholieke Universiteit Leuven, KU Leuven R&D (Belgium)
Inventor
De Volder, Michael
Abstract
Disclosed are methods for fabricating pyrolysed carbon nanostructures. An example method includes providing a substrate, depositing a polymeric material, subjecting the polymeric material to a plasma etching process to form polymeric nanostructures, and pyrolysing the polymeric nanostructures to form carbon nanostructures. The polymeric material comprises either compounds with different plasma etch rates or compounds that can mask a plasma etching process. The plasma etching process may be an oxygen plasma etching process.
Katholieke Universiteit Leuven, KU LEUVEN R&D (Belgium)
Inventor
Morgado, Alonso
Porrazzo, Serena
Cannillo, Francesco
Abstract
A circuit for digitizing a sum of a first input signal and a plurality of second input signals has a passive adder that sums the second input signals and outputs a summation signal and a multi-bit quantizer circuit. The quantizer circuit compares the summation signal at a first comparator input with a signal at a second comparator input, which is derived from the first input signal and has an appropriate polarity so that the difference between the summation signal and the signal at the second comparator input is indicative of the sum of the first input signal and the plurality of second input signals. The comparator also produces a comparator output signal based on the sum of the first input signal and the plurality of second input signals. The quantizer circuit also has a control logic block for determining a multi-bit representation of the sum from the comparator output signal.
The disclosure is related to an SSRM method for measuring the local resistivity and carrier concentration of a conductive sample. The method includes contacting the conductive sample at one side with an AFM probe and at another side with a contact electrode, modulating, at a modulation frequency, the force applied to maintain physical contact between the AFM probe and the sample while preserving the physical contact between the AFM probe and the sample, thereby modulating at the modulation frequency the spreading resistance of the sample; measuring the current flowing through the sample between the AFM probe and the contact electrode; and deriving from the measured current the modulated spreading resistance. Deriving the modulated spreading resistance includes measuring the spreading current using a current-to-voltage amplifier, converting the voltage signal into a resistance signal, and filtering out from the resistance signal, the resistance amplitude at the modulation frequency.
This present application relates to a system for delivering megasonic energy to a liquid, involving one or more megasonic transducers, each transducer having a single operating frequency within an ultrasound bandwidth and comprising two or more groups of piezoelectric elements arranged in one or more rows, and a megasonic generator means for driving the one or more transducers at frequencies within the bandwidth, the generator means being adapted for changing the voltage applied to each group of piezoelectric elements so as to achieve substantially the same maximum acoustic pressure for each group of piezoelectric elements. The generator means and transducers being constructed and arranged so as to produce ultrasound within the liquid. Such a system may be part of an apparatus for cleaning a surface of an article such as a semiconductor wafer or a medical implant.
H01L 41/09 - Piezo-electric or electrostrictive elements with electrical input and mechanical output
B08B 3/12 - Cleaning involving contact with liquid with additional treatment of the liquid or of the object being cleaned, e.g. by heat, by electricity or by vibration by sonic or ultrasonic vibrations
B06B 1/06 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
83.
Methods for manufacturing a field-effect semiconductor device
A method of fabricating a field-effect transistor is disclosed. In one aspect, the method includes forming a channel layer comprising germanium over a substrate. The method additionally includes forming a gate structure on the channel layer, where the gate structure comprises a gate layer comprising silicon, and the gate layer has sidewalls above a surface of the channel layer. The method additionally includes forming sidewall spacers comprising silicon dioxide on the sidewalls by subjecting the gate structure to a solution adapted for forming a chemical silicon oxide on materials comprising silicon. The method further includes forming elevated source/drain structures on the channel layer adjacent to the gate structure by selectively epitaxially growing a source/drain material on the channel layer.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
85.
Method for selective growth of highly doped group IV—Sn semiconductor materials
Disclosed are methods for selective deposition of doped Group IV-Sn materials. In some embodiments, the method includes providing a patterned substrate comprising at least a first region and a second region, where the first region includes an exposed first semiconductor material and the second region includes an exposed insulator material, and performing at least two cycles of a grow-etch cyclic process. Each cycle includes depositing a doped Group IV-Tin (Sn) layer, where depositing the doped Group IV-Sn layer includes providing a Group IV precursor, a Sn precursor, and a dopant precursor, and using an etch gas to etch back the deposited doped Group IV-Sn layer.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
86.
Method for doping semiconductor structures and the semiconductor device thereof
A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
87.
Complementary metal-oxide-semiconductor device comprising silicon and germanium and method for manufacturing thereof
z, and where z is less than x. In some embodiments, the example CMOS device may be a fin field-effect transistor (FinFET) CMOS device and may further include a first fin structure including the pMOS channel layer element(s) and a second fin structure including the nMOS channel layer element(s).
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
88.
Heat-transfer resistance based analysis bioparticles
A method an system is disclosed for characterizing DNA and/or RNA duplexes. The biosensing device comprises a heating element using a power and being suitable for providing thermal denaturation of target DNA and/or RNA bioparticles, a sample holder adapted for receiving a biocompatible substrate having a functionalized surface which is coated with probe DNA and/or RNA whereto target DNA and/or RNA duplexes can be attached, the sample holder further being adapted for exposing the biocompatible substrate at one side to the heating element, a first temperature sensing element for sensing a temperature at the side where the biocompatible substrate can be exposed to the heating element and a second temperature sensing element for sensing a temperature at the side opposite thereto with respect to the biocompatible substrate. The device also comprises a processing means programmed for calculating at least one heat transfer resistivity value based on temperature values obtained with the first temperature sensing element and the second temperature sensing element and the power for the heating element, for deriving a characteristic of the target DNA and/or RNA bioparticles from said heat transfer resistivity value.
C12M 1/34 - Measuring or testing with condition measuring or sensing means, e.g. colony counters
C12M 3/00 - Tissue, human, animal or plant cell, or virus culture apparatus
C12M 1/00 - Apparatus for enzymology or microbiology
C12Q 1/68 - Measuring or testing processes involving enzymes, nucleic acids or microorganismsCompositions thereforProcesses of preparing such compositions involving nucleic acids
C07H 21/02 - Compounds containing two or more mononucleotide units having separate phosphate or polyphosphate groups linked by saccharide radicals of nucleoside groups, e.g. nucleic acids with ribosyl as saccharide radical
C07H 21/04 - Compounds containing two or more mononucleotide units having separate phosphate or polyphosphate groups linked by saccharide radicals of nucleoside groups, e.g. nucleic acids with deoxyribosyl as saccharide radical
G01N 15/06 - Investigating concentration of particle suspensions
G01N 27/00 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
G01N 25/00 - Investigating or analysing materials by the use of thermal means
G01N 31/22 - Investigating or analysing non-biological materials by the use of the chemical methods specified in the subgroupsApparatus specially adapted for such methods using chemical indicators
The disclosed technology relates to a light-emitting diode (LED) and a method of fabricating the same. In one aspect, the LED includes a GaN p-n junction formed at a junction between a p-type GaN layer and an n-type GaN layer. The LED further includes a first metal electrode layer provided on the p-type GaN layer, where the first metal electrode layer is configured to reflect light emitted by the p-n junction towards a light emitting side of the LED. The LED additionally includes an attachment layer interposed between and configured to electrically connect the p-type GaN layer and the metal electrode layer, wherein the attachment layer comprises a transition metal oxide and is configured to transmit light emitted by the p-n junction and to transmit light reflected by the metal electrode layer.
A method for forming a nanostructure penetrating a layer and the device made thereof is disclosed. In one aspect, the device has a substrate, a layer present thereon, and a nanostructure penetrating the layer. The nanostructure defines a nanoscale passageway through which a molecule to be analyzed can pass through. The nanostructure has, in cross-sectional view, a substantially triangular shape. This shape is particularly achieved by growth of an epitaxial layer having crystal facets defining tilted sidewalls of the nanostructure. It is highly suitably for use for optical characterization of molecular structure, particularly with surface plasmon enhanced transmission spectroscopy.
The present invention relates to a method for fabricating a semiconductor device for stimulation and/or data recording of biological material to a such semiconductor device. The method comprises providing a semiconductor substrate comprising a first insulating layer; providing a patterned conductive layer on top of the first insulating layer; depositing and patterning a second insulating layer atop the patterned conductive layer; growing carbon nano-sheets atop the second insulating layer; and defining carbon nano-sheet electrode areas on the second insulating layer by etching away the carbon nano-sheets outside of the carbon nano-sheet electrode areas.
Described herein is a method for forming a vertical memory device (150) having a vertical channel region (113) sandwiched between a source region (109, 112) and a drain region (114). A charge trapping layer (106) is provided either side of the vertical channel region (113) and associated source and drain regions (109, 112, 114). The source region (109, 112) comprises a junction between a first region (109) comprising a first doping type with a first doping concentration and a second region (112) comprising a second doping type which is opposite to the first doping type and with a second doping concentration. The drain region (114) comprises the first doping type with a first doping concentration. In another embodiment, the drain region has two regions of differing doping types and concentrations and the source region comprises the first doping type with the first doping concentration.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
The present disclosure relates to a circuit for providing a signal gain, comprising: a first stage comprising a first set of variable gain transconductors arranged for receiving an input signal and for performing phase-shifting of the input signal, thereby producing an intermediate signal, and a second stage, comprising a second set of transconductors and a plurality of capacitors arranged for receiving the intermediate signal and for providing an output signal to a combiner, wherein the first stage and second stage together form a filter, and wherein the first set of variable gain transconductors and at least one of the transconductors of the second set define the signal gain of the circuit.
H04B 7/00 - Radio transmission systems, i.e. using radiation field
H04B 1/18 - Input circuits, e.g. for coupling to an antenna or a transmission line
H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
94.
Low voltage drop unidirectional smart bypass elements
Described herein is a low-voltage unidirectional bypass element connected across a solar cell and operable to allow current to flow when the operation of the solar cell is suspended. The bypass element includes a single field effect transistor connected between first and second terminals as a switch, and a detection circuit for detecting suspension of the solar cell's operation and activating the switch to bypass the solar cell in the event of its operation suspension. Diodes are connected in parallel with the normally-open switch and receive current, when the solar cell's operation is suspended, to trigger operation of the detection circuit. The detection circuit includes a charge pump, a timer circuit, a control generation unit and a switch control circuit. The switch control circuit generates a control signal to close the switch and to allow current to bypass the solar cell.
H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
H03K 17/06 - Modifications for ensuring a fully conducting state
H01L 31/042 - PV modules or arrays of single PV cells
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
95.
Tunnel field effect transistor device and method for making the device
A Tunnel Field Effect Transistor device (TFET) made of at least following layers: a highly doped drain layer, a highly doped source layer, a channel layer, a gate dielectric layer and a gate electrode layer, the gate dielectric layer extending along the source layer, and a highly doped pocket layer extending in between and along the gate dielectric layer and the source layer, characterized in that the pocket layer extends to between and along the source layer and the channel layer.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A method an system is disclosed for the detection and/or allocation of at least one point mutation in target DNA and/or RNA duplexes. The method comprises obtaining a functionalized surface which is coated with probe DNA and/or RNA whereto target DNA and/or RNA duplexes are attached, contacting said functionalized surface to an electrolytic solution having a neutral pH in a flow cell and measuring a first impedance value within said electrolytic solution, and then adding a chemical to the electrolytic solution which is able to achieve denaturation of the target DNA and/or RNA. The method further comprises measuring a second impedance value within the flow cell after completion of the denaturation of the DNA and/or RNA target, and then obtaining a value representative for the impact of the chemical on the impedance of the electrolytic solution. The amount and/or allocation of point mutation(s) within the target DNA and/or RNA is then determined by calculating the denaturation-time constant based on the difference between the first and second impedance value and taking into account the impact of the chemical by third impedance value.
A semiconductor device is provided comprising a bilayer graphene comprising a first and a second adjacent graphene layer, and a first electrically insulating layer contacting the first graphene layer, the first electrically insulating layer comprising an electrically insulating material, and a substance suitable for creating free charge carriers of a first type in the first graphene layer, the semiconductor device further comprising an electrically insulating region contacting the second graphene layer and suitable for creating free charge carriers of a second type, opposite to the first type, in the second graphene layer.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 51/05 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier
A microfluidic chip for use in multiplexed analysis of samples is described. The microfluidic chip comprises a plurality of sensing chambers and further comprises at least a first fluid supply channel for providing a first fluid and a plurality of microfluidic channels. These are in fluid communication with at least one sensing chamber and with the first fluid supply channel for delivery of said first fluid to the at least one sensing chamber. The microfluidic channels are branching off from the supply channel in the neighborhood of the sensing chamber that can be provided with the first fluid through the microfluidic channel. The different channels thus form a tree-like delivery distribution system for supplying the first fluid to said plurality of sensing chambers.
A sensor chip for use in multiplexed analysis of at least one sample is described. The sensor chip comprises a plurality of sensing sites, each sensing site adapted for sensing an optional interaction of a sample with a component and an input waveguide for receiving radiation from a frequency comb radiation source and guiding said radiation along said plurality of sensing sites. At each sensing site, a distinct optical sensitive element is adapted for, at a distinct frequency, sensing an optional interaction of said sample with said component. An output means provides output of the radiation representative for the sensing dependent on said optional interaction of said sample with said component at said plurality of sensing sites.
G01N 21/39 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using tunable lasers
G01N 21/77 - Systems in which material is subjected to a chemical reaction, the progress or the result of the reaction being investigated by observing the effect on a chemical indicator
A holographic imaging device for imaging an object under study includes a partially reflective surface having a contact side for contacting the object under study and an imaging side for partially reflecting a radiation wave. The device also includes at least one radiation source for projecting the radiation wave onto the imaging side of the partially reflective surface and an image sensor arranged to receive the radiation wave when reflected by the partially reflective surface. The image sensor is adapted for determining an interference pattern between the radiation wave reflected by the imaging side of the partially reflective surface and the radiation wave reflected by the object under study when contacting the contact side of the partially reflective surface.
G02B 1/10 - Optical coatings produced by application to, or surface treatment of, optical elements
G03H 1/04 - Processes or apparatus for producing holograms
G03H 1/00 - Holographic processes or apparatus using light, infrared, or ultraviolet waves for obtaining holograms or for obtaining an image from themDetails peculiar thereto
G03H 1/02 - Holographic processes or apparatus using light, infrared, or ultraviolet waves for obtaining holograms or for obtaining an image from themDetails peculiar thereto Details
