Abstract

A bipolar junction transistor with adjustable gain is provided, including a semiconductor substrate and doped layer of a first conductivity type, a doped well region of a second conductivity type and a plurality of heavily doped regions. At least one detection circuit is provided with an input voltage and operable to generate an output voltage for a conducting layer to receive, such that current paths generated in the transistor can be determined when the input voltage varies under different operating conditions, including a normal operating mode, a positive and a negative surged operating mode. When a transient event takes place, the bipolar junction transistor is characterized by having a higher gain than it is operating in the normal mode. The proposed invention achieves in integrating the unidirectional and bidirectional electrical characteristics in the disclosed bipolar junction transistor structure by employing the detection circuit such that adjustable gain is obtained.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

An electrostatic discharge protection device includes a P-type substrate, an N-type well, a first P-type heavily-doped area, an N-type doped area, and a first N-type heavily-doped area. The N-type well is formed in the P-type substrate. The first P-type heavily-doped area is formed in the N-type well. The N-type doped area and the first N-type heavily-doped area are formed in the P-type substrate. The N-type doped area is coupled to the N-type well through an external conductive wire decoupled to the first P-type heavily-doped area. Alternatively, the P-type substrate and the N-type well are respectively replaced with an N-type substrate and a P-type well.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H02H 1/00 - Details of emergency protective circuit arrangements
• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

Abstract

A bipolar junction transistor is provided, including a semiconductor substrate and a doped layer of a first conductivity type, a doped well region of a second conductivity type formed in the doped layer, a first, second heavily doped region of the second conductivity type, and a third, fourth and fifth heavily doped region of the first conductivity type in the doped well region. The fifth heavily doped region is coupled with a first pin. The third and fourth heavily doped regions are coupled with a second pin. A sixth and seventh heavily doped region of the first conductivity type are disposed in the doped layer. The sixth and first heavily doped regions are connected in common. The seventh and second heavily doped regions are connected in common. When applying either a positive or negative surged mode, the bipolar junction transistor is formed, having both lateral and vertical conducting paths.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/735 - Lateral transistors

Abstract

A transient voltage suppression device includes at least one N-type lightly-doped structure, a first P-type well, a second P-type well, a first N-type heavily-doped area, and a second N-type heavily-doped area. The first P-type well and the second P-type well are formed in the N-type lightly-doped structure. The first N-type heavily-doped area and the second N-type heavily-doped area are respectively formed in the first P-type well and the second P-type well. The doping concentration of the first P-type well is higher than that of the second P-type well. The first P-type well and the second P-type well can be replaced with P-type lightly-doped wells respectively having P-type heavily-doped areas under the N-type heavily-doped areas.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/861 - Diodes

Abstract

An ESD protection device includes an N-type semiconductor substrate, a P-type semiconductor layer, a first N-type well, a P-type well, a second N-type well, a first P-type heavily-doped area, a first N-type heavily-doped area, and a second P-type heavily-doped area. The semiconductor layer is formed on the substrate. The wells are formed in the semiconductor layer. The second N-type well directly touches the substrate. The first P-type heavily-doped area is formed in the first N-type well. The first N-type heavily-doped area and the second P-type heavily-doped area are formed in the P-type well. The second P-type heavily-doped area is coupled to the second N-type well through an external conductive wire and replaced with a second N-type heavily-doped area.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A transient voltage suppressor with adjustable trigger and holding voltages is provided, including a heavily doped substrate of a first conductivity type connected to a first node, a lightly doped epitaxial layer of a second conductivity type on the substrate, a first and third well region of the first conductivity type, a second well region of the second conductivity type, a first and third heavily doped region of the second conductivity type and a second heavily doped region of the first conductivity type. The heavily doped regions are commonly electrically connected to a second node, and individually disposed in the well regions. Trenches are disposed opposite in the substrate for electrical isolation. A floating base bipolar junction transistor and silicon controlled rectifier can be respectively formed under a positive and negative surged mode. Accordingly, the invention is advantageous of superior electrical performances, high layout flexibility and low area consumption.

IPC Classes  ?

• H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]

Abstract

A ringing suppression circuit applicable to a transmitter module in a controller area network is provided, which includes a CANH driver circuit, a CANL driver circuit, a first operable circuit transmitting a CAN high signal, a second operable circuit transmitting a CAN low signal, and a termination component connected between the first operable circuit and the second operable circuit. By sequentially turning on a first, second, and third transistor of the CANH driver circuit and sequentially turning on a fourth, fifth, and sixth transistor of the CANL driver circuit, conventional ringing phenomenon is effectively suppressed. A plurality of transistors may also be configured for implementing the CANH driver circuit or the CANL driver circuit for further reducing a glitch. The transmitter module employing the proposed ringing suppression circuit is able to pull the bus to a recessive state and meanwhile suppress the ringing and improve the maximum data rate.

IPC Classes  ?

• H04M 19/02 - Current supply arrangements for telephone systems providing ringing current or supervisory tones, e.g. dialling tone or busy tone
• H04L 25/02 - Baseband systems Details

Abstract

A transient voltage suppression device includes at least one P-type lightly-doped structure and at least one electrostatic discharge structure. The electrostatic discharge structure includes an N-type lightly-doped well, an N-type well, a first P-type heavily-doped area, and a first N-type heavily-doped area. The N-type lightly-doped well is formed in the P-type lightly-doped structure. The N-type well is formed in the N-type lightly-doped well. The doping concentration of the N-type lightly-doped well is less than that of the N-type well. The first P-type heavily-doped area is formed in the N-type well. The first N-type heavily-doped area is formed in the P-type lightly-doped structure.

IPC Classes  ?

• H01L 29/87 - Thyristor diodes, e.g. Shockley diodes, break-over diodes
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

A bidirectional electrostatic discharge protection device includes at least one bipolar junction transistor and at least one silicon-controlled rectifier. The silicon-controlled rectifier is coupled to the bipolar junction transistor in series. The absolute value of the breakdown voltage of the bipolar junction transistor is lower than that of the silicon-controlled rectifier and the absolute value of the holding voltage of the bipolar junction transistor is higher than that of the silicon-controlled rectifier when an electrostatic discharge voltage is applied to the bipolar junction transistor and the silicon-controlled rectifier.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A bidirectional electrostatic discharge protection device includes a first transient voltage suppressor chip, a second transient voltage suppressor chip, a first conductive wire, and a second conductive wire. The first transient voltage suppressor chip includes a first diode and a first bipolar junction transistor. The first diode and the first bipolar junction transistor are electrically connected to a first pin. The second transient voltage suppressor chip includes a second diode and a second bipolar junction transistor. The second diode and the second bipolar junction transistor are electrically connected to a second pin. The first conductive wire is electrically connected between the first diode and the second bipolar junction transistor. The second conductive wire is electrically connected between the second diode and the first bipolar junction transistor.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A diode test module and method applicable to the diode test module are provided. A substrate having first conductivity type and an epitaxial layer having second conductivity type on the substrate are formed. A well region having first conductivity type is formed in the epitaxial layer. A first and second heavily doped region having second conductivity type are theoretically formed in the well and connected to a first and second I/O terminal, respectively. Isolation trench is formed there in between for electrical isolation. A monitor cell comprising a third and fourth heavily doped region is provided in a current conduction path between the first and second I/O terminal when inputting an operation voltage. By employing the monitor cell, the invention achieves to determine if the well region is missing by measuring whether a leakage current is generated without additional testing equipment and time for conventional capacitance measurements.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• G01R 31/26 - Testing of individual semiconductor devices
• G01R 31/30 - Marginal testing, e.g. by varying supply voltage

Abstract

A multi-channel transient voltage suppression device includes a semiconductor substrate, a semiconductor layer, at least two bidirectional transient voltage suppression structures, and at least one isolation trench. The semiconductor substrate, having a first conductivity type, is coupled to a grounding terminal. The semiconductor layer, having a second conductivity type opposite to the first conductivity type, is formed on the semiconductor substrate. The bidirectional transient voltage suppression structures are formed in the semiconductor layer. Each bidirectional transient voltage suppression structure is coupled to an input/output (I/O) pin and the grounding terminal. The isolation trench is formed in the semiconductor substrate and the semiconductor layer and formed between the bidirectional transient voltage suppression structures. The isolation trench has a height larger than the height of the semiconductor layer and surrounds the bidirectional transient voltage suppression structures.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A transmitter circuit applicable to a digital isolator is provided, adapted to receive a data input signal and coupled to an isolation barrier, developing a receiver input signal to a receiver circuit for generating a data output signal. The transmitter circuit generates a transmitter output signal in response to a rising edge and falling edge of the data input signal, and includes a rising and falling converter for outputting a converted data input signal according to the rising edge and falling edge of the data input signal, a delay and logic unit for receiving the converted data input signal and generating a carrier signal, and an AND gate receiving the converted data input signal and the carrier signal, and outputting the transmitter output signal. Since a number of pulses of the carrier signal is limited and definite, the present invention achieves to reduce power consumption and electromagnetic interferences effectively.

IPC Classes  ?

• H04B 1/04 - Circuits
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
• H03K 5/01 - Shaping pulses
• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass

Abstract

A digital isolator module with pulse carrier modulation is provided, comprising an isolation barrier, operable to develop an isolated output signal in response to an input signal, a transmitter circuit adapted to receive a data input signal and coupled to the isolation barrier, and a receiver circuit coupled to the isolation barrier to receive the isolated output signal and generate a data output signal. The transmitter circuit is adapted to be operable to generate a transmitter output signal in response to the data input signal, and the transmitter output signal comprises different number of pulse carrier respectively responsive to a rising edge and a falling edge of the data input signal. By employing the proposed pulse carrier modulation of the present invention, it has been verified to reduce channel numbers, IC power consumption and electromagnetic interferences. In addition, jitter disturbances can be avoided and solved effectively.

IPC Classes  ?

• H04B 1/40 - Circuits
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

A transient voltage suppression device includes at least one diode string, a power clamp device, at least one first bypass diode, and at least two second bypass diodes. The diode string is coupled between a power terminal and a common bus and coupled to an input output (I/O) port. The power clamp device is coupled between the power terminal and the common bus. The first bypass diode is coupled between the common bus and a ground terminal. The second bypass diodes are coupled in series, coupled between the common bus and the ground terminal, and coupled to the first bypass diode in reverse parallel. Alternatively, the first bypass diode and the second bypass diodes are replaced with at least one bi-directional electrostatic discharge (ESD) device.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
• H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection

Abstract

A bus driving device includes at least three high-side output drivers and at least three low-side output drivers. A part of the high-side output drivers and a part of the low-side output drivers are alternately coupled in series, and the remains of the high-side output drivers and the low-side output drivers are alternately coupled in series. The part of the high-side output drivers and the part of the low-side output drivers receive an input digital signal and sequentially drive a first supply bus and a second supply bus based on the input digital signal, and the remains of the high-side output drivers and the low-side output drivers receive the inverted input digital signal and sequentially drive the first supply bus and the second supply bus based on the inverted input digital signal.

IPC Classes  ?

• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage
• H04L 12/40 - Bus networks

Abstract

A transient voltage suppression device includes a P-type semiconductor layer, a first N-type well, a first N-type heavily-doped area, a first P-type heavily-doped area, a second P-type heavily-doped area, and a second N-type heavily-doped area. The first N-type well and the second N-type heavily-doped area are formed in the layer. The first P-type heavily-doped area is formed in the first N-type well. The first P-type heavily-doped area is spaced from the bottom of the first N-type well. The second P-type heavily-doped area is formed within the first N-type well and spaced from the sidewall of the first N-type well. The second P-type heavily-doped area is formed between the first P-type heavily-doped area and the second N-type heavily-doped area.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one doped well, an isolation structure, and an external conductor. The heavily-doped semiconductor substrate and the doped well have a first conductivity type, and the first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The doped well is formed in the first semiconductor epitaxial layer. The isolation structure, formed in the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer, surrounds the first semiconductor epitaxial layer and the at least one doped well. The external conductor is arranged outside the first semiconductor epitaxial layer and the doped well and electrically connected to the first semiconductor epitaxial layer and the doped well.

IPC Classes  ?

• H01L 29/861 - Diodes
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Abstract

A vertical bipolar transistor device is disclosed. The vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one first doped well, and an external conductor. The heavily-doped semiconductor substrate and the first doped well have a first conductivity type. The first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The first doped well is formed in the first semiconductor epitaxial layer. The external conductor is arranged outside the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer and electrically connected to the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer.

IPC Classes  ?

• H01L 29/732 - Vertical transistors
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

An Electrostatic Discharge protection circuit with low parasitic capacitance is provided, comprising a first bipolar junction transistor and a first ESD power clamp device. The first bipolar junction transistor is an NPN type of bipolar junction transistor, including a base and an emitter commonly connected to an I/O terminal and a collector connected with the first ESD power clamp device. The first ESD power clamp device is further connected to ground, and can be a Zener diode, PNP type, NPN type of bipolar junction transistor or the like. When a positive ESD pulse is injected, an ESD protection path is consisting of the first bipolar junction transistor and the first ESD power clamp device. When a negative ESD pulse is injected, the ESD protection path is consisting of a parasitic silicon controlled rectifier, thereby reducing parasitic capacitance effectively.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/866 - Zener diodes
• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

Abstract

A bidirectional electrostatic discharge protection device and a method for fabricating the same is disclosed. The protection device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, a second semiconductor epitaxial layer, a heavily-doped area, and a lightly-doped area. The substrate, the heavily-doped area, and the lightly-doped area have a first conductivity type and the epitaxial layers have a second conductivity type. The first semiconductor epitaxial layer and the second semiconductor epitaxial layer are sequentially formed on the substrate, and the heavily-doped area and the lightly-doped area are formed in the second semiconductor epitaxial layer. The lightly-doped area covers the corner of the heavily-doped area, and the breakdown voltage of a junction between the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer corresponds to the breakdown voltage of a junction between the second semiconductor epitaxial layer and the heavily-doped area.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/732 - Vertical transistors
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Abstract

A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Abstract

A receiver circuit with input common mode voltage sensing is provided. The receiver circuit is applied to a controller area network and comprises a resistor assembly, connected with a high end and a low end of the controller area network, a common mode voltage sensor and a receiving amplifier. The resistor assembly bucks voltage, respectively generating the high end and low end voltage divisions at first and second nodes and outputting the voltage divisions to the receiving amplifier to generate a resultant signal to an output end of the controller area network. The common mode voltage sensor is connected between the resistor assembly and the receiving amplifier, and able to sense the common mode voltage on bus and control the voltage on center tap of the resistor assembly so the receiver circuit for controller area network can receive the differential signal with a much wider input common mode range.

IPC Classes  ?

• H03F 3/18 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices of complementary types
• H03F 3/189 - High-frequency amplifiers, e.g. radio frequency amplifiers
• H03F 3/45 - Differential amplifiers
• H04L 12/40 - Bus networks

Abstract

An embedded NMOS triggered silicon controlled rectification device includes a P-type substrate, at least one rectifying zone, and at least one trigger. The rectifying zone includes a first N-type heavily doped area, an N-type well, and a first P-type heavily doped area. Alternatively, the device includes an N-type substrate, a first P-type well, at least one rectifying zone, and at least one trigger. The rectifying zone includes a second P-type well, a first N-type heavily doped area, and a first P-type heavily doped area. The trigger cooperates with the P-type substrate or the first P-type well to form at least one NMOSFET. The trigger is independent to the rectifying zone. The first P-type heavily doped area is arranged between the trigger and the first N-type heavily doped area.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action

Abstract

A bus driver module with controlled circuit is connected to a controller area network bus for generating a high side output or a low side output, comprising a transition controlled circuit and an output driver. The transition controlled circuit comprises a first pathway controlled unit connected in parallel with a second pathway controlled unit for generating a side switching voltage. The output driver is connected in series with the transition controlled circuit and receives the side switching voltage so as to accordingly generate the output bus signal. Each of the first and second pathway controlled unit comprises a plurality of switches and can be activated depending on an input signal. By controlling the switches of the first or second pathway controlled unit to be sequentially turned on and off successively, the side switching voltage is characterized by a smooth phase transition, low common mode noise and better EMI performances.

IPC Classes  ?

• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• H03K 5/13 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• H04L 12/40 - Bus networks
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

A silicon controlled rectifier includes a P-type substrate, an N-type doped well, a first P-type strip-shaped heavily-doped area arranged in the N-type doped well, a first N-type strip-shaped heavily-doped area arranged in the P-type substrate, and at least one N-type heavily-doped area arranged in the P-type substrate and the N-type doped well. The at least one N-type heavily-doped area is not arranged between the first P-type strip-shaped heavily-doped area and the first N-type strip-shaped heavily-doped area, thus the surface area of a semiconductor substrate can be reduced. The conductivity types of the abovementioned components are alternatively changed.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

A digital isolator module for high level common mode transient immunity is provided, comprising a transmitter circuit (TX), a receiver circuit (RX) and an isolation barrier which is connected there in between, wherein the transmitter circuit is electrically connected to a first ground voltage level and the receiver circuit is electrically connected to a second ground voltage level. The receiver circuit further comprises a resistance set, a high speed detector and a demodulator. By employing the proposed circuit diagram of the invention, interferences occurring at the common mode are suppressed and an RX output signal is synchronized with its input signal without having propagation delay.

IPC Classes  ?

• H04B 1/40 - Circuits
• H04B 15/02 - Reducing interference from electric apparatus by means located at or near the interfering apparatus

Abstract

A transient voltage suppressor is provided, comprising a heavily doped substrate connected to a first node, a first doped layer formed on the heavily doped substrate, a second doped layer formed on the first doped layer, a first heavily doped region and a second heavily doped region formed in the second doped layer and coupled to a second node, and a plurality of trenches arranged in the heavily doped substrate, having a depth not less than that of the first doped layer for electrical isolation. The heavily doped substrate, the second doped layer, and the second heavily doped region belong to a first conductivity type. The first doped layer and the first heavily doped region belong to a second conductivity type. By employing the proposed present invention, pn junctions of the transient voltage suppressor can be controlled beneath the surface, thereby reducing the junction capacitance effectively.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

A multi-channel transient voltage suppressor with ultra-low capacitance is provided, which comprises a plurality of diode strings coupled between an ESD bus line and ground, having each diode string coupled to an I/O pin; a power clamp circuit coupled to the ESD bus line; and a first diode having an anode coupled to the power clamp circuit and a cathode coupled to ground. A second diode may be alternatively disposed between the first diode and the diode strings, having an anode coupled to the ground and a cathode coupled to a common anode of the diode strings. By employing the proposed present invention, it is advantageous of reaching an ultra-low capacitance and meanwhile still maintaining a lower layout area of the circuit structure.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

Abstract

A transient voltage suppression device includes a lightly-doped semiconductor structure, a first doped well, a first heavily-doped area, a first buried area, and a second heavily-doped area. The lightly-doped semiconductor structure has a first conductivity type. The first doped well has a second conductivity type and is formed in the lightly-doped semiconductor structure. The first heavily-doped area has the second conductivity type and is formed in the first doped well. The first buried area has the first conductivity type and is formed in the lightly-doped semiconductor structure and under the first doped well, and the first buried area is adjacent to the first doped well. The second heavily-doped area has the second conductivity type and is formed in the lightly-doped semiconductor structure.

IPC Classes  ?

• H01L 27/082 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
• H01L 27/102 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
• H01L 29/70 - Bipolar devices
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/735 - Lateral transistors
• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

Abstract

A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Abstract

A vertical transient voltage suppression device includes a semiconductor substrate having a first conductivity type, a first doped well having a second conductivity type, a first heavily-doped area having the first conductivity type, a second heavily-doped area having the first conductivity type, and a diode. The first doped well is arranged in the semiconductor substrate and spaced from the bottom of the semiconductor substrate, and the first doped well is floating. The first heavily-doped area is arranged in the first doped well. The second heavily-doped area is arranged in the semiconductor substrate. The diode is arranged in the semiconductor substrate and electrically connected to the second heavily-doped area through a conductive trace.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/861 - Diodes

Abstract

A lateral transient voltage suppressor device is provided, comprising a doped substrate, a lateral clamping structure disposed on the doped substrate, a buried doped layer disposed between the doped substrate and the lateral clamping structure for isolation, at least one diode module, and at least one trench arranged in the doped substrate, having a depth not less than that of the buried doped layer, and being disposed between the lateral clamping structure and the at least one diode module for electrical isolation. The doped substrate and the buried doped layer have opposite conductivity types such that the doped substrate is electrically floating. The buried doped layer can be further disposed to separate the diode module from the doped substrate. By employing the proposed invention, the lateral transient voltage suppressor device is advantageous of maintaining both a lower clamping voltage as well as a reduced dynamic resistance.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/861 - Diodes

Abstract

A transient voltage suppression device with improved electrostatic discharge (ESD) robustness includes a semiconductor substrate having a first conductivity type, a first doped well having a second conductivity type, a first heavily-doped area having the first conductivity type, a second doped well having the second conductivity type, a second heavily-doped area having the first conductivity type, and a first current blocking structure. The first doped well is arranged in the semiconductor substrate. The first heavily-doped area is arranged in the first doped well. The second doped well is arranged in the semiconductor substrate. The second heavily-doped area is arranged in the second doped well. The first current blocking structure is arranged in the semiconductor substrate, spaced from the bottom of the semiconductor substrate, and arranged between the first doped well and the second doped well.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 27/082 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
• H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
• H01L 21/761 - PN junctions
• H01L 21/762 - Dielectric regions

Abstract

An active surge protection structure is provided between a power line and a core circuit, comprising a surge-to-digital converter and a clamp circuit. The surge-to-digital converter comprises a plurality of surge detection circuit. Each surge detection circuit detects a surge event occurring on the power line and generates a digital signal. The clamp circuit is disposed adjacent to the core circuit and electrically connected with the surge-to-digital converter and the power line where the core circuit is connected for dissipating surge energy. The clamp circuit receives and is driven by the digital signals from the surge-to-digital converter such that its protection flexibility can be achieved according to the digital signals. By employing the present invention, it is extraordinarily advantageous of improving system stability and achieving comprehensive surge protection with configuration of driving capability dependent on surge levels.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H02H 1/00 - Details of emergency protective circuit arrangements

Abstract

An on-chip multiple-stage electrical overstress (EOS) protection device is disclosed. The protection device includes a surge protector having a first clamping voltage and a first electrostatic discharge (ESD) protector having a second clamping voltage lower than the first clamping voltage. The surge protector is electrically connected to the first ESD protector in parallel. The surge protector and the first ESD protector are electrically connected between a receiving terminal and a voltage terminal, and the receiving terminal is electrically connected to an internal circuit. When an electrical overstress (EOS) signal including an electrostatic discharge (ESD) signal and a surge signal appears at the receiving terminal, the first ESD protector and the surge protector are triggered on in turn to clamp a voltage received by the internal circuit.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
• H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 49/02 - Thin-film or thick-film devices

Abstract

A bidirectional silicon-controlled rectifier includes a lightly-doped semiconductor structure, a first lightly-doped region, a second lightly-doped region, a first doped well, a second doped well, a first heavily-doped area, a second heavily-doped area, a third heavily-doped area, a fourth heavily-doped area. The lightly-doped semiconductor structure, the first heavily-doped area, and the third heavily-doped area have a first conductivity type. The first lightly-doped region, the second lightly-doped region, the first doped well, the second doped well, the fourth heavily-doped area, and the second heavily-doped area have a second conductivity type. A first part of the first lightly-doped region is arranged under the first doped well. A second part of the second lightly-doped region is arranged under the second doped well.

IPC Classes  ?

• H01L 29/747 - Bidirectional devices, e.g. triacs
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

An improved transient voltage suppression device includes a semiconductor substrate, a transient voltage suppressor, at least one first diode, at least one conductive pad, and at least one second diode. The transient voltage suppressor has an N-type heavily-doped clamping area. The first anode of the first diode is electrically connected to the N-type heavily-doped clamping area. The conductive pad is electrically connected to the first cathode of the first diode. The second anode of the second diode is electrically connected to the conductive pad and the second cathode of the second diode is electrically connected to the transient voltage suppressor. The first anode is closer to the N-type heavily-doped clamping area rather than the conductive pad. The conductive pad is closer to the N-type heavily-doped clamping area rather than the second anode.

IPC Classes  ?

• H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
• H01L 31/111 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by at least three potential barriers, e.g. photothyristor
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 23/528 - Layout of the interconnection structure
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 29/861 - Diodes
• H01L 29/735 - Lateral transistors

Abstract

A heat-dissipating Zener diode includes a heavily-doped semiconductor substrate having a first conductivity type, a first epitaxial layer having the first conductivity type, a first heavily-doped area having a second conductivity type, a second epitaxial layer, and a second heavily-doped area having the second conductivity type or the first conductivity type. The first epitaxial layer is formed on the heavily-doped semiconductor substrate. The first heavily-doped area is formed in the first epitaxial layer and spaced from the heavily-doped semiconductor substrate. The second epitaxial layer is formed on the first epitaxial layer and penetrated with a first doped area, and the first doped area has the second conductivity type and contacts the first heavily-doped area. The second heavily-doped area is formed in the first doped area.

IPC Classes  ?

• H01L 29/866 - Zener diodes
• H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/66 - Types of semiconductor device

Abstract

A self-balanced diode device includes a substrate, a doped well, at least one first conductivity type heavily doped fin and at least two second conductivity type heavily doped fins. The doped well is arranged in the substrate. The first conductivity type heavily doped fin is arranged in the doped well, arranged in a line along a first direction, and protruded up from a surface of the substrate. The second conductivity type heavily doped fins is arranged in the doped well, arranged in a line along a second direction intersecting the first direction, respectively arranged at two opposite sides of the first conductivity type heavily doped fin, and protruded up from the surface of the substrate. Each second conductivity type heavily doped fin and the first conductivity type heavily doped fin are spaced at a fixed interval.

IPC Classes  ?

• H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
• H01L 29/861 - Diodes
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Abstract

A self-balanced diode device includes a substrate, a doped well, at least one first conductivity type heavily doped fin and at least two second conductivity type heavily doped fins. The doped well is arranged in the substrate. The first conductivity type heavily doped fin is arranged in the doped well, arranged in a line along a first direction, and protruded up from a surface of the substrate. The second conductivity type heavily doped fins is arranged in the doped well, arranged in a line along a second direction intersecting the first direction, respectively arranged at two opposite sides of the first conductivity type heavily doped fin, and protruded up from the surface of the substrate. Each second conductivity type heavily doped fin and the first conductivity type heavily doped fin are spaced at a fixed interval.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/861 - Diodes

Abstract

A self-balanced silicon-controlled rectification device includes a substrate, an N-type doped well, a P-type doped well, at least one heavily doped clamping fin, at least one first P-type heavily doped fin, and at least one first N-type heavily doped fin. The N-type doped well and the P-type doped well are arranged in the substrate. The heavily doped clamping fin is arranged in the N-type doped well and the P-type well and protruded up from a surface of the substrate. The first P-type heavily doped fin and the first N-type heavily doped fin are respectively arranged in the N-type doped well and the P-type doped well, and protruded up from the surface of the substrate. The abovementioned elements forms silicon-controlled rectifiers (SCRs) are forward biased to generate uniform electrostatic discharge (ESD) currents through the SCRs.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 23/528 - Layout of the interconnection structure

Abstract

A bipolar transistor device includes a substrate and at least one first transistor unit. The first transistor unit includes a first doped well of first conductivity type, at least one first fin-based structure and at least one second fin-based structure. The first fin-based structure includes a first gate strip and first doped fins arranged in the first doped well, and the first gate strip is floating. The second fin-based structure includes a second gate strip and second doped fins arranged in the first doped well, and the second gate strip is floating. The first doped fins, the second doped fins and the first doped well form first BJTs, and the first doped fins and the second doped fins are respectively coupled to high and low voltage terminals.

IPC Classes  ?

• H01L 27/102 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/732 - Vertical transistors
• H01L 27/082 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
• H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities

Abstract

A self-feedback control circuit is connected to a controller area network bus for controlling a high-level output and a low-level output, comprising a controller area network driving circuit and a replica circuit. The replica circuit is connected in parallel with the controller area network driving circuit and comprises an upper feedback path and a lower feedback path. The upper feedback path and the lower feedback path are connected jointly to a common mode, and the replica circuit provides a feedback signal from the common mode such that the feedback signal is able to be respectively transmitted to two individual transistors of the controller area network driving circuit through the upper feedback path and through the lower feedback path so as to control DC level stability of the high-level output and the low-level output.

IPC Classes  ?

• H03L 5/00 - Automatic control of voltage, current, or power
• H03K 5/003 - Changing the DC level
• G06F 13/40 - Bus structure
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only

Abstract

A slope control circuit is connected between a replica circuit and a controller area network bus. The replica circuit generates an upper and a lower feedback signal. The slope control circuit receives and is driven by the feedback signals for controlling a voltage slope of a high-level output and a low-level output. The slope control circuit comprises an upper and a lower driving circuit, individually connected between the replica circuit, the high-level output and the low-level output. The upper driving circuit and the lower driving circuit respectively include at least one charging and discharging circuit. By controlling the charging and discharging circuit, the present invention controls decreasing voltage slope of the high-level output to be symmetric to increasing voltage slope of the low-level output, and delay time of the circuit switching between different operating modes to be equivalent.

IPC Classes  ?

• H03K 5/01 - Shaping pulses
• H03K 3/353 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback

Abstract

A receiving circuit with an ultra-wide common-mode input voltage range applies to a controller area network (CAN) and comprises a resistor assembly electrically connected with a CANH and a CANL, a reference amplifier, a first input amplifier assembly, a second input amplifier assembly, and an analog adder. The receiving circuit receives voltages from the CANH and CANL. The resistor assembly bucks voltage, respectively generating CANH and CANL voltage divisions at first and second nodes and outputting the voltage divisions to the first and second input amplifier assemblies. The first and second input amplifier assemblies amplify the differential signal between the first and second nodes and convert the differential signal into single-end signals. The analog adder adds the single-end signals as the output signal. The receiving circuit can receive the signal ranging between the maximum and minimum common-mode voltages and reduce electromagnetic emission.

IPC Classes  ?

• H04B 3/02 - Line transmission systems Details
• H03K 19/0175 - Coupling arrangementsInterface arrangements
• H04L 7/00 - Arrangements for synchronising receiver with transmitter
• H04Q 1/54 - Amplifier switched-on automatically in dependence on automatically selected lines

Abstract

In a test method for eliminating electrostatic charges, at least one test process is firstly performed by a test equipment comprising a tester and a platform, and electrostatic charges are generated on the test equipment in the test process. In the test process, the tester contacts and tests at least one tested integrated circuit (IC) on a test area of the platform, and then the tested IC is removed from the tester and the test area. Next, a conduction device which is grounded is moved to the test area, so that the tester contacts the conduction device to discharge the electrostatic charges to ground. Next, the conduction device is removed from the tester and the test area. Finally, the method returns to the test process to test the next tested IC.

IPC Classes  ?

• G01R 31/20 - Preparation of articles or specimens to facilitate testing
• H01L 23/495 - Lead-frames
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

Abstract

The present invention discloses a splicing type electret loudspeaker. The splicing type electret loudspeaker may comprise a plurality of electret loudspeaker units. Each electret loudspeaker unit may comprise a plurality of connection ports, and these connection ports may be disposed around the edge of each electret loudspeaker unit. In particular, the connection ports of each electret loudspeaker unit can respectively connect to one of the connection ports of another electret loudspeaker unit; in this way, these electret loudspeaker units can connect to each other in parallel, such that the power input signal and the audio input signal can be transmitted to all electret loudspeaker units to drive them.

IPC Classes  ?

• H04R 25/00 - Deaf-aid sets
• H04R 19/01 - Electrostatic transducers characterised by the use of electrets

Abstract

A silicon-controlled rectification device with high efficiency is disclosed, which comprises a P-type region surrounding an N-type region. A first P-type heavily doped area is arranged in the N-type region and connected with a high-voltage terminal. A plurality of second N-type heavily doped areas is arranged in the N-type region. A plurality of second P-type heavily doped areas is closer to the second N-type heavily doped areas than the first N-type heavily doped area and arranged in the P-type region. At least one third N-type heavily doped area is arranged in the P-type region and connected with a low-voltage terminal. Alternatively or in combination, the second N-type heavily doped areas and the second P-type heavily doped areas are respectively arranged in the P-type region and the N-type region.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/747 - Bidirectional devices, e.g. triacs
• H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
• H01L 29/861 - Diodes
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A three-dimension (3D) integrated circuit (IC) package is disclosed. The 3D IC package has a package substrate having a surface. At least one integrated circuit (IC) chip with or without suppressing a transient voltage and at least one transient voltage suppressor (TVS) chip are arranged on the surface of the substrate and electrically connected with each other. The IC chip is independent from the TVS chip. The IC chip and the TVS chip stacked on each other are arranged on the package substrate. Alternatively, the IC chip and the TVS chip are together arranged on an interposer formed on the package substrate.

IPC Classes  ?

• H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
• H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

The present invention discloses a serial transmission driving method, wherein a serial transmission driving device (STD) is connected with a first terminal (FT) and a second terminal (ST) of an equivalent load capacitor through a first differential bus (FDB) and a second differential bus (SDB). FDB and SDB are respectively connected with a high-potential terminal (HPT) and a low-potential terminal (LPT) through a first equivalent resistor and a second equivalent resistor. STD receives a trigger signal (TS) appearing during the transition between a turn-on signal (Ton) and a turn-off signal (Toff), generates a first potential (FP) and a second potential (SP) greater than FP according to TS, and respectively applies FP and SP to SDB and FDB. FP and SP fast change the potential of FT to be greater than that of ST. HPT and LPT maintain potentials of FDB and SDB until Toff ends.

IPC Classes  ?

• H03K 19/0175 - Coupling arrangementsInterface arrangements
• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
• H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
• H04L 5/16 - Half-duplex systemsSimplex/duplex switchingTransmission of break signals
• H03K 19/003 - Modifications for increasing the reliability
• H03K 19/01 - Modifications for accelerating switching

Abstract

A low-cost ESD protection device for high-voltage open-drain pad is disclosed, which has a first high-voltage (HV) NMOSFET coupled to a high-voltage (HV) open drain pad, a ground pad, a HV block unit and an ESD clamp unit and a low-voltage (LV) bias unit coupled to the first HV NMOSFET, a low-voltage (LV) trigger, the ESD clamp unit and the ground pad. The LV trigger is coupled to the HV block unit. The HV block unit blocks a high voltage from the HV open drain pad diode during normal operation and generates a trigger signal to the LV trigger when an ESD event is applied to the HV open drain pad. Then, the LV trigger turns on the ESD clamp unit to discharge an ESD current and switches the LV bias unit to turn off the first HV NMOSFET.

IPC Classes  ?

• H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
• H02H 3/02 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection Details
• H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage
• H02H 1/04 - Arrangements for preventing response to transient abnormal conditions, e.g. to lightning
• H02H 3/22 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage of short duration, e.g. lightning
• H02H 9/06 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage using spark-gap arresters

Abstract

A silicon-controlled rectification device with high efficiency is disclosed, which comprises a P-type region surrounding an N-type region. A first P-type heavily doped area is arranged in the N-type region and connected with a high-voltage terminal. A plurality of second N-type heavily doped areas is arranged in the N-type region. A plurality of second P-type heavily doped areas is closer to the second N-type heavily doped areas than the first N-type heavily doped area and arranged in the P-type region. At least one third N-type heavily doped area is arranged in the P-type region and connected with a low-voltage terminal. Alternatively or in combination, the second N-type heavily doped areas and the second P-type heavily doped areas are respectively arranged in the P-type region and the N-type region.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
• H01L 29/861 - Diodes

Abstract

A high voltage open-drain electrostatic discharge (ESD) protection device is disclosed, which comprises a high-voltage n-channel metal oxide semiconductor field effect transistor (HV NMOSFET) coupled to a high-voltage pad and a low-voltage terminal and receiving a high voltage on the high-voltage pad to operate in normal operation. The high-voltage pad and the HV NMOSFET are further coupled to a high-voltage ESD unit blocking the high voltage, and receiving a positive ESD voltage on the high-voltage pad to bypass an ESD current when an ESD event is applied to the high-voltage pad. The high-voltage ESD unit and the low-voltage terminal are coupled to a power clamp unit, which receives the positive ESD voltage via the high-voltage ESD unit to bypass the ESD current.

IPC Classes  ?

• H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

Abstract

The present invention discloses a flat speaker output device and a method for starting the same. Wherein, a plurality of flat speakers utilizes an initial delay unit and a plurality of intermediary delay units connected in series. The initial delay unit connects with the power controller and a first one of the flat speakers. The intermediary delay units respectively connect with the residual each flat speakers. The power controller controls a power source to the initial delay unit to delay the start of the first one of flat speakers, and outputs the power source to the intermediary delay units to sequentially delay the starts time of the residual each flat speaker. The present invention can sequentially start flat speakers without using a high-output power supply device and thus decrease the required capacity of the external power supply device.

IPC Classes  ?

• H04R 3/00 - Circuits for transducers
• H04R 29/00 - Monitoring arrangementsTesting arrangements

Abstract

A method for fabricating a semiconductor-based planar micro-tube discharger structure is provided, including the steps of forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap, forming an insulating layer over the patterned electrodes and the separating block, and filling the insulating layer into the gap. At least two discharge paths are formed. The method can fabricate a plurality of discharge paths in a semiconductor structure, the structure having very high reliability and reusability.

IPC Classes  ?

• H01J 1/88 - Mounting, supporting, spacing, or insulating of electrodes or of electrode assemblies
• H01J 19/42 - Mounting, supporting, spacing, or insulating of electrodes or of electrode assemblies
• H01K 1/18 - Mountings or supports for the incandescent body
• H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
• H01H 47/00 - Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
• H05F 3/00 - Carrying-off electrostatic charges
• H01J 9/02 - Manufacture of electrodes or electrode systems
• H01J 17/06 - Cathodes

Abstract

A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation.

IPC Classes  ?

• H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection

Abstract

The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.

IPC Classes  ?

• H01J 1/88 - Mounting, supporting, spacing, or insulating of electrodes or of electrode assemblies
• H01J 19/42 - Mounting, supporting, spacing, or insulating of electrodes or of electrode assemblies
• H01J 1/00 - Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
• H01J 1/18 - SupportsVibration-damping arrangements

Abstract

A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.

IPC Classes  ?

• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/866 - Zener diodes
• H01L 29/861 - Diodes

Abstract

An electrostatic discharge protection device structure is disclosed, which comprises a semiconductor substrate and an N-type epitaxial layer arranged on the semiconductor substrate. At least one snapback cascade structure is arranged in the N-type epitaxial layer, wherein the snapback cascade structure further comprises first and second P-type wells arranged in the N-type epitaxial layer. First and second heavily doped areas arranged in the first P-type well respectively belong to opposite types. And, third and fourth heavily doped areas arranged in the second P-type well respectively belong to opposite types, wherein the second and third heavily doped areas respectively belong to opposite types and are electrically connected with each other. When the first heavily doped area receives an ESD signal, an ESD current flows from the first heavily doped area to the fourth heavily doped area through the first P-type well, the N-type epitaxial layer, and the second P-type well.

IPC Classes  ?

• H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

Abstract

A low capacitance transient voltage suppressor is disclosed. The suppressor comprises an N-type heavily doped substrate and an epitaxial layer formed on the substrate. At least one steering diode structure formed in the epitaxial layer comprises a diode lightly doped well and a first P-type lightly doped well, wherein a P-type heavily doped area is formed in the diode lightly doped well and a first N-type heavily doped area and a second P-type heavily doped area are formed in the first P-type lightly doped well. A second P-type lightly doped well having two N-type heavily doped areas is formed in the epitaxial layer. In addition, an N-type heavily doped well and at least one deep isolation trench are formed in the epitaxial layer, wherein the trench has a depth greater than or equal to depths of all the doped wells, so as to separate at least one doped well.

IPC Classes  ?

• H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts
• H01L 21/336 - Field-effect transistors with an insulated gate

Abstract

The present invention relates a transient voltage suppressor (TVS) for directional ESD protection. The TVS includes: a conductivity type substrate; a first type lightly doped region, having a first type heavily doped region arranged therein; a second type lightly doped region, having a second type heavily doped region and a third type heavily doped region arranged therein; a third type lightly doped region, having a fourth type heavily doped region arranged therein; a plurality of closed isolation trenches, arranged on the conductivity type substrate, wherein at least one of the plurality of closed isolation trenches is neighbored one of the type lightly doped regions; and a first pin. Accordingly, the TVS of present invention may adaptively provide effective ESD protection under positive and negative ESD stresses, improve the efficiency of ESD protection within the limited layout area.

IPC Classes  ?

• H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts

Abstract

The present invention relates a transient voltage suppressor (TVS) for directional ESD protection. The TVS includes: a conductivity type substrate; a first type lightly doped region, having a first type heavily doped region arranged therein; a second type lightly doped region, having a second type heavily doped region and a third type heavily doped region arranged therein; a third type lightly doped region, having a fourth type heavily doped region arranged therein; a plurality of closed isolation trenches, arranged on the conductivity type substrate, wherein at least one of the plurality of closed isolation trenches is neighbored one of the type lightly doped regions; and a first pin. Accordingly, the TVS of present invention may adaptively provide effective ESD protection under positive and negative ESD stresses, improve the efficiency of ESD protection within the limited layout area.

IPC Classes  ?

• H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts

Abstract

A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

+ substrate and the N well, to bypass a negative ESD stress on the bond pad.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device

Abstract

A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first conductivity type substrate and at least one diode cascade structure arranged in the first conductivity type substrate. The cascade structure further comprises at least one second conductivity type lightly doped well and at least one first conductivity type lightly doped well, wherein there are two heavily doped areas arranged in the second conductivity type lightly doped well and the first conductivity type lightly doped well. The cascade structure neighbors a second conductivity type well, wherein there are three heavily doped areas arranged in the second conductivity type well. The suppressor further comprises a plurality of deep isolation trenches arranged in the first conductivity type substrate and having a depth greater than depths of the second conductivity type lightly doped well, the second conductivity type well and the first conductivity type lightly doped well. Each doped well is isolated by trenches.

IPC Classes  ?

• H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts

Abstract

A lateral transient voltage suppressor for low-voltage applications. The suppressor includes an N-type heavily doped substrate and at least two clamp diode structures horizontally arranged in the N-type heavily doped substrate. Each clamp diode structure further includes a clamp well arranged in the N-type heavily doped substrate and having a first heavily doped area and a second heavily doped area. The first and second heavily doped areas respectively belong to opposite conductivity types. There is a plurality of deep isolation trenches arranged in the N-type heavily doped substrate and having a depth greater than depth of the clamp well. The deep isolation trenches can separate each clamp well. The present invention avoids the huge leakage current to be suitable for low-voltage application.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

A package structure and an electronic apparatus of the package structure are disclosed. The package structure includes a substrate and a plurality of pins. The plurality of pins is disposed on the substrate. The plurality of pins is interlaced to each other, so that a line along a specific direction will only pass one of the plurality of pins at most.

IPC Classes  ?

• H01R 9/00 - Structural associations of a plurality of mutually-insulated electrical connecting elements, e.g. terminal strips or terminal blocksTerminals or binding posts mounted upon a base or in a caseBases therefor

Abstract

The invention discloses a transient voltage detection circuit suitable for an electronic system. The electronic system includes a high voltage line and a low voltage line. The transient voltage detection circuit includes at least one detection circuit and a judge module. Each detection circuit includes a P-typed transistor and/or an N-typed transistor, a capacitor and a detection node. The transistor is coupled with the capacitor, and the detection node is located between the transistor and the capacitor. The judge module is coupled to each of the detection nodes. The judge module generates a judgment according to voltage levels of the detection nodes. Accordingly, the transient voltage detection circuit is formed. The electronic system may selectively execute a protective action according to the judgment.

IPC Classes  ?

• H02H 3/22 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage of short duration, e.g. lightning

Abstract

A bidirectional transient voltage suppression device is disclosed. The bi-directional transient voltage suppression device comprises a semiconductor die. The semiconductor die has a multi-layer structure comprising a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type, an epitaxial layer, and five diffused regions. The buried layer and the semiconductor substrate form a first semiconductor junction. The first diffused region of the second conductivity type and the semiconductor substrate form a second semiconductor junction. The fourth diffused region of the first conductivity type and the third diffused region of the second conductivity type form a third semiconductor junction. The fifth diffused region of the first conductivity type and the second diffused region of the second conductivity type form a fourth semiconductor junction.

IPC Classes  ?

• H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material

Abstract

An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.

IPC Classes  ?

• H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection

Abstract

A class D amplifier including a PWM circuit, a buffer amplifying circuit, a low-pass filter, and two current sources is provided. The PWM circuit transfers an analog signal into a PWM signal. The buffer amplifying circuit amplifies the PWM signal and generates an amplified signal. The low-pass filter will filter high frequency components out from the amplified signal and then transmit the filtered signal to a loading of the class D amplifier. The two current sources provide currents flowing into and out from a feedback node in the PWM circuit, respectively. The charging and discharging provided by the two current sources can generate a triangular signal for the PWM circuit.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers

Abstract

An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the negative power line and an input terminal of the triggering unit. The MOS capacitor is coupled between the positive power line and an input terminal of the triggering unit for ESD protection. During a normal power operation, a switching terminal of the triggering unit enables the MOS capacitor to be coupled between the negative power line and an input terminal of the triggering unit. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

Abstract

An ESD protection circuit for a differential I/O pair is provided. The circuit includes an ESD detection circuit, a discharge device, and four diodes. The first diode is coupled between the first I/O pin and the discharge device in a forward direction toward the discharge device. The second diode is coupled between the second I/O pin and the discharge device in a forward direction toward the second I/O pin. The third diode is coupled between the discharge device and the positive power line in a forward direction toward the positive power line. The fourth diode is coupled between the discharge device and the negative power line in a forward direction toward the discharge device. Via an output end, the ESD detection circuit triggers the discharge device during ESD events.

IPC Classes  ?

• H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
• H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage
• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

Abstract

An ESD detection circuit for detecting a level of an ESD voltage on a power rail is provided. The ESD detection circuit includes a resistive component, a diode unit, and a controller. The resistive component is coupled between a detection node and a ground node corresponding to the power rail. The diode unit is coupled between the power rail and the detection node in a forward direction toward the power rail. The controller, coupled to the detection node, is used for determining the level of the ESD voltage based on the voltage of the detection node and the breakdown voltage of the diode unit.

IPC Classes  ?

• G01R 31/02 - Testing of electric apparatus, lines, or components for short-circuits, discontinuities, leakage, or incorrect line connection
• G01R 31/26 - Testing of individual semiconductor devices

Abstract

The present invention discloses a bidirectional PNPN silicon-controlled rectifier comprising: a p-type substrate; a N-type epitaxial layer; a P-type well and two N-type wells all formed inside the N-type epitaxial layer with the two N-type wells respectively arranged at two sides of the P-type well; a first semiconductor area, a second semiconductor area and a third semiconductor area all formed inside the P-type well and all coupled to an anode, wherein the second semiconductor area and the third semiconductor area are respectively arranged at two sides of the first semiconductor area, and wherein the first semiconductor area is of first conduction type, and the second semiconductor area and the third semiconductor area are of second conduction type; and two P-type doped areas respectively formed inside the N-type wells, wherein each P-type doped area has a fourth semiconductor area neighboring the P-type well and a fifth semiconductor area, and wherein both the fourth semiconductor area and the fifth semiconductor area are coupled to a cathode, and wherein the fourth semiconductor area is of second conduction type, and the fifth semiconductor area is of first conduction type.

IPC Classes  ?

• H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action

Abstract

The present invention proposed a slew-rate control circuitry without the use of external components such as amplifiers. Therefore slew-rate control circuitry of the present invention not only provides an IC with build-in slew-rate control, but also reduces number of transistors used externally which will increase gate-oxide reliability of the IC. The slew-rate control circuitry of the present invention is primarily comprised by an output buffer and feedback circuitry, the output buffer mainly consisted four transistors and depends on output of the IC, these four transistors will interact with each other to control the slew-rate of IC output. Additional feedback circuitry and gate-tracking circuitry are also disclosed to enhance the performance of the slew-rate control circuitry.

IPC Classes  ?

• H03K 3/00 - Circuits for generating electric pulsesMonostable, bistable or multistable circuits

Abstract

An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the positive power line and an input terminal of the triggering unit. The MOS capacitor has a first end and a second end. The first end is coupled to the input terminal of the triggering unit. During a normal power operation, a switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the positive power line. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

Abstract

An ESD protection circuit suitable for applying in an integrated circuit with separated power domains is provided. The circuit includes a P-type MOSFET coupled between a first circuit in a first power domain and a second circuit in a second power domain. A source terminal of the P-type MOSFET is coupled to a connection node for connecting the first circuit and the second circuit. A gate terminal of the P-type MOSFET is coupled to a positive power line of the second power domain. A drain terminal of the P-type MOSFET is coupled to a negative power line of the second power domain. A body terminal of the P-type MOSFET is also coupled to the connection node.

IPC Classes  ?

• H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection

Abstract

The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial layer; a first buried layer formed in a junction between the first well and the substrate; a second buried layer formed in a junction between the second well and the substrate; a first and a second semiconductor area with opposite conduction type both formed inside the first well; a third and a fourth semiconductor area with opposite conduction type both formed inside the second well, wherein the first and second semiconductor areas are connected to the anode of the silicon-controlled rectifier, and the third and fourth semiconductor areas are connected to the cathode of the silicon-controlled rectifier.

IPC Classes  ?

• H01L 29/747 - Bidirectional devices, e.g. triacs

Abstract

The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device

Abstract

A charge pump circuit with bipolar output comprises a first set of switch device capable of selectively connecting two terminals of a first transfer capacitor to a voltage source and a ground terminal, respectively, a second set of switch device capable of selectively connecting the two terminals of the first transfer capacitor to a grounded first storage capacitor and the voltage source, respectively, a third set of switch device capable of selectively connecting two terminals of a second transfer capacitor to the first transfer capacitor connected to the voltage source and the ground terminal, respectively, and a fourth set of switch device capable of selectively connecting the two terminals of the second transfer capacitor to a grounded second storage capacitor and the ground terminal, respectively. These four sets of switch devices totally have nine switches, and are collocated with clock signals to be selectively driven by a four-phase signal or a two-phase signal so as to produce bipolar voltages with magnitudes higher than the input voltage and also accomplish the highest conversion efficiency.

IPC Classes  ?

• G05F 1/10 - Regulating voltage or current

Abstract

An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.

IPC Classes  ?

• H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection

Abstract

A high/low voltage tolerant interface circuit and a crystal oscillator circuit using the same are provided herein. The interface circuit includes a first transistor, a bulk-voltage generator module and an bias module. The first transistor includes a gate, a first source/drain, a bulk coupled to the first source/drain of the first transistor and a second source/drain coupled to an input node. The bulk-voltage generator module is, used to determine whether a first voltage or a predetermined voltage is being provided to the bulk of the first transistor according to the voltage of the input node. The bias module is coupled to the gate of the first transistor. The bias module is used to provide an bias voltage to the gate of the first transistor and makes the first transistor conduct in order to control the voltage of the second source/drain voltage of the first transistor.

IPC Classes  ?

• H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device

Abstract

An electrostatic discharge (ESD) protection device and a layout thereof are provided. A bias conducting wire is mainly used to couple each base of a plurality of parasitic transistors inside ESD elements together, in order to simultaneously trigger all the parasitic transistors to bypass the ESD current, avoid the elements of a core circuit being damaged, and solve the non-uniform problem of bypassing the ESD current when ESD occurs. Furthermore, in the ESD protection layout, it only needs to add another doped region on a substrate neighboring to, but not contacting, doped regions of the ESD protection elements and use contacts to connect the added doped region, so as to couple each base of the parasitic transistors together without requiring for additional layout area.

IPC Classes  ?

• H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts