Abstract

A method for manufacturing a non-volatile memory device, comprising: providing a substrate; forming a select gate on the substrate; forming a conformal conductive layer on the substrate and the select gate; forming a control gate covering a sidewall of the select gate and the conformal conductive layer, wherein the control gate comprises a non-vertical surface; etching the conformal conductive layer exposed from the control gate to thereby form a floating gate, the floating gate comprising: a vertical portion disposed between the select gate and the control gate; and a horizontal portion disposed between the substrate and the control gate, wherein the horizontal portion comprises a lateral tip; and forming an erase gate covering the non-vertical surface of the control gate and the lateral tip of the horizontal portion of the floating gate.

IPC Classes  ?

• H10D 30/68 - Floating-gate IGFETs
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H10D 30/01 - Manufacture or treatment
• H10D 64/01 - Manufacture or treatment

Abstract

A non-volatile memory device includes multiple memory cell, and the memory cell includes an assist gate structure, a tunneling dielectric layer, a floating gate, an upper gate and a middle structure. The floating gate is disposed on the tunneling dielectric layer and includes two first top edges opposite each other, two first sidewalls connected to the two top edges respectively, two second sidewalls arranged along a second direction. An upper gate structure covers the assist gate structure and the floating gate, where at least one of the two first top edges of the floating gate is embedded in the upper gate structure. A middle structure covers one of the two first sidewalls of the floating gate and opposite the assist gate structure. The floating gate is disposed between the middle structure and the assist gate structure, and the middle structure is an insulating structure or a control gate structure.

IPC Classes  ?

• H10D 30/68 - Floating-gate IGFETs
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H10D 30/01 - Manufacture or treatment
• H10D 64/01 - Manufacture or treatment

Abstract

A method of manufacturing a non-volatile memory device includes steps of forming an assist gate on the substrate, the assist gate including two sidewalls opposite to each other, forming a patterned conductive layer on the substrate, the patterned conductive layer covering at least one of the two sidewalls of the assist gate, forming a spacer on a top surface of the patterned conductive layer, where a portion of the top surface of the patterned conductive layer is covered by the spacer, etching the patterned conductive layer using the spacer as an etch mask to form a floating gate, the floating gate including two first top edges opposite to each other, and forming an upper gate covering the assist gate and the floating gate, where at least one of the two first top edges of the floating gate is embedded in the upper gate.

IPC Classes  ?

• H10D 30/68 - Floating-gate IGFETs
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H10D 30/01 - Manufacture or treatment
• H10D 64/01 - Manufacture or treatment

Abstract

A method for manufacturing a non-volatile memory device includes: forming two stack structures on a substrate, and a gap is formed between the stack structures; forming a floating gate layer covering the two stack structures and filled into the gap, wherein the floating gate layer includes a recess region; filling a first mask layer into the recess region; removing portions of the first mask layer to form a first mask in the recess region; removing portions of the floating gate layer to leave the floating gate layer in the gap, where top surface of the floating gate layer in the gap is laterally separated from the first mask; converting the top surface of the floating gate layer into second masks under the coverage of the first mask; removing the first mask in the recess region; and etching the floating gate layer using the second masks as an etch mask.

IPC Classes  ?

• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Abstract

A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, a trench, an erase gate, a control gate, and a floating gate. The trench is disposed in the substrate. The erase gate is disposed in the trench and includes a concave corner. The control gate is disposed on the substrate, and a bottom surface of the control gate is higher than a bottom surface of the erase gate. The floating gate is disposed on the substrate, and the floating gate includes a lower tip pointing toward the concave corner of the erase gate and extending beyond a sidewall of the trench.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 29/66 - Types of semiconductor device
• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Abstract

A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, a select gate, a control gate, an erase gate, and a floating gate. The select gate is disposed on the substrate. The control gate is disposed on the substrate and laterally spaced apart from the select gate. The erase gate is disposed on the substrate and laterally spaced apart from the control gate, and the erase gate includes a concave corner. The floating gate is covered with the control gate and the erase gate. The floating gate includes a convex corner which faces the concave corner of the erase gate, and the vertex of the floating gate is lower than a top surface of the select gate.

IPC Classes  ?

• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate

Abstract

A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.

IPC Classes  ?

• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H10D 30/01 - Manufacture or treatment
• H10D 30/68 - Floating-gate IGFETs

Abstract

A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, a select gate, a floating gate, a floating gate cap layer, and an erase gate. The select gate is disposed on the substrate. The floating gate is disposed on the substrate and laterally spaced apart from the select gate, where the floating gate includes top edges forming a closed shape as viewed from a top-down perspective. The floating gate cap layer is disposed on a top surface of the floating gate, where an area of a top surface of the floating gate cap layer is less than an area of a bottom surface of the floating gate. The erase gate is disposed on the floating gate, and one or more of the top edges are covered with the erase gate. A control gate is covered with the erase gate.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Abstract

A non-volatile memory device includes at least one memory cell including a substrate, an assist gate, a byte select gate, a floating gate, and an upper gate. The substrate includes a first doped region and a second doped region. The assist gate is disposed on the substrate and adjacent to the second doped region. The byte select gate is disposed on the substrate and adjacent to the first doped region. The floating gate is disposed on the substrate and between the assist gate and byte select gate, and the floating gate includes an upper edge higher than top surfaces of the assist gate and the byte select gate. The upper gate covers the assist gate and the floating gate, and the upper gate is spaced apart from the byte select gate. The upper edge of the floating gate is embedded in the upper gate.

IPC Classes  ?

• H10D 30/68 - Floating-gate IGFETs
• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• H10D 30/01 - Manufacture or treatment
• H10D 64/01 - Manufacture or treatment

Abstract

A non-volatile memory device includes at least one memory cell and the memory cell includes a substrate, a select gate, a control gate, a floating gate, and an erase gate. The select gate is disposed on the substrate, and the control gate is disposed on the substrate and laterally spaced apart from the select gate. The control gate comprises a non-vertical surface. The floating gate includes a vertical portion and a horizontal portion. The vertical portion disposed between the select gate and the control gate and includes a first top tip laterally spaced apart from the control gate. The horizontal portion is disposed between the substrate and the control gate, where the horizontal portion includes a lateral tip laterally and vertically spaced apart from the control gate. The erase gate covers the non-vertical surface of the control gate and the lateral tip of the horizontal portion of the floating gate.

IPC Classes  ?

• H10D 30/68 - Floating-gate IGFETs
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H10D 30/01 - Manufacture or treatment
• H10D 64/01 - Manufacture or treatment

Abstract

A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, an assist gate structure, a tunneling dielectric layer, a floating gate, and an upper gate structure. The assist gate structure is disposed on the substrate. The floating gate includes two opposite first top edges arranged along a first direction, two opposite first sidewalls arranged along the first direction, and two opposite second sidewalls arranged along a second direction different from the first direction. The upper gate structure covers the assist gate structure and the floating gate, where at least one of the first top edges of the floating gate is embedded in the upper gate structure. Portions of the upper gate structure extend beyond the second sidewalls of the floating gate in the second direction, and the portions of the upper gate structure are disposed above the substrate.

IPC Classes  ?

• H10D 30/68 - Floating-gate IGFETs
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H10D 30/01 - Manufacture or treatment
• H10D 64/01 - Manufacture or treatment

Abstract

A non-volatile memory device includes a memory cell including a substrate, a select gate, a control gate, a planar floating gate, a coupling dielectric layer, an erase gate dielectric layer, and an erase gate. The select gate and the control gate are disposed on the substrate and laterally spaced apart from each other, and the control gate includes a non-vertical surface. The planar floating gate includes a lateral tip laterally spaced apart from the control gate. The coupling dielectric layer includes a first thickness (T1). The erase gate dielectric layer covers the non-vertical surface of the control gate and the lateral tip of the planar floating gate, and includes a second thickness (T2). The erase gate covers the erase gate dielectric layer and the lateral tip of the planar floating gate. The first thickness and the second thickness satisfy the following relation: (T2)<(T1)<2(T2).

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 29/66 - Types of semiconductor device
• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Abstract

A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.

IPC Classes  ?

• H10B 41/44 - Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
• H10B 41/48 - Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor

Abstract

A method of manufacturing a non-volatile memory includes the following steps. A stacked structure is formed on a substrate and includes a gate dielectric layer, an assist gate, an insulation layer, and a sacrificial layer stacked in order. A tunneling dielectric layer is formed at one side of the stacked structure. A floating gate is formed on the tunneling dielectric layer. The stacked structure is etched until an uppermost edge of the floating gate is higher than a top surface of the insulation layer. A dielectric material layer is formed to cover sidewalls of the floating gate. The dielectric material layer is etched to form an etched dielectric material layer and expose the uppermost edge of the floating gate. An upper gate structure is formed on the etched dielectric material layer, where a portion of the etched dielectric material layer is disposed between the upper gate structure and the substrate.

IPC Classes  ?

• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout

Abstract

A non-volatile memory having memory cells is provided. The memory cell includes a source region and a drain region, a select gate, a dummy select gate, a floating gate, an erase gate, and a control gate. The select gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed on the substrate between the select gate and the source region, and a top portion of the floating gate has corners in symmetry. The height of the floating gate is lower than the height of the select gate. The erase gate is provided on the source region and covers the corner at the side of the source. The control gate is disposed on the erase gate and the floating gate.

IPC Classes  ?

• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
• H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 29/51 - Insulating materials associated therewith
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups

Abstract

A non-volatile memory having memory cells is provided. A stacked gate structure has gate dielectric layer, assist gate, insulation layer, and erase gate disposed in order. The floating gate is disposed on a first sidewall of the stacked gate structure, the floating gate has a corner portion at the top portion, and erase gate covers the corner portion. The tunneling dielectric layer is disposed under the floating gate. The erase gate dielectric layer is disposed between the erase gate and the floating gate. The assist gate dielectric layer is disposed between the assist gate and the floating gate. The source region and the drain region are respectively disposed at two sides of the stacked structure and the floating gate. The control gate is disposed on the source region and the floating gate. The inter-gate dielectric layer is disposed between the control gate and the floating gate.

IPC Classes  ?

• H01L 27/115 - Electrically programmable read-only memories; Multistep manufacturing processes therefor
• H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND

Abstract

A non-volatile memory having memory cells is provided. The memory cells include stack structures, floating gates, tunneling dielectric layers, erase gate dielectric layers, auxiliary gate dielectric layers, source regions, drain regions, control gates and inter-gate dielectric layers. The stacked structures include gate dielectric layers, auxiliary gates, insulating layers and erase gates. The floating gates are disposed on sidewalls on a first side of the stacked structures. The tunneling dielectric layers are disposed under the floating gates. The erase gate dielectric layers are disposed between the erase gates and floating gates. The auxiliary gate dielectric layers are disposed between the auxiliary gates and the floating gates. The source and drain regions are separately disposed on sides of the stack structures and the floating gates. The control gates are disposed on the source regions and the floating gates. The inter-gate dielectric layers are disposed between the control gates and the floating gates.

IPC Classes  ?

• H01L 27/115 - Electrically programmable read-only memories; Multistep manufacturing processes therefor
• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
• H01L 29/66 - Types of semiconductor device
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 27/11521 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region