The present disclosure relates to a layered structure comprising: a substrate; a first semiconductor layer over the substrate; an epitaxial metal layer over the first semiconductor layer; and a second semiconductor layer over the epitaxial metal layer. The epitaxial metal layer is configured to modify carrier movement in the second semiconductor layer.
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10H 20/816 - Bodies having carrier transport control structures, e.g. highly-doped semiconductor layers or current-blocking structures
A semiconductor structure comprises a high electron mobility transistor (HEMT) comprising: a channel layer (110) comprising a first surface (112) and a barrier layer (120). The semiconductor structure further comprises an insulating material (176) contacting the first surface. The channel layer is between the barrier layer and the insulating layer.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 64/00 - Electrodes of devices having potential barriers
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
The present disclosure relates to a high electron mobility transistor (HEMT) comprising: a channel layer (110); a gate contact (140) on a first side of the channel layer; and at least one of a source contact (160) and a drain contact (150) on a second side of the channel layer, opposite the first side; wherein the channel layer is between the gate contact and the at least one of the source contact and the drain contact; wherein the channel layer comprises a channel for lateral carrier flow across the channel layer between the source contact and the drain contact.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
The present disclosure relates to a method that comprises: forming a plurality of III-nitride layers over a substrate; forming a porous layer in the plurality of III-nitride layers; bonding the plurality of III-nitride layers to a handle wafer; and removing the handle wafer and at least one of the plurality of III-nitride layers from the substrate comprising cleaving the porous layer.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
The present disclosure relates to a semiconductor structure that comprises: a substrate; a buffer layer over the substrate; a back-barrier region over the buffer layer; a channel layer over the back-barrier region; and a barrier layer over the channel layer. The back barrier region comprises: a first semiconductor layer configured to form a first potential barrier; and a second semiconductor layer configured to form a second potential barrier in the second semiconductor layer, wherein the second potential barrier is greater than the first potential barrier.
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
The present disclosure relates to a semiconductor structure comprising: a substrate; a semiconductor multilayer structure over the substrate. The semiconductor multilayer structure comprises: a first III-V semiconductor layer comprising a first set of III-V elements; and a strain compensation layer comprising a second set of III-V elements and N; wherein the first set of III-V elements and the second set of III-V elements respectively comprise one of: GaAs and AlAs; GaP and AlP; GaSb and AlSb.
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
A CAVET comprises: a drain terminal (110); a source terminal (170); and a current blocking layer (240), CBL, between the drain terminal and the source terminal, wherein the CBL comprises at least one porous region (244, 246) for blocking current between the source terminal and the drain terminal and a non-porous aperture region (242) for allowing current flow between the source terminal and the drain terminal.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 21/338 - Field-effect transistors with a Schottky gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/15 - Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
An epitaxial semiconductor structure comprising a silicon substrate in <100> orientation. On the substrate are sequentially a bixbyite oxide layer in <111> orientation, a rare earth nitride layer, an aluminium nitride layer, and a gallium nitride layer in <0001> orientation. Advantageously the semiconductor structure results in a better quality GaN layer.
The present disclosure relates to a semiconductor structure that comprises: a substrate comprising Si with a (100) crystal orientation; a first transition layer comprising a rare earth oxide over the substrate, wherein the first transition layer comprises a (111) crystal orientation; a first semiconductor layer comprising a first III-N semiconductor material over the first transition layer; and an active region over the first semiconductor layer comprising quantum dots, wherein the quantum dots comprise a second III-N semiconductor material.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
H01L 33/16 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A layered structure (300'', 300''', 300'''', 300''''') includes a conductive layer (303, 305b, 303', 305b') coupled to a backside (302b) of a substrate (302), and a porous layer (304, 304', 304'') over the substrate. The conductive layer has a lower resistivity than the substrate. The porous layer has a higher resistivity than the substrate. Advantageously the backside conductive layer can improve current conduction through the substrate during electrochemical etching, improve a thickness uniformity of the porous layer, reduce a charge transfer depletion region width on the backside of the substrate, and reduce metal contamination in the layered structure.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
A method (700) for forming a layered structure (500) can include forming a porous layer (504) by electrochemical etching a portion (501) of a substrate (502). The substrate can have a first resistivity (602) no greater than about 10 Ω·cm. The porous layer (504) can have a second resistivity (604) greater than the first resistivity. The second resistivity can be dependent upon the first resistivity.
A layered structure (300'') can include a porous layer (304') over a substrate (302) and a thermal layer (342, 344) coupled to pore walls (340) of the porous layer. The porous layer can have a higher resistivity than the substrate. A stress of the porous layer can be proportional to a variance of infrared (IR) transmission data of the porous layer. The variance of IR transmission data can be no greater than 2,500. Advantageously the thermal layer can decrease stress in the porous layer, increase thermal stability of the porous layer, decrease cracking and flaking during high temperature processing, maintain high resistivity of the porous layer, and increase the quality of the epitaxial layer and/or semiconductor devices formed using the porous layer.
g1g2g1g2g1g2g1g2g1g1) can decrease thermal donor effects, maintain high resistivity of the porous layer, decrease harmonic losses at device operating temperatures, and increase device performance.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
A porous tool (200'', 200''') for porosifying a wafer (302) includes an electrolytic cell (225), a housing (220'', 220'''), a voltage source (230), and a controller (250). The electrolytic cell includes a cathode (224), an anode (226), and an electrolyte (222). A diameter of the wafer (302c) is at least 200 mm. The housing encloses the electrolytic cell and is configured to receive the wafer for a porosification process. The housing includes a seal (221'), an input line (242), and an output line (246). The controller is coupled to the housing and the voltage source. The controller is configured to control the porosification process of the wafer. Advantageously the porous tool can provide dryin and dry-out full-scale (e.g., at least 200 mm diameter) wafer porosification, programmable wafer porosification, a closed cleanroom compatible processing environment, epitaxy and CMOS compatible processing, and automated large volume cassette-to-cassette processing.
A layered structure (300'') includes a substrate (302), a porous layer (304') over the substrate, and a coating (342, 344, 346) coupled to porous walls (340) of the porous layer. The porous layer has a higher resistivity than the substrate. Advantageously the coating can improve thermal stability of the porous layer, reduce cracking and flaking during high temperature processing, maintain high resistivity of the porous layer, increase thermal conductivity of the porous layer, and reduce self-heating in a device.
The present invention provides a semiconductor structure (10) comprising: a silicon substrate (12) in [100] orientation; a scandium oxide layer (14) over the substrate (12), in [111] orientation; and a scandium-rare earth-oxide layer (16) over the scandium oxide layer (14). The scandium-rare earth-oxide layer can have a graded composition to transition lattice constant to match to a subsequent layer, such as an indium nitride layer having very high electron drift velocity. InN over Si (100) offers transistors, photonics and passive electronics that operate in the terahertz frequency range.
A light emitting device (10) comprising a germanium first layer (12); a nucleation layer (14); a buffer layer 16 comprising a III-V composition; and an active layer (24). The sum product of As concentration and layer thickness in each of the layers is less than 20%. This enables the devices to be fabricated in an environment which must be free, or substantially free, of arsenic.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01S 5/02 - Structural details or components not essential to laser action
H01S 5/343 - Structure or shape of the active regionMaterials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser
The present disclosure relates to a layered structure comprising: a substrate comprising a p-type semiconductor material; a plurality of semiconductor layers, on the substrate, comprising at least one p-on-n junction; and a tunnel junction layer between the substrate and the plurality of semiconductor layers.
H01L 33/04 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
H01L 33/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
H01L 33/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
H01S 5/30 - Structure or shape of the active regionMaterials used for the active region
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
19.
METHOD AND SYSTEM FOR MIXED GROUP V PRECURSOR PROCESS
A method of forming a layer includes introducing a Group III precursor in a reactor, introducing a hydride Group V precursor in the reactor, and introducing a metal-organic Group V precursor in the reactor to form the layer. The method can further include mixing the hydride Group V precursor and the metal-organic Group V precursor. Advantageously, the layer and method of forming the layer utilize mixed Group V precursors, improve uniformity, decrease thermal sensitivity of the end material, normalize concentration profiles of precursors, improve yield, increase manufacturing efficiency, improve control of III-V ratios (e.g., pressure, growth rate, flux), and reduce manufacturing costs.
A method of fabricating a layered structure comprising growing an epitaxial layer on a substrate with a first resistivity proximal to the substrate and a second resistivity (less than the first) distal therefrom. Porosify the epitaxial layer to form a porous layer with porosity >30% proximal to the substrate and ≤25% distal from the substrate. Epitaxially grow a semiconductor (channel) layer over the porous layer. Also a layered structure comprising: a substrate; a porous layer; and an epitaxial semiconductor (channel) layer. The porous layer has a first porosity >30% proximal to the substrate and a second porosity ≤25% adjacent to the semiconductor layer. The two different porosities can be optimized. The higher porosity is effective at insulating the channel from the substrate. The lower porosity provides a crystalline structure with single crystal orientation exposed that supports the channel layer comprising high quality, low defect, epitaxial growth.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
A layered structure comprising a substrate having a first deformation. Also one or more device layers forming a device and having a second deformation. A deformation control layer which is pseudomorphic with respect to the substrate and having a third deformation. The deformation control layer is selected such that a sum of the first, second and third deformations matches a target level of deformation. Advantageously the layered structure has a controlled, known deformation which can be compressive, tensile or zero.
H01L 33/46 - Reflective coating, e.g. dielectric Bragg reflector
H01L 33/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
H01S 5/06 - Arrangements for controlling the laser output parameters, e.g. by operating on the active medium
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
H01S 5/20 - Structure or shape of the semiconductor body to guide the optical wave
22.
POROUS DISTRIBUTED BRAGG REFLECTOR APPARATUSES, SYSTEMS, AND METHODS
A layered structure includes a first layer being a single material and a cavity coupled to the first layer. The first layer includes a porous region to form a first distributed Bragg reflector (DBR). The porous region includes alternating first porous and second porous sublayers of the single material to form the first DBR. The cavity includes an active region to generate radiation, detect radiation, or both. Advantageously, the layered structure and method of forming the layered structure improves the speed of manufacturing DBRs, reduces strain in the layered structure, reduces the size of the layered structure, and increases throughput.
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
A high electron mobility transistor comprising a nucleation layer having a first lattice constant, a back-barrier layer having a second lattice constant and a stress management layer having a third lattice constant which is larger than both first and second lattice constants. The stress management layer compensates some or all of the stress due to the lattice mismatch between the nucleation layer and back barrier layer so that the resulting structure experiences less bow and warp.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A multi-wavelength light-emitting semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a first reflector on the substrate, a light emission layer on the first reflector, second reflectors on corresponding active regions; and apertures on corresponding active regions. The light emission layer includes active regions. Each of the active regions includes a primary emission wavelength different from each other.
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
H01S 5/323 - Structure or shape of the active regionMaterials used for the active region comprising PN junctions, e.g. hetero- or double- hetero-structures in AIIIBV compounds, e.g. AlGaAs-laser
A high electron mobility transistor 22 comprising a nucleation layer 14 having a first lattice constant, a back-barrier layer 24 having a second lattice constant and a stress management layer 26 having a third lattice constant which is larger than both first and second lattice constants. The stress management layer 26 compensates some or all of the stress due to the lattice mismatch between the nucleation layer 14 and back barrier layer 24 so that the resulting structure experiences less bow and warp.
A layered structure including a substrate in [100] crystal orientation, a crystalline bixbyite oxide layer in [111] orientation, and a metal-containing layer crystallographically matched to the crystalline bixbyite oxide layer. Also a method of fabricating a layered structure comprising steps to: epitaxially deposit a crystalline bixbyite oxide in [111] orientation on a substrate in [100] crystal orientation; and deposit a metal-containing layer on the crystalline bixbyite oxide layer.
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 62/80 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
H10F 77/124 - Active materials comprising only Group III-V materials, e.g. GaAs
H10H 20/825 - Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
A layered structure includes a substrate, a porous layer over the substrate, an epitaxial layer grown directly over the porous layer, and a semiconductor device in the epitaxial layer. The porous layer has a higher resistivity than the substrate. A porosity of the porous layer reduces radio frequency (RF) bleeding from the semiconductor device into the substrate.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
09 - Scientific and electric apparatus and instruments
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Electronic components; electronic components, namely wafers;
semiconductor wafers; wafers for integrated circuits;
silicon wafers; epitaxial wafers; compound semiconductor
wafers; gallium arsenide based wafers; indium phosphide
based wafers; gallium nitride based wafers; gallium
antimonide based wafers; indium antimonide based wafers;
group IV wafers; sapphire-based wafers; III-V
semiconductors; germanium based wafers; semiconductor
templates; on-wafer optics; photonic quasi-crystal
semiconductor components; parts and fittings of all the
aforesaid goods. Custom manufacturing services; custom manufacture of
electronic, wireless, photonic, optoelectronic, infrared,
photovoltaic, power control and microelectromechanical
systems (MEMS) components; custom manufacture of wafer
products; custom manufacture of on-wafer optics products or
component parts thereof; custom manufacture of photonic
quasi-crystal semiconductor components; nano-imprint
lithography; photolithography [material processing];
information and advisory services relating to all the
aforesaid services. Technological support services; technical support services
in relation to design and development of electronic,
wireless, photonic, optoelectronic, infrared, photovoltaic,
power control and microelectromechanical systems (MEMS)
components; technological support services in relation to
wafer products; information and advisory services relating
to all the aforesaid services.
A layered structure having controllable stress is described herein. The layered structure includes a starting material, a porous layer formed over a starting material having tunable porosity and/or thickness, a stressor material deposited within the porous layer, and an epitaxial layer formed over the porous layer. The porous layer and the stressor material within the porous layer induce controllable stress in the starting material. Additionally, techniques for controlling stress in the layered structure are described herein. A process for controlling stress in the layered structure includes forming a porous layer having tunable porosity and thickness over a starting material, inducing stress in the starting material including depositing a stressor material within the porous layer, and tuning the induced stress using the tunable porosity and/or thickness of the porous layer.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
40 - Treatment of materials; recycling, air and water treatment,
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Custom manufacturing of semiconductors; custom manufacture of electronic, wireless, photonic, optoelectronic, infrared, photovoltaic, power control and microelectromechanical systems (MEMS) components; custom manufacture of semiconductor wafer products; custom manufacture of on-wafer optics products or component parts thereof; custom manufacture of photonic quasi-crystal semiconductor components; nano-imprint lithography; providing custom photolithographic material processing services; information and advisory services relating to all the aforesaid services Electronic components, namely, wafers being semiconductor wafers; semiconductor wafers; wafers for integrated circuits; silicon wafers; epitaxial wafers being semiconductor wafers; compound semiconductor wafers; gallium arsenide based semiconductor wafers; indium phosphide based semiconductor wafers; gallium nitride based semiconductor wafers; gallium antimonide based semiconductor wafers; indium antimonide based semiconductor wafers; group IV semiconductor wafers; sapphire-based wafers being semiconductor wafers having a sapphire substrate; III-V semiconductors; germanium based semiconductor wafers; semiconductor templates being semi-finished semiconductor wafers; on-wafer optics, namely, on-wafer optical sensors and light emitters; photonic quasi-crystal semiconductor components, namely, on-wafer optical sensors and light emitters Technological support services, namely, providing technology advice in the field of semiconductors; technical support services, namely, providing technical advice and technological consultation services related to the design and development of electronic, wireless, photonic, optoelectronic, infrared, photovoltaic, power control and microelectromechanical systems (MEMS) components; technological support services in relation to wafer products, namely, providing technology advice in the field of semiconductor wafers; information and advisory services relating to all the aforesaid services
31.
Localized strain fields in epitaxial layer over cREO
Systems and methods are described herein to grow a layered structure. The layered structure is implemented as a VCSEL and comprises a first germanium substrate layer having a first lattice constant, a second layer that has a second lattice constant and is epitaxially grown over the first germanium substrate layer, wherein the second layer comprises a compound of a first constituent and a second constituent, and a third layer that has a third lattice constant and is epitaxially grown over the second layer, wherein the third layer comprises a compound of a third constituent and a fourth constituent, wherein the first, second, third and fourth constituents are selected such that the layered structure is pseudomorphic and the first lattice constant is between the second lattice constant and the third lattice constant.
A passivated semiconductor device structure includes a III-nitride structure and a passivation layer. The III-nitride structure includes a high electron mobility transistor (HEMT). The passivation layer includes a dielectric, which is formed over the structure to provide passivation and forms an interface with the structure. The interface provides a transition between the structure and the dielectric having a thickness of at least two atomic layers. The interface also has a characteristic density of interface states less than a reference density of interface states that corresponds to a thickness of at most one atomic layer. The transition, which constitutes a rough interface, allows a relatively low density of interface states, and thus improves high-frequency performance of the device structure.
A passivated semiconductor device structure includes a Ill-nitride structure (102) and a passivation layer (104). The Ill-nitride structure includes a high electron mobility transistor (HEMT). The passivation layer includes a dielectric, which is formed over the structure to provide passivation and forms an interface with the structure. The interface provides a transition (110) between the structure and the dielectric having a thickness of at least two atomic layers. The interface also has a characteristic density of interface states less than a reference density of interface states that corresponds to a thickness of at most one atomic layer. The transition, which constitutes a rough interface, allows a relatively low density of interface states, and thus improves high-frequency performance of the device structure.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
35.
SEMICONDUCTOR MATERIAL HAVING TUNABLE PERMITTIVITY AND TUNABLE THERMAL CONDUCTIVITY
A layered structure for semiconductor application is described herein. The layered structure includes a starting material and a fully depleted porous layer formed over the starting material with high resistivity. In some embodiments, the layered structure further includes epitaxial layer grown over the fully depleted porous layer. Additionally, a process of making the layered structure including forming the fully depleted porous layer and epitaxial layer grown over the porous layer is described herein.
A layered structure for semiconductor application is described herein. The layered structure includes a starting material and a fully depleted porous layer formed over the starting material with high resistivity. In some embodiments, the layered structure further includes epitaxial layer grown over the fully depleted porous layer. Additionally, a process of making the layered structure including forming the fully depleted porous layer and epitaxial layer grown over the porous layer is described herein.
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
37.
Electronic device with 2-dimensional electron gas between polar-oriented rare-earth oxide layer grown over a semiconductor
Layered structures described herein include electronic devices with 2-dimensional electron gas between polar-oriented cubic rare-earth oxide layers on a non-polar semiconductor. Layered structure includes a semiconductor device, comprising a III-N layer or rare-earth layer, a polar rare-earth oxide layer grown over the III-N layer or rare-earth layer, a gate terminal deposited or grown over the polar rare-earth oxide layer, a source terminal that is deposited or epitaxially grown over the layer, and a drain terminal that is deposited or grown over the layer.
H01L 29/267 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups , , , , in different semiconductor regions
A layered structure having controllable stress is described herein. The layered structure includes a starting material, a tunable porous layer formed over a starting material, and an epitaxial layer formed over the porous layer. The tunable porous layer induces a tunable bow in the starting material to set net stress in the layered structure. Additionally, techniques for controlling stress in the layered structure are described herein. A process for controlling stress in the layered structure includes forming a porous layer having tunable porosity and thickness over a starting material, inducing a bow in the starting material by oxidizing the porous layer, and tuning the induced bow to set net stress in the layered structure that results from a layer subsequently grown or deposited over the tunable porous layer.
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
Structures having an epitaxial metal layer, a semiconductor layer, or both, may be formed as part of a first process in a first chamber, and then undergo subsequent processing in a second chamber. A modified device may be formed from a pre-form ed device by application of further layers in a second process. One or more layers may be formed directly over the device, formed directly over a seed layer formed over the device, or formed over a substrate that is subsequently bonded and partially cleaved from the device. A seed layer may include a lattice constant transition, chemical transition, or other suitable transition between the device and an epitaxial layer. A cleave layer may include a porous layer configured to fracture at a relatively lower shear loading than the rest of the structure, thus providing a predictable separation plane.
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
A layered structure used for detecting incident light includes a substrate having a surface with a high Miller index crystal orientation and a superlattice structure formed over the substrate at the surface. The superlattice structure is aligned to the high Miller index crystal orientation and exhibits a red-shifted long wave infrared response range based on the crystal orientation as compared to a superlattice structure formed over a substrate at a surface with a (100) crystal orientation.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 31/036 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
H01L 31/103 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN homojunction type
41.
LONG-WAVE INFRARED PHOTODETECTOR STRUCTURES FORMED ON HIGH-INDEX SUBSTRATES
A layered structure used for detecting incident light includes a substrate having a surface with a high Miller index crystal orientation and a superlattice structure formed over the substrate at the surface. The superlattice structure is aligned to the high Miller index crystal orientation and exhibits a red-shifted long wave infrared response range based on the crystal orientation as compared to a superlattice structure formed over a substrate at a surface with a (100) crystal orientation.
H01L 31/101 - Devices sensitive to infrared, visible or ultraviolet radiation
H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
H01L 31/036 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
42.
Pnictide nanocomposite structure for lattice stabilization
A layered structure for semiconductor application is described herein. The layered structure includes III-V semiconductor and uses pnictide nanocomposites to control lattice distortion in a series of layers. The distortion is tuned to bridge lattice mismatch between binary III-V semiconductors. In some embodiments, the layered structure further includes dislocation filters.
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
43.
A PNICTIDE NANOCOMPOSITE STRUCTURE FOR LATTICE STABILIZATION
A layered structure for semiconductor application is described herein. The layered structure includes III-V semiconductor and uses pnictide nanocomposites to control lattice distortion in a series of layers. The distortion is tuned to bridge lattice mismatch between binary III-V semiconductors. In some embodiments, the layered structure further includes dislocation filters.
Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer. Specifically, the substrate may include a porous portion, which is usually aligned with the metal layer, with or without a rare earth oxide layer in between.
Systems and methods are described herein for growing epitaxial metal oxide as buffer for epitaxial III-V layers. A layer structure includes a base layer and a first rare earth oxide layer epitaxially grown over the base layer. The first rare earth oxide layer includes a first rare earth element and oxygen, and has a bixbyite crystal structure. The layer structure also includes a metal oxide layer epitaxially grown directly over the first rare earth oxide layer. The metal oxide layer includes a first cation element selected from Group III and oxygen, and has a bixbyite crystal structure.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
46.
III-N TO RARE EARTH TRANSITION IN A SEMICONDUCTOR STRUCTURE
In view of the high-temperature issues in III-N layer growth process, embodiments described herein use layered structure including a rare earth oxide (REO) or rare earth nitride (REN) buffer layer and a polymorphic III-N-RE transition layer to transit from a REO layer to a III-N layer. In some embodiments, the piezoelectric coefficient of III-N layer is increased by introduction of additional strain in the layered structure. The polymorphism of RE-III-N nitrides can then be used for lattice matching with the III-N layer.
In view of the high-temperature issues in III-N layer growth process, embodiments described herein use layered structure including a rare earth oxide (REO) or rare earth nitride (REN) buffer layer and a polymorphic III-N-RE transition layer to transit from a REO layer to a III-N layer. In some embodiments, the piezoelectric coefficient of III-N layer is increased by introduction of additional strain in the layered structure. The polymorphism of RE-III-N nitrides can then be used for lattice matching with the III-N layer.
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/15 - Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
An optoelectronic device includes an Sb-based metamorphic photodetector grown over a silicon substrate via a buffer layer. The device includes a layered structure. The layered structure can include a silicon substrate, a buffer layer formed over the Si substrate, and an infrared photodetector formed over the buffer layer. In some embodiments, the buffer layer includes a composite buffer layer having sublayers. For example, the composite buffer layer includes a Ge-based sublayer formed over the substrate, a III-As sublayer grown over the Ge-based sublayer, and a III-Sb sublayer formed over the III-As sublayer.
H01L 31/0336 - Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups in different semiconductor regions, e.g. Cu2X/CdX hetero-junctions, X being an element of Group VI of the Periodic System
H01L 31/036 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 31/028 - Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System
H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
An optoelectronic device includes an Sb-based metamorphic photodetector grown over a silicon substrate via a buffer layer. The device includes a layered structure. The layered structure can include a silicon substrate, a buffer layer formed over the Si substrate, and an infrared photodetector formed over the buffer layer. In some embodiments, the buffer layer includes a composite buffer layer having sublayers. For example, the composite buffer layer includes a Ge-based sublayer formed over the substrate, a III-As sublayer grown over the Ge-based sublayer, and a Ill-Sb sublayer formed over the III-As sublayer.
Layered structures described herein include electronic devices with 2- dimensional electron gas between polar-oriented cubic rare-earth oxide layers on a non-polar semiconductor. Layered structure includes a semiconductor device, comprising a III-N layer or rare-earth layer, a polar rare-earth oxide layer grown over the III-N layer or rare-earth layer, a gate terminal deposited or grown over the polar rare-earth oxide layer, a source terminal that is deposited or epitaxially grown over the layer, and a drain terminal that is deposited or grown over the layer.
Systems and methods describe growing RE-based integrated photonic and electronic layered structures on a single substrate. The layered structure comprises a substrate, an epi-twist rare earth oxide layer over a first region of the substrate, and a rare earth pnictide layer over a second region of the substrate, wherein the first region and the second region are non-overlapping.
H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/8258 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by , , or
52.
POROUS DISTRIBUTED BRAGG REFLECTORS FOR LASER APPLICATIONS
Embodiments described herein provide a layered structure that comprises a substrate that includes a first porous multilayer of a first porosity, an active quantum well capping layer epitaxially grown over the first porous multilayer, and a second porous multilayer of the first porosity over the active quantum well capping layer, where the second porous multilayer aligns with the first porous multilayer.
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
H01S 5/40 - Arrangement of two or more semiconductor lasers, not provided for in groups
Embodiments described herein provide a layered structure that comprises a substrate that includes a first porous multilayer of a first porosity, an active quantum well capping layer epitaxially grown over the first porous multilayer, and a second porous multilayer of the first porosity over the active quantum well capping layer, where the second porous multilayer aligns with the first porous multilayer.
H01S 5/02 - Structural details or components not essential to laser action
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
H01S 5/10 - Construction or shape of the optical resonator
H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers
H01S 5/40 - Arrangement of two or more semiconductor lasers, not provided for in groups
H01L 33/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
H01S 5/34 - Structure or shape of the active regionMaterials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer. Specifically, the substrate may include a porous portion, which is usually aligned with the metal layer, with or without a rare earth oxide layer in between.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
Systems and methods are described herein to grow a layered structure. The layered structure comprises a first germanium substrate layer having a first lattice constant, a second layer that has a second lattice constant and is epitaxially grown over the first germanium substrate layer, wherein the second layer has a composite of a first constituent and a second constituent, and has a first ratio between the first constituent and the second constituent, and a third layer that has a third lattice constant and is epitaxially grown over the second layer, wherein the third layer has a composite of a third constituent and a fourth constituent, and has a second ratio between the third constituent and the fourth constituent, wherein the first ratio and the second ratio are selected such that the first lattice constant is between the second lattice constant and the third lattice constant.
The structures and methods disclosed herein include changing composition of a metal alloy layer in an epitaxial electrode material to achieve tunable work functions for the electrode. In one example, the tunable work function is achieved using a layered structure, in which a crystalline rare earth oxide (REO) layer is epitaxially over a substrate or semiconductor, and a metal layer is over the crystalline REO layer. A semiconductor layer is thus in turn epitaxially grown over the metal layer, with a metal alloy layer over the semiconductor layer such that the ratio of constituents in the metal alloy is used to tune the work function of the metal layer.
Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
Layer structures for RF filters can be fabricated using rare earth oxides and epitaxial aluminum nitride, and methods for growing the layer structures. A layer structure can include an epitaxial crystalline rare earth oxide (REO) layer over a substrate, a first epitaxial electrode layer over the crystalline REO layer, and an epitaxial piezoelectric layer over the first epitaxial electrode layer. The layer structure can further include a second electrode layer over the epitaxial piezoelectric layer. The first electrode layer can include an epitaxial metal. The epitaxial metal can be single-crystal. The first electrode layer can include one or more of a rare earth pnictide, and a rare earth silicide (RESi).
H03H 1/00 - Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
H01L 41/08 - Piezo-electric or electrostrictive elements
H01L 41/319 - Applying piezo-electric or electrostrictive parts or bodies onto an electrical element or another base by depositing piezo-electric or electrostrictive layers, e.g. aerosol or screen printing using intermediate layers, e.g. for growth control
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
H03H 9/17 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 29/207 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer.
A photovoltaic diode comprising an emitter layer of doped Group III- V semiconductor material, having a first conductivity type and a first bandgap in at least part of the layer, an intrinsic layer of dilute nitride Group III-V semiconductor material having a composition given by the formula Ga1-zInzNxAsySb1-x-y , where 0 < z < 0.20, 0.01 < x < 0.05, and y > 0.80 having a second bandgap, a base layer of semiconductor material having a third bandgap and a second conductivity type opposite to the first conductivity type. The emitter, intrinsic and base layers form a diode junction. The first bandgap is greater than the second bandgap.
Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure (100), comprising a substrate (102), a first rare earth oxide layer (104) epitaxially grown over the substrate, a first metal layer (106) epitaxially grown over the rare earth oxide layer, and a first semiconductor layer (108) epitaxially grown over the first metal layer.
Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.
H01L 31/072 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/207 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
64.
NUCLEATION LAYER FOR GROWTH OF III-NITRIDE STRUCTURES
Nucleation layers for growth of Ill-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a Ill-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.
Proposed is a layer structure (1100, 1030) comprising a crystalline piezoelectric III-N layer (1110, 1032) epitaxially grown over a metal layer which is epitaxially grown over a rare earth oxide layer on a semiconductor (1102, 1002). The rare earth oxide layer includes at least two discrete portions (1104, 1004), and the metal layer includes at least one metal portion (1108, 1006) that partially overlaps adjacent discrete portions, preferably forming a bridge over an air gap (1008), particularly suitable for RF filters.
H01L 41/08 - Piezo-electric or electrostrictive elements
H01L 41/319 - Applying piezo-electric or electrostrictive parts or bodies onto an electrical element or another base by depositing piezo-electric or electrostrictive layers, e.g. aerosol or screen printing using intermediate layers, e.g. for growth control
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
Systems and methods described herein may include a first semiconductor layer with a first lattice constant, a rare earth pnictide buffer epitaxially grown over the first semiconductor, wherein a first region of the rare earth pnictide buffer adjacent to the first semiconductor has a net strain that is less than 1%, a second semiconductor layer epitaxially grown over the rare earth pnictide buffer, wherein a second region of the rare earth pnictide buffer adjacent to the second semiconductor has a net strain that is a desired strain, and wherein the rare earth pnictide buffer may comprise one or more rare earth elements and one or more Group V elements. In some examples, the desired strain is approximately zero.
Structures described herein may include mechanically bonded interlayers for formation between a first Group III-V semiconductor layer and a second semiconductor layer. The mechanically bonded interlayers provide reduced lattice strain by strain balancing between the Group III-V semiconductor layer and the second semiconductor layer, which may be silicon.
Systems and methods described herein may include a first semiconductor layer with a first lattice constant, a rare earth pnictide buffer epitaxially grown over the first semiconductor, wherein a first region of the rare earth pnictide buffer adjacent to the first semiconductor has a net strain that is less than 1%, a second semiconductor layer epitaxially grown over the rare earth pnictide buffer, wherein a second region of the rare earth pnictide buffer adjacent to the second semiconductor has a net strain that is a desired strain, and wherein the rare earth pnictide buffer may comprise one or more rare earth elements and one or more Group V elements. In some examples, the desired strain is approximately zero.
A structure can include a III-N layer with a first lattice constant, a first rare earth pnictide layer with a second lattice constant epitaxially grown over the III-N layer, a second rare earth pnictide layer with a third lattice constant epitaxially grown over the first rare earth pnictide layer, and a semiconductor layer with a fourth lattice constant epitaxially grown over the second rare earth pnictide layer. A first difference between the first lattice constant and the second lattice constant and a second difference between the third lattice constant and the fourth lattice constant are less than one percent.
A structure can include a substrate layer with an interface and a carrier concentration at the interface, a rare earth oxide barrier layer grown over the substrate layer, and a Group III layer grown over the rare earth oxide barrier layer. The carrier concentration at the interface can be different by more than an order of magnitude than the bulk carrier concentration. The rare earth oxide layer can include a rare earth oxide material and can prevent diffusion of Group III species into the substrate layer. The Group III layer can include a Group III element.
Layer structures are described for the formation of Group III-V semiconductor material over Si<110> and Si<100>. Various buffer layers and interfaces reduce the lattice strain between the Group III-V semiconductor material and the Si<110> or Si<100> layers, allowing for the epitaxial formation of high quality Group III-V semiconductor material.
Systems and methods are described herein for growing epitaxial metal oxide as buffer for epitaxial III-V layers. A layer structure includes a base layer and a first rare earth oxide layer epitaxially grown over the base layer. The first rare earth oxide layer includes a first rare earth element and oxygen, and has a bixbyite crystal structure. The layer structure also includes a metal oxide layer epitaxially grown directly over the first rare earth oxide layer. The metal oxide layer includes a first cation element selected from Group III and oxygen, and has a bixbyite crystal structure.
A III-nitride structure can include a silicon substrate, a nucleation layer over the silicon substrate, and a carbon-doped buffer layer over the nucleation layer. The carbon-doped buffer layer can include a III-nitride material and a concentration of carbon that is greater than 1 x 1020 cm-3. The III-nitride structure can include a III-nitride channel layer over the carbon-doped buffer layer and a III-nitride barrier layer over the III-nitride channel layer. The carbon doping to a carbon concentration greater than 1 x 1020 cm-3 can increase the compressive stress in the III-nitride structure.
Layer structures for RF filters can be fabricated using rare earth oxides and epitaxial aluminum nitride, and methods for growing the layer structures. A layer structure can include an epitaxial crystalline rare earth oxide (REO) layer over a substrate, a first epitaxial electrode layer over the crystalline REO layer, and an epitaxial piezoelectric layer over the first epitaxial electrode layer. The layer structure can further include a second electrode layer over the epitaxial piezoelectric layer. The first electrode layer can include an epitaxial metal. The epitaxial metal can be single-crystal. The first electrode layer can include one or more of a rare earth pnictide, and a rare earth silicide (RESi).
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H03H 1/00 - Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 41/08 - Piezo-electric or electrostrictive elements
H01L 41/083 - Piezo-electric or electrostrictive elements having a stacked or multilayer structure
H01L 41/319 - Applying piezo-electric or electrostrictive parts or bodies onto an electrical element or another base by depositing piezo-electric or electrostrictive layers, e.g. aerosol or screen printing using intermediate layers, e.g. for growth control
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
H03H 9/17 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
75.
LAYER STRUCTURES FOR RF FILTERS FABRICATED USING RARE EARTH OXIDES AND EPITAXIAL ALUMINUM NITRIDE
Layer structures for RF filters can be fabricated using rare earth oxides and epitaxial aluminum nitride, and methods for growing the layer structures. A layer structure (300) can include an epitaxial crystalline rare earth oxide (REO) layer (306) over a substrate (302), a first epitaxial electrode layer (310) over the crystalline REO layer (306), and an epitaxial piezoelectric layer (312) over the first epitaxial electrode layer (310). The layer structure (300) can further include a second electrode layer (314) over the epitaxial piezoelectric layer (312). The first electrode layer (310) can include an epitaxial metal. The epitaxial metal can be single-crystal. The first electrode layer (310) can include one or more of a rare earth pnictide, and a rare earth silicide (RESi).
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
H03H 9/17 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
H01L 41/08 - Piezo-electric or electrostrictive elements
H01L 41/083 - Piezo-electric or electrostrictive elements having a stacked or multilayer structure
H01L 41/319 - Applying piezo-electric or electrostrictive parts or bodies onto an electrical element or another base by depositing piezo-electric or electrostrictive layers, e.g. aerosol or screen printing using intermediate layers, e.g. for growth control
76.
Multijunction photovoltaic device having an Si barrier between cells
A photovoltaic device, particularly a solar cell, comprises an interface between a layer of Group III-V material and a layer of Group IV material with a thin silicon diffusion barrier provided at or near the interface. The silicon barrier controls the diffusion of Group V atoms into the Group IV material, which is doped n-type thereby. The n-type doped region can provide the p-n junction of a solar cell in the Group IV material with superior solar cell properties. It can also provide a tunnel diode in contact with a p-type region of the III-V material, which tunnel diode is also useful in solar cells.
H01L 31/0725 - Multiple junction or tandem solar cells
H01L 31/0328 - Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups
H01L 31/0687 - Multiple junction or tandem solar cells
H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
H01L 31/074 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a heterojunction with an element of Group IV of the Periodic System, e.g. ITO/Si, GaAs/Si or CdTe/Si solar cells
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/267 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups , , , , in different semiconductor regions
H01L 31/068 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
A method of growing III-N semiconducting material on a silicon substrate including the steps of growing a layer of epitaxial rare earth oxide on a single crystal silicon substrate and modifying the surface of the layer of epitaxial rare earth oxide with nitrogen plasma. The method further includes the steps of growing a layer of low temperature epitaxial gallium nitride on the modified surface of the layer of epitaxial rare earth oxide and growing a layer of bulk epitaxial III-N semiconductive material on the layer of low temperature epitaxial gallium nitride.
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
78.
OPTOELECTRONIC DETECTORS HAVING A DILUTE NITRIDE LAYER ON A SUBSTRATE WITH A LATTICE PARAMETER NEARLY MATCHING GAAS
Optoelectronic detectors having one or more dilute nitride layers on substrates with lattice parameters matching or nearly matching GaAs are described herein. A photodetector includes a substrate with a lattice parameter matching or nearly matching GaAs and a first doped III-V layer over the substrate. The photodector also includes an InGaNAsSb absorber layer over the first doped III-V layer, the absorber layer having a bandgap between approximately 0.7 eV and 0.95 eV and a carrier concentration less than approximately 1 x 1016cm-3at room temperature. The photodetector includes as well a second doped III-V layer over the absorber layer.
H01L 31/105 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
79.
Optoelectronic detectors having a dilute nitride layer on a substrate with a lattice parameter nearly matching GaAs
H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 31/105 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
A method of forming a REO dielectric layer and a layer of a-Si between a III-N layer and a silicon substrate. The method includes depositing single crystal REO on the substrate. The single crystal REO has a lattice constant adjacent the substrate matching the lattice constant of the substrate and a lattice constant matching a selected III-N material adjacent an upper surface. A uniform layer of a-Si is formed on the REO. A second layer of REO is deposited on the layer of a-Si with the temperature required for epitaxial growth crystallizing the layer of a-Si and the crystallized silicon being transformed to amorphous silicon after transferring the lattice constant of the selected III-N material of the first layer of REO to the second layer of REO, and a single crystal layer of the selected III-N material deposited on the second layer of REO.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
81.
Strain compensated REO buffer for III-N on silicon
A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
82.
III-N material grown on ErAlN buffer on Si substrate
1-xN, is positioned on the substrate. A layer of single crystal III-N material is positioned on the surface of the buffer and the single crystal alloy has a lattice constant substantially crystal lattice matched to the layer of single crystal III-N material. When the III-N material is GaN, the x in the formula for the alloy varies from less than 1 adjacent the substrate to greater than or equal to 0.249 adjacent the layer of single crystal GaN.
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
83.
Method of growing III-N semiconductor layer on Si substrate
A method of growing III-N semiconducting material on a silicon substrate including the steps of growing a layer of epitaxial rare earth oxide on a single crystal silicon substrate and modifying the surface of the layer of epitaxial rare earth oxide with nitrogen plasma. The method further includes the steps of growing a layer of low temperature epitaxial gallium nitride on the modified surface of the layer of epitaxial rare earth oxide and growing a layer of bulk epitaxial III-N semiconductive material on the layer of low temperature epitaxial gallium nitride.
09 - Scientific and electric apparatus and instruments
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Electronic components, namely wafers; semiconductor wafers;
wafers for integrated circuits; silicon wafers; epitaxial
wafers; compound semiconductor wafers; gallium arsenide
based wafers; indium phosphide based wafers; gallium nitride
based wafers; gallium antimonide based wafers; indium
antimonide based wafers. Custom manufacturing services; custom manufacture of
electronic, wireless, photonic, optoelectronic, infrared,
photovoltaic, power control and microelectromechanical
systems (mems) components; custom manufacture of wafer
products; information and advisory services relating to all
the aforesaid services. Technological support services; technical support services
in relation to the development, design and manufacture of
electronic, wireless, photonic, optoelectronic, infrared,
photovoltaic, power control and microelectromechanical
systems (MEMS) components; technological support services in
relation to wafer products.
85.
Heterostructure with carrier concentration enhanced by single crystal REO induced strains
A heterostructure grown on a silicon substrate includes a single crystal rare earth oxide template positioned on a silicon substrate, the template being substantially crystal lattice matched to the surface of the silicon substrate. A heterostructure is positioned on the template and defines at least one heterojunction at an interface between a III-N layer and a III-III-N layer. The template and the heterostructure are crystal matched to induce an engineered predetermined tensile strain at the at least one heterojunction. A single crystal rare earth oxide dielectric layer is grown on the heterostructure so as to induce an engineered predetermined compressive stress in the single crystal rare earth oxide dielectric layer and a tensile strain in the III-III-N layer. The tensile strain in the III-III-N layer and the compressive stress in the REO layer combining to induce a piezoelectric field leading to higher carrier concentration in 2DEG at the heterojunction.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
86.
III-N material grown on REN epitaxial buffer on Si substrate
A method of growing III-N material on a silicon substrate includes the steps of epitaxially growing a single crystal rare earth oxide on a silicon substrate, epitaxially growing a single crystal rare earth nitride on the single crystal rare earth oxide, and epitaxially growing a layer of single crystal III-N material on the single crystal rare earth nitride.
An iron-doped high-electron-mobility transistor (HEMT) structure includes a substrate, a nucleation layer over the substrate, and a buffer layer over the nucleation layer. The gallium-nitride buffer layer includes a iron-doping-stop layer having a concentration of iron that drops from a juncture with an iron-doped component of the buffer layer over a thickness that is relatively small compared to that of the iron-doped component. The iron-doping-stop layer is formed at lower temperature compared to the temperature at which the iron-doped component is formed. The iron-doped HEMT structure also includes a channel layer over the buffer layer. A carrier-supplying barrier layer is formed over the channel layer.
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/207 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
88.
Multijunction photovoltaic device having SiGe(Sn) and (In)GaAsNBi cells
A multijunction tandem photovoltaic device is disclosed having a bottom subcell of silicon germanium or silicon germanium tin material and above that a subcell of gallium nitride arsenide bismide, or indium gallium nitride arsenide bismide, material. The materials are lattice matched to gallium arsenide, which preferably forms the substrate. Preferably, further lattice matched subcells of gallium arsenide, indium gallium phosphide and aluminum gallium arsenide or aluminum indium gallium phosphide are provided.
H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 31/06 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
H01L 31/0725 - Multiple junction or tandem solar cells
H01L 31/074 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a heterojunction with an element of Group IV of the Periodic System, e.g. ITO/Si, GaAs/Si or CdTe/Si solar cells
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 31/0328 - Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups
H01L 31/0687 - Multiple junction or tandem solar cells
H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/267 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups , , , , in different semiconductor regions
H01L 31/068 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
A method of growing GaN material on a silicon substrate includes providing a single crystal silicon substrate with a (100) surface orientation or a (100) with up to a 10° offset surface orientation and using epi-twist technology, epitaxially growing a single crystal stress managing layer on the silicon substrate. The single crystal stress managing layer includes rare earth oxide with a (110) crystal orientation and a cubic crystal structure. The method further includes epitaxially growing a single crystal buffer layer on the stress managing layer. The single crystal buffer layer includes rare earth oxide with a lattice spacing closer to a lattice spacing of GaN than the rare earth oxide of the stress managing layer. Epitaxially growing a layer of single crystal GaN material on the surface of the buffer, the GaN material having one of a (11-20) crystal orientation and a (0001) crystal orientation.
A semiconductor structure includes a substrate and a semiconductor buffer structure overlying the substrate. The semiconductor buffer structure includes a semiconductor body of a gallium nitride material, and a stack of strain compensation layers. The stack of strain compensation layers includes a layer of a first semiconductor material with an in-plane lattice constant that is smaller than a lattice constant of the semiconductor body, and a layer of a second semiconductor material with an in-plane lattice constant that is greater than the lattice constant of the semiconductor body.
H01L 29/15 - Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
91.
III-N material grown on ErAIN buffer on Si substrate
III-N material grown on a buffer on a silicon substrate includes a single crystal electrically insulating buffer positioned on a silicon substrate. The single crystal buffer includes rare earth aluminum nitride substantially crystal lattice matched to the surface of the silicon substrate, i.e. a lattice co-incidence between REAlN and Si better than a 5:4 ratio. A layer of single crystal III-N material is positioned on the surface of the buffer and substantially crystal lattice matched to the surface of the buffer.
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/201 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds
H01L 29/207 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
92.
AlN cap grown on GaN/REO/silicon substrate structure
III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A method of forming a REO dielectric layer and a layer of a-Si between a III-N layer and a silicon substrate. The method includes depositing single crystal REO on the substrate. The single crystal REO has a lattice constant adjacent the substrate matching the lattice constant of the substrate and a lattice constant matching a selected III-N material adjacent an upper surface. A uniform layer of a-Si is formed on the REO. A second layer of REO is deposited on the layer of a-Si with the temperature required for epitaxial growth crystallizing the layer of a-Si and the crystallized silicon being transformed to amorphous silicon after transferring the lattice constant of the selected III-N material of the first layer of REO to the second layer of REO, and a single crystal layer of the selected III-N material deposited on the second layer of REO.
40 - Treatment of materials; recycling, air and water treatment,
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Custom manufacturing services, namely, custom manufacture of electronic, wireless, photonic, optoelectronic, infrared, photovoltaic, power control and microelectromechanical systems (mems) components; custom manufacture of electronic component wafer products; information and advisory services relating to all the aforesaid services Electronic components, namely, wafers; semiconductor wafers; wafers for integrated circuits; silicon wafers; epitaxial wafers; compound semiconductor wafers; gallium arsenide based wafers; indium phosphide based wafers; gallium nitride based wafers; gallium antimonide based wafers; indium antimonide based wafers Technological consultation services and technical support services in relation to the development, design and manufacture of electronic, wireless, photonic, optoelectronic, infrared, photovoltaic, power control and microelectromechanical systems (MEMS) components
95.
III-V semiconductor interface with graded GeSn on silicon
A method of depositing III-V solar collection materials on a GeSn template on a silicon substrate including the steps of providing a crystalline silicon substrate and epitaxially growing a single crystal GeSn layer on the silicon substrate using a grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 μm to approximately 5 μm. A layer of III-V solar collection material is epitaxially grown on the graded single crystal GeSn layer. The graded single crystal GeSn layer includes Sn up to an interface with the layer of III-V solar collection material.
III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
09 - Scientific and electric apparatus and instruments
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Electronic components; wafers; semiconductor wafers; wafers for integrated circuits; silicon wafers; epitaxial wafers; compound semiconductor wafers; gallium arsenide based wafers; indium phosphide based wafers; gallium nitride based wafers; gallium antimonide based wafers; indium antimonide based wafers. Custom manufacturing services; custom manufacture of electronic, wireless, photonic, optoelectronic, infrared, photovoltaic, power control and Microelectromechanical systems (MEMS) components; custom manufacture of wafer products; information and advisory services relating to all the aforesaid services. Technical support services; technical support services in relation to electronic, wireless, photonic, optoelectronic, infrared, photovoltaic, power control and Microelectromechanical systems (MEMS) components; technical support services in relation to wafer products; information and advisory services relating to all the aforesaid services.
98.
ENHANCEMENT-MODE HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE AND METHOD OF MAKING SAME
An epitaxial structure of an enhancement-mode high electron mobility transistor (HEMT) includes a first barrier layer (20) over an lnxGa1-xΚN channel layer (18), where 0≤x≤1. The first barrier layer is formed at a first temperature and is overlaid by a second barrier layer formed at a second temperature that is lower than that of the first temperature. The first barrier layer acts as an etch stop when forming a gate recess in the second barrier layer by a wet or dry etching.
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
99.
DOUBLE ALUMINUM NITRIDE SPACERS FOR NITRIDE HIGH ELECTRON-MOBILITY TRANSISTORS
An epitaxial structure and a high electron mobility transistor (HEMT) employing the epitaxial structure includes a first spacer layer over a channel layer, a first barrier layer over the first spacer layer, and a second spacer layer over the first barrier layer.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
A method of fabricating a layer of single crystal III-N material on a silicon substrate includes epitaxially growing a REO template on a silicon substrate. The template includes a REO layer adjacent the substrate with a crystal lattice spacing substantially matching the crystal lattice spacing of the substrate and selected to protect the substrate from nitridation. Either a rare earth oxynitride or a rare earth nitride is formed adjacent the upper surface of the template and a layer of single crystal III-N material is epitaxially grown thereon.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
