An internal voltage compensation circuit is provided which includes a power up signal generator configured to generate a power up signal, a select signal generator configured to compare a level of a first external voltage with a level of a second external voltage to generate first and second select signals, wherein the second select signal is generated in response to the power up signal, and a voltage compensation unit configured to electrically connect an internal voltage to the first external voltage or the second external voltage in response to the first and second select signals.
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
A method for fabricating a semiconductor memory device with a vertical channel transistor includes forming a plurality of pillars each having a hard mask pattern thereon over a substrate, each of the plurality of pillars comprising an upper pillar and a lower pillar; forming a surround type gate electrode surrounding the lower pillar; forming an insulation layer filling a space between the pillars; forming a preliminary trench by primarily etching the insulation layer using a mask pattern for a word line until a portion of the upper pillar is exposed; forming a buffer layer over a resultant structure including the preliminary trench except on a bottom of the preliminary trench; and forming a trench for a word line by secondarily etching the insulation layer until the surround type gate electrode is exposed.
A semiconductor memory device includes a first fuse having one end coupled with a first bit line and configured to be programmed with a data, a second fuse having one end coupled with a second bit line and configured to be programmed with the data; a program controller coupled with the other ends of the first fuse and the second fuse and configured to perform a program operation on at least one of the first fuse and the second fuse in response to a program voltage, and a read controller coupled with the other ends of the first fuse and the second fuse and configured to perform a read operation on the first fuse and the second fuse in response to a read voltage.
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
4.
Page buffer circuit and nonvolatile memory device having the same
A page buffer circuit includes first and second bit lines coupled to a first sensing circuit and with a first space therebetween, and third and fourth bit lines coupled to a second sensing circuit and with the first space therebetween. The second bit line and the third bit line are adjacent to each other with a second space therebetween, and the second space is smaller than the first space.
A semiconductor integrated circuit includes a decoding circuit configured to decode one or more test source signals and generate a plurality of test decoding signals, a transmission circuit configured to transmit the plurality of test decoding signals as a plurality of test mode group signals in response to a test enable signal, wherein the transmission circuit outputs the test mode group signals with maintaining a previous output, when the test decoding signals different from each other are sequentially activated, and a test mode signal output circuit configured to output a plurality of test mode signals corresponding to test mode groups, respectively, in response to the plurality of test mode group signals and one or more test mode select signals.
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
A semiconductor memory device includes a delay locked loop configured to generate a delay locked loop (DLL) clock signal by delaying an external clock signal by a first delay time and generate a feedback clock signal by delaying the DLL clock signal by the second delay time, wherein the first delay time corresponds to a phase difference between the external clock signal and the feedback clock signal and an output enable control circuit configured to generate an output enable signal in response to CAS latency information and the first and second delay times after the delay locked loop performs a locking operation.
A semiconductor memory device includes a plurality of repair fuse units configured to program repair target addresses respectively for repair target memory cells, wherein at least one of the repair fuse units is programmed with data information used for different purposes from the repair target addresses, a plurality of address comparison units each configured to compare an access target address with a corresponding address of the repair target addresses and determine whether to perform a repair operation or not, and a data transfer unit configured to transfer the data information to a corresponding circuit of the semiconductor memory device.
A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer.
A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit.
H03K 3/00 - Circuits for generating electric pulsesMonostable, bistable or multistable circuits
10.
Semiconductor device for generating initialization of information in response to a first clock and outputting the initialization information in response to a second clock
A semiconductor device includes an initialization information generation unit configured to operate in response to a first clock and generate first initialization information having a value that is adjusted according to a value of an address signal that corresponds to output data, a domain crossing unit configured to receive the first initialization information in response to the first clock and output the first initialization information as second initialization information by outputting the second initialization information in response to a second clock, and a pulse generation unit configured to operate in response to the second clock and adjust a toggling point in time of a control pulse in response to the second initialization information.
A semiconductor device fabricating method includes forming an etch target layer and a first hard mask layer over a substrate, forming a second hard mask pattern having lines over the first hard mask layer, forming a third hard mask layer over the second hard mask pattern, forming a sacrificial pattern over the third hard mask layer, forming a cell spacer on sidewalls of the sacrificial pattern, removing the sacrificial pattern, etching the third hard mask layer using the cell spacer as an etch barrier, etching the first hard mask layer using the third hard mask pattern and the second hard mask pattern as etch barriers, forming an elliptical opening having an axis pointing in a second direction by etching the etch target layer, and forming a silicon layer that fills the elliptical opening.
H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
A semiconductor memory device includes an internal signal generation unit configured to output a column select signal and a write enable signal in response to an external address, a write circuit unit configured to output internal data corresponding to external data in response to the write enable signal, a core unit configured to store the internal data in response to the column select signal, and an output timing control unit configured to control output timings of the internal signal generation unit and the write circuit unit in response to an external command, an internal synchronization signal, and preamble related information.
A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers
A semiconductor device includes an internal voltage input buffer configured to determine voltage levels of a pull-up driving node and a pull-down driving node as a result of a comparison between a voltage level of an internal voltage node and a voltage level of a reference voltage node such that the pull-up driving node and the pull-down driving node to maintain a voltage level difference, and an internal voltage driving block configured to pull-up drive the internal voltage node in response to the voltage level of the pull-up driving node and pull-down drive the internal voltage node in response to the voltage level of the pull-down driving node.
A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
17.
Semiconductor memory device and method of testing the same
A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous to the first mat, a first sense amplifier coupled to a first bit line of the first mat, a second sense amplifier coupled to a second bit line of the first mat and a third bit line of the second mat, a third sense amplifier coupled to a fourth bit line of the second mat, and a plurality of bit line precharge voltage providers for varying a level of a bit line precharge voltage provided to the first, second, and third sense amplifiers, selectively providing the resultant bit line precharge voltage level, and providing the same voltage as that of data of a selected cell to a non-selected sense amplifier during a read operation.
A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.
A semiconductor device includes a comparison unit configured to compare the phases of a plurality of clocks having different frequencies and output a phase comparison signal, a phase inversion control unit configured to generate a phase inversion control signal, and a start control unit configured to generate a start control signal in response to a clock enable signal, wherein the comparison unit is configured to start an operation in response to the start control signal and invert, in response to the phase inversion control signal, a phase of an internal clock generated from one of the plurality of clocks when the plurality of clocks have different phases.
A semiconductor device including a buried gate is disclosed. In the semiconductor device, a bit line contact contacts a top surface and lateral surfaces of an active region, such that a contact area between a bit line contact and the active region is increased and a high-resistivity failure is prevented from occurring in a bit line contact.
A semiconductor device includes: a unit configured to, in a period before power up, compare a voltage obtained by dividing a voltage of a first voltage node at a first division ratio with a voltage obtained by dividing a voltage of a second voltage node at a second division ratio and determine whether to activate an enable signal according to a result of the comparison; and a voltage driving unit configured to increase the voltage of the second voltage node when the enable signal is activated in the period before power up.
Industry-University Cooperation Foundation Hanyang University (Republic of Korea)
Inventor
Choi, Hae-Rang
Kim, Yong-Ju
Kwon, Oh-Kyong
Kwak, Kang-Sub
Song, Jun-Yong
Seol, Hyeon-Cheon
Abstract
A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.
A semiconductor device includes a main driving unit configured to serialize first and second data applied in parallel and output the serialized data to a data output pad, and an auxiliary driving unit configured to drive the data output pad in a period when the first and second data have different logic levels.
A semiconductor device includes a data storage unit configured to receive input data, outputs the input data with a difference in voltage level between logic levels, and output comparison data whose logic level is distinguished from the input data; a test operation unit configured to determine a logic level of test data periodically in response to a data reference voltage whose voltage level is determined in response to a level test code during a test operation period defined by a test entry command and a test exit command, and generate a test result signal by comparing a logic level of the comparison data with the logic level of the test data; and a test operation sensing signal generation unit configured to generate a test operation sensing signal that is activated in response to the test entry command and inactivated in response to the test result signal.
An impedance control circuit includes a first impedance unit configured to terminate an impedance node using an impedance value that is determined by an impedance control code, a second impedance unit configured to terminate the impedance node using an impedance value that is determined by an impedance control voltage, a comparison circuit configured to compare a voltage level of the impedance node and a voltage level of a reference voltage, generate an up/down signal indicating whether the voltage at the impedance node is greater than the reference voltage, and generate the impedance control voltage that has a voltage level corresponding to a difference between the voltage at the impedance node and the reference voltage, and a counter unit configured to increase or decrease a value of the impedance control code in response to the up/down signal.
A control signal generation circuit includes a voltage detection unit which detects a level of an external voltage and generates first and second detection signals and a control signal control unit which delays a sense amplifier enable signal in response to the first and second detection signals and generates first through third control signals. The enable period of the first and second control signals are controlled based on the levels of the first and second detection signals.
An integrated circuit system comprising a first chip including a first period signal generation unit configured to generate a first period signal, transmit a first signal applied from a circuit outside of the integrated circuit system to a second chip, and transmit a second signal transmitted from the second chip to the circuit outside of the integrated circuit system, and the second chip including a second period signal generation unit configured to generate a second period signal, a code generation unit configured to generate codes corresponding to a difference between periods of the first period signal and the second period signal, and a delay unit configured to delay the second signal by using a delay value that is changed according to the codes.
A clock transfer circuit includes a clock transfer unit configured to receive an external clock and transfer the received external clock as one or more internal clocks and a clock control unit configured to control the clock transfer unit to transfer the external clock as a column clock among the internal clocks in response to an active command and block a transfer of the external clock as the column clock in response to a precharge command.
A semiconductor device and a method for fabricating the same are provided to enable a bit line to be formed easily, increase a bit line process margin and reduce capacitance between the adjacent bit lines. The semiconductor device comprises: a first pillar and a second pillar each extended vertically from a semiconductor substrate and including a vertical channel region; a first bit line located in the lower portion of the vertical channel region inside the first pillar and the second pillar; and an interlayer insulating film located between the first pillar and the second pillar that include the first bit line.
A semiconductor memory device using a termination scheme in a global data line includes a global data line and a data line drive unit. The global data line transfers data between an interface region and a plurality of core regions each having a memory bank. The data line drive unit is disposed in each of the core regions, and drives the data global line in response to data in a data transfer operation. The data line drive unit sets the global data line to a termination voltage level in a termination operation.
A semiconductor device and a method for fabricating the same are provided to prevent a floating body effect and reduce coupling capacitance between buried bit lines. The semiconductor device comprises a first pillar disposed over a semiconductor substrate and including a vertical channel region, a bit line located in the lower portion of the vertical channel region inside the first pillar and a semiconductor layer extended from the semiconductor substrate to one sidewall of the first pillar.
H01L 27/108 - Dynamic random access memory structures
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
32.
Semiconductor integrated circuit and method for driving the same
A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.
Methods of manufacturing a phase-change memory device and a semiconductor device are provided. The method of manufacturing the phase-change memory device includes forming a switching device layer, an ohmic contact layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer to form a hard mask pattern, etching the ohmic layer and the switching layer using the hard mask pattern to form a pattern structure including an ohmic contact pattern, a switching device pattern, and the hard mask pattern, selectively oxidizing a surface of the pattern structure, forming an insulating layer to bury the pattern structure, and selectively removing the hard mask pattern other than the oxidized surface thereof to form a contact hole.
A combined memory block includes a first memory unit configured to store data and an additional memory unit that forms a stacked structure with the memory unit, wherein the memory unit and the storage unit together form multi-level cells having variable resistance in storing data.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
G11C 16/06 - Auxiliary circuits, e.g. for writing into memory
A technology is capable of simplifying a process of manufacturing an asymmetric device in forming a Tunneling Field Effect Transistor (TFET) structure. A method for manufacturing a semiconductor device comprises forming a conductive pattern over a semiconductor substrate, implanting impurity ions with the conductive pattern as a mask to form a first junction region in the semiconductor substrate, forming a first insulating film planarized with the conductive pattern over the first junction region, etching the top of the conductive pattern to expose a sidewall of the first insulating film, forming a spacer at the sidewall of the first insulating film disposed over the conductive pattern, etching the conductive pattern with the spacer as an etching mask to form a gate pattern, and forming a second junction region in the semiconductor substrate with the gate pattern as a mask.
H01L 33/08 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
36.
Phase mixer and delay locked loop including the same
A phase mixer includes a first driver configured to drive a first input signal to a mixing node with a driving force determined by a first setting value, a second driver configured to drive a second input signal to the mixing node with a driving force determined by a second setting value, and a slew rate control unit configured to control a slew rate at the mixing node.
A precharge signal generation circuit includes a control signal generation unit configured to activate a control signal in response to a read command or write command and a precharge signal generation unit configured to use a clock signal in a period when the control signal is activated to activate a precharge signal at a time point when a delay time passes from an input of the read command or the write command to precharge signal generation circuit.
A method for forming a semiconductor device is disclosed. An anti-fuse is formed at a buried bit line such that the area occupied by the anti-fuse is smaller than that of a conventional planar-gate-type anti-fuse, and a breakdown efficiency of an insulation film is increased. This results in an increase in reliability and stability of the semiconductor device. A semiconductor device includes a line pattern formed over a semiconductor substrate, a device isolation film formed at a center part of the line pattern, a contact part formed at both sides of the line pattern, configured to include an oxide film formed over the line pattern, and a bit line formed at a bottom part between the line patterns, and connected to the contact part.
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
G11C 17/14 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/12 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
39.
Integrated circuit chip and semiconductor memory device
An integrated circuit chip includes an internal circuit configured to generate output data, an inversion determination unit configured to activate/deactivate an inversion signal according to state information regarding a state of the integrate circuit chip, and a signal output circuit configured to invert or not to invert the output data in response to the inversion signal and output the inverted or non-inverted output data.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 29/48 - Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
G11C 29/40 - Response verification devices using compression techniques
G11C 29/44 - Indication or identification of errors, e.g. for repair
G11C 29/50 - Marginal testing, e.g. race, voltage or current testing
40.
Semiconductor device and level shifting circuit for the same
A level shifting circuit includes an inverter inverting an input voltage of an input node and driving a first voltage of a first node, a first output driving unit driving an output voltage of an output node to a first level in response to the first voltage of the first node, a first connection unit electrically coupling the first node to a second node or electrically isolating the first node from the second node in response to the first voltage of the first node, an internal driving unit driving a second voltage of the second node to a second level in response to the input voltage of the input node and the output voltage of the output node, and a second output driving unit driving the output voltage of the output node to the second level in response to the second voltage of the second node.
A filtering circuit includes jitter determination reference control unit configured to determine a jitter determination reference in correspondence to an operation mode and output a control signal in response to the jitter determination reference, and a filtering unit configured to set the jitter determination reference in response to the control signal and determine whether an input signal is maintained during a sample period in response to the set jitter determination reference.
A temperature detection circuit of a semiconductor memory apparatus includes a fixed period oscillator, a temperature variable signal generating unit and a counting unit. The oscillator is configured to generate a fixed period oscillator signal when an enable signal is enabled. The temperature variable signal generating unit is configured to generate a temperature variable signal whose enable interval varies based on temperature variations, when the enable signal is enabled. The counting unit is configured to count the oscillator signal during the enable interval of the temperature variable signal to generate a temperature information signal.
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
43.
Nonvolatile memory device and operation method thereof
A nonvolatile memory device includes at least a memory cell block including memory cells that are coupled to a plurality of word lines, respectively, and store data; a content addressable memory (CAM) block including CAM cells that are coupled to the word lines, respectively, and store chip information for operations of the nonvolatile memory device; and a block switching circuit configured to couple the word lines with global word lines; and a voltage supply circuit coupled to the global word lines, for supplying a first read voltage to a selected global word line while supplying a first pass voltage to unselected global word lines in reading the memory cell block, and supplying a second read voltage to a selected global word line while supplying a second pass voltage to unselected global word lines in reading the CAM block, wherein the second pass voltage is lower than the first pass voltage.
G11C 15/00 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
44.
Semiconductor device and method for fabricating the same
A method for manufacturing a semiconductor device includes forming plural layers of a MTJ device, depositing a conductive layer over the plural layers, forming a hard mask pattern used for patterning the plural layers over the conductive layer, where the conductive layer is exposed through the hard mask pattern, performing hydrogen peroxide process to volatilize the exposed conductive layer and removing the volatilized conductive layer, and patterning the plural layers by using the hard mask pattern as an etch mask to form the MTJ device.
H01L 43/12 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01F 41/30 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates for applying nanostructures, e.g. by molecular beam epitaxy [MBE]
B82Y 40/00 - Manufacture or treatment of nanostructures
45.
Semiconductor device including data output circuit supporting pre-emphasis operation
A semiconductor device includes a code generator configured to generate a supplementary code with a value changing in response to a variation of an impedance code, a main driver configured to receive an output data and drive the received output data to a data output pad, wherein a driving force of the main driver is controlled according to the impedance code, and an auxiliary driver configured to receive the output data and drive the received output data to the data output pad, wherein a driving force of the auxiliary driver is controlled according to the supplementary code.
A non-volatile memory device includes a memory cell including a resistance variable device and a switching unit for controlling a current flowing through the resistance variable device; a read reference voltage generator configured to generate a reference voltage according to a skew occurring in the switching unit; and a sense amplifier configured to sense a voltage corresponding to the current that flows through the resistance variable device based on the reference voltage.
A substrate having a first region and second regions disposed on two sides of the first region; a first group of conductive lines extending from the first region to the second regions on the substrate; a second group of conductive lines alternating with the first group of times and extending from the first region to the second regions on the substrate; interlayer insulating layers formed over the substrate; insulating layers formed in first open regions of the interlayer insulating layers and the first group of conductive lines in the second region; and contact plugs contacting second group of conductive line formed in second open regions of the interlayer insulating layer in the second region.
A system for transmitting data includes a plurality of data lines configured to transmit the data and a transmitting chip configured to output the data to the data lines and perform a crosstalk prevention operation in response to a data pattern of the data to be transmitted through the data lines and array information of the data lines to prevent crosstalk from occurring in the data lines.
A semiconductor apparatus is provided. The apparatus includes a transmission control unit configured to generate, in response to a received pulse signal having a first pulse width, transmission control signals with a second pulse width larger than the first pulse width and synchronization control signals with a third pulse width larger than the second pulse width. The apparatus also includes a reception control unit configured to generate reception control signals in response to the synchronization control signals.
An anti-fuse circuit and an integrated circuit (IC) including the same are disclosed, which are applied to a technology for use in all kinds of semiconductor devices or system ICs, each of which includes an anti-fuse circuit using the breakdown phenomenon of a gate oxide, so as to prevent the occurrence of an anti-breakdown phenomenon. The anti-fuse circuit includes an anti-fuse, a breakdown of which occurs by a program voltage, configured to be electrically short-circuited, a read controller configured to be controlled by a read voltage received through the anti-fuse so as to output a short-circuiting status of the anti-fuse, and a switching unit configured to form a path that prevents a current flowing through the anti-fuse from being applied to the read controller during a program operation and prevents a current from flowing in the anti-fuse during a read operation.
G11C 17/14 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
51.
Non-volatile memory device with vertical memory cells
A non-volatile memory device includes a plurality of gate electrodes stacked over a semiconductor substrate and stretched in a first direction along the semiconductor substrate and a plurality of junction layers having a first region protruding from the semiconductor substrate and crossing the gate electrodes and a second region formed between the gate electrodes.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A semiconductor device includes first conductive patterns adjacent to each other and isolated by a trench including first and second trenches, a second conductive pattern formed in the first trench, and an insulating pattern partially filling the second trench under the second conductive pattern and formed between the first conductive patterns and the second conductive pattern.
A system includes a first chip configured to supply a training command and a second chip configured to transfer to the first chip a measured time for performing an operation in response to the training command.
A magneto-resistance memory device includes a first pinned layer having a first magnetic polarity regardless of current applied to the first pinned layer, a first tunnel insulating layer arranged on the first pinned layer, a first free layer arranged on the first tunnel insulating layer and having a magnetic polarity that changes in response to current of a first amount, a second pinned layer coupled to the first free layer and having the first magnetic polarity regardless of current applied to the first pinned layer, a second tunnel insulating layer arranged on the second pinned layer, a second free layer arranged on the second tunnel insulating layer and having a magnetic polarity that changes in response to current of a second amount, wherein the second amount is smaller than the first amount, and a connection layer.
A magnetic resistance memory apparatus capable of implementing various levels and a method of driving the same are provided. The magnetic resistance memory apparatus includes a first magnetic device that includes a fixed layer having a fixed magnetization direction, a tunnel layer disposed on the fixed layer, and a first free layer disposed on the tunnel layer having a variable magnetization direction, and a second magnetic device disposed on the first magnetic device including a plurality of free layers insulated with a spacer layer interposed.
A semiconductor device includes an impedance control signal generation unit configured to generate an impedance control signal for controlling an impedance value, a first processing unit configured to process the impedance control signal in response to a first setup value and generate a first process signal, a first clock termination unit configured to be coupled with a first clock path and determine an impedance value responding to the impedance control signal, and a second clock termination unit configured to be coupled with a second clock path and determine an impedance value responding to the first process signal.
An integrated circuit includes a random address generation unit configured to generate a first random address for a data randomizing operation, an address conversion unit configured to convert the first random address and generate a second random address, and a synchronization output unit configured to sequentially output the first and second random addresses in synchronization with a clock signal.
A semiconductor integrated circuit includes a command generating unit configured to generate a plurality of second commands in response to a first command, each second command for indicating an operation sections of a corresponding anti-fuse circuit, and a plurality of anti-fuse circuits, each comprising an anti-fuse and configured to receives a corresponding second command and perform a rupture operation of the anti-fuse in response to the received corresponding second command.
H01H 37/76 - Contact member actuated by melting of fusible material, actuated due to burning of combustible material or due to explosion of explosive material
59.
Semiconductor fabricating device and method for driving the same, and method for fabricating magnetic tunnel junction using the same
In a method for fabricating a magnetic tunnel junction, a first magnetic layer is formed on a substrate, and a tunnel insulating layer is formed on the first magnetic layer. Subsequently, a second magnetic layer is formed on the tunnel insulating layer. In the method, the first magnetic layer is formed by periodically sputtering a magnetic target while a metal target is continuously sputtered.
A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.
An self-refresh control circuit for controlling a self-refresh operation of a memory device includes a self-refresh control logic block configured to control the memory device to perform the self-refresh operation and an initial refresh control block configured to activate the self-refresh control logic block in an initialization period of the memory device.
The present invention relates to a semiconductor device, which includes a junction region formed in an active area of a semiconductor substrate; a trench defining a buried gate predetermined area within the semiconductor substrate; a gate electrode buried in an lower portion of the trench; an ion implantation region formed in a sidewall of the trench; and a capping insulation layer formed in an upper portion of the gate electrode.
The present invention relates to a semiconductor device and a method for manufacturing the same. According to the present invention, a method of manufacturing a semiconductor device includes: forming a recess on a semiconductor substrate; forming a first gate electrode material and a hard mask layer on an entire surface including the recess; etching the hard mask layer and the first gate electrode material to form the first gate electrode pattern on a lower portion of inside of the recess; forming a second gate electrode material on an entire surface including the recess; and etching the second gate electrode material and separating the second gate electrode material.
A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level.
A method for operating a non-volatile memory device includes performing an erase operation onto a memory block including a plurality of memory cells, and performing a first soft program operation onto all the memory cells of a string, after the erase operation, grouping word lines of the string into a plurality of word line groups, and performing a second soft program operation onto memory cells coupled with the word lines of each word line group.
A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operation gate and a non-operation gate. A height of a gate electrode layer (conductive material) of the non-operation gate is formed to be lower than that of a gate electrode layer of the operation gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the non-operation gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device.
A nonvolatile memory device includes a channel vertically extending from a substrate and comprising a first region that is doped with first impurities and a second region that is disposed under the first region, a plurality of memory cells and a selection transistor stacked over the substrate along the channel, and a diffusion barrier interposed between the first region and the second region, wherein a density of the first impurities is higher than a density of impurities of the second region.
A non-volatile memory device includes a semiconductor substrate having a peripheral circuit region and a cell region, wherein the cell region of the semiconductor substrate is lower in height than the peripheral circuit region of the semiconductor substrate, a control gate structure disposed over the cell region of the semiconductor substrate and comprising a plurality of inter-layer dielectric layers that are alternately stacked with a plurality of control gate electrodes, a first insulation layer covering the cell region of the semiconductor substrate where the control gate structure is formed, a selection gate electrode disposed over the first insulation layer, and a peripheral circuit device disposed over the peripheral circuit region of the semiconductor substrate.
A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.
A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
71.
Semiconductor memory cell and semiconductor device
A technology is a semiconductor cell and a semiconductor device capable of reducing the coupling capacitance between adjacent bit lines by forming a bit line junction region in a separated island shape when forming a buried bit line, thereby improving characteristics of the semiconductor devices. The semiconductor cell includes a transistor including a gate and a gate junction region, a plurality of buried bit lines disposed to intersect the gate, and a plurality of bit line junction regions, each bit line junction region having an island shape formed between the buried bit lines and connected to the buried bit line.
G11C 11/24 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using capacitors
H01L 27/108 - Dynamic random access memory structures
72.
Non-volatile memory device and method for fabricating the same
A non-volatile memory device includes a channel that extends from a substrate in a vertical direction and includes a first portion including an impurity doped region and a second portion disposed under the first portion; and a plurality of memory cells and a selection transistor that are stacked over the substrate along the channel, where the impurity doped region includes a second impurity doped region that forms a side surface and an upper surface of the first portion and a first impurity doped region that covers the second impurity doped region, and a bandgap energy of the second impurity doped region is lower than a bandgap energy of the first impurity doped region.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A method for operating a non-volatile memory device which includes a plurality of memory cells serially coupled between a source selection transistor and a drain selection transistor, a first dummy memory cell coupled between the source selection transistor and the memory cells, and a second dummy memory cell coupled between the drain selection transistor and the memory cells includes applying a verification voltage to a gate of a selected memory cell, applying a first voltage to gates of unselected memory cells, and applying a second voltage that is lower than the first voltage to a gate of at least one of the first dummy memory cell and the second dummy memory cell, during a program verification operation.
A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level.
A program method of a nonvolatile memory device includes applying a program voltage to a selected word line, applying a first pass voltage to at least one word line adjacent to the selected word line, applying at least one first middle voltage lower than the first pass voltage but higher than an isolation voltage to at least one word line adjacent to the word line receiving the first pass voltage, applying the isolation voltage to a word line adjacent to the word line receiving the first middle voltage, applying at least one second middle voltage higher than the isolation voltage but lower than a second pass voltage to at least one word line adjacent to the word line receiving the isolation voltage, and applying a second pass voltage to at least one word line adjacent to the word line receiving the second middle voltage.
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
A semiconductor memory device includes an isolation layer formed in a substrate and defining an active region, a trench formed in the substrate and defining a part of the active region as an active pillar; a word line formed inside the trench, a sub-source line formed under the trench and crossing the word line, a main source line formed over the substrate, coupled to the sub-source line, and crossing the word line, a variable resistor pattern formed over the active pillar, and a bit line contacting the variable resistor pattern and crossing the word line.
H01L 47/00 - Bulk negative resistance effect devices, e.g. Gunn-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/108 - Dynamic random access memory structures
H01L 29/82 - Types of semiconductor device controllable by variation of the magnetic field applied to the device
77.
Non-volatile memory device and sensing method thereof
A non-volatile memory device and a sensing method thereof are disclosed, which can sense multi-level data using resistance variation. The non-volatile memory device includes a cell array and a sensing unit. The cell array includes a plurality of unit cells where data is read out or written. The sensing unit compares a sensing voltage corresponding to data stored in the unit cell with a reference voltage, amplifies/outputs the compared result, measures a difference in discharge time where the sensing voltage is discharged in response to a resistance value of the unit cell during an activation period of a sensing enable signal after a bit line is precharged, and senses the data in response to the measured result.
A sense-amp transistor for a semiconductor device and a method for manufacturing the same are disclosed. A sense-amp transistor for a semiconductor device includes a recess array formed in a gate region of a sense-amp, a plurality of buried gates formed in each recess of the recess array so as to form a vertical channel region, and an upper gate configured to form a horizontal channel region in an active region between the buried gates. As a result, the number of additional processes is minimized, and the sensing margin of the sense-amp is guaranteed.
A method of manufacturing a semiconductor device is provided. According to an embodiment, the method includes forming a layer to be etched on a semiconductor substrate, and forming a photoresist pattern on the layer to be etched. A block copolymer including a hydrophobic radical and a hydrophilic radical is formed in the photoresist pattern, and the block copolymer is assembled to allow a polymer having the hydrophobic radical to be formed in a pillar pattern within a polymer having the hydrophilic radical. The polymer having the hydrophobic radical is then selectively removed.
A semiconductor memory device selects one of a plurality of memory cells as a dummy memory cell. The dummy memory cell is connected to a bit line that is complementary to a bit line connected to a selected memory cell. This technique advantageously compensates capacitance of the bit line. The semiconductor memory device comprises a selected memory cell connected to a first bit line and a first word line, a dummy memory cell connected to a second bit line complementary to the first bit line and a second word line, and a sense amplifier connected to the first and second bit lines and configured to read data stored in the selected memory cell by simultaneously enablement of the first and second word lines.
G11C 11/24 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using capacitors
A semiconductor cell includes first trenches defining fin type active regions within the semiconductor substrate and adjacent to each other, second trenches disposed at one side and the other side of the first trenches, adjacent to the first trench and including fin type active regions, a first oxide layer formed on each of surfaces of the first trenches, and a second oxide layer formed on each of surfaces of the second trenches and having a thicker thickness than the first oxide layer. Although the critical dimension of the fin is increased, the gate drivability can be improved.
A semiconductor device includes gates formed over a semiconductor substrate that are spaced apart from one another and each have a stack structure of a tunnel insulation layer, a floating gate, a dielectric layer, a first conductive layer, and a metal silicide layer, a first insulation layer formed along the sidewalls of the gates and a surface of the semiconductor substrate between the gates and configured to have a height lower than the top of the metal silicide layer; and a second insulation layer formed along surfaces of the first insulation layer and surfaces of the metal silicide layer and configured to cover an upper portion of a space between the gates, wherein an air gap is formed between the gates.
A semiconductor device containing a cylindrical shaped capacitor and a method for manufacturing the same is presented. The semiconductor device includes a plurality of storage nodes and a support pattern. The plurality of storage nodes is formed over a semiconductor substrate. The support pattern is fixed to adjacent storage nodes in which the support pattern has a flowable insulation layer buried within the support pattern. The buried flowable insulation layer direct contacts adjacent storage nodes.
A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.
A nonvolatile memory device includes a first channel comprising a pair of first pillars vertically extending from a substrate and a first coupling portion positioned under the pair of first pillars and coupling the pair of first pillars, a second channel adjacent to the first channel comprising a pair of second pillars vertically extending from the substrate and a second coupling portion positioned under the pair of second pillars and coupling the pair of second pillars, a plurality of gate electrode layers and interlayer dielectric layers alternately stacked along the first and second pillar portions, and first and second trenches isolating the plurality of gate electrode layers between the pair of first pillar portions and between the pair of second pillar portions, respectively.
A method of manufacturing a semiconductor device includes forming an interlayer dielectric layer, forming trenches by etching the interlayer dielectric layer, forming a copper (Cu) layer to fill the trenches, and implanting at least one of an inert element, a nonmetallic element, and a metallic element onto a surface of the Cu layer.
Semiconductor memory device with high-speed data transmission capability, system having the same includes a plurality of address input circuits and a plurality of data output circuits and a training driver configured to distribute address information input through the plurality of address input circuits together with a data loading signal for a read training, and generate data training patterns to be output through the plurality of data output circuits.
A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices.
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
89.
Method for fabricating an electrostatic discharge protection device
An electrostatic discharge protection device includes a substrate where an active region is defined by an isolation layer, a gate electrode simultaneously crossing both the isolation layer and the active region, and a junction region formed in the active region at both sides of the gate electrode and separated from the isolation layer by a certain distance in a direction where the gate electrode is extended. The electrostatic discharge protection device is able to prevent the increase of a leakage current while securing an electrostatic discharge protection property that a semiconductor device requires.
A semiconductor device includes a first phase detector for detecting a phase of a second clock by comparing the phase of the second clock with the phase of the first clock, a second phase detector for detecting a phase of a clock obtained by delaying the second clock by a set delay amount, a third phase detector for detecting the phase of the second clock by delaying the first clock by the set delay amount, and a phase difference detection signal generator for setting a logic level of a phase difference detection signal corresponding to a phase difference between the first and second clocks detecting that the phase of the first or second clock is changed, and change the logic level of the phase difference detection signal.
A memory device includes a data line sense amplifier configured to receive a sense amplifying power source voltage and a sense amplifying ground voltage through a sense amplifying power source line and a sense amplifying ground line, respectively, and sense-amplify data loaded on a pair of data lines, and a pre-charging unit configured to pre-charge and equalize the sense amplifying power source line and the sense amplifying ground line with a sense amplifying pre-charge voltage, generate the sense amplifying pre-charge voltage by voltage dividing the sense amplifying power source voltage and the sense amplifying ground voltage through a voltage dividing path including the sense amplifying power source line and the sense amplifying ground line, and apply the sense amplifying power source voltage to the sense amplifying power source line and the sense amplifying ground voltage to the sense amplifying ground line in response to a sense amplifying pre-charge control signal.
A semiconductor memory device includes a random address generation unit configured to receive a multi-bit source address and generate a multi-bit random address and a signal mixing unit configured to mix the multi-bit random address with a data, wherein the random address generation unit has a plurality of transmission lines configured to electrically connect the plurality of input terminals respectively corresponding to bits of the source address and the plurality of output terminals respectively corresponding to bits of the random address in one-to-one correspondence regardless of an order of the bits of the source address.
G11C 8/00 - Arrangements for selecting an address in a digital store
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
93.
Multi-test apparatus and method for testing a plurailty of semiconductor chips
An apparatus and method is capable of reducing instantaneously consumed current by allowing write drivers and input buffers not to be simultaneously driven in a multi-test of semiconductor chips. A multi-test apparatus includes an input unit configured to receive data for testing, wherein the data for testing is inputted from a circuit outside of the multi-test apparatus, a plurality of memory banks each including a plurality of memory cells, a plurality of write drivers, corresponding to the respective memory banks, configured to write the test data in the plurality of memory banks, and a write control unit configured to control the plurality of write drivers so that the test data is written in the memory banks in at least two time periods.
A semiconductor memory device includes a bit line sense amplification unit configured to sense/amplify data loaded on a bit line, and a driving control unit configured to supply a power line of the bit line sense amplification unit with an overdriving voltage in an overdriving period and supply an internal voltage line with a voltage of the power line of the bit line sense amplification unit in a discharge driving period.
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
An image sensor includes: a substrate having a plurality of unit pixel region; a light receiving element formed in the substrate at the unit pixel region; an interlayer dielectric layer formed over the substrate; a lightguide formed in the interlayer dielectric layer for the light receiving element; a light focusing pattern formed over the interlayer dielectric layer at the pixel region; a planarization layer formed over the substrate and covering the light focusing pattern; and a lens formed over the planarization layer at the pixel region.
A semiconductor memory device includes at least one first semiconductor chip including a plurality of memory cells and a second semiconductor chip including a fuse circuit configured to repair defective cells among the memory cells of the at least one first semiconductor chip.
G11C 29/04 - Detection or location of defective memory elements
G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
97.
Semiconductor device and semiconductor system including the same
A semiconductor device and a power voltage supply circuit for a test operation of a semiconductor system including the semiconductor device. The semiconductor device receives first and second power supply voltages in a normal operation mode from an external device and receives the first power supply voltage in a test operation mode. The semiconductor device includes a voltage level setting unit configured to set a power connection node at a voltage between a voltage level of a first power supply voltage terminal and a voltage level of a ground voltage terminal according to an operation mode signal, and a voltage driving unit configured to drive a second power supply voltage terminal with the first power supply voltage in the test operation mode, wherein the driving power is controlled according to the voltage level of the power connection node.
H03B 1/00 - GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNERGENERATION OF NOISE BY SUCH CIRCUITS Details
H03K 3/00 - Circuits for generating electric pulsesMonostable, bistable or multistable circuits
G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
G11C 29/48 - Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
A semiconductor memory device includes a plurality of first pads and a plurality of memory unit blocks. The plurality of first pads are configured to input/output data in a test mode. The plurality of memory unit blocks each include a plurality of second pads configured to input/output data in a normal mode, and a plurality of data path selection units configured to connect internal circuits of the corresponding memory unit block to the plurality of first pads or the plurality of second pads in response to a unit block selection flag signal, a write enable signal, a read enable signal, and a mode control signal.
A latency control circuit of a semiconductor device includes a phase detection unit configured to generate phase information regarding a phase difference between an external clock and an internal clock, a delay amount deciding unit configured to decide a latency delay amount based on path information of an input signal, a latency value of the input signal, and the phase information, and a latency delay unit configured to generate a latency signal by delaying the input signal according to the latency delay amount and the phase information to produce a delayed input signal and by synchronizing the delayed input signal with the internal clock.
A method for operating a non-volatile memory device includes selecting a word line of a plurality of word lines in response to a program command and an received address, determining whether the selected word line is a word line set among the word lines, performing an erase operation on a second word line group of the word lines in response to a result of the determining, and performing a program operation on the selected word line.
patents
