A mixed-signal integrated circuit (IC), including: a voltage booster that includes one or more charge pump devices configured to receive an input voltage, an oscillator signal, and a control signal, wherein the one or more charge pump devices comprise a network of capacitors switchable to provide a charged pumped in response to the control signal, and wherein the one or more charge pump devices, using the pumped, generate a boosted voltage based on the input voltage and at least a portion of an amplitude of the oscillator signal, a voltage regulator coupled to the one or more charge pump devices and configured to receive the boosted voltage and generate a regulated boosted voltage based on the boosted voltage, and a control and monitoring engine configured to provide the control signal based on, at least in part, the input voltage, the oscillator signal, and the regulated boosted voltage.
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
A clock device including: an LC network comprising: a first inductive portion; a second inductive portion connected to the first inductive portion; a third inductive portion connected to the second inductive portion; a first capacitive portion connected to the first, the second, and the third inductive portions; and a second capacitive portion connected to the first inductive portion and the third inductive portion, wherein the LC network is configured to simultaneously resonate at a first frequency and a second frequency that is substantially three times the first frequency, and wherein the clock signal is provided between the first and the third inductive portions by combining a first signal component and a second signal component that is a third harmonic of the first signal component and each inflection point of the first signal component is phase aligned with a corresponding inflection point of the second signal component.
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
A clock device including: an LC network comprising: a first inductive portion; a second inductive portion connected to the first inductive portion; a third inductive portion connected to the second inductive portion; a first capacitive portion connected to the first, the second, and the third inductive portions; and a second capacitive portion connected to the first inductive portion and the third inductive portion, wherein the LC network is configured to simultaneously resonate at a first frequency and a second frequency that is substantially three times the first frequency, and wherein the clock signal is provided between the first and the third inductive portions by combining a first signal component and a second signal component that is a third harmonic of the first signal component and each inflection point of the first signal component is phase aligned with a corresponding inflection point of the second signal component.
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
4.
Method and apparatus for low latency charge coupled decision feedback equalization
A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.
A temperature measuring circuit uses a diode to drain a switched capacitor at two different lengths of time. The capacitor's voltage is amplified, measured, and compared for each length of time to calculate a temperature. The circuitry may cancel out errors due to manufacturing tolerances and variations, as well as offset voltages, supply noise, substrate noise, and other issues. The process may charge a capacitor, then drain the capacitor with a diode for a first period of time, at which point, the diode is switched out of the circuit. The remaining charge in the diode may be amplified, then analyzed using an analog to digital converter. A second measurement may be taken with a different period of time, and the two measurements may be subtracted to yield an absolute temperature.
A clock device includes an LC network that has a first inductive portion; a second inductive portion connected to the first inductive portion; a third inductive portion connected to the second inductive portion; a first capacitive portion connected to the first, the second, and the third inductive portions; and a second capacitive portion connected to the first inductive portion and the third inductive portion, wherein the LC network is configured to simultaneously resonate at a first frequency and a second frequency that is substantially three times the first frequency, and wherein the clock signal is provided between the first and the third inductive portions by combining a first signal component and a second signal component that is a third harmonic of the first signal component and each inflection point of the first signal component is phase aligned with a corresponding inflection point of the second signal component.
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
A high speed but power-efficient electronic communications protocol may comprise dual simplex links, each operating in a differential high-speed mode and each capable of a low-speed signaling mode. When both links operate in high speed mode, signaling is performed in-band, with signals embedded as metadata attached to transmitted packets. When one of the links is put into a low-power mode, the return-path signaling may be performed on the two wires previously used for high-speed transmissions. One wire may be used for flow control or other signaling, while the other wire may be used for a wake command, which may initiate the low-power mode to be elevated to a high-speed mode. Multiple lanes may be organized to operate in parallel for each link, allowing for a very high speed communications protocol that may be easily switched into and out of a low-power state without additional sideband wiring.
A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.
A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.
A variable capacitance circuit may operate a Metal Oxide Semiconductor (MOS) transistor or other semiconductor device to switch a capacitor in and out. Several circuits may be combined in a parallel network having offset bias voltages, such that the combined network may produce a variable capacitance over a large voltage range. The variable capacitance circuit may be incorporated into a phase locked loop (PLL) circuit where similar devices may be configured to produce a voltage reference as part of the PLL circuitry. Such a circuit may be immune to temperature, process, or voltage variances, since the current pulse magnitude times the low pass filter resistance times the sensitivity of a controlled voltage oscillator can be held constant.
H03B 5/00 - Generation of oscillations using amplifier with regenerative feedback from output to input
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
H03L 7/00 - Automatic control of frequency or phaseSynchronisation
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A mixed-signal integrated circuit (IC), including: a voltage booster that includes one or more charge pump devices configured to receive an input voltage, an oscillator signal, and a control signal, wherein the one or more charge pump devices comprise a network of capacitors switchable to provide a charged pumped in response to the control signal, and wherein the one or more charge pump devices, using the pumped, generate a boosted voltage based on the input voltage and at least a portion of an amplitude of the oscillator signal, a voltage regulator coupled to the one or more charge pump devices and configured to receive the boosted voltage and generate a regulated boosted voltage based on the boosted voltage, and a control and monitoring engine configured to provide the control signal based on, at least in part, the input voltage, the oscillator signal, and the regulated boosted voltage.
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
12.
METHOD AND CIRCUITS TO PROVIDE HIGHER SUPPLY VOLTAGE FOR ANALOG COMPONENTS FROM LOWER SUPPLY VOLTAGES
A mixed-signal integrated circuit (IC), including: a voltage booster that includes one or more charge pump devices configured to receive an input voltage, an oscillator signal, and a control signal, wherein the one or more charge pump devices comprise a network of capacitors switchable to provide a charged pumped in response to the control signal, and wherein the one or more charge pump devices, using the pumped, generate a boosted voltage based on the input voltage and at least a portion of an amplitude of the oscillator signal, a voltage regulator coupled to the one or more charge pump devices and configured to receive the boosted voltage and generate a regulated boosted voltage based on the boosted voltage, and a control and monitoring engine configured to provide the control signal based on, at least in part, the input voltage, the oscillator signal, and the regulated boosted voltage.
A mixed-signal integrated circuit (IC), including: a voltage booster that includes one or more charge pump devices configured to receive an input voltage, an oscillator signal, and a control signal, wherein the one or more charge pump devices comprise a network of capacitors switchable to provide a charged pumped in response to the control signal, and wherein the one or more charge pump devices, using the pumped, generate a boosted voltage based on the input voltage and at least a portion of an amplitude of the oscillator signal, a voltage regulator coupled to the one or more charge pump devices and configured to receive the boosted voltage and generate a regulated boosted voltage based on the boosted voltage, and a control and monitoring engine configured to provide the control signal based on, at least in part, the input voltage, the oscillator signal, and the regulated boosted voltage.
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
14.
METHOD AND CIRCUITS FOR REDUCING NOISE IN PHASE-LOCKED LOOPS
A phase locked loop (PLL) includes: a phase frequency detector configured to: generate one or more comparison signals indicating whether a reference input signal is leading a feedback signal or whether the feedback signal is leading the reference input signal; a charge pump coupled to the phase frequency detector and configured to convert the one or more comparison signals into a driving current; a loop filter coupled to the charge pump and configured to split the driving current to generate a first voltage signal and a second voltage signal; and a voltage controlled oscillator coupled to the loop filter and configured to: receive the first voltage signal and generate a first control current; receive the second voltage signal and generate a second control current; and combine the first and second control currents to jointly drive a charge controlled oscillator such that the output signal of a desired frequency is generated.
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
15.
Method and circuits for fine-controlled phase/frequency offsets in phase-locked loops
Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate a VCO clock signal, multiple divider configured to receive the VCO clock signal and frequency divide the VCO clock signal in stages to generate a series statically divided VCO clock signals and a dynamically divided VCO clock signal; a feedback portion including a first component configured to receive the dynamically divided VCO clock signal and generate indicator signals; and a second component configured to multiplex from the indicator signals to generate the feedback clock signal set for the PFD and CP portion; and a master phase/frequency control engine configured to assert a division control over at least one divider and a multiplex control over the multiplex network.
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
16.
Method and circuits to provide higher supply voltage for analog components from lower supply voltages
A mixed-signal integrated circuit (IC), including: a voltage booster that includes one or more charge pump devices configured to receive an input voltage, an oscillator signal, and a control signal, wherein the one or more charge pump devices comprise a network of capacitors switchable to provide a charged pumped in response to the control signal, and wherein the one or more charge pump devices, using the pumped, generate a boosted voltage based on the input voltage and at least a portion of an amplitude of the oscillator signal, a voltage regulator coupled to the one or more charge pump devices and configured to receive the boosted voltage and generate a regulated boosted voltage based on the boosted voltage, and a control and monitoring engine configured to provide the control signal based on, at least in part, the input voltage, the oscillator signal, and the regulated boosted voltage.
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
17.
PASSIVE LINEAR EQUALIZER FOR SERIAL WIRELINE RECEIVERS
Some implementations provide a passive equalizer section configured to filter an input signal, the passive equalizer section including: a first passive filter that comprises: a first resistor characterized by a first resistance, and a first reactive component characterized by a first reactance, wherein the first resistor and the first reactive component are in series and connected at a first connection node; and a second passive filter that comprises: a second resistor characterized by a second resistance, and a second reactive component characterized by a second reactance, wherein the second resistor and the second reactive component are in series and connected at a second connection node; and a signal mixing section comprising a plurality of transistors to mix signals with different frequency response characteristics.
Some implementations provide a passive equalizer section configured to filter an input signal, the passive equalizer section including: a first passive filter that comprises: a first resistor characterized by a first resistance, and a first reactive component characterized by a first reactance, wherein the first resistor and the first reactive component are in series and connected at a first connection node; and a second passive filter that comprises: a second resistor characterized by a second resistance, and a second reactive component characterized by a second reactance, wherein the second resistor and the second reactive component are in series and connected at a second connection node; and a signal mixing section comprising a plurality of transistors to mix signals with different frequency response characteristics.
Implementations provide a receiver circuit that includes: an alternate current (AC)-coupling network to filter an input signal, the AC-coupling network including a first RC filter connected between a first input node and a first common node and a second RC filter connected between a second input node and the first common node; a differential amplifier coupled to the AC-coupling network and configured to receive a filtered input signal from the AC-coupling network and generate an output signal, the differential amplifier including a differential pair of transistors and a common-mode measurement network coupled to source terminals of a first and a second transistors in the differential pair; and a first operational amplifier having an input coupled to output terminal of the common-mode measurement network and an output coupled to the first common node.
Implementations provide a receiver circuit that includes: an alternate current (AC)- coupling network to filter an input signal, the AC-coupling network including a first RC filter connected between a first input node and a first common node and a second RC filter connected between a second input node and the first common node; a differential amplifier coupled to the AC-coupling network and configured to receive a filtered input signal from the AC-coupling network and generate an output signal, the differential amplifier including a differential pair of transistors and a common-mode measurement network coupled to source terminals of a first and a second transistors in the differential pair; and a first operational amplifier having an input coupled to output terminal of the common-mode measurement network and an output coupled to the first common node.
A phase locked loop (PLL) includes: a phase frequency detector configured to: generate one or more comparison signals indicating whether a reference input signal is leading a feedback signal or whether the feedback signal is leading the reference input signal; a charge pump coupled to the phase frequency detector and configured to convert the one or more comparison signals into a driving current; a loop filter coupled to the charge pump and configured to split the driving current to generate a first voltage signal and a second voltage signal; and a voltage controlled oscillator coupled to the loop filter and configured to: receive the first voltage signal and generate a first control current; receive the second voltage signal and generate a second control current; and combine the first and second control currents to jointly drive a charge controlled oscillator such that the output signal of a desired frequency is generated.
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
A phase lock loop (PLL) includes: a binary phase detector configured to generate a first and second polarity signals that respectively indicating whether an incoming data stream is leading a feedback signal, or whether the feedback signal is leading the incoming data stream, wherein a difference between the first and second polarity signals does not represent an amount of phase difference between the incoming data stream and the feedback signal; a digital filter configured to: generate filtered first polarity signal on a first path and a second path that are different; and generate filtered second polarity signal on a third path and a fourth path that are different; a charge pump coupled to the digital filter and configured to: integrate the filtered first polarity signal and the filtered second polarity signal; and an oscillator configured to generate the synthesized clock signal serving as the feedback signal.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H04L 7/00 - Arrangements for synchronising receiver with transmitter
23.
Method and circuits for charge pump devices of phase-locked loops
A charge pump includes: (I) a current source; (II) a p-channel source current network including: a first p-channel transistor; a second p-channel transistor; a p-channel current switch including at least one source terminal coupled to the drain terminal of the first p-channel transistor, at least one gate coupled to a phase comparator, and at least one drain terminal; a third p-channel transistor; and (III) a n-channel sink current network including: a first n-channel transistor; a second n-channel transistor; a third n-channel transistor; a n-channel current switch comprising at least one drain terminal coupled to the source terminal of the third n-channel transistor, at least one gate coupled to the phase comparator; and at least one source terminal coupled to the drain terminal of the first n-channel transistor; and wherein the p-channel source current network and the n-channel sink current network draw a baseline current from the first p-channel transistor.
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
24.
Method and circuits for fine-controlled phase/frequency offsets in phase-locked loops
Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate a VCO clock signal, multiple divider configured to receive the VCO clock signal and frequency divide the VCO clock signal in stages to generate a series statically divided VCO clock signals and a dynamically divided VCO clock signal; a feedback portion including a first component configured to receive the dynamically divided VCO clock signal and generate indicator signals; and a second component configured to multiplex from the indicator signals to generate the feedback clock signal set for the PFD and CP portion; and a master phase/frequency control engine configured to assert a division control over at least one divider and a multiplex control over the multiplex network.
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
25.
METHOD AND CIRCUITS FOR FINE-CONTROLLED PHASE/FREQUENCY OFFSETS IN PHASE-LOCKED LOOPS
Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate a VCO clock signal, multiple divider configured to receive the VCO clock signal and frequency divide the VCO clock signal in stages to generate a series statically divided VCO clock signals and a dynamically divided VCO clock signal; a feedback portion including a first component configured to receive the dynamically divided VCO clock signal and generate indicator signals; and a second component configured to multiplex from the indicator signals to generate the feedback clock signal set for the PFD and CP portion; and a master phase/frequency control engine configured to assert a division control over at least one divider and a multiplex control over the multiplex network.
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
26.
Method and circuits for fine-controlled phase/frequency offsets in phase-locked loops
Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate a VCO clock signal, multiple divider configured to receive the VCO clock signal and frequency divide the VCO clock signal in stages to generate a series statically divided VCO clock signals and a dynamically divided VCO clock signal; a feedback portion including a first component configured to receive the dynamically divided VCO clock signal and generate indicator signals; and a second component configured to multiplex from the indicator signals to generate the feedback clock signal set for the PFD and CP portion; and a master phase/frequency control engine configured to assert a division control over at least one divider and a multiplex control over the multiplex network.
H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
A phase lock loop (PLL) includes: a binary phase detector configured to generate a first and second polarity signals that respectively indicating whether an incoming data stream is leading a feedback signal, or whether the feedback signal is leading the incoming data stream, wherein a difference between the first and second polarity signals does not represent an amount of phase difference between the incoming data stream and the feedback signal; a digital filter configured to: generate filtered first polarity signal on a first path and a second path that are different; and generate filtered second polarity signal on a third path and a fourth path that are different; a charge pump coupled to the digital filter and configured to: integrate the filtered first polarity signal and the filtered second polarity signal; and an oscillator configured to generate the synthesized clock signal serving as the feedback signal.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
28.
METHOD AND CIRCUITS FOR CHARGE PUMP DEVICES OF PHASE-LOCKED LOOPS
A charge pump includes: (I) a current source; (II) a p-channel source current network including: a first p-channel transistor; a second p-channel transistor; a p-channel current switch including at least one source terminal coupled to the drain terminal of the first p-channel transistor, at least one gate coupled to a phase comparator, and at least one drain terminal; a third p-channel transistor; and (III) a n-channel sink current network including: a first n-channel transistor; a second n-channel transistor; a third n-channel transistor; a n-channel current switch comprising at least one drain terminal coupled to the source terminal of the third n-channel transistor, at least one gate coupled to the phase comparator; and at least one source terminal coupled to the drain terminal of the first n-channel transistor; and wherein the p-channel source current network and the n-channel sink current network draw a baseline current from the first p-channel transistor.
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
29.
Method and circuits for charge pump devices of phase-locked loops
A charge pump includes: (I) a current source; (II) a p-channel source current network including: a first p-channel transistor; a second p-channel transistor; a p-channel current switch including at least one source terminal coupled to the drain terminal of the first p-channel transistor, at least one gate coupled to a phase comparator, and at least one drain terminal; a third p-channel transistor; and (III) a n-channel sink current network including: a first n-channel transistor; a second n-channel transistor; a third n-channel transistor; a n-channel current switch comprising at least one drain terminal coupled to the source terminal of the third n-channel transistor, at least one gate coupled to the phase comparator; and at least one source terminal coupled to the drain terminal of the first n-channel transistor; and wherein the p-channel source current network and the n-channel sink current network draw a baseline current from the first p-channel transistor.
H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
A phase lock loop (PLL) includes: a binary phase detector configured to generate a first and second polarity signals that respectively indicating whether an incoming data stream is leading a feedback signal, or whether the feedback signal is leading the incoming data stream, wherein a difference between the first and second polarity signals does not represent an amount of phase difference between the incoming data stream and the feedback signal; a digital filter configured to: generate filtered first polarity signal on a first path and a second path that are different; and generate filtered second polarity signal on a third path and a fourth path that are different; a charge pump coupled to the digital filter and configured to: integrate the filtered first polarity signal and the filtered second polarity signal; and an oscillator configured to generate the synthesized clock signal serving as the feedback signal.
H03L 7/097 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a comparator for comparing the voltages obtained from two frequency to voltage converters
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
A phase lock loop (PLL) includes: a binary phase detector configured to generate a first and second polarity signals that respectively indicating whether an incoming data stream is leading a feedback signal, or whether the feedback signal is leading the incoming data stream, wherein a difference between the first and second polarity signals does not represent an amount of phase difference between the incoming data stream and the feedback signal; a digital filter configured to: generate filtered first polarity signal on a first path and a second path that are different; and generate filtered second polarity signal on a third path and a fourth path that are different; a charge pump coupled to the digital filter and configured to: integrate the filtered first polarity signal and the filtered second polarity signal; and an oscillator configured to generate the synthesized clock signal serving as the feedback signal.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
32.
ENCODER/DECODER FOR BALANCED TRANSMISSION OF VARIABLES OVER FEW MULTI-VARIABLE CHANNELS
A method is described for encoding N variables onto less than 2N channels by forming a respective signal for each of the channels by combining inverted and/or non inverted forms of the variables, such that, each of the N variables is balanced across the channels, and, combination on any particular channel is not the polar opposite of a combination on any other channel.
patents
