Abstract

A semiconductor integrated circuit device and a manufacturing method therefor are provided. The semiconductor integrated circuit device includes a resistance layer, a first electrode and a second electrode which are respectively disposed at two sides of the resistance layer. The resistance layer is a layer of thin film covering a protruding block, the first electrode is either a part of the protruding block or is connected with a lower end of the protruding block, the second electrode is disposed above the resistance layer, and forms full coverage for the resistance layer, and the first electrode and the second electrode are enabled to form a conductive filament on a side wall of the resistance layer in a manner of arranging a first insulation layer above the first electrode. The resistance layer covers the protruding block, and the conductive filament is formed on the side wall of the resistance layer.

IPC Classes  ?

• H10N 70/20 - Multistable switching devices, e.g. memristors
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

A semiconductor structure and a preparation method thereof are provided. The semiconductor structure includes: a substrate; and a plurality of resistive devices, disposed on the substrate; each of the resistive devices includes a lower electrode, a resistive layer and an upper electrode, a groove is formed in the lower electrode to form a concave structure, the resistive layer covers a side wall and a bottom of the groove and an outer surface of the lower electrode, and the upper electrode covers a surface of the resistive layer and fills the groove.

IPC Classes  ?

• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

The present disclosure provides a semiconductor structure and a preparation method therefor. The semiconductor structure comprises a substrate and a plurality of resistive devices located on the substrate. Each resistive device comprises: a lower electrode located on the substrate; a plurality of resistive layers respectively located on the periphery of the lower electrode and in contact with side walls of the lower electrode; and a plurality of upper electrodes wrapped by the resistive layers and isolated from the lower electrode by means of the resistive layers.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

A data processing method and apparatus, an electronic device, and a storage medium are provided. The method includes: obtaining to-be-processed array data; performing first mapping on the to-be-processed array data to obtain target array data, and determining a weight corresponding to each target data in the target array data during the first mapping; performing multiplier and accumulation operation on the target data according to a first or second rule to obtain a first and second operation values; performing analog-to-digital conversion on the first operation value and the second operation value to obtain a first quantized value and a second quantized value, respectively; performing second mapping on the first quantized value and the second quantized value based on the weights to obtain a third quantized value and a fourth quantized value; and summing the third quantized value and the fourth quantized value to obtain a target output value.

IPC Classes  ?

• G06F 17/16 - Matrix or vector computation
• G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
• H03M 1/12 - Analogue/digital converters

Abstract

A method for operating a memory apparatus, a memory apparatus, a device, and a storage medium are provided. The method includes: providing a semiconductor device including a substrate, a deep N-well region disposed in the substrate, a P-well region disposed in the deep N-well region, and a plurality of transistor structures disposed in the P-well region, where each of the transistor structures includes a gate, a source and a drain; and applying a first voltage to a port of the gate, a second voltage to a port of the deep N-well region, and a third voltage to a port of the P-well region. When a first operation is performed, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a negative voltage; when a second operation is performed, the first, second and third voltages are positive voltages.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

A semiconductor structure and a preparation method thereof are provided. The semiconductor structure includes: a substrate; and a plurality of resistive devices disposed on the substrate; each of the resistive devices includes a lower electrode, a resistive layer and an upper electrode, the resistive layer covers a side wall and at least part of an upper surface of the lower electrode to isolate the lower electrode from the upper electrode, the upper electrode includes a first upper sub-electrode, a second upper sub-electrode and a third upper sub-electrode, the first upper sub-electrode and the second upper sub-electrode are disposed on two sides of the lower electrode respectively, and the third upper sub-electrode is disposed on the lower electrode.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

A chip testing method and apparatus are provided, and the method includes: providing a plurality of chips, each of the chips including an input pin, an output pin, and a state machine circuit; connecting the input pin of each of the chips to a same input start module which outputs a start signal to each of the chips to start the state machine circuits; configuring the state machine circuit of each of the chips to output a test excitation to test the chips and obtain a test result; and connecting the output pin of each of the chips to a same testing module which outputs the test result of each of the chips.

IPC Classes  ?

• G01R 31/317 - Testing of digital circuits
• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning

Abstract

A method and apparatus for initializing an RRAM and an electronic device are provided. The method includes: inputting a plurality of pulses of a first voltage into an RRAM until memory cells in the RRAM transition from a high resistance state to a low resistance state; inputting a plurality of pulses of a second voltage, a third voltage . . . and an Nth voltage into the RRAM, so that resistance values of the memory cells reach a corresponding preset value, respectively. Voltage values of the first voltage to the Nth voltage gradually decrease. When a total number of input pulses of an ith voltage is greater than a second preset threshold and a resistance change rate is less than a rate threshold, a plurality of pulses of an increased ith voltage are input into the RRAM until the resistance values of the memory cells reach an ith preset value.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

The present disclosure provides a semiconductor structure and a preparation method therefor. The semiconductor structure comprises: a substrate; a plurality of resistive devices arranged in an array on the substrate along a first direction and a second direction, wherein the first direction and the second direction are directions parallel to the plane of the substrate, and the first direction intersects with the second direction, and the resistive devices and the first direction are at a preset angle; and a plurality of first metal layers located above the resistive devices and extending in the first direction.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

Disclosed is a memory read-write verification method. Firstly, margin verify is carried out on all input/output (IO) of the memory according to input data, readout data corresponding to each piece of the IO is acquired according to a verify result, and whether to execute a write operation on the IO corresponding to the readout data is determined according to the readout data. Then, the write operation is executed on IO on which the write operation is required to be executed. Finally, the margin verify is carried out again after the write operation is completed, and whether write-in of corresponding IO succeeds is determined according to a verify result. Thus, rewrite-in can be avoided, and verify efficiency can be improved.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

Disclosed in the present application are a data processing method and apparatus, an electronic device and a storage medium. The method comprises: obtaining array data to be processed; performing first mapping processing on said array data to obtain target array data, and determining weightings corresponding to each piece of target data among the target array data during the first mapping processing; according to a first rule, performing multiply-accumulate operation processing on the target data having the weighting of 1 to obtain a first operation value; according to a second rule of multiplying the same column by the same value, performing multiply-accumulate operation processing on the target data of which the weighting is not 1 so as to obtain a second operation value; separately performing analog-to-digital conversion processing on the first operation value and the second operation value to obtain a first quantized value and a second quantized value; on the basis of the weightings, performing second mapping processing on the first quantized value and the second quantized value to obtain a third quantized value and a fourth quantized value; and adding the third quantized value and the fourth quantized value to obtain a target output value.

IPC Classes  ?

• G06G 7/16 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for multiplication or division
• G16H 50/70 - ICT specially adapted for medical diagnosis, medical simulation or medical data miningICT specially adapted for detecting, monitoring or modelling epidemics or pandemics for mining of medical data, e.g. analysing previous cases of other patients

Abstract

Provided in the present disclosure are an operation method for a memory apparatus, and a memory apparatus, a device and a storage medium. The operation method for a memory apparatus comprises: providing a semiconductor device, which comprises: a substrate, a deep N-well region located in the substrate, a P-well region located in the deep N-well region, and a plurality of transistor structures located in the P-well region, wherein each of the transistor structures comprises a gate, and a source and a drain that are located at two sides of the gate respectively; and applying a first voltage to a port of the gate, applying a second voltage to a port of the deep N-well region, and applying a third voltage to a port of the P-well region, wherein when a first operation is executed, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a negative voltage; and when a second operation is executed, the first voltage is a positive voltage, the second voltage is a positive voltage, and the third voltage is a positive voltage.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

The disclosure discloses a data writing operation method and device of a resistive random access memory, and the method includes: applying a first pulse voltage to the resistive random access memory, and adding one to a corresponding number to obtain a first number; if the current first number is greater than a first set upper limit value and a current second number is smaller than or equal to a second set upper limit value, obtaining a test value; if the test value does not satisfy a preset condition, applying a second pulse voltage to the resistive random access memory, and adding one to the corresponding number to obtain a second number until the test value satisfies the preset condition or the current second number is greater than the second set upper limit value, thereby improving the writing efficiency.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

A memory cell group and a manufacturing method therefor are provided. The memory cell group includes: a first resistive memory cell and a second resistive memory cell. The first resistive memory cell includes a first electrode, a first resistive layer and a second electrode, the first electrode is connected to a first line through a first metal layer, the second electrode is connected to a second line, and the first line and the second line together achieve independent control over the first resistive memory cell. The second resistive memory cell includes the second electrode, a second resistive layer and a third electrode, the third electrode is connected to a third line through a second metal layer, and the third line and the second line together achieve independent control over the second resistive memory cell. The first and second resistive memory cells share the second electrode.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

Disclosed in the present application are an initialization method for a resistive random access memory, an apparatus, and an electronic device. The method comprises: inputting into a resistive random access memory a plurality of pulses under a first voltage until a storage unit in the resistive random access memory is suddenly changed from a high-resistance state into a low-resistance state; sequentially inputting into the resistive random access memory a plurality of pulses under a second voltage, a plurality of pulses under a third voltage, ... , a plurality of pulses under an Nth voltage, such that the resistance value of the storage unit in the resistive random access memory separately reaches a second preset value, a third preset value, ... , and an Nth preset value, the voltage values of the first voltage, the second voltage, the third voltage, ... , the Nth voltage gradually decreasing; if the total number of pulses under the input ith voltage is greater than a second preset threshold and the rate of resistance change is less than a rate threshold, increasing the ith voltage, and inputting into the resistive random access memory a plurality of pulses under the increased ith voltage until the resistance value of the storage unit in the resistive random access memory reaches an ith preset value.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

A semiconductor device and a manufacturing method therefor are provided. The method includes: depositing a first dielectric layer material on a semiconductor substrate, and etching the first dielectric layer material to form a trench corresponding to each via in the semiconductor substrate in a first dielectric layer; the via being filled with a metal material; depositing a bottom electrode material in the trench, and etching the bottom electrode material to form a bottom electrode covering a bottom of the trench; depositing a resistive layer material to form a resistive layer covering an upper surface of the bottom electrode and a sidewall of the trench; and depositing a top electrode material in a groove of the resistive layer, such that the groove is filled with the top electrode material to form a top electrode which is arranged in the groove and fills the groove.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

Provided in the present disclosure is a memory array. The memory array comprises at least one main array and at least one dummy array, wherein the main array is arranged adjacent to the dummy array; at least one resistive random access memory cell of the dummy array shares the same bit line with a resistive random access memory cell of the adjacent main array; and the size of the at least one resistive random access memory cell of the dummy array is greater than the size of the resistive random access memory cell of the adjacent main array. Since a greater size of the resistive random access memory cell corresponds to a lower forming voltage, it is easier to convert from a high-resistance state into a low-resistance state; and in two adjacent resistive random access memory cells, when one of which is in the low-resistance state, the other one cannot be in the high-resistance state. Therefore, an initial state of the resistive random access memory cell of the main array can be the high-resistance state, thereby improving the yield of the memory array.

IPC Classes  ?

• G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array

Abstract

A semiconductor integrated circuit device includes a resistive layer having a trench-like structure with an upward opening, a first electrode located on an outer side of the resistive layer, and a second electrode located on an inner side of the resistive layer; the first electrode and the second electrode are opposite to each other on two sides of a sidewall of the resistive layer; and the resistive layer, the first electrode and the second electrode form a first memory cell. A manufacturing method includes forming a first electrode on a substrate, the substrate including a first via connected with a first metal layer; etching a recess in the first electrode at a position staggered from the first via and forming a resistive layer in the recess; and forming a second electrode in the opening of the resistive layer to obtain a first memory cell.

IPC Classes  ?

• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

Disclosed in embodiments of the present application are a linear resistive element and a preparation method therefor. The linear resistive element includes a substrate unit, a function unit and an electrode unit. The substrate unit includes a substrate layer, which is configured to connect the function unit and the electrode unit. The electrode unit includes a first electrode and a second electrode. The first and second electrodes are deposited on the substrate layer, and the function unit is connected between the first and second electrodes. The function unit includes first dielectric layers and resistive layers. The first dielectric layers and the resistive layers are deposited on the substrate layer in an alternately stacked manner. A number of the resistive layers is at least two, and a conductive filament for conductively connecting the first and second electrodes is formed in each of the resistive layers.

IPC Classes  ?

• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

Disclosed in the present application are a semiconductor device and a manufacturing method therefor. The manufacturing method comprises: sequentially depositing a first barrier layer and a first dielectric layer in an array of a metal substrate; etching first through holes in the first barrier layer and the first dielectric layer in the array, depositing lower electrodes in the first through holes, and carrying out planarization treatment to make the upper surfaces of the lower electrodes flush with the upper surface of the first dielectric layer; sequentially depositing a resistive layer and a second barrier layer on the upper surface of the first dielectric layer and the upper surfaces of the lower electrodes in the array; depositing a second dielectric layer on the second barrier layer in the array; etching second through holes and wiring ducts, which are in communication with each other, in layers on the resistive layer in the array, wherein the bottoms of the second through holes are in communication with the resistive layer, and the tops of the second through holes are in communication with the wiring ducts; and sequentially depositing oxygen capture layers and upper electrodes in the second through holes and the wiring ducts, and then filling metal wires. The problems of easy deformation of the contours of existing stacked resistive structures and bridging of metal wires can be avoided.

IPC Classes  ?

• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

A semiconductor device and a manufacturing method therefor. The semiconductor device has the following configurations: a fin (20) is perpendicular to an upper surface of a substrate (10); a resistive structure is located on a side wall of the fin (20), and consists of a vertical portion (31) of a bottom electrode (30), a vertical portion (41) of a resistive layer (40) and a vertical portion (51) of a top electrode (50); and a resistive region is a region where the vertical portion (31) of the bottom electrode (30) overlaps the vertical portion (51) of the top electrode (50). The size of the resistive region is calculated according to the area of the resistive region in a vertical direction, and if the size of the resistive structure is required to be adjusted, only the height of the fin (20) needs to be adjusted. Therefore, on the basis of the resistive structure of the fin (20), the size of the resistive region thereof is not related to the area of the substrate occupied thereby, such that reduction in the resistive structure can be realized, and the size of the resistive region can be adjusted and controlled.

IPC Classes  ?

• H10N 70/20 - Multistable switching devices, e.g. memristors
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

The present application discloses a semiconductor integrated circuit device and a manufacturing method therefor. According to the semiconductor integrated circuit device, by controlling the number of times of etching and the etching depth in each etching when performing etching to form a side wall layer, the top of the side wall layer is lower than the top of an upper electrode and/or the bottom of the side wall layer is higher than the bottom of a lower electrode as far as possible while it is ensured that the side wall layer covers a resistive switching layer, thereby forming an optimized structure. When the top of the side wall layer is lower than the top of the upper electrode, a deposition space having a wide upper portion and a narrow lower portion can be formed, thereby reducing holes formed during the deposition of a dielectric layer; and when the bottom of the side wall layer is higher than the bottom of the lower electrode, the lower electrode can form a structure having a narrow upper portion and a wide lower portion, so as to better support the resistive switching layer and the upper electrode, thereby making the structure of an entire element more stable. Therefore, the semiconductor integrated circuit device can more easily meet miniaturization requirements, and has better quality.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

Disclosed in the present application are a semiconductor integrated circuit device and a manufacturing method therefor. The semiconductor integrated circuit device comprises a resistive switching layer, and a first electrode and a second electrode that are respectively located on two sides of the resistive switching layer, wherein the resistive switching layer is a layer of film covering a protruding block; the first electrode is a part of the protruding block or is connected to the lower end of the protruding block; the second electrode is located above the resistive switching layer and fully covers the resistive switching layer; and a first insulating layer is provided above the first electrode, so that the first electrode and the second electrode form conductive filaments on the side wall of the resistive switching layer. The resistive switching layer covers the protruding block, and the conductive filaments are formed on the side wall of the resistive switching layer, so that the area of a resistive switching region can be multiplied by increasing the height of the protruding block. In addition, the second electrode fully covers the resistive switching layer, so that the area of the resistive switching region can be further maximized, thereby greatly reducing a forming voltage of the conductive filaments and a plasma induced damage (PID) effect.

IPC Classes  ?

• H10N 99/00 - Subject matter not provided for in other groups of this subclass

Abstract

Disclosed in the present invention is a memory read-write verification method, comprising: firstly, performing margin verification on all IOs of a memory according to input data, and according to a verification result, acquiring read-out data corresponding to each IO, so as to determine, according to the read-out data, whether to execute a write operation on an IO corresponding to the read-out data; then executing a write operation on the IO on which the write operation needs to be executed; and finally, after the execution of the write operation is completed, performing margin verification again so as to determine, according to the verification result, whether the corresponding IO is successfully written. Therefore, repeated writing can be avoided, thereby improving the verification efficiency.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• G11C 7/24 - Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writingStatus cellsTest cells

Abstract

The present disclosure provides a semiconductor integrated circuit device and a manufacturing method therefor. In the device, an electrode in a resistive random-access memory (RRAM) cell is directly connected to a metal layer, thereby omitting the steps of filling a connection via with other metal materials (such as tungsten) and of polishing. The manufacturing process is hence simplified, and different degrees of depressions caused by polishing are correspondingly reduced. The uniformity of resistive performance of the RRAM and the quality of the semiconductor integrated circuit device are hence greatly improved. In addition, a resistive layer having a trench structure is formed by using a trench where an original connection via is located, thereby embedding the entire RRAM cell into the trench. The structure of the RRAM cell is more compact, a gap between RRAM cells is smaller, and the requirements for miniaturization and high density can thus be better met.

IPC Classes  ?

• H10N 70/20 - Multistable switching devices, e.g. memristors
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

A semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a semiconductor substrate; a bottom electrode metal layer and a top electrode metal layer located on the semiconductor substrate; a resistive layer located between the bottom electrode metal layer and the top electrode metal layer, where the transverse width of the resistive layer is greater than the transverse width of the bottom electrode metal layer and/or the top electrode metal layer, and the resistive layer has a variable resistance; an oxygen barrier layer located between the bottom electrode metal layer and the top electrode metal layer, where the oxygen barrier layer is located above the resistive layer; and an oxygen grasping layer located between the bottom electrode metal layer and the top electrode metal layer, where the transverse width of the oxygen grasping layer is less than the transverse width of the resistive layer.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

A semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a semiconductor substrate; a bottom electrode metal layer located in the semiconductor substrate and a top electrode metal layer located on the semiconductor substrate; a resistive layer located between the bottom electrode metal layer and the top electrode metal layer, where the resistive layer has a variable resistance; a first oxygen grasping layer located between the bottom electrode metal layer and the top electrode metal layer, where the first oxygen grasping layer is located above the resistive layer; a second oxygen grasping layer located in the bottom electrode metal layer, where upper surfaces of the semiconductor substrate, the bottom electrode metal layer, and the second oxygen grasping layer are flush, and the resistive layer covers the semiconductor substrate, the bottom electrode metal layer, and the second oxygen grasping layer.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

The present application discloses a memory cell group and a manufacturing method therefor. According to the memory cell group, an upper resistive memory cell and a lower resistive memory cell share an electrode, and share a line by means of the electrode, and then are connected to different lines by means of another non-shared electrode, so that two resistive memory units which are overlapped up and down but can be independently controlled are implemented. On one hand, the memory cell group can form a 1T2R memory cell array, and the number of the memory cells can be greatly increased on the premise that the number of transistors is not increased, so that the storage capacity of a system is improved; on the other hand, by sharing one electrode, the space of one electrode can be saved, and the requirement for element miniaturization is better met. In addition, in an array having the same element integration level, the length of a wire can be halved by means of a double-layer stacked structure, so that the IR drop is greatly reduced.

IPC Classes  ?

• H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier

Abstract

A semiconductor device and a manufacturing method therefor. The manufacturing method comprises: depositing a first dielectric layer material on a semiconductor substrate (10), and etching the first dielectric layer material, such that a trench corresponding to each through hole (11) in the semiconductor substrate (10) is formed in the first dielectric layer material; filling the through hole (11) with a metal material; depositing a bottom electrode material in the trench, and etching the bottom electrode material, so as to form a bottom electrode (30) covering the bottom of the trench; depositing a resistive layer material, so as to form a resistive layer (40) covering an upper surface of the bottom electrode (30) and a side wall of the trench; and depositing a top electrode material in a groove of the resistive layer (40), such that the groove is filled with the top electrode material, so as to form a top electrode (50) which is located in the groove and fills the groove.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

Disclosed in the present application are a semiconductor integrated circuit device and a manufacturing method therefor. The structure used by the semiconductor integrated circuit device involves first electrodes being connected to resistive layers on side walls of the resistive layers, and being connected out from inner sides of the resistive layers by means of second electrodes, such that conductive filaments are formed on the side walls of the resistive layers after a voltage is applied. In this way, a resistive occurrence region can be reduced by means of reducing the height of a first electrode, such that an electric field is applied to resistive layers in a more centralized manner during an electrical operation process, thereby improving the uniformity of a device. In addition, resistive regions are located on side walls of the resistive layers, are formed by means of deposition, are not etched, and also have no damage caused by etching; moreover, the resistive regions being located on the side walls of the resistive layers can also prevent the problem of the resistive layers being uneven due to the recess of vias; thus, the performance of the resistive layers can be better, and the service life thereof can be longer.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
• H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier

Abstract

Disclosed in the embodiments of the present application are a linear resistance variation element and a preparation method therefor. The linear resistance variation element comprises a substrate unit, a functional unit and an electrode unit, wherein the substrate unit comprises a substrate layer, and the substrate layer is used for allowing the functional unit and the electrode unit to be connected; the electrode unit comprises a first electrode and a second electrode, the first electrode and the second electrode are deposited on the substrate layer, and the functional unit is connected between the first electrode and the second electrode; the functional unit comprises a first dielectric layer and resistance variation layers, and the first dielectric layer and the resistance variation layers are deposited on the substrate layer in an alternately stacked manner; and at least two resistance variation layers are provided, and a conductive wire for conductively connecting the first electrode to the second electrode is formed on the resistance variation layers.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

Disclosed in the present application are a semiconductor integrated circuit device and a manufacturing method therefor. By means of the semiconductor integrated circuit device, a resistance variation layer covers an outer side of a bump structure, and the layer cannot be damaged by an etching process during a process preparation procedure thereof, thereby avoiding the possibility of a strong and single conductive filament being formed due to damage by the etching process during an electrical operation procedure. In addition, a thermal enhanced layer (TEL) that completely covers the semiconductor integrated circuit device is added to the device, such that a plurality of weakly conductive filaments are formed more easily in the device, thereby achieving the aim of regulating a pulse to control a continuous change in conductance; furthermore, the semiconductor integrated circuit device can be better used as an analog-type memory, so as to be applied to scenarios such as CIM.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
• H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier

Abstract

An integrated circuit and an electronic device, and provides an integrated circuit having better area efficiency. The integrated circuit may be a resistive random access memory, which includes a plurality of resistive memory cells arranged in row and column directions; each resistive memory cell includes a resistive switching unit and a switch unit coupled to the resistive switching unit; the resistive switching units in the column direction are respectively coupled to corresponding source lines; the source lines include first source lines and second source lines; and the first source lines and the second source lines are located on different interconnect layers.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

Provided in the present disclosure are a semiconductor integrated circuit device and a manufacturing method therefor. In the semiconductor integrated circuit device, an electrode in a resistance random access memory cell is directly connected to a metal layer, thereby omitting the steps of filling a connection via by using other metal materials (e.g. tungsten) and performing polishing. In this way, manufacturing processes are reduced, and different degrees of recesses caused by polishing are also correspondingly reduced, such that the uniformity of the resistance performance of a resistance random access memory is improved, and the quality of the semiconductor integrated circuit device is higher. In addition, according to the embodiments of the present disclosure, a resistance layer of a trench structure is formed by skillfully using a trench where an original connection via is located, thereby embedding the entire resistance random access memory cell into the trench where the original connection via is located, such that the structure of a single resistance random access memory cell is more compact, the gap between resistance random access memory cells is smaller, and the requirements for miniaturization and high density can thus be better met.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

Disclosed is a preparation method for a resistive element, comprising the following steps: using an etching process, a deposition process, and a polishing process in a crossed manner to prepare the bottom electrode, the resistive layer, and the top electrode; and in the process of preparing the bottom electrode and the resistive layer, using a sidewall process to optimize at least one of the bottom electrode, the resistive dielectric layer, and the oxygen storage layer, so that the contact area between the bottom electrode and the resistive dielectric layer is reduced, and/or the contact area between the resistive dielectric layer and the oxygen storage layer is reduced. According to the preparation method of the present invention, conductive wires can be formed in the resistive layer, so that a low resistance state and a high resistance state are realized by means of the formation and breakage of the conductive wires. Also disclosed are a resistive element and a resistive random-access memory having same.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
• H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier

Abstract

A semiconductor device, and a method for manufacturing the semiconductor device. The semiconductor device comprises: a semiconductor substrate (100); a bottom electrode metal layer (104) located in the semiconductor substrate (100) and a top electrode metal layer (106) located above the semiconductor substrate (100); a resistive layer (108) located between the bottom electrode metal layer (104) and the top electrode metal layer (106), wherein the resistive layer (108) has a variable resistance; a first oxygen-capturing layer (110) located between the bottom electrode metal layer (104) and the top electrode metal layer (106), wherein the first oxygen-capturing layer (110) is located above the resistive layer (108); and a second oxygen-capturing layer (210) located in the bottom electrode metal layer (104), wherein upper surfaces of the semiconductor substrate (100), the bottom electrode metal layer (104) and the second oxygen-capturing layer (210) are flush, and the resistive layer (108) covers the semiconductor substrate (100), the bottom electrode metal layer (104) and the second oxygen-capturing layer (210).

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

The present disclosure provides a semiconductor device and a semiconductor device manufacturing method. The semiconductor device comprises: a semiconductor substrate; a bottom electrode metal layer and a top electrode metal layer which are located on the semiconductor substrate; a resistive switching layer located between the bottom electrode metal layer and the top electrode metal layer, the transverse width of the resistive switching layer being greater than that of the bottom electrode metal layer and/or the top electrode metal layer, and the resistive switching layer having a variable resistor; an oxygen barrier layer located between the bottom electrode metal layer and the top electrode metal layer, the oxygen barrier layer being located above the resistive switching layer; and an oxygen capturing layer located between the bottom electrode metal layer and the top electrode metal layer, the transverse width of the oxygen capturing layer being less than that of the resistive switching layer, and the oxygen capturing layer being located above the oxygen barrier layer.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

An integrated circuit and an electronic apparatus. The present invention aims to provide an integrated circuit having better area efficiency. The integrated circuit can be a resistive random access memory comprising multiple resistive memory cells arranged in row and column directions. The resistive memory cell comprises a variable impedance unit (106) and a switch unit coupled with the variable impedance unit (106). The respective variable impedance units (106) in the column direction are respectively coupled with corresponding source electrode lines (SL1, SL2). The source electrode lines (SL1, SL2) include a first source electrode line and a second source electrode line which are positioned in different wiring layers.

IPC Classes  ?

• H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
• H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects