A computer-implemented planning agent employing a dictionary of goal, action, and method, refiners to build refiner tree via iteratively relevance binding refiners to distal nodes of the tree, according relevance to the node as defined in the dictionary, then applicability binding those added refiners supported by the current state at that node of the tree. When one or more branches achieve a state in which the top-level goal is achieved, a plan made by choosing the actions along a selected successful branch. The plan can be an unscheduled dependency-ordered sequence of actions, which can be scheduled by atomizing each action into separate sets of start and end conditions and paralleling the atomic action components to the extent permissible by action dependencies.
A63F 13/533 - Controlling the output signals based on the game progress involving additional visual information provided to the game scene, e.g. by overlay to simulate a head-up display [HUD] or displaying a laser sight in a shooting game for prompting the player, e.g. by displaying a game menu
2.
METHOD AND SYSTEM FOR EFFICIENT COMMUNICATION AND COMMAND SYSTEM FOR DEFERRED OPERATION
A method and system for efficiently executing a delegate of a program by a processor coupled to an external memory. A payload including state data or command data is bound with a program delegate. The payload is mapped with the delegate via the payload identifier. The payload is pushed to a repository buffer in the external memory. The payload is flushed by reading the payload identifier and loading the payload from the repository buffer. The delegate is executed using the loaded payload.
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 12/0868 - Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
3.
METHOD AND SYSTEM OF A COMMAND BUFFER BETWEEN A CPU AND GPU
A method and system for a command processor for efficient processing of a program multi-processor core system with a CPU and GPU. The multi-core system includes a general purpose CPU executing commands in a CPU programming language and a graphic processing unit (GPU) executing commands in a GPU programming language. A command processor is coupled to the CPU and CPU. The command processor sequences jobs from a program for processing by the CPU or the GPU. The command processor creates commands from the jobs in a state free command format. The command processor generates a sequence of commands for execution by either the CPU or the GPU in the command format. A compiler running a meta language converts program data for the commands into a first format readable by the CPU programming language and a second format readable by the GPU programming language.
A method of generating an intermediate layer comprises generating local surface properties for a graphics object from parameter image maps, generating a first object image surface layer based on the local surface properties, storing intermediate surface results as an object image layer from the object local surface properties, and rendering a second object image surface layer based on the stored intermediate surface results.
A method for generating a graphic display of frame images comprises collecting one or more graphic objects to be rendered into a frame image, the one or more graphic objects being represented as a mesh in object space; determining one or more shadels to be computed for the frame image based at least on the one or more input attributes for each of the one or more graphic objects, each shadel being a shaded portion of the mesh; allocating space in a shadel storage buffer for the one or more shadels; populating a work queue buffer, the work queue buffer containing a list of commands to be executed to compute each of the one or more shadels; computing the determined one or more shadels to generate a shaded mesh; and rasterizing the shaded mesh into the frame image. The method can be implemented using a graphics processing unit (GPU).
A method and system for a command processor for efficient processing of a program multi-processor core system with a CPU and GPU. The multi-core system includes a general purpose CPU executing commands in a CPU programming language and a graphic processing unit (GPU) executing commands in a GPU programming language. A command processor is coupled to the CPU and CPU. The command processor sequences jobs from a program for processing by the CPU or the GPU. The command processor creates commands from the jobs in a state free command format. The command processor generates a sequence of commands for execution by either the CPU or the GPU in the command format. A compiler running a meta language converts program data for the commands into a first format readable by the CPU programming language and a second format readable by the GPU programming language.
A method and system for efficiently executing a delegate of a program by a processor coupled to an external memory. A payload including state data or command data is bound with a program delegate. The payload is mapped with the delegate via the payload identifier. The payload is pushed to a repository buffer in the external memory. The payload is flushed by reading the payload identifier and loading the payload from the repository buffer. The delegate is executed using the loaded payload.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 12/0868 - Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
8.
ORGANIZING TASKS BY A HIERARCHICAL TASK SCHEDULER FOR EXECUTION IN A MULTI-THREADED PROCESSING SYSTEM
A method for scheduling tasks from a program executed by a multi-processor core system is disclosed. The method includes a scheduler that groups a plurality of tasks, each having an assigned priority, by priority in a task group. The task group is assembled with other task groups having identical priorities in a task group queue. A hierarchy of task group queues is established based on priority levels of the assigned tasks. Task groups are assigned to one of a plurality of worker threads based on the hierarchy of task group queues. Each of the worker threads is associated with a processor in the multi-processor system. The tasks of the task groups are executed via the worker threads according to the order in the hierarchy.
A method of generating an intermediate layer comprises generating local surface properties for a graphics object from parameter image maps, generating a first object image surface layer based on the local surface properties, storing intermediate surface results as an object image layer from the object local surface properties, and rendering a second object image surface layer based on the stored intermediate surface results.
A method and system for efficiently executing a delegate of a program by a processor coupled to an external memory. A payload including state data or command data is bound with a program delegate. The payload is mapped with the delegate via the payload identifier. The payload is pushed to a repository buffer in the external memory. The payload is flushed by reading the payload identifier and loading the payload from the repository buffer. The delegate is executed using the loaded payload.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 12/0868 - Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
11.
Method and system for efficient communication and command system for deferred operation
A method and system for efficiently executing a delegate of a program by a processor coupled to an external memory. A payload including state data or command data is bound with a program delegate. The payload is mapped with the delegate via the payload identifier. The payload is pushed to a repository buffer in the external memory. The payload is flushed by reading the payload identifier and loading the payload from the repository buffer. The delegate is executed using the loaded payload.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
G06F 12/0868 - Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
12.
Method and system of decoupled object space shading
A method for generating a graphic display of frame images comprises collecting one or more graphic objects to be rendered into a frame image, the one or more graphic objects being represented as a mesh in object space; determining one or more shadels to be computed for the frame image based at least on the one or more input attributes for each of the one or more graphic objects, each shadel being a shaded portion of the mesh; allocating space in a shadel storage buffer for the one or more shadels; populating a work queue buffer, the work queue buffer containing a list of commands to be executed to compute each of the one or more shadels; computing the determined one or more shadels to generate a shaded mesh; and rasterizing the shaded mesh into the frame image. The method can be implemented using a graphics processing unit (GPU).
A method for scheduling tasks from a program executed by a multi-processor core system is disclosed. The method includes a scheduler that groups a plurality of tasks, each having an assigned priority, by priority in a task group. The task group is assembled with other task groups having identical priorities in a task group queue. A hierarchy of task group queues is established based on priority levels of the assigned tasks. Task groups are assigned to one of a plurality of worker threads based on the hierarchy of task group queues. Each of the worker threads is associated with a processor in the multi-processor system. The tasks of the task groups are executed via the worker threads according to the order in the hierarchy.
A method and system for a command processor for efficient processing of a program multi-processor core system with a CPU and GPU. The multi-core system includes a general purpose CPU executing commands in a CPU programming language and a graphic processing unit (GPU) executing commands in a GPU programming language. A command processor is coupled to the CPU and CPU. The command processor sequences jobs from a program for processing by the CPU or the GPU. The command processor creates commands from the jobs in a state free command format. The command processor generates a sequence of commands for execution by either the CPU or the GPU in the command format. A compiler running a meta language converts program data for the commands into a first format readable by the CPU programming language and a second format readable by the GPU programming language.
A method of generating an intermediate layer comprises generating local surface properties for a graphics object from parameter image maps, generating a first object image surface layer based on the local surface properties, storing intermediate surface results as an object image layer from the object local surface properties, and rendering a second object image surface layer based on the stored intermediate surface results.
A method for generating a graphic display of frame images comprises collecting one or more graphic objects to be rendered into a frame image, the one or more graphic objects being represented as a mesh in object space; determining one or more shadels to be computed for the frame image based at least on the one or more input attributes for each of the one or more graphic objects, each shadel being a shaded portion of the mesh; allocating space in a shadel storage buffer for the one or more shadels; populating a work queue buffer, the work queue buffer containing a list of commands to be executed to compute each of the one or more shadels; computing the determined one or more shadels to generate a shaded mesh; and rasterizing the shaded mesh into the frame image. The method can be implemented using a graphics processing unit (GPU).
A method and system for a command processor for efficient processing of a program multi-processor core system with a CPU and GPU. The multi-core system includes a general purpose CPU executing commands in a CPU programming language and a graphic processing unit (GPU) executing commands in a GPU programming language. A command processor is coupled to the CPU and CPU. The command processor sequences jobs from a program for processing by the CPU or the GPU. The command processor creates commands from the jobs in a state free command format. The command processor generates a sequence of commands for execution by either the CPU or the GPU in the command format. A compiler running a meta language converts program data for the commands into a first format readable by the CPU programming language and a second format readable by the GPU programming language.
A method and system for efficiently executing a delegate of a program by a processor coupled to an external memory. A payload including state data or command data is bound with a program delegate. The payload is mapped with the delegate via the payload identifier. The payload is pushed to a repository buffer in the external memory. The payload is flushed by reading the payload identifier and loading the payload from the repository buffer. The delegate is executed using the loaded payload.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
19.
Method and system for efficient communication and command system for deferred operation
A method and system for efficiently executing a delegate of a program by a processor coupled to an external memory. A payload including state data or command data is bound with a program delegate. The payload is mapped with the delegate via the payload identifier. The payload is pushed to a repository buffer in the external memory. The payload is flushed by reading the payload identifier and loading the payload from the repository buffer. The delegate is executed using the loaded payload.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
20.
Organizing tasks by a hierarchical task scheduler for execution in a multi-threaded processing system
A method for scheduling tasks from a program executed by a multi-processor core system is disclosed. The method includes a scheduler that groups a plurality of tasks, each having an assigned priority, by priority in a task group. The task group is assembled with other task groups having identical priorities in a task group queue. A hierarchy of task group queues is established based on priority levels of the assigned tasks. Task groups are assigned to one of a plurality of worker threads based on the hierarchy of task group queues. Each of the worker threads is associated with a processor in the multi-processor system. The tasks of the task groups are executed via the worker threads according to the order in the hierarchy.
A method and system for efficiently executing a delegate of a program by a processor coupled to an external memory. A payload including state data or command data is bound with a program delegate. The payload is mapped with the delegate via the payload identifier. The payload is pushed to a repository buffer in the external memory. The payload is flushed by reading the payload identifier and loading the payload from the repository buffer. The delegate is executed using the loaded payload.
A method and system for a command processor for efficient processing of a program multi-processor core system with a CPU and GPU. The multi-core system includes a general purpose CPU executing commands in a CPU programming language and a graphic processing unit (GPU) executing commands in a GPU programming language. A command processor is coupled to the CPU and CPU. The command processor sequences jobs from a program for processing by the CPU or the GPU. The command processor creates commands from the jobs in a state free command format. The command processor generates a sequence of commands for execution by either the CPU or the GPU in the command format. A compiler running a meta language converts program data for the commands into a first format readable by the CPU programming language and a second format readable by the GPU programming language.
A method and system for rendering a graphic object that decouples shading from rasterization is disclosed. The method includes selecting a set of points of a graphic object for shading. At least one shading parameter is determined for application to the selected set of points of the graphic object. The selected points are shaded using the shading parameter image to produce a shaded graphic object image via a graphic processor at a first frequency relative to the frame rate. The shaded graphic object image is rasterized into a frame image in parallel at a second frequency relative to the frame rate. Multiple processors may be used for the shading and rasterization.
A method and system for a command processor for efficient processing of a program multi-processor core system with a CPU and GPU. The multi-core system includes a general purpose CPU executing commands in a CPU programming language and a graphic processing unit (GPU) executing commands in a GPU programming language. A command processor is coupled to the CPU and GPU. The command processor sequences jobs from a program for processing by the CPU or the GPU. The command processor creates commands from the jobs in a state free command format. The command processor generates a sequence of commands for execution by either the CPU or the GPU in the command format. A compiler running a meta language converts program data for the commands into a first format readable by the CPU programming language and a second format readable by the GPU programming language.
A method and system for efficiently executing a delegate of a program by a processor coupled to an external memory. A payload including state data or command data is bound with a program delegate. The payload is mapped with the delegate via the payload identifier. The payload is pushed to a repository buffer in the external memory. The payload is flushed by reading the payload identifier and loading the payload from the repository buffer. The delegate is executed using the loaded payload.
A method and system for rendering a graphic object is disclosed. The method includes selecting a set of points of a graphic object for shading. At least one shading parameter is determined for application to the selected set of points of the graphic object. A shading parameter image is precalculated based on the determined at least one shading parameter. The shading parameter image is stored in a memory. The selected points are shaded using the shading parameter image to produce a shaded graphic object image via a graphic processor. The shaded graphic object image is rasterized into a frame image.
A method for scheduling tasks from a program executed by a multi-processor core system is disclosed. The method includes a scheduler that groups a plurality of tasks, each having an assigned priority, by priority in a task group. The task group is assembled with other task groups having identical priorities in a task group queue. A hierarchy of task group queues is established based on priority levels of the assigned tasks. Task groups are assigned to one of a plurality of worker threads based on the hierarchy of task group queues. Each of the worker threads is associated with a processor in the multi-processor system. The tasks of the task groups are executed via the worker threads according to the order in the hierarchy.
