An integrated circuit for use in a first vehicle may include: an interface circuit that communicates with a second integrated circuit in a second vehicle; and a processing circuit. During operation, the processing circuit may determine that the second vehicle has better situational awareness for a portion of a road or an environment proximate to the road than the first vehicle, where the second vehicle is proximate to the first vehicle. Then, the processing circuit may dynamically establish, with the second integrated circuit, a communication pairing with the second vehicle. Moreover, the integrated circuit may exchange, via the pairing, information with the second integrated circuit. For example, the exchanged information may include or may specify: measurement data, one or more detected objects, one or more object identifiers, seed information for a detection technique (such as a priori information), and/or a priority or urgency of the exchanged information.
H04W 4/02 - Services making use of location information
H04W 4/46 - Services specially adapted for particular environments, situations or purposes for vehicles, e.g. vehicle-to-pedestrians [V2P] for vehicle-to-vehicle communication [V2V]
Embodiments of an integrated circuit are described. This integrated circuit may include a Universal Data Bus Serializer. Moreover, the Universal Data Bus Serializer may include: an input to receive data for transmission over a data bus of a vehicle; memory storing a plurality of protocol operating instructions, where each protocol operating instruction corresponds to a given operating protocol; a selection unit, coupled to the input and the memory, that chooses one of the plurality of protocol operating instructions based on a given protocol; and a serial data output to couple to the data bus and to output serial data based at least in part on the given protocol.
Embodiments of an integrated circuit are described. This integrated circuit may include a Universal Data Bus Serializer. Moreover, the Universal Data Bus Serializer may include: an input to receive data for transmission over a data bus of a vehicle; memory storing a plurality of protocol operating instructions, where each protocol operating instruction corresponds to a given operating protocol; a selection unit, coupled to the input and the memory, that chooses one of the plurality of protocol operating instructions based on a given protocol; and a serial data output to couple to the data bus and to output serial data based at least in part on the given protocol.
An integrated circuit is described. This integrated circuit may include multiple stages. At a given time, the integrated circuit may be configured to use one or more of the stages in the processing of received signals associated with measurements in an environment. For example, a control circuit or control logic in the integrated circuit may configure the use of one or more of the stages in the integrated circuit. A first stage in the stages may perform coherent interference mitigation by correcting the received signals for a predicted complex signal associated with a spurious source. Moreover, a second stage in the stages may perform equalization of the received signals based at least in part on a target criterion. Furthermore, a third stage in the stages may combine different received signals (such as received signals associated with different measurements) and may detect one or more peaks in the received signals.
G01S 13/524 - Discriminating between fixed and moving objects or between objects moving at different speeds using transmissions of interrupted pulse modulated waves based upon the phase or frequency shift resulting from movement of objects, with reference to the transmitted signals, e.g. coherent MTi
G01S 17/36 - Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated with phase comparison between the received signal and the contemporaneously transmitted signal
An integrated circuit is described. This integrated circuit may include multiple stages. At a given time, the integrated circuit may be configured to use one or more of the stages in the processing of received signals associated with measurements in an environment. For example, a control circuit or control logic in the integrated circuit may configure the use of one or more of the stages in the integrated circuit. A first stage in the stages may perform coherent interference mitigation by correcting the received signals for a predicted complex signal associated with a spurious source. Moreover, a second stage in the stages may perform equalization of the received signals based at least in part on a target criterion. Furthermore, a third stage in the stages may combine different received signals (such as received signals associated with different measurements) and may detect one or more peaks in the received signals.
An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.
An integrated circuit is described. This integrated circuit may include an optical transmit circuit that outputs optical signals (such as optical pulses or FMCW optical signals) having a carrier-frequency (or chirp) pattern as a function of time, where a modulation signal, associated with an optical source and corresponding to the carrier-frequency pattern, includes a predistortion to reduce a nonlinearity associated with the optical transmit circuit. Moreover, the integrated circuit may include a feedback circuit that measures the nonlinearity (e.g., using an interferometer) and that dynamically adjusts the predistortion based at least in part on the measured nonlinearity. Note that the integrated circuit may provide closed-loop adjustment of the predistortion. In some embodiments, the correction of the nonlinearity may be performed in the frequency domain.
An integrated circuit is described. This integrated circuit may include an optical transmit circuit that outputs optical signals (such as optical pulses or FMCW optical signals) having a carrier-frequency (or chirp) pattern as a function of time, where a modulation signal, associated with an optical source and corresponding to the carrier-frequency pattern, includes a predistortion to reduce a nonlinearity associated with the optical transmit circuit. Moreover, the integrated circuit may include a feedback circuit that measures the nonlinearity (e.g., using an interferometer) and that dynamically adjusts the predistortion based at least in part on the measured nonlinearity. Note that the integrated circuit may provide closed-loop adjustment of the predistortion. In some embodiments, the correction of the nonlinearity may be performed in the frequency domain.
A centralized occupancy detection system enables monitoring of multiple seats, or more generally, multiple stations, with a single sensor. One illustrative vehicle includes: one or more stations each configured to accommodate an occupant of the vehicle, a radar-reflective surface, and a radar transceiver configured to use the radar-reflective surface to detect an occupant of at least one of the stations. Another illustrative vehicle includes: multiple stations to each accommodate an occupant of the vehicle, and a radar transceiver configured to examine each of the multiple stations to determine whether that station has an occupant.
B60R 21/015 - Electrical circuits for triggering safety arrangements in case of vehicle accidents or impending vehicle accidents including means for detecting the presence or position of passengers, passenger seats or child seats, e.g. for disabling triggering
G01S 13/04 - Systems determining presence of a target
G01S 13/46 - Indirect determination of position data
G01S 13/931 - Radar or analogous systems, specially adapted for specific applications for anti-collision purposes of land vehicles
10.
Wireless Charger with Selective Filtering of Interference
An integrated circuit is described. This integrated circuit may include wireless-charger transmitter. The wireless-charger transmitter includes a driver circuit. Moreover, the wireless-charger transmitter selectively filters out an interference signal in a band of frequencies corresponding to AM radio. Note that the selective filtering may be performed by at least a filtering circuit. For example, the filtering circuit may include a low-pass filter. Moreover, the selective filtering using the filtering circuit may be based at least in part on a switching frequency of the wireless-charger transmitter. Furthermore, a filtering frequency associated with the filtering circuit (such as a 3 dB cutoff frequency of a low-pass filter) may be adjusted by selectively electrically coupling a set of capacitors in parallel with the filtering circuit.
An integrated circuit is described. This integrated circuit may include wireless-charger transmitter. The wireless-charger transmitter includes a driver circuit. Moreover, the wireless-charger transmitter selectively filters out an interference signal in a band of frequencies corresponding to AM radio. Note that the selective filtering may be performed by at least a filtering circuit. For example, the filtering circuit may include a low-pass filter. Moreover, the selective filtering using the filtering circuit may be based at least in part on a switching frequency of the wireless-charger transmitter. Furthermore, a filtering frequency associated with the filtering circuit (such as a 3 dB cutoff frequency of a low-pass filter) may be adjusted by selectively electrically coupling a set of capacitors in parallel with the filtering circuit.
H04W 24/02 - Arrangements for optimising operational condition
H04W 72/0453 - Resources in frequency domain, e.g. a carrier in FDMA
H04W 72/541 - Allocation or scheduling criteria for wireless resources based on quality criteria using the level of interference
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
G08C 17/02 - Arrangements for transmitting signals characterised by the use of a wireless electrical link using a radio link
H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.
An integrated circuit that performs multiple separate types of measurements is described. This integrated circuit may include a measurement circuit. Moreover, the integrated circuit may include or may be electrically coupled to at least one sensor. During operation, the integrated circuit may perform the separate types of measurements of or associated with an object in an environment with reduced or obscured information in a visual band of frequencies. For example, the environment with reduced or obscured information may include fog or a cloud. Note that performing of the separate types of measurements may include: filtering measurements based at least in part on velocity relative to ground; and providing data streams having different spatial frequencies and sampling rates based at least in part on the filtering.
An integrated circuit that performs multiple separate types of measurements is described. This integrated circuit may include a measurement circuit. Moreover, the integrated circuit may include or may be electrically coupled to at least one sensor. During operation, the integrated circuit may perform the separate types of measurements of or associated with an object in an environment with reduced or obscured information in a visual band of frequencies. For example, the environment with reduced or obscured information may include fog or a cloud. Note that performing of the separate types of measurements may include: filtering measurements based at least in part on velocity relative to ground; and providing data streams having different spatial frequencies and sampling rates based at least in part on the filtering.
G01S 17/88 - Lidar systems, specially adapted for specific applications
G01S 13/88 - Radar or analogous systems, specially adapted for specific applications
G01S 17/86 - Combinations of lidar systems with systems other than lidar, radar or sonar, e.g. with direction finders
G01S 13/86 - Combinations of radar systems with non-radar systems, e.g. sonar, direction finder
B60W 40/02 - Estimation or calculation of driving parameters for road vehicle drive control systems not related to the control of a particular sub-unit related to ambient conditions
An integrated circuit that dynamically adapts power to be provided by at least a first node in network is described. This integrated circuit may include a control circuit (or control logic) that performs the operations of: receiving charging information associated with one or more nodes in the network; determining, based at least in part on the charging information, a dynamic power to be supplied to an electronic device by at least the first node in the one or more nodes; and providing, addressed to at least the first node, an instruction specifying or indicating the dynamic power of at least the first node at a given time.
An integrated circuit that dynamically adapts power to be provided by at least a first node in network is described. This integrated circuit may include a control circuit (or control logic) that performs the operations of: receiving charging information associated with one or more nodes in the network; determining, based at least in part on the charging information, a dynamic power to be supplied to an electronic device by at least the first node in the one or more nodes; and providing, addressed to at least the first node, an instruction specifying or indicating the dynamic power of at least the first node at a given time.
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
B60L 1/00 - Supplying electric power to auxiliary equipment of electrically-propelled vehicles
H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
17.
Stable Low-Power Analog-to-Digital Converter (ADC) Reference Voltage
A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.
An integrated circuit that selectively filters out common-mode and differential signals is described. This integrated circuit may include an RF receiver with a mixer that converts signals between a band of frequencies in the RF and a second band of frequencies based at least in part on second signals, where the second band of frequencies is less than the band of frequencies. Moreover, the mixer may include input ports that receive the second signals and include a filter circuit, electrically coupled in parallel with the input ports, that filters out the common-mode signals above a threshold frequency and filters out the differential signals below the threshold frequency. For example, the filter circuit may include a half-wavelength transmission line. Note that the mixer may convert the differential signals to the common mode signals below the threshold frequency and may convert the common-mode signals to the differential signals above the threshold frequency.
G01S 13/32 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated
G01S 13/931 - Radar or analogous systems, specially adapted for specific applications for anti-collision purposes of land vehicles
An integrated circuit that selectively filters out common-mode and differential signals is described. This integrated circuit may include an RF receiver with a mixer that converts signals between a band of frequencies in the RF and a second band of frequencies based at least in part on second signals, where the second band of frequencies is less than the band of frequencies. Moreover, the mixer may include input ports that receive the second signals and include a filter circuit, electrically coupled in parallel with the input ports, that filters out the common-mode signals above a threshold frequency and filters out the differential signals below the threshold frequency. For example, the filter circuit may include a half-wavelength transmission line. Note that the mixer may convert the differential signals to the common-mode signals below the threshold frequency and may convert the common-mode signals to the differential signals above the threshold frequency.
An integrated circuit is described. This integrated circuit may include: an interface module with a first power domain and a second power domain. The first power domain may include a digital controller, and the second power domain may include a first analog front end (AFE) circuit. Moreover, the interface module may include up/down level shifters that communicate electrical signals that include a DC component from the first power domain to the second power domain. In some embodiments, the integrated circuit may provide a fully on-chip solution to handle level shifting between the AFE circuit and a digital controller in Universal Serial Bus (USB) 2.0 during communication of electrical signals in a full-speed mode and/or a high-speed mode.
An interface circuit may convert an input electrical signal at an input node in a first power domain having a first ground or reference voltage into an output electrical signal at an output node in a second power domain having a second ground or reference voltage. Notably, a level-shifting circuit in the interface circuit may selectively electrically couple to the input node and the output node. Then, when there is electrical coupling, the level-shifting circuit may perform level shifting between the first power domain and the second power domain. The level shifting may involve: passing, using a first filter, frequencies in the input electrical signal below a first corner frequency; passing, using a second filter in parallel with the first filter, frequencies in the input electrical signal above a second corner frequency; and combining outputs of the first filter and the second filter as the output electrical signal.
An integrated circuit may include K transmit circuits that output K transmit signals, where K is a non-zero integer and the K transmit signals are encoded using first Doppler code multiplexing. Moreover, the integrated circuit may include L receive circuits that provide L receive signals (which may correspond to the K transmit signals), where L is a non-zero integer and the L receive signals are encoded using second Doppler code multiplexing. Note that the first and/or the second Doppler code multiplexing may be different from Doppler division multiplexing. Furthermore, the first Doppler code multiplexing may include selectively Doppler shifting a kth transmit signal in the K transmit signals by nk bins between chirps in a frame, and the second Doppler code multiplexing may include selectively Doppler shifting an lth receive signal in the L transmit signals by n1 bins between the chirps in the frame.
An integrated circuit may include K transmit circuits that output K transmit signals, where K is a non-zero integer and the K transmit signals are encoded using first Doppler code multiplexing. Moreover, the integrated circuit may include L receive circuits that provide L receive signals (which may correspond to the K transmit signals), where L is a non-zero integer and the L receive signals are encoded using second Doppler code multiplexing. Note that the first and/or the second Doppler code multiplexing may be different from Doppler division multiplexing. Furthermore, the first Doppler code multiplexing may include selectively Doppler shifting a kth transmit signal in the K transmit signals by nk bins between chirps in a frame, and the second Doppler code multiplexing may include selectively Doppler shifting an 1th receive signal in the L transmit signals by m bins between the chirps in the frame.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
24.
Integrated electromagnetic-acoustic sensor and sensing
One illustrative integrated electromagnetic-acoustic sensor includes: a ground plane; a patch antenna above the ground plane to send or receive an electromagnetic (EM) signal having an EM signal frequency; and an array of capacitive micromachined acoustic transducers formed by cavities between the patch antenna and a base electrode to send or receive an acoustic signal having an acoustic signal frequency. One illustrative sensing method includes: driving or sensing a EM signal between a ground plane and a patch antenna; and driving or sensing an acoustic signal between the patch antenna and a base electrode, the base electrode and the patch antenna having an array of capacitive micromachined acoustic transducer cavities therebetween.
B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy
B06B 1/04 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy operating with electromagnetism
G01S 7/52 - Details of systems according to groups , , of systems according to group
G01S 15/04 - Systems determining presence of a target
G01S 15/52 - Discriminating between fixed and moving objects or between objects moving at different speeds
G01S 15/931 - Sonar systems specially adapted for specific applications for anti-collision purposes of land vehicles
An integrated circuit that performs testing of a circuit sub-block is described. This integrated circuit may include the circuit sub-block that performs a function, where the circuit sub-block is implemented in an analog domain using analog components and in a digital domain using digital components. Moreover, the integrated circuit may perform the testing of the circuit sub-block using independent testing of individual components in the circuit subblock instead of testing the function of the circuit sub-block as a whole. Note that the individual components include the analog components and the digital components. In some embodiments, the testing may include functional safety testing.
G01S 13/36 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated with phase comparison between the received signal and the contemporaneously transmitted signal
H01Q 3/30 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elementsArrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the distribution of energy across a radiating aperture varying the phase
H01Q 3/36 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elementsArrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the distribution of energy across a radiating aperture varying the phase by electrical means with variable phase-shifters
H01Q 3/38 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elementsArrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the distribution of energy across a radiating aperture varying the phase by electrical means with variable phase-shifters the phase-shifters being digital
G01S 13/26 - Systems for measuring distance only using transmission of interrupted, pulse modulated waves wherein the transmitted pulses use a frequency- or phase-modulated carrier wave
H01Q 3/26 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elementsArrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the distribution of energy across a radiating aperture
H01Q 3/34 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elementsArrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the distribution of energy across a radiating aperture varying the phase by electrical means
An integrated circuit that performs testing of a circuit sub-block is described. This integrated circuit may include the circuit sub-block that performs a function, where the circuit sub-block is implemented in an analog domain using analog components and in a digital domain using digital components. Moreover, the integrated circuit may perform the testing of the circuit sub-block using independent testing of individual components in the circuit sub-block instead of testing the function of the circuit sub-block as a whole. Note that the individual components include the analog components and the digital components. In some embodiments, the testing may include functional safety testing.
In an illustrative integrated circuit, a chirp generator provides a chirp signal having linearly-ramped chirp intervals, while a shift frequency generator provides a signal having a different shift frequency during each of multiple segments in each chirp interval. A modulator combines the signals to derive a segmented chirp signal having multiple linearly-ramped chirp segments in each chirp interval. The modulator may be a single sideband modulator to provide frequency up-shifted and frequency down-shifted chirp segments. The segmented chirp signal may be suppressed during resettling intervals of the original chirp signal.
G01S 13/58 - Velocity or trajectory determination systemsSense-of-movement determination systems
G01S 13/34 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
G01S 13/534 - Discriminating between fixed and moving objects or between objects moving at different speeds using transmissions of interrupted pulse modulated waves based upon the phase or frequency shift resulting from movement of objects, with reference to the transmitted signals, e.g. coherent MTi based upon amplitude or phase shift resulting from movement of objects, with reference to the surrounding clutter echo signal, e.g. non-coherent MTi, clutter referenced MTi, externally coherent MTi
28.
LOCAL INTERCONNECTED NETWORK BUS REPEATER DELAY COMPENSATION
An integrated circuit is described. This integrated circuit may include: a receive circuit, coupled to a segment of a LIN bus, that receives bits; a measurement circuit, coupled to the receive circuit, that measures: a rising-edge time and a falling-edge time in the bits, or a bit time and a second bit time in the bits; control logic, coupled to the measurement circuit, that compares the rising-edge time and the falling-edge time, or the bit time and the second bit time; a transmit circuit, coupled to the receive circuit, that transmits the bits on a second segment of the LIN bus; and a delay circuit, coupled to the control logic, that applies, based at least in part on the comparison, a delay to: one or more rising edges or falling edges in the bits; or one or more bit times or second bit times in the bits.
H04L 12/403 - Bus networks with centralised control, e.g. polling
H04L 12/407 - Bus networks with decentralised control
H04B 1/3822 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving specially adapted for use in vehicles
H04L 12/28 - Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
29.
Local Interconnected Network Bus Repeater Delay Compensation
An integrated circuit is described. This integrated circuit may include: a receive circuit, coupled to a segment of a LIN bus, that receives bits; a measurement circuit, coupled to the receive circuit, that measures: a rising-edge time and a falling-edge time in the bits, or a bit time and a second bit time in the bits; control logic, coupled to the measurement circuit, that compares the rising-edge time and the falling-edge time, or the bit time and the second bit time; a transmit circuit, coupled to the receive circuit, that transmits the bits on a second segment of the LIN bus; and a delay circuit, coupled to the control logic, that applies, based at least in part on the comparison, a delay to: one or more rising edges or falling edges in the bits; or one or more bit times or second bit times in the bits.
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.
Disclosed active reflector apparatus and methods that inhibit self-induced oscillation. One illustrative apparatus embodiment includes an amplifier and an adjustable phase shifter. The amplifier amplifies a receive signal to generate a transmit signal, the transmit signal causing interference with the receive signal. The adjustable phase shifter modifies the phase of the transmit signal relative to that of the receive signal to inhibit oscillation. A controller may periodically test a range of settings for the adjustable phase shifter to identify undesirable phase shifts prone to self-induced oscillation, and may maintain the phase shift setting at a value that inhibits oscillation.
An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.
An integrated circuit is described. This integrated circuit may include a control circuit. During operation, the control circuit may detect when an output current provided to a load exceeds a current threshold. Moreover, in response to the detection, the control circuit may reduce a loop gain associated with an amplifier in the control circuit. Note that the output current may be associated with a switched-mode power supply. For example, the reduced loop gain may transition the switched-mode power supply from a constant voltage mode to a constant current mode. In some embodiments, the output current may be associated with a power supply or a source. Notably, the reduced loop gain may transition the power supply or the source from a constant voltage mode to a constant current mode.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
An integrated circuit is described. This integrated circuit may include a control circuit. During operation, the control circuit may detect when an output current provided to a load exceeds a current threshold. Moreover, in response to the detection, the control circuit may reduce a loop gain associated with an amplifier in the control circuit. Note that the output current may be associated with a switched-mode power supply. For example, the reduced loop gain may transition the switched-mode power supply from a constant voltage mode to a constant current mode. In some embodiments, the output current may be associated with a power supply or a source. Notably, the reduced loop gain may transition the power supply or the source from a constant voltage mode to a constant current mode.
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/135 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
H02M 3/137 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 3/139 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/142 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
35.
Multi-sensing PTAT for multiple-location temperature sensing
An integrated circuit that controls distributed temperature sensors in a semiconductor die is described. This integrated circuit may include: memory; a controller (such as a PTAT controller) coupled to the memory; temperature sensors distributed at measurement locations in the semiconductor die (such as remote locations from the controller), where a given temperature sensor includes building blocks (or components) that are common to the temperature sensors; and routing between the controller and the building blocks over an addressable bus, where signal lines for analog signals in the addressable bus are reused when communicating between the controller and different temperature sensors.
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
G01K 13/00 - Thermometers specially adapted for specific purposes
G05D 23/19 - Control of temperature characterised by the use of electric means
G05D 23/20 - Control of temperature characterised by the use of electric means with sensing elements having variation of electric or magnetic properties with change of temperature
36.
SINGLE-THREAD DETECTION OF VALID SYNCHRONIZATION HEADERS
An integrated circuit with an interface circuit is described. During operation, the interface circuit may receive signals corresponding to a header of a frame that is compatible with a serial communication protocol, where the received signals include a temporal pattern of binary bits with instances of a dominant signal level and a recessive signal level. Then, the interface circuit may compute a set of conditions based at least in part on the receive signals, where, when valid, the set of conditions identify a first dominant bit in the binary bits having the dominant signal level. Moreover, when the set of conditions are valid, the interface circuit may: determine a location of synchronization field in the header relative to the identified first dominant bit; and calculate a baud rate of the receive signals based at least in part on a subset of the binary bits in the synchronization field.
An integrated circuit with an interface circuit is described. During operation, the interface circuit may receive signals corresponding to a header of a frame that is compatible with a serial communication protocol, where the received signals include a temporal pattern of binary bits with instances of a dominant signal level and a recessive signal level. Then, the interface circuit may compute a set of conditions based at least in part on the receive signals, where, when valid, the set of conditions identify a first dominant bit in the binary bits having the dominant signal level. Moreover, when the set of conditions are valid, the interface circuit may: determine a location of synchronization field in the header relative to the identified first dominant bit; and calculate a baud rate of the receive signals based at least in part on a subset of the binary bits in the synchronization field.
An automotive radar system includes multiple radar antennas and a radar front end chip. The front end chip includes a plurality of phase rotators coupled to a local oscillator, wherein each phase rotator of the plurality of phase rotators is coupled to multiple digital phase modulators; a plurality of switches that couple selectable ones of the multiple digital phase modulators to respective amplifiers, each amplifier coupled to a respective antenna output; and a controller which provides digital control signals to the plurality of phase rotators, the multiple digital phase modulators, and the plurality of switches to synthesize transmit signals for each of the multiple radar antennas.
G01S 13/931 - Radar or analogous systems, specially adapted for specific applications for anti-collision purposes of land vehicles
G01S 13/32 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated
An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.
A receive extender in an integrated circuit may include: N phase-adjustment circuits that adjust phases of N receive signals from N receive antennas; and an N:1 demultiplexer that coherently combines the N receive signals into an output signal, which is provided to the transceiver chip. Moreover, a transmit extender in the integrated circuit may include: a 1:M multiplexer that coherently separates a transmit signal from the transceiver chip into M transmit signals, where N and M are non-zero integers that may be different; and M phase-adjustment circuits that adjust phases of the M transmit signals, which are provided to M transmit antennas. Note that the integrated circuit may be coupled to a second integrated circuit that phase shifts the output signal and the transmit signal based at least in part on the oscillator signal. Moreover, control signals between the integrated circuit and the second integrated circuit may be synchronized.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
41.
Envelope regulation in a frequency-modulated continuous-wave radar system
A radar system that can block false echoes includes: a local oscillator configured to generate a chirp signal comprising a plurality of chirps, each having a corresponding envelope; a transmitter configured to transmit a signal corresponding to the chirp signal; and a modulation circuit configured to modulate the transmitted signal by regulating a magnitude of one or more portions of the chirp envelopes in a predetermined pattern such that the radar system can discern false echoes which do not match the pattern.
G01S 13/34 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
G06F 13/36 - Handling requests for interconnection or transfer for access to common bus or bus system
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
G06F 13/14 - Handling requests for interconnection or transfer
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/26 - Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/364 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
An integrated circuit is described. This integrated circuit may include a wireless- charger transmitter, which includes a driver circuit electrically coupled to multiple branches associated with multiple transmission coils. A given branch may include or may be electrically coupled to: a capacitor, a multiplexor (MUX) switch that includes a single field¬ effect transistor (FET) or a single integrated-gate bipolar transistor (IGBT), and a given transmission coil. Moreover, the wireless-charger transmitter may include a control circuit that provides control signals to gates of FETs or the IGBTs in the branches that selectively activate at least the MUX switch in the given branch and selectively deactivate remaining MUX switches in a remainder of the branches. Furthermore, the driver circuit may perform wireless charging by driving the given transmission coil in the activated given branch using an electrical signal having a fundamental frequency component.
An integrated circuit is described. This integrated circuit may include a wireless-charger transmitter, which includes a driver circuit electrically coupled to multiple branches associated with multiple transmission coils. A given branch may include or may be electrically coupled to: a capacitor, a multiplexor (MUX) switch that includes a single field-effect transistor (FET) or a single integrated-gate bipolar transistor (IGBT), and a given transmission coil. Moreover, the wireless-charger transmitter may include a control circuit that provides control signals to gates of FETs or the IGBTs in the branches that selectively activate at least the MUX switch in the given branch and selectively deactivate remaining MUX switches in a remainder of the branches. Furthermore, the driver circuit may perform wireless charging by driving the given transmission coil in the activated given branch using an electrical signal having a fundamental frequency component.
H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
H02J 50/40 - Circuit arrangements or systems for wireless supply or distribution of electric power using two or more transmitting or receiving devices
H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 17/567 - Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
45.
SIGNAL-ADAPTIVE AND TIME-DEPENDENT ANALOG-TO-DIGITAL CONVERSION RATE IN A RANGING RECEIVER
An integrated circuit may include a ranging receiver that includes an analog-to-digital converter (ADC) having a time-variant sampling or data rate. Notably, the sampling rate may be increased when a return signal is detected by the ranging receiver. For example, the return signal may be detected using a matched filter (such as a correlation of the return signal and a target signal) and a comparator having a time-variant threshold. The time-variant threshold may be decreased as a function of time after a transmit signal is output in order to track the channel response, such as a decrease in the return signal amplitude for objects at larger ranges. Alternatively or additionally, the sampling rate may be increased based at least in part on a predefined function (such as a closed-form expression or a stepwise function, e.g., a stairstep function) after the transmit signal is output.
G01S 13/12 - Systems for measuring distance only using transmission of interrupted, pulse modulated waves wherein the pulse-recurrence frequency is varied to provide a desired time relationship between the transmission of a pulse and the receipt of the echo of a preceding pulse
G01S 7/4861 - Circuits for detection, sampling, integration or read-out
G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference
46.
Signal-Adaptive and Time-Dependent Analog-to-Digital Conversion Rate in a Ranging Receiver
An integrated circuit may include a ranging receiver that includes an analog-to-digital converter (ADC) having a time-variant sampling or data rate. Notably, the sampling rate may be increased when a return signal is detected by the ranging receiver. For example, the return signal may be detected using a matched filter (such as a correlation of the return signal and a target signal) and a comparator having a time-variant threshold. The time-variant threshold may be decreased as a function of time after a transmit signal is output in order to track the channel response, such as a decrease in the return signal amplitude for objects at larger ranges. Alternatively or additionally, the sampling rate may be increased based at least in part on a predefined function (such as a closed-form expression or a stepwise function, e.g., a stairstep function) after the transmit signal is output.
An integrated circuit for use in a first vehicle may include: an interface circuit that communicates with a second integrated circuit in a second vehicle; and a processing circuit. During operation, the processing circuit may determine that the second vehicle has better situational awareness for a portion of a road or an environment proximate to the road than the first vehicle, where the second vehicle is proximate to the first vehicle. Then, the processing circuit may dynamically establish, with the second integrated circuit, a communication pairing with the second vehicle. Moreover, the integrated circuit may exchange, via the pairing, information with the second integrated circuit. For example, the exchanged information may include or may specify: measurement data, one or more detected objects, one or more object identifiers, seed information for a detection technique (such as a priori information), and/or a priority or urgency of the exchanged information.
G05D 1/02 - Control of position or course in two dimensions
H04W 4/46 - Services specially adapted for particular environments, situations or purposes for vehicles, e.g. vehicle-to-pedestrians [V2P] for vehicle-to-vehicle communication [V2V]
48.
Dynamic and selective pairing between proximate vehicles
An integrated circuit for use in a first vehicle may include: an interface circuit that communicates with a second integrated circuit in a second vehicle; and a processing circuit. During operation, the processing circuit may determine that the second vehicle has better situational awareness for a portion of a road or an environment proximate to the road than the first vehicle, where the second vehicle is proximate to the first vehicle. Then, the processing circuit may dynamically establish, with the second integrated circuit, a communication pairing with the second vehicle. Moreover, the integrated circuit may exchange, via the pairing, information with the second integrated circuit. For example, the exchanged information may include or may specify: measurement data, one or more detected objects, one or more object identifiers, seed information for a detection technique (such as a priori information), and/or a priority or urgency of the exchanged information.
H04W 4/02 - Services making use of location information
H04W 4/46 - Services specially adapted for particular environments, situations or purposes for vehicles, e.g. vehicle-to-pedestrians [V2P] for vehicle-to-vehicle communication [V2V]
An interface circuit may convert an input electrical signal at an input node in a first power domain having a first ground or reference voltage into an output electrical signal at an output node in a second power domain having a second ground or reference voltage. Notably, a level-shifting circuit in the interface circuit may selectively electrically couple to the input node and the output node. Then, when there is electrical coupling, the level-shifting circuit may perform level shifting between the first power domain and the second power domain. The level shifting may involve: passing, using a first filter, frequencies in the input electrical signal below a first corner frequency; passing, using a second filter in parallel with the first filter, frequencies in the input electrical signal above a second corner frequency; and combining outputs of the first filter and the second filter as the output electrical signal.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H03K 3/35 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar semiconductor devices with more than two PN junctions, or more than three electrodes, or more than one electrode connected to the same conductivity region
H03K 3/353 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
An interface circuit may convert an input electrical signal at an input node in a first power domain having a first ground or reference voltage into an output electrical signal at an output node in a second power domain having a second ground or reference voltage. Notably, a level-shifting circuit in the interface circuit may selectively electrically couple to the input node and the output node. Then, when there is electrical coupling, the level-shifting circuit may perform level shifting between the first power domain and the second power domain. The level shifting may involve: passing, using a first filter, frequencies in the input electrical signal below a first corner frequency; passing, using a second filter in parallel with the first filter, frequencies in the input electrical signal above a second corner frequency; and combining outputs of the first filter and the second filter as the output electrical signal.
An integrated circuit is described. This integrated circuit may include: an interface module with a first power domain and a second power domain. The first power domain may include a digital controller, and the second power domain may include a first analog front end (AFE) circuit. Moreover, the interface module may include up/down level shifters that communicate electrical signals that include a DC component from the first power domain to the second power domain. In some embodiments, the integrated circuit may provide a fully on-chip solution to handle level shifting between the AFE circuit and a digital controller in Universal Serial Bus (USB) 2.0 during communication of electrical signals in a full-speed mode and/or a high-speed mode.
An integrated circuit is described. This integrated circuit may include: an interface module with a first power domain and a second power domain. The first power domain may include a digital controller, and the second power domain may include a first analog front end (AFE) circuit. Moreover, the interface module may include up/down level shifters that communicate electrical signals that include a DC component from the first power domain to the second power domain. In some embodiments, the integrated circuit may provide a fully on-chip solution to handle level shifting between the AFE circuit and a digital controller in Universal Serial Bus (USB) 2.0 during communication of electrical signals in a full-speed mode and/or a high-speed mode.
Automotive radar methods and systems for enhancing resistance to interference using a built-in self-test (BIST) module. In one illustrative embodiment, an automotive radar transceiver includes: a signal generator that generates a transmit signal; a modulator that derives a modulated signal from the transmit signal using at least one of phase and amplitude modulation; at least one receiver that mixes the transmit signal with a receive signal to produce a down-converted signal, the receive signal including the modulated signal during a built-in self-test (BIST) mode of operation; and at least one transmitter that drives a radar antenna with a selectable one of the transmit signal and the modulated signal.
G01S 13/34 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
G01S 13/36 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated with phase comparison between the received signal and the contemporaneously transmitted signal
G01S 13/931 - Radar or analogous systems, specially adapted for specific applications for anti-collision purposes of land vehicles
Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
An integrated circuit that includes an analog frequency-selective gain filter having a frequency-selective gain corresponding to a high-pass filter prior to an analog-to-digital converter (ADC) is described. During operation, the analog frequency-selective gain filter may provide frequency-selective gain (such as a high-pass filter characteristic) to an electrical signal corresponding to a received signal (such as a LiDAR signal, a sonar signal, an ultrasound signal and/or a radar signal) in a ranging receiver. Note that the received signal may correspond to a received frequency-modulated continuous-wave (FMCW) signal. Moreover, the integrated circuit may include a digital processing circuit after the ADC and control logic that instructs the digital processing circuit to characterize the frequency-selective gain (such as an amplitude and/or a phase at a frequency) during a calibration mode. Furthermore, the digital processing circuit may correct an output signal from the ADC based at least in part on the characterized frequency-selective gain.
G01S 13/34 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
G01S 7/4913 - Circuits for detection, sampling, integration or read-out
G01S 13/42 - Simultaneous measurement of distance and other coordinates
G01S 17/34 - Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
G01S 17/42 - Simultaneous measurement of distance and other coordinates
G01S 17/93 - Lidar systems, specially adapted for specific applications for anti-collision purposes
H03H 11/12 - Frequency selective two-port networks using amplifiers with feedback
56.
FREQUENCY-SELECTIVE COMPENSATION IN RANGING RECEIVERS UTILIZING CHIRPED WAVEFORMS
An integrated circuit that includes an analog frequency-selective gain filter having a frequency-selective gain corresponding to a high-pass filter prior to an analog-to-digital converter (ADC) is described. During operation, the analog frequency-selective gain filter may provide frequency-selective gain (such as a high-pass filter characteristic) to an electrical signal corresponding to a received signal (such as a LiDAR. signal, a sonar signal, an ultrasound signal and/or a radar signal) in a ranging receiver. Note that the received signal may correspond to a received frequency-modulated continuous-wave (FMCW) signal. Moreover, the integrated circuit may include a digital processing circuit after the ADC and control logic that instructs the digital processing circuit to characterize the frequency-selective gain (such as an amplitude and/or a phase at a frequency) during a calibration mode. Furthermore, the digital processing circuit may correct an output signal from the ADC based at least in part on the characterized frequency-selective gain.
G01S 13/10 - Systems for measuring distance only using transmission of interrupted, pulse modulated waves
G01S 13/26 - Systems for measuring distance only using transmission of interrupted, pulse modulated waves wherein the transmitted pulses use a frequency- or phase-modulated carrier wave
G01S 13/32 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated
G01S 13/34 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
57.
STABLE LOW-POWER ANALOG-TO-DIGITAL CONVERTER REFERENCE VOLTAGE
A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.
Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/364 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 13/14 - Handling requests for interconnection or transfer
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.
H03K 5/12 - Shaping pulses by steepening leading or trailing edges
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.
Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
G06F 13/36 - Handling requests for interconnection or transfer for access to common bus or bus system
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
G06F 13/14 - Handling requests for interconnection or transfer
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/26 - Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/364 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.
An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.
H03M 1/14 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
H03M 1/26 - Analogue/digital converters pattern-reading type using relatively movable reader and disc or strip with weighted coding, i.e. the weight given to a digit depends on the position of the digit within the block or code word, e.g. there is a given radix and the weights are powers of this radix
H03M 1/40 - Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type
64.
Configuration of ADC data rates across multiple physical channels
An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.
An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.
An analog-to-digital converter (ADC) is described. This ADC includes a conversion circuit with multiple bit-conversion circuits. During operation, the ADC may receive an input signal. Then, the conversion circuit may asynchronously perform successive- approximation-register (SAR) analog-to-digital conversion of the input signal using the bit- conversion circuits, where the bit-conversion circuits to provide a quantized representation of the input signal. For example, the bit-conversion circuits may asynchronously and sequentially perform the SAR analog-to-digital conversion to determine different bits in the quantized representation of the input signal. Moreover, the ADC may selectively perform self-calibration of a global delay of the bit-conversions circuits. Note that the timing self- calibration may be iterative and subject to a constraint that a maximum conversion time is less than a target conversion time.
H03M 1/14 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
H03M 1/26 - Analogue/digital converters pattern-reading type using relatively movable reader and disc or strip with weighted coding, i.e. the weight given to a digit depends on the position of the digit within the block or code word, e.g. there is a given radix and the weights are powers of this radix
H03M 1/40 - Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type
67.
INTERLEAVED ANALOG-TO-DIGITAL CONVERTER GAIN CALIBRATION
An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.
H03M 1/14 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
H03M 1/26 - Analogue/digital converters pattern-reading type using relatively movable reader and disc or strip with weighted coding, i.e. the weight given to a digit depends on the position of the digit within the block or code word, e.g. there is a given radix and the weights are powers of this radix
H03M 1/40 - Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type
An integrated circuit is described. This integrated circuit may include an input connector, coupled to a signal line, that conveys an input signal corresponding to encoded data, where the encoded data is encoded using a BMC, and the input signal may have different rise times and fall times. Moreover, the integrated circuit may include a recovery circuit, coupled to the input connector, that outputs the data based at least in part on a first threshold and a second threshold, where the output data may include data values with equal half-bit periods and variable frequency. Note that the recovery circuit may implement a state machine corresponding to the data.
An integrated circuit that controls distributed temperature sensors in a semiconductor die is described. This integrated circuit may include: memory; a controller (such as a PTAT controller) coupled to the memory; temperature sensors distributed at measurement locations in the semiconductor die (such as remote locations from the controller), where a given temperature sensor includes building blocks (or components) that are common to the temperature sensors; and routing between the controller and the building blocks over an addressable bus, where signal lines for analog signals in the addressable bus are reused when communicating between the controller and different temperature sensors.
G01K 7/00 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
G01K 7/16 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements
H05K 7/02 - Arrangements of circuit components or wiring on supporting structure
70.
Multi-sensing PTAT for multiple-location temperature sensing
An integrated circuit that controls distributed temperature sensors in a semiconductor die is described. This integrated circuit may include: memory; a controller (such as a PTAT controller) coupled to the memory; temperature sensors distributed at measurement locations in the semiconductor die (such as remote locations from the controller), where a given temperature sensor includes building blocks (or components) that are common to the temperature sensors; and routing between the controller and the building blocks over an addressable bus, where signal lines for analog signals in the addressable bus are reused when communicating between the controller and different temperature sensors.
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
G01K 13/00 - Thermometers specially adapted for specific purposes
G05D 23/19 - Control of temperature characterised by the use of electric means
G05D 23/20 - Control of temperature characterised by the use of electric means with sensing elements having variation of electric or magnetic properties with change of temperature
Analog-to-digital converters (ADCs) with a high sampling rate and larger spurious-free dynamic range (SFDR) in the spectral domain are used in many applications, including, but not limited to, range finders, meteorology, spectroscopy, and/or coherent medical imaging. Circuit techniques for time-interleaving a set of low-sampling-rate sub-ADCs into a higher sampling-rate ADC with a larger SFDR than existing approaches are described. In one embodiment, the circuit techniques add a small number of additional units or sub-ADCs. This change in architecture enables a dynamic-selection procedure to time-interleave the set of sub-ADCs in such a way that mismatch-related non-idealities of the constituent sub-ADCs are spread in the frequency domain into a noise-like spectral shape in order to prevent the creation of spurious tones, which would otherwise deleteriously impact the SFDR.
Analog-to-digital converters (ADCs) with a high sampling rate and larger spurious-free dynamic range (SFDR) in the spectral domain are used in many applications, including, but not limited to, range finders, metrology, spectroscopy, and/or coherent medical imaging. Circuit techniques for time-interleaving a set of low-sampling-rate sub- ADCs into a higher sampling- rate ADC with a larger SFDR than existing approaches are described. In one embodiment, the circuit techniques add a small number of additional units or sub- ADCs. This change in architecture enables a dynamic-selection procedure to time-interleave the set of sub- ADCs in such a way that mismatch-related non-idealities of the constituent sub-ADCs are spread in the frequency domain into a noise-like spectral shape in order to prevent the creation of spurious tones, which would otherwise deleteriously impact the SFDR.
An integrated circuit is described. This integrated circuit may include an input connector, coupled to a signal line, that conveys an input signal corresponding to encoded data, where the encoded data is encoded using a BMC, and the input signal may have different rise times and fall times. Moreover, the integrated circuit may include a recovery circuit, coupled to the input connector, that outputs the data based at least in part on a first threshold and a second threshold, where the output data may include data values with equal half-bit periods and variable frequency. Note that the recovery circuit may implement a state machine corresponding to the data.
Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/364 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 13/14 - Handling requests for interconnection or transfer
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
75.
Inter-die memory-bus transaction in a seamlessly integrated microcontroller chip
Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G06F 13/26 - Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/364 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 13/14 - Handling requests for interconnection or transfer
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
76.
Power management in a seamlessly integrated microcontroller chip
A system that includes a first die with a central processing unit (CPU) and a second die electrically coupled to the first die by die-to-die interconnects is described. During operation, the first die: provides, to the second die, a set of predefined wake-up events; provides, to the second die, a message that transitions power-management control of the first die to the second die; and transitions the first die from a first operating mode to a second operating mode that has lower power consumption than that of the first operating mode. Then, the second die: determines an occurrence of a predefined wake-up event based at least in part on the set of predefined wake-up events; and provides, to the first die, information that initiates a transition of the first die from the second operating mode to the first operating mode.
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/364 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 13/14 - Handling requests for interconnection or transfer
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
77.
Security policy management in a seamlessly integrated microcontroller chip
Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G06F 13/26 - Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/364 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 13/14 - Handling requests for interconnection or transfer
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
78.
Dynamically configurable interconnect in a seamlessly integrated microcontroller chip
Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/364 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 13/14 - Handling requests for interconnection or transfer
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/364 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 13/14 - Handling requests for interconnection or transfer
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
patents
