A semiconductor device includes a drift layer including silicon carbide and having a first conductivity type, a channel layer on the drift layer, the channel layer including silicon carbide and having the first conductivity type, and a source layer on the channel layer, the source layer including silicon carbide and having the first conductivity type. The device includes first and second trenches extending through the source layer and at least partially into the channel layer. The first and second trenches define a mesa therebetween having a mesa sidewall adjacent the channel layer. A heterojunction layer is in the first trench. The heterojunction layer includes a semiconductor material having a second conductivity type opposite the first conductivity type, wherein the heterojunction layer forms a PN heterojunction with silicon carbide.
H01L 29/80 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
Systems and methods for determining optical properties of a workpiece (e.g., silicon carbide workpiece). In some examples, the method includes providing emission of one or more electromagnetic radiation signals to the silicon carbide semiconductor workpiece such that the one or more electromagnetic radiation signals are at least partially transmitted through the silicon carbide semiconductor workpiece and internally reflected within the silicon carbide semiconductor workpiece. In some implementations, the example method includes receiving the one or more electromagnetic radiation signals at one or more detectors.
Systems and methods for optical characteristic measurements are provided. In one example, a system includes one or more electromagnetic radiation sources, one or more reflectors, and at least one detector. The one or more electromagnetic radiation sources provide emission of one or more electromagnetic radiation signals to a workpiece such that each of the one or more electromagnetic radiation signals are at least partially transmitted through the workpiece. The one or more reflectors reflect the one or more electromagnetic radiation signals back through the workpiece such that the one or more electromagnetic radiation signals are transmitted through the workpiece a plurality of transmission instances. One or more characteristics of the workpiece may be determined based at least in part on the one or more electromagnetic radiation signals received at the at least one detector.
H01L 21/66 - Testing or measuring during manufacture or treatment
G01N 21/33 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using ultraviolet light
G01N 21/3563 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light for analysing solidsPreparation of samples therefor
4.
METHOD AND SYSTEM TO MEASURE OPTICAL CHARACTERISTICS OF LIGHT-TRANSMISSIVE MATERIALS
Systems and methods for optical characteristic measurements are provided. In one example, a system includes one or more electromagnetic radiation sources, one or more reflectors, and at least one detector. The one or more electromagnetic radiation sources provide emission of one or more electromagnetic radiation signals to a workpiece such that each of the one or more electromagnetic radiation signals are at least partially transmitted through the workpiece. The one or more reflectors reflect the one or more electromagnetic radiation signals back through the workpiece such that the one or more electromagnetic radiation signals are transmitted through the workpiece a plurality of transmission instances. One or more characteristics of the workpiece may be determined based at least in part on the one or more electromagnetic radiation signals received at the at least one detector.
A power package includes an assembly having a first power package side, a second power package side, a third power package side, and a fourth power package side; first power terminals arranged at the first power package side; second power terminals arranged at the second power package side; first signal terminals arranged at the third power package side; second signal terminals arranged at the fourth power package side. The power package in addition includes where a location of the first power terminals at the first power package side is symmetrical with respect to a location of the second power terminals at the second power package side and/or a location of the first signal terminals on third power package side is symmetrical with respect to a location of the second signal terminals on fourth power package side.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
An example method includes obtaining data indicative of a workpiece processing parameter. In some implementations, the example method includes determining a grinding depth for a semiconductor workpiece based at least in part on the data indicative of the workpiece processing parameter. In some implementations, the example method includes performing a grinding operation to remove material from the semiconductor workpiece to reduce a thickness of the semiconductor workpiece by the grinding depth.
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
B24B 49/03 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation according to the instantaneous size and required size of the workpiece acted upon, the measuring or gauging being continuous or intermittent according to the final size of the previously ground workpiece
B24B 49/05 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation according to the instantaneous size and required size of the workpiece acted upon, the measuring or gauging being continuous or intermittent involving measurement of the workpiece at the place of grinding during grinding operation including the measurement of a first workpiece already machined and of another workpiece being machined and to be matched with the first one
H01L 21/66 - Testing or measuring during manufacture or treatment
An example method includes obtaining data indicative of a workpiece processing parameter. In some implementations, the example method includes determining a grinding depth for a semiconductor workpiece based at least in part on the data indicative of the workpiece processing parameter. In some implementations, the example method includes performing a grinding operation to remove material from the semiconductor workpiece to reduce a thickness of the semiconductor workpiece by the grinding depth.
A power package includes an assembly having a first power package side, a second power package side, a third power package side, and a fourth power package side; first power terminals arranged at the first power package side; second power terminals arranged at the second power package side; first signal terminals arranged at the third power package side; second signal terminals arranged at the fourth power package side. The power package in addition includes where a location of the first power terminals at the first power package side is symmetrical with respect to a location of the second power terminals at the second power package side and/or a location of the first signal terminals on third power package side is symmetrical with respect to a location of the second signal terminals on fourth power package side.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
9.
TREATMENTS FOR IMPROVING FRACTURE STRENGTH FOR SEMICONDUCTOR WORKPIECE
Systems and methods for increasing fracture strength of a semiconductor workpiece (e.g., silicon carbide) are provided. In some examples, a method includes removing a semiconductor wafer from a boule. The method includes implementing a treatment process on the semiconductor wafer removed from the boule. The treatment process includes a thermal treatment process or a chemical etching process. The treatment process provides a fracture strength of the semiconductor wafer in a range of about 17.5 Newtons or greater, such as in a range of about 17.5 Newtons to about 75 Newtons.
Systems and methods for laser-based surface processing operations on a wide bandgap semiconductor wafer, such as a silicon carbide semiconductor wafer, are provided. In one example, a method includes removing a wide bandgap semiconductor wafer from a boule using a removal process. The method includes ablating, with one or more lasers, an exposed surface resulting from the removal process to remove material from the exposed surface, wherein ablating, with one or more lasers, the exposed surface reduces a thickness of semiconductor material (e.g., by about 25 microns or greater).
Systems and methods for increasing fracture strength of a semiconductor workpiece (e.g., silicon carbide) are provided. In some examples, a method includes removing a semiconductor wafer from a boule. The method includes implementing a treatment process on the semiconductor wafer removed from the boule. The treatment process includes a thermal treatment process or a chemical etching process. The treatment process provides a fracture strength of the semiconductor wafer in a range of about 17.5 Newtons or greater, such as in a range of about 17.5 Newtons to about 75 Newtons.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
12.
Multi-Scale Autoencoders for Semiconductor Workpiece Understanding
An example method includes obtaining a workpiece image of a semiconductor workpiece. The example method includes providing the workpiece image as input to a machine-learned encoding model. The example method includes obtaining an output from the machine-learned encoding model, the output includes an encoding corresponding to the semiconductor workpiece. The example method includes determining one or more characteristics of the semiconductor workpiece based at least in part on the encoding or modifying a semiconductor manufacturing process based at least in part on the encoding.
An example method includes obtaining a workpiece image of a semiconductor workpiece. The example method includes providing the workpiece image as input to a machine-learned encoding model. The example method includes obtaining an output from the machine-learned encoding model, the output includes an encoding corresponding to the semiconductor workpiece. The example method includes determining one or more characteristics of the semiconductor workpiece based at least in part on the encoding or modifying a semiconductor manufacturing process based at least in part on the encoding.
Systems and methods for surface processing of a semiconductor workpiece, such as a silicon carbide semiconductor wafer, are provided. An example surface processing system includes a platen configured to rotate about an axis. The example surface processing system includes a surface processing pad on the platen. The example surface processing system includes a workpiece carrier operable to bring a semiconductor workpiece into contact with the surface processing pad. The workpiece carrier includes a head and a retaining ring around at least a portion of the head. At least one of the head and the retaining ring is movable relative to each other.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
15.
Polishing Pad Assembly for Electrochemical Mechanical Polishing
An example polishing system, such as an electrochemical mechanical polishing (ECMP) system, includes a polishing pad assembly having a polishing pad. The example polishing system includes a bias source. The example polishing system includes a workpiece carrier operable to bring the semiconductor workpiece into contact with the polishing pad. In some implementations, the polishing pad assembly is operable to provide an electrically conductive path for one or more charge carriers to the bias source.
A slurry for electrochemical mechanical polishing of semiconductor workpieces (e.g., silicon carbide semiconductor wafers) is provided. In one example embodiment, the slurry contains a solvent an abrasive particle, and an ionic compound. The ionic compound contains a cation and an anion. One or more of the cation or the anion is bonded to the abrasive particle, for instance, with a functional group or other bonding.
A semiconductor device includes semiconductor layer, a gate pad on the semiconductor layer, and a longitudinal gate finger on the semiconductor layer, the longitudinal gate finger having opposing first and second ends. The semiconductor device includes a first gate bus segment on the semiconductor layer. The first gate bus segment extends adjacent the first end of the longitudinal gate finger and has a proximal end nearest the gate pad and a distal end farthest from the gate pad. The first gate bus segment has a first width at the proximal end and a second width at the distal end. The first width is greater than the second width.
An example method includes providing a wide bandgap semiconductor workpiece. The example method includes exposing the wide bandgap semiconductor workpiece to one or more electrical discharges from an electrical discharge machining (EDM) system to reduce a surface roughness of the wide bandgap semiconductor workpiece. Exposing the wide bandgap semiconductor workpiece to the one or more electrical discharges may include submerging a surface of the wide bandgap semiconductor workpiece in a dielectric fluid; positioning an electrode head relative to the surface such that a gap is defined between an end of the electrode head and the surface; and generating an electrical discharge across the gap to create a plasma zone within the gap such that a material is removed from the surface.
An example method includes providing a first semiconductor workpiece including a first portion and a second portion. The example method includes providing emission of one or more lasers through a thickness of the first semiconductor workpiece to remove the first portion of the first semiconductor workpiece from the second portion. In some implementations, the second portion has a shape corresponding to a second semiconductor workpiece of a different diameter relative to the first semiconductor workpiece.
An example polishing system, such as an electrochemical mechanical polishing (ECMP) system, includes a polishing pad assembly having a polishing pad. The example polishing system includes a bias source. The example polishing system includes a workpiece carrier operable to bring the semiconductor workpiece into contact with the polishing pad. In some implementations, the polishing pad assembly is operable to provide an electrically conductive path for one or more charge carriers to the bias source.
B24B 37/22 - Lapping pads for working plane surfaces characterised by a multi-layered structure
B24B 37/24 - Lapping pads for working plane surfaces characterised by the composition or properties of the pad materials
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
21.
IONIC SLURRY FOR ELECTROCHEMICAL MECHANICAL POLISHING
A slurry for electrochemical mechanical polishing is provided. In one example embodiment, the slurry contains a solvent an abrasive particle, and an ionic compound. The ionic compound contains a cation and an anion. One or more of the cation or the anion is bonded to the abrasive particle.
An example method includes providing a first semiconductor workpiece including a first portion and a second portion. The example method includes providing emission of one or more lasers through a thickness of the first semiconductor workpiece to remove the first portion of the first semiconductor workpiece from the second portion. In some implementations, the second portion has a shape corresponding to a second semiconductor workpiece of a different diameter relative to the first semiconductor workpiece.
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
B23K 26/38 - Removing material by boring or cutting
B23K 26/40 - Removing material taking account of the properties of the material involved
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
23.
NONDESTRUCTIVE CHARACTERIZATION FOR CRYSTALLINE WAFERS
A method of analyzing semiconductor wafers includes capturing a first image of a first crystalline material, etching a first surface of the first crystalline material to delineate etch defects in the first crystalline material, and capturing a second image of first crystalline material after etching the first surface of the first crystalline material. Based on the second image, labels of etch defects delineated in the first surface of the first crystalline material are generated. The first image and the labels of etch defects are spatially coordinated to form a defect map identifying one or more defects in the first image based on the delineated etch defects, and based on the defect map and nondestructive data obtained from a second crystalline material, defects in the second crystalline material are identified.
Semiconductor devices comprise a semiconductor layer structure having an active region therein, a gate pad on the semiconductor layer structure and positioned to be closest to a first side of the active region, a plurality of gate electrodes, and a metal gate runner that electrically connects the gate pad to at least some of the gate electrodes. The metal gate runner comprises an outer runner that extends around a portion of a periphery of the active region. The outer gate runner comprises a first outer segment that extends along at least a portion of the first side of the active region and a second outer segment that extends along at least a portion of a second side of the active region that connects to the first side, but the outer gate runner does not extend along a third side of the active region that is opposite the second side.
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
Power semiconductor devices and power semiconductor device packages are provided. In one example, a power semiconductor device package includes a submount and a semiconductor die on the submount. In some examples, the semiconductor die includes a metallization structure, a first passivation layer on the metallization structure, a buffer layer on the first passivation layer, a second passivation layer on the buffer layer, and a polyimide layer directly on the second passivation layer. In some examples, the second passivation layer includes the same material as the first passivation layer.
H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - Details of semiconductor or other solid state devices
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
26.
Electrical discharge machining processing for semiconductor workpiece
An example method includes providing a wide bandgap semiconductor workpiece. The example method includes exposing the wide bandgap semiconductor workpiece to one or more electrical discharges from an electrical discharge machining (EDM) system to reduce a surface roughness of the wide bandgap semiconductor workpiece. Exposing the wide bandgap semiconductor workpiece to the one or more electrical discharges may include submerging a surface of the wide bandgap semiconductor workpiece in a dielectric fluid; positioning an electrode head relative to the surface such that a gap is defined between an end of the electrode head and the surface; and generating an electrical discharge across the gap to create a plasma zone within the gap such that a material is removed from the surface.
Power semiconductor devices and power semiconductor device packages are provided. In one example, a power semiconductor device package includes a submount and a semiconductor die on the submount. In some examples, the semiconductor die includes a metallization structure, a first passivation layer on the metallization structure, a buffer layer on the first passivation layer, a second passivation layer on the buffer layer, and a polyimide layer directly on the second passivation layer. In some examples, the second passivation layer includes the same material as the first passivation layer.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/784 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
28.
SEMICONDUCTOR DEVICES HAVING METAL GATE RUNNERS WITH ASYMMETRIC OUTER GATE RUNNERS, UNEVENLY-SPACED INNER GATE RUNNERS AND/OR SPINE-RIB INNER GATE RUNNERS WITH MULTIPLE RIBS
Semiconductor devices comprise a semiconductor layer structure having an active region therein, a gate pad on the semiconductor layer structure and positioned to be closest to a first side of the active region, a plurality of gate electrodes, and a metal gate runner that electrically connects the gate pad to at least some of the gate electrodes. The metal gate runner comprises an outer runner that extends around a portion of a periphery of the active region. The outer gate runner comprises a first outer segment that extends along at least a portion of the first side of the active region and a second outer segment that extends along at least a portion of a second side of the active region that connects to the first side, but the outer gate runner does not extend along a third side of the active region that is opposite the second side.
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
29.
TRENCH GATE WIDE BANDGAP JUNCTION FIELD EFFECT TRANSISTORS WITH TERMINATION REGIONS HAVING PLANAR UPPER SURFACES
JFETs are provided that comprise a wide bandgap semiconductor layer structure comprising an active region and a termination region. The termination region comprises a plurality of termination structures. A first major surface of the semiconductor layer structure in the active region comprises a plurality of spaced-apart mesas and the first major surface of the semiconductor layer structure in the termination region is a planar surface.
A method for conditioning a polishing pad of a polishing system is provided. The method comprises performing an in-situ pad conditioning process and an ex-situ pad conditioning process outside of a polishing operation. The in-situ pad conditioning process comprises causing a pad conditioner to contact the polishing pad during the polishing operation. The ex-situ pad conditioning process comprises causing the pad conditioner to contact the polishing pad while a cleaning agent is applied to the polishing pad.
Systems and methods for laser-based surface processing operations on a wide bandgap semiconductor wafer, such as a silicon carbide semiconductor wafer, are provided. In one example, a method includes providing a semiconductor workpiece having a surface, the semiconductor workpiece including silicon carbide. The method includes providing a filler material on at least a portion of the surface. The method includes, subsequent to providing the filler material, performing a surface processing operation on the surface.
Gate trench semiconductor devices having reduced capacitance between a semiconductor layer structure and a gate electrode thereof. For example, a semiconductor device may include a semiconductor layer structure that comprises a drift region having a first conductivity type, a well layer having a second conductivity type, and a source region having the first conductivity type; a first gate trench extending into an upper portion of the semiconductor layer structure; a first dielectric layer within the first gate trench and conforming to an interior perimeter of the first gate trench; and a first gate electrode within the first gate trench and on the first dielectric layer. The gate electrode may have first and second portions that are spaced apart from each other by a second dielectric layer.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
33.
GATE TRENCH POWER SEMICONDUCTOR DEVICES HAVING SPLIT GATE ELECTRODES
Gate trench semiconductor devices having reduced capacitance between a semiconductor layer structure and a gate electrode thereof. For example, a semiconductor device may include a semiconductor layer structure that comprises a drift region having a first conductivity type, a well layer having a second conductivity type, and a source region having the first conductivity type; a first gate trench extending into an upper portion of the semiconductor layer structure; a first dielectric layer within the first gate trench and conforming to an interior perimeter of the first gate trench; and a first gate electrode within the first gate trench and on the first dielectric layer. The gate electrode may have first and second portions that are spaced apart from each other by a second dielectric layer.
An example seed structure, systems, and methods for conducting crystal growth processes are provided. In one example, the present disclosure provides an example seed structure for a silicon carbide crystal growth system. The seed structure includes a carrier layer. The carrier layer is silicon carbide. The seed structure includes a seed layer bonded to the carrier layer with a bond. The seed layer is crystalline silicon carbide. The seed layer provides a growth surface for growing a crystalline silicon carbide structure in a silicon carbide crystal growth process.
A method for conditioning a polishing pad of a polishing system is provided. The method comprises performing an in-situ pad conditioning process and an ex-situ pad conditioning process outside of a polishing operation. The in-situ pad conditioning process comprises causing a pad conditioner to contact the polishing pad during the polishing operation. The ex-situ pad conditioning process comprises causing the pad conditioner to contact the polishing pad while a cleaning agent is applied to the polishing pad.
B24B 53/017 - Devices or means for dressing, cleaning or otherwise conditioning lapping tools
B24B 37/10 - Lapping machines or devicesAccessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping
Example aspects of the present disclosure are directed to power semiconductor device packages and methods of forming the same. In one example, a power semiconductor device package includes a submount, a semiconductor die on the submount, a die-attach material coupling the semiconductor die to the submount, and a housing formed around at least a portion of the submount and the semiconductor die. The semiconductor die includes a semiconductor structure, a metallization structure on a major surface of the semiconductor structure, and one or more support structures on the metallization structure. In one example, the die-attach material is provided around the one or more support structures between the semiconductor die and the submount.
A semiconductor device includes a semiconductor layer structure including a drift region, a gate trench in the semiconductor layer structure extending in a first direction parallel to an upper surface of the semiconductor layer structure, and a trench shielding region in the semiconductor layer structure beneath a bottom of the gate trench. The trench shielding region includes a first portion having a uniform width in a third direction, parallel to the upper surface of the semiconductor layer structure and perpendicular to the first direction, at a first depth in a second direction perpendicular to the upper surface of the semiconductor layer structure and a second portion having a non-uniform width in the third direction at the first depth in the second direction.
At least one negative voltage generator that is configured for implementation with at least one gate driver and at least one power device. The at least one negative voltage generator including at least one energy storage device; at least one current flow control circuit; and at least one current limiting circuit. The at least one negative voltage generator is configured as a circuit to ensure a resulting gate drive signal is negative.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
39.
GATE TRENCH POWER SEMICONDUCTOR DEVICES HAVING ENHANCED AVALANCHE ROBUSTNESS AND METHODS OF FORMING SUCH DEVICES
A semiconductor device includes a semiconductor layer structure including a drift region, a gate trench in the semiconductor layer structure extending in a first direction parallel to an upper surface of the semiconductor layer structure, and a trench shielding region in the semiconductor layer structure beneath a bottom of the gate trench. The trench shielding region includes a first portion having a uniform width in a third direction, parallel to the upper surface of the semiconductor layer structure and perpendicular to the first direction, at a first depth in a second direction perpendicular to the upper surface of the semiconductor layer structure and a second portion having a non-uniform width in the third direction at the first depth in the second direction.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
40.
VERTICAL JFET SEMICONDUCTOR DEVICES WITH LOCALIZED AVALANCHE BREAKDOWN
A semiconductor device includes an active region comprising first and second mesa stripes and a trench between the mesa stripes. The trench has a first width between the first and second mesa stripes near a central portion of the first and second mesa stripes and a second width between the first and second mesa stripes near end portions of the first and second mesa stripes. The second width is less than the first width.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
Systems and methods for laser-based processing of semiconductor wafers are provided. In one example, a method includes providing emission of a laser from a laser source towards an edge portion of a wide bandgap semiconductor workpiece from a direction facing a side surface of the wide bandgap semiconductor workpiece, the side surface extending between a first major surface of the wide bandgap semiconductor workpiece and an opposing second major surface of the wide bandgap semiconductor workpiece. The method includes ablating the edge portion of the wide bandgap semiconductor workpiece with the laser to remove material from the edge portion of the wide bandgap semiconductor workpiece.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H01L 21/66 - Testing or measuring during manufacture or treatment
B23K 26/03 - Observing, e.g. monitoring, the workpiece
B23K 26/0622 - Shaping the laser beam, e.g. by masks or multi-focusing by direct control of the laser beam by shaping pulses
Systems and methods for laser-based surface processing operations on a wide bandgap semiconductor wafer, such as a silicon carbide semiconductor wafer, are provided. In one example, a method includes providing a semiconductor workpiece having a surface, the semiconductor workpiece including silicon carbide. The method includes providing a filler material on at least a portion of the surface. The method includes, subsequent to providing the filler material, performing a surface processing operation on the surface.
Semiconductor device packages and methods for manufacturing the same are provided. In one example, a semiconductor structure may be provided on a substrate, and a metastable reactive layer may be provided on the semiconductor structure. Energy may be applied to the metastable reactive layer to form a silicide layer on the semiconductor structure, and, in some examples, a metallization structure may be provided on the silicide layer.
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
Systems and methods for laser-based processing of semiconductor wafers are provided. In one example, a method includes providing emission of a laser from a laser source towards an edge portion of a wide bandgap semiconductor workpiece from a direction facing a side surface of the wide bandgap semiconductor workpiece, the side surface extending between a first major surface of the wide bandgap semiconductor workpiece and an opposing second major surface of the wide bandgap semiconductor workpiece. The method includes ablating the edge portion of the wide bandgap semiconductor workpiece with the laser to remove material from the edge portion of the wide bandgap semiconductor workpiece.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
45.
POWER SILICON CARBIDE BASED SEMICONDUCTOR DEVICES HAVING SUPER JUNCTION DRIFT REGIONS AND METHODS OF FORMING SUCH DEVICES
A semiconductor device such as a MOSFET or IGBT comprises a semiconductor layer structure that comprises a drift region, a plurality of well regions having a second conductivity type on the drift region, and a plurality of source regions having a first conductivity type on the well regions. The drift region comprises a plurality of first pillars that have the first conductivity type and a first doping concentration, a plurality of second pillars that have the second conductivity type and a second doping concentration, and a plurality of third pillars that have the first conductivity type and a third doping concentration, The second and third doping concentrations exceed the first doping concentration, and the first, second and third pillars forming a super junction structure in the drift region
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
46.
LASER-BASED SURFACE PROCESSING FOR SEMICONDUCTOR WORKPIECE
Systems and methods for laser-based surface processing operations on a wide bandgap semiconductor wafer, such as a silicon carbide semiconductor wafer, are provided. In one example, a method includes removing a wide bandgap semiconductor wafer from a boule using a removal process. The method includes ablating, with one or more lasers, an exposed surface resulting from the removal process to remove material from the exposed surface, wherein ablating, with one or more lasers, the exposed surface reduces a thickness of semiconductor material (e.g., by about 25 microns or greater).
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
Systems and methods for laser-based surface processing operations on a semiconductor wafer, such as a silicon carbide semiconductor wafer, are provided. In one example, a method includes providing a semiconductor workpiece having a surface. The method includes providing emission of one or more lasers to the surface of a semiconductor workpiece at a non-perpendicular incidence angle relative to the surface. The method includes imparting relative motion between the one or more lasers and the semiconductor workpiece while providing emission of the one or more lasers to the surface of the semiconductor workpiece at the non-perpendicular incidence angle.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
Systems and methods for laser-based surface processing operations on a wide bandgap semiconductor wafer, such as a silicon carbide semiconductor wafer, are provided. In one example, a method includes removing a wide bandgap semiconductor wafer from a boule using a removal process. The method includes ablating, with one or more lasers, an exposed surface resulting from the removal process to remove material from the exposed surface, wherein ablating, with one or more lasers, the exposed surface reduces a thickness of semiconductor material (e.g., by about 25 microns or greater).
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
B23K 26/03 - Observing, e.g. monitoring, the workpiece
B23K 26/08 - Devices involving relative movement between laser beam and workpiece
B23K 26/40 - Removing material taking account of the properties of the material involved
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
Systems and methods for laser-based surface processing operations on a semiconductor wafer, such as a silicon carbide semiconductor wafer, are provided. In one example, a method includes providing a semiconductor workpiece having a surface. The method includes providing emission of one or more lasers to the surface of a semiconductor workpiece at a non-perpendicular incidence angle relative to the surface. The method includes imparting relative motion between the one or more lasers and the semiconductor workpiece while providing emission of the one or more lasers to the surface of the semiconductor workpiece at the non-perpendicular incidence angle.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Semiconductor die and methods for manufacturing the same are provided. In one example, a semiconductor wafer having a plurality of lateral semiconductor device units may be provided. One or more cut lines, which group the plurality of lateral semiconductor device units into a plurality of semiconductor die, may be determined, and the semiconductor wafer may be cut along the one or more cut lines. In some examples, semiconductor die cut from the semiconductor wafer may have the same or different sizes. In some examples, semiconductor die cut from the semiconductor wafer may have the same or different numbers of lateral semiconductor device units. In some examples, a semiconductor die cut from the semiconductor wafer may include one or more uncut scribe lines between each of a plurality of lateral semiconductor device units.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
51.
POWER MODULE IMPLEMENTING TRUE AND PARTIAL SOURCE KELVIN INTERCONNECTIONS FOR ENHANCING SWITCHING PERFORMANCE AND PROCESS OF IMPLEMENTING THE SAME
A power module includes a power substrate, at least one first power device arranged on the power substrate, at least one second power device arranged on the power substrate, at least one true Kelvin interconnection, and at least one pseudo-Kelvin interconnection.
A semiconductor device such as a MOSFET or IGBT comprises a semiconductor layer structure that comprises a drift region, a plurality of well regions having a second conductivity type on the drift region, and a plurality of source regions having a first conductivity type on the well regions. The drift region comprises a plurality of first pillars that have the first conductivity type and a first doping concentration, a plurality of second pillars that have the second conductivity type and a second doping concentration, and a plurality of third pillars that have the first conductivity type and a third doping concentration, The second and third doping concentrations exceed the first doping concentration, and the first, second and third pillars forming a super junction structure in the drift region
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A power module includes a power substrate, at least one first power device arranged on the power substrate, at least one second power device arranged on the power substrate, at least one true Kelvin interconnection, and at least one pseudo- Kelvin interconnection.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups or
54.
GATE TRENCH POWER SEMICONDUCTOR DEVICES HAVING TRENCH SHIELDING REGIONS AND METHODS OF FORMING THE SAME
A semiconductor device comprises a semiconductor layer structure that comprises a drift region having a first conductivity type and a trench shielding region having a second conductivity type, and a gate trench extending in a longitudinal direction in the semiconductor layer structure. The trench shielding region extends in the longitudinal direction underneath the gate trench, and at least a portion of the trench shielding region comprises sidewalls that angle inwardly with increasing distance from the gate trench.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
55.
POWER DEVICES WITH BARRIER METAL EXTENSION AND SEALING
A semiconductor device includes a semiconductor layer (and a metal contact structure on the semiconductor layer, the metal contact structure comprising a first metal layer structure on the semiconductor layer. The first metal layer structure may include a barrier layer and a first metal contact layer on the barrier layer. An outer edge of the first metal contact layer is inset from an outer edge of the barrier layer so that a peripheral portion of the barrier layer extends farther outward than the outer edge of the first metal contact layer.
A semiconductor device includes a semiconductor die, and a topside metallization on a first side of the semiconductor die. The topside metallization includes a metal layer on the semiconductor die, the metal layer having a first thickness, and at least two discrete bond pads on the metal layer. The discrete bond pads have a second thickness that is larger than the first thickness. A backside metallization may be formed on the back side of the semiconductor die. The backside metallization includes a metal layer having a first portion having a first thickness and a second portion having a second thickness that is smaller than the first thickness.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
57.
POWER DEVICES WITH BARRIER METAL EXTENSION AND SEALING
A semiconductor device includes a semiconductor layer (and a metal contact structure on the semiconductor layer, the metal contact structure comprising a first metal layer structure on the semiconductor layer. The first metal layer structure may include a barrier layer and a first metal contact layer on the barrier layer. An outer edge of the first metal contact layer is inset from an outer edge of the barrier layer so that a peripheral portion of the barrier layer extends farther outward than the outer edge of the first metal contact layer.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
58.
POWER DEVICES WITH MULTIPLE METAL LAYER THICKNESSES
A semiconductor device includes a semiconductor die, and a topside metallization on a first side of the semiconductor die. The topside metallization includes a metal layer on the semiconductor die, the metal layer having a first thickness, and at least two discrete bond pads on the metal layer. The discrete bond pads have a second thickness that is larger than the first thickness. A backside metallization may be formed on the back side of the semiconductor die. The backside metallization includes a metal layer having a first portion having a first thickness and a second portion having a second thickness that is smaller than the first thickness.
A semiconductor device comprises a semiconductor layer structure that comprises a drift region having a first conductivity type and a trench shielding region having a second conductivity type, and a gate trench extending in a longitudinal direction in the semiconductor layer structure. The trench shielding region extends in the longitudinal direction underneath the gate trench, and at least a portion of the trench shielding region comprises sidewalls that angle inwardly with increasing distance from the gate trench.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
60.
VERTICAL JFET SEMICONDUCTOR DEVICES WITH AVALANCHE CURRENT BALLAST RESISTANCE
A semiconductor device includes a semiconductor layer structure that includes an active region including a plurality of gate trenches, a plurality of gate contacts in respective ones of the gate trenches, a gate pad on the semiconductor layer structure, a gate bus extending from the gate pad, and a conductive path between the gate bus and a first one of the plurality of gate contacts. The conductive path includes a first resistivity region and at least one second resistivity region that has a higher resistivity than the first resistivity region.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
61.
SEMICONDUCTOR DEVICES HAVING INTRINSIC GATE-TO-DRAIN CAPACITANCES THAT ARE ONLY PARTLY IN SERIES WITH A GATE RESISTOR
Power JFETs are provided that include a semiconductor layer structure that has an active region and a termination region, where the termination region at least partially surrounds the active region. These power JFETs further comprise a plurality of gate regions and a gate pad on the semiconductor layer structure, as well as a gate resistor that is electrically connected between the gate pad and the gate regions. The gate resistor extends around a periphery of the active region when the semiconductor device is viewed in plan view.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
Grinding systems and methods for semiconductor workpieces are provided. In one example, a grinding system includes a workpiece support operable to support a semiconductor workpiece and rotate the semiconductor workpiece about a first axis. The grinding system further includes a grind wheel operable to rotate about a second axis. The grind wheel has a plurality of grinding teeth arranged in a grinding ring on the grind wheel. A radius of the grinding ring is less than or equal to a radius of the semiconductor workpiece (e.g., such that an effective gap ratio between grinding teeth on the grind wheel are reduced).
B24B 7/22 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfacesAccessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
Systems and methods for grinding semiconductor workpieces are provided. In one example, a method includes providing a surface of the semiconductor workpiece against a grinding apparatus. The grinding apparatus includes an abrasive surface. The method further includes imparting relative motion between the abrasive surface and the semiconductor workpiece to implement a grinding operation on the semiconductor workpiece. The method further includes providing a fluid to the surface of the semiconductor workpiece or the abrasive surface during the grinding operation. The fluid includes an additive. The additive includes one or more of an oxidizing agent, an etchant, a surfactant, or a lubricant.
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
B24B 7/22 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfacesAccessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
64.
Disc Grinding for Semiconductor Wafers on Polishing System
Grind discs for semiconductor polishing systems are provided. In one example, a semiconductor workpiece polishing system includes a platen configured to rotate about an axis. The semiconductor workpiece polishing system further includes a grind disc on the platen, the grind disc has an abrasive surface configured to grind silicon carbide. The semiconductor workpiece polishing system includes a workpiece carrier operable to bring a silicon carbide semiconductor workpiece into contact with the grind disc to implement a grinding operation on the silicon carbide semiconductor workpiece. The grinding operation reduces a thickness of the silicon carbide semiconductor workpiece by at least about 0.5 microns.
B24B 37/24 - Lapping pads for working plane surfaces characterised by the composition or properties of the pad materials
B24B 55/02 - Equipment for cooling the grinding surfaces, e.g. devices for feeding coolant
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/463 - Mechanical treatment, e.g. grinding, ultrasonic treatment
Grinding systems and methods for semiconductor workpieces are provided. In one example, a grinding system includes a workpiece support operable to support a semiconductor workpiece and rotate the semiconductor workpiece about a first axis. The grinding system further includes a grind wheel operable to rotate about a second axis. The grind wheel has a plurality of grinding teeth arranged in a grinding ring on the grind wheel. A radius of the grinding ring is less than or equal to a radius of the semiconductor workpiece (e.g., such that an effective gap ratio between grinding teeth on the grind wheel are reduced).
B24B 7/22 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfacesAccessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
B24D 7/06 - Bonded abrasive wheels, or wheels with inserted abrasive blocks, designed for acting otherwise than only by their periphery, e.g. by the front faceBushings or mountings therefor with inserted abrasive blocks, e.g. segmental
Systems and methods for grinding semiconductor workpieces are provided. In one example, a method includes providing a surface of the semiconductor workpiece against a grinding apparatus. The grinding apparatus includes an abrasive surface. The method further includes imparting relative motion between the abrasive surface and the semiconductor workpiece to implement a grinding operation on the semiconductor workpiece. The method further includes providing a fluid to the surface of the semiconductor workpiece or the abrasive surface during the grinding operation. The fluid includes an additive. The additive includes one or more of an oxidizing agent, an etchant, a surfactant, or a lubricant.
B24B 7/22 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfacesAccessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
B24B 37/10 - Lapping machines or devicesAccessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping
B24B 55/02 - Equipment for cooling the grinding surfaces, e.g. devices for feeding coolant
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
B24D 3/34 - Physical features of abrasive bodies, or sheets, e.g. abrasive surfaces of special natureAbrasive bodies or sheets characterised by their constituents characterised by additives enhancing special physical properties, e.g. wear resistance, electric conductivity, self-cleaning properties
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
B24B 37/24 - Lapping pads for working plane surfaces characterised by the composition or properties of the pad materials
Systems and methods for polishing semiconductor workpieces are provided. In one example, the polishing system includes a platen operable to rotate about an axis. The polishing system further includes a polishing pad on the platen. The polishing system further includes a workpiece carrier operable to bring a semiconductor workpiece into contact with the polishing pad. The polishing pad includes a first zone and a second zone.
B24B 37/26 - Lapping pads for working plane surfaces characterised by the shape of the lapping pad surface, e.g. grooved
B24B 37/005 - Control means for lapping machines or devices
B24B 37/22 - Lapping pads for working plane surfaces characterised by a multi-layered structure
B24B 37/24 - Lapping pads for working plane surfaces characterised by the composition or properties of the pad materials
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
68.
DISC GRINDING FOR SEMICONDUCTOR WAFERS ON POLISHING SYSTEM
Grind discs for semiconductor polishing systems are provided. In one example, a semiconductor workpiece polishing system includes a platen configured to rotate about an axis. The semiconductor workpiece polishing system further includes a grind disc on the platen, the grind disc has an abrasive surface configured to grind silicon carbide. The semiconductor workpiece polishing system includes a workpiece carrier operable to bring a silicon carbide semiconductor workpiece into contact with the grind disc to implement a grinding operation on the silicon carbide semiconductor workpiece. The grinding operation reduces a thickness of the silicon carbide semiconductor workpiece by at least about 0.5 microns.
B24D 3/34 - Physical features of abrasive bodies, or sheets, e.g. abrasive surfaces of special natureAbrasive bodies or sheets characterised by their constituents characterised by additives enhancing special physical properties, e.g. wear resistance, electric conductivity, self-cleaning properties
B24B 37/24 - Lapping pads for working plane surfaces characterised by the composition or properties of the pad materials
69.
DEVICE PACKAGE HAVING A CONTACTLESS SENSOR AND PROCESS OF IMPLEMENTING THE SAME
A device package includes an assembly that includes an assembly top surface; signal contacts arranged in and/or on the assembly; power contacts arranged in and/or on the assembly; at least one power device; at least one sensor receptacle; and at least one sensor arranged in the at least one sensor receptacle.
A snubber device includes a snubber assembly, a snubber circuit including at least one snubber capacitor, and moreover includes a snubber substrate. The snubber device also includes where the snubber device is configured to be arranged outside and separate from a power module.
A semiconductor device having expanded creepage distance includes a drift region comprising an active region, including at least one active element therein, and an edge termination region around at least a portion of a perimeter of the active region when viewed in plan view. The semiconductor device further includes a passivation structure on the edge termination region, the passivation structure including an insulating layer on the drift region, and a first polymer layer on the insulating layer opposite the drift region. The first polymer layer includes a top surface that is nonplanar.
H01L 23/24 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel, at the normal operating temperature of the device
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A device package includes an assembly that includes an assembly top surface; signal contacts arranged in and/or on the assembly; power contacts arranged in and/or on the assembly; at least one power device; at least one sensor receptacle; and at least one sensor arranged in the at least one sensor receptacle.
Semiconductor device packages are provided. In one example, the semiconductor device package includes a housing, a submount, a thermoelectric structure on the submount, at least one semiconductor die on the thermoelectric structure, and at least one connection structure extending from the housing that is coupled to the thermoelectric structure. The thermoelectric structure includes an array of thermoelectric semiconductor structures and is operable to adjust a temperature difference between a first side and a second side of the thermoelectric structure based on a bias voltage applied to the thermoelectric structure.
H01L 23/38 - Cooling arrangements using the Peltier effect
H01L 23/373 - Cooling facilitated by selection of materials for the device
H10N 10/17 - Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the structure or configuration of the cell or thermocouple forming the device
Semiconductor device packages are provided. In one example, the semiconductor device package includes a submount and a semiconductor die on the submount. In one example, the semiconductor die includes a semiconductor structure and a multilayer metallization structure on the semiconductor structure. The multilayer metallization structure includes a first metallization layer and a second metallization layer, which includes a different grain microstructure than the first metallization layer, on the first metallization layer. In one example, the first metallization layer and the second metallization layer include at least one common element.
H01L 23/528 - Layout of the interconnection structure
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
75.
SILICON CARBIDE POWER DEVICES HAVING EXPANDED CREEPAGE DISTANCES
A semiconductor device having expanded creepage distance includes a drift region comprising an active region, including at least one active element therein, and an edge termination region around at least a portion of a perimeter of the active region when viewed in plan view. The semiconductor device further includes a passivation structure on the edge termination region, the passivation structure including an insulating layer on the drift region, and a first polymer layer on the insulating layer opposite the drift region. The first polymer layer includes a top surface that is nonplanar.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A semiconductor wafer is provided. The semiconductor wafer includes a substrate. The semiconductor wafer further includes a first device structure on the substrate. The semiconductor wafer further includes a second device structure on the substrate. The semiconductor wafer further includes a gap region on the substrate between the first device structure and the second device structure. The semiconductor wafer further includes one or more process control monitor structures in the gap region. The semiconductor wafer further includes a first scribe line on a first side of the gap region and a second scribe line on a second side of the gap region.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
77.
SEMICONDUCTOR WAFER WITH PROCESS CONTROL MONITOR STRUCTURES
A semiconductor wafer is provided. The semiconductor wafer includes a substrate. The semiconductor wafer further includes a first device structure on the substrate. The semiconductor wafer further includes a second device structure on the substrate. The semiconductor wafer further includes a gap region on the substrate between the first device structure and the second device structure. The semiconductor wafer further includes one or more process control monitor structures in the gap region. The semiconductor wafer further includes a first scribe line on a first side of the gap region and a second scribe line on a second side of the gap region.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
78.
DEVICES IMPLEMENTING SELECTIVE CAP LAYERS AND PROCESSES FOR IMPLEMENTING THE SAME
A device includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a source electrically coupled to the barrier layer and/or the channel layer, a gate at least partially on the barrier layer, and a drain electrically coupled to the barrier layer and/or the channel layer. The device moreover includes a cap layer structured, configured, and/or arranged under an edge of the gate at a drain side.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A power semiconductor device includes a semiconductor structure comprising an active region, a plurality of gates that extend in a first direction in or on the active region of the semiconductor structure, at least one integrated polysilicon device in or on the semiconductor structure adjacent the active region, and a gate connector electrically connecting the plurality of gates. The gate connector is in or on the semiconductor structure between the at least one integrated polysilicon device and the plurality of gates. The at least one integrated polysilicon device is electrically isolated from the gate connector devoid of an inter-polysilicon dielectric layer therebetween. Related devices and fabrication methods are also discussed.
Semiconductor device are provided. In one example, a semiconductor device includes a substrate. The semiconductor device includes a plurality of semiconductor layers on the substrate. The plurality of semiconductor layers are bonded to one another in a stacked arrangement.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
81.
POWER SEMICONDUCTOR DEVICE INCLUDING INTEGRATED POLYSILICON DEVICE
A power semiconductor device includes a semiconductor structure comprising an active region, a plurality of gates that extend in a first direction in or on the active region of the semiconductor structure, at least one integrated polysilicon device in or on the semiconductor structure adjacent the active region, and a gate connector electrically connecting the plurality of gates. The gate connector is in or on the semiconductor structure between the at least one integrated polysilicon device and the plurality of gates. The at least one integrated polysilicon device is electrically isolated from the gate connector devoid of an inter-polysilicon dielectric layer therebetween. Related devices and fabrication methods are also discussed.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
A semiconductor device includes a substrate (108). The semiconductor device includes a plurality of semiconductor layers (110, 120, 130, 140) on the substrate. The plurality of semiconductor layers are bonded to one another in a stacked arrangement.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
A semiconductor device includes an active region comprising a plurality of alternating trenches and mesas in an epitaxial layer, the plurality of alternating trenches and mesas extending in a first direction, and an edge termination region adjacent the active region and including a first edge termination region and a second edge termination region. The edge termination region includes first and second guard ring trenches adjacent the active region that are separated by a termination mesa that extends in the first direction in the first edge termination region and extends in a second direction, perpendicular to the first direction, in the second edge termination region. The termination mesa has a first width in the first edge termination region and the termination mesa has a second width in the second edge termination region that is different from the first width.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
Semiconductor structures including N-polar Group III-nitride are provided. The semiconductor structure includes an anti-reflective layer provided on an N-polar Group III-nitride semiconductor structure. The semiconductor structure includes a photoresist layer on the N-Polar Group III-nitride semiconductor structure. The anti-reflective layer has a thickness outside of an anti-reflectivity range associated with a photolithography process.
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
85.
Thermally Stable FinFET Device for High Temperature Operation
A semiconductor device is provided. The semiconductor device includes a semiconductor structure comprising silicon carbide. The semiconductor device further includes a mesa structure protruding in a first direction from the semiconductor structure, the mesa structure extending in a second direction between a first contact on the semiconductor structure and a second contact on the semiconductor structure. The semiconductor device further includes a channel region in the mesa structure. The semiconductor device further includes an electrically floating confining region, the electrically floating confining region in contact with the channel region in the mesa structure. The semiconductor device further includes a third contact on at least one sidewall of the mesa structure.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate
86.
GATE TRENCH POWER SEMICONDUCTOR DEVICES HAVING DEEP TRENCH SHIELD CONNECTION PATTERNS
A semiconductor device comprises a semiconductor layer structure that has a gate trench therein and a source metallization layer on the semiconductor layer structure. The semiconductor layer structure comprises a drift region having a first conductivity type, a trench shield that has a second conductivity type, the trench shield positioned underneath the gate trench, and a trench shield connection pattern that has the second conductivity type, the trench shield connection pattern electrically connecting the trench shield to the source metallization layer, where the trench shield connection pattern extends deeper into the semiconductor layer structure than the trench shield.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
87.
GATE TRENCH POWER SEMICONDUCTOR DEVICES HAVING DEEP TRENCH SHIELD CONNECTION PATTERNS
A semiconductor device comprises a semiconductor layer structure that has a gate trench therein and a source metallization layer on the semiconductor layer structure. The semiconductor layer structure comprises a drift region having a first conductivity type, a trench shield that has a second conductivity type, the trench shield positioned underneath the gate trench, and a trench shield connection pattern that has the second conductivity type, the trench shield connection pattern electrically connecting the trench shield to the source metallization layer, where the trench shield connection pattern extends deeper into the semiconductor layer structure than the trench shield.
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
88.
Thermal Management Enhancement of Electronic Components
An electronics arrangement comprises an electrically insulative substrate comprising a top side and a bottom side. The electronics arrangement further comprises an inductor, a capacitor, or both. The electronics arrangement further comprises a thermally conductive heat transfer structure operative to transfer heat away from the ferrite core, the capacitor, or both.
Power semiconductor devices are provided. In one example, a power semiconductor device includes a semiconductor structure. The power semiconductor device further includes a polysilicon gate layer on the semiconductor structure in an inactive region of the semiconductor device. The power semiconductor device further includes a gate insulating pattern between the polysilicon gate layer and the semiconductor structure, the gate insulating pattern having a thickness such that a distance between the semiconductor in the inactive region and the polysilicon gate layer through the gate insulating pattern is less than about 100 nm. The power semiconductor device further includes a shunt contact structure on semiconductor structure in the inactive region. A gate insulating electric field across the gate insulating pattern associated with a displacement current is less than about 8 MV/cm.
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
90.
Power Semiconductor Device Having Improved Transient Handling Without Field Insulating Layer
Power semiconductor devices are provided. In one example, a power semiconductor device includes a semiconductor structure. The power semiconductor device further includes a polysilicon gate layer on the semiconductor structure in an inactive region of the semiconductor device. The power semiconductor device further includes a gate insulating pattern between the polysilicon gate layer and the semiconductor structure, the gate insulating pattern having a thickness such that a distance between the semiconductor in the inactive region and the polysilicon gate layer through the gate insulating pattern is less than about 100 nm. The power semiconductor device further includes a shunt contact structure on semiconductor structure in the inactive region. A gate insulating electric field across the gate insulating pattern associated with a displacement current is less than about 8 MV/cm.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Systems and methods for laser-based surface processing operations on a wide bandgap semiconductor wafer, such as a silicon carbide semiconductor wafer, are provided. In one example, a method includes providing a semiconductor workpiece having a surface, the semiconductor workpiece including silicon carbide. The method includes providing a filler material on at least a portion of the surface. The method includes, subsequent to providing the filler material, performing a surface processing operation on the surface.
04 - Industrial oils and greases; lubricants; fuels
09 - Scientific and electric apparatus and instruments
Goods & Services
Renewable energy, namely, wind energy, solar energy, hydropower energy, geothermal energy and bioenergy. Battery chargers; renewable battery system to provide backup power; wireless chargers; solar inverters; batteries, electric for vehicles; charging stations for charging electric vehicles; power supplies, electrical; voltage stabilizing power supply; high-voltage power supplies; low-voltage power supplies; electronic power supplies for electric motors; solar panels for the production of electricity; energy storage systems for storing energy by using silicon carbide semiconductor power modules, transistors, and diodes; energy storage systems for managing power grids by using silicon carbide semiconductor power modules, transistors, and diodes.
93.
Power Semiconductor Devices Including Shape-Memory Metallization
Semiconductor device packages are provided. In one example, the semiconductor device package includes a submount. The semiconductor device package further includes one or more semiconductor die on the submount. The one or more semiconductor die include one or more metallization layers. In one example, the one or more metallization layers include a shape-memory metallization (SMM) structure.
A semiconductor device such as a MOSFET or IGBT comprises a semiconductor layer structure that includes a drift region having a first conductivity type, a plurality of channel regions that each have a second conductivity type, and a plurality of JFET regions that each have the first conductivity type. Each channel region comprises a ring-shaped channel region that has a ring shape and surrounds a respective one of the JFET regions when viewed in plan view.
A semiconductor device includes a substrate and a drift layer on the substrate, the drift layer having a first conductivity type. The device includes a first plurality of vertical junction field effect (JFET) subcells and a second plurality of vertical JFET subcells on the drift layer. The first plurality of vertical JFET subcells are connected in parallel to form a first JFET device, and the second plurality of vertical JFET subcells are connected in parallel to form a second JFET device. The second JFET device is connected in anti-series with the first JFET device through the drift layer. The device further includes a first gate electrode and a first current terminal in contact with the first plurality of vertical JFET subcells, and a second gate electrode and a second current terminal in contact with the second plurality of vertical JFET subcells.
H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
H01L 27/098 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being PN junction gate field-effect transistors
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
96.
SILICON CARBIDE BASED SEMICONDUCTOR DEVICES WITH RING-SHAPED CHANNEL REGIONS AND/OR CHANNEL REGIONS THAT EXTEND IN MULTIPLE DIRECTIONS IN PLAN VIEW
A semiconductor device such as a MOSFET or IGBT comprises a semiconductor layer structure that includes a drift region having a first conductivity type, a plurality of channel regions that each have a second conductivity type, and a plurality of JFET regions that each have the first conductivity type. Each channel region comprises a ring-shaped channel region that has a ring shape and surrounds a respective one of the JFET regions when viewed in plan view.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
09 - Scientific and electric apparatus and instruments
14 - Precious metals and their alloys; jewelry; time-keeping instruments
28 - Games; toys; sports equipment
Goods & Services
Power modules; power conversion systems, namely, power conversion system for conversion of electrical energy; integrated circuit chips; transistors; diodes; semiconductor devices; semiconductor chips; semiconductor wafers, namely, silicon carbide semiconductor wafers; discrete bare die; power transistor switching devices; electric switches; electric controllers; electric circuitry, namely, electric circuits, electric circuit closers, and electric circuit openers; Electric converters; DC/DC power converters; DC/AC power converters; battery chargers; renewable battery system to provide backup power; wireless chargers; inverters; power inverters; solar power inverters; batteries, electric for vehicles; charging stations for charging electric vehicles; semiconductor materials and devices, namely, silicon carbide and gallium nitride power systems; metal oxide semiconductor field effect transistors; electric circuit boards; amplifiers; power amplifiers; electrical power supplies; voltage stabilizing power supply; high-voltage power supplies; low-voltage power supplies; electronic power supplies for powering electric motors; solar panels for the production of electricity; energy storage systems for storing energy by using silicon carbide semiconductor power modules, transistors, and diodes; energy storage systems for managing power grids by using silicon carbide semiconductor power modules, transistors, and diodes; optical apparatus and instruments; virtual reality headsets; smartglasses Jewelry, precious and semi-precious stones; Silicon Carbide (SiC) crystals sold as an integral component of jewelry; Silicon carbide (SiC) crystals for use in the manufacture of jewelry Video game apparatus, namely, video game consoles, handheld video game units; amusement and game apparatus in the nature of electronic gaming equipment, namely, electronic video game machines, player-operated electronic controllers for electronic video games
09 - Scientific and electric apparatus and instruments
14 - Precious metals and their alloys; jewelry; time-keeping instruments
28 - Games; toys; sports equipment
Goods & Services
Power modules; power conversion systems; integrated circuit chips; transistors; diodes; semiconductor devices; semiconductor chips; semiconductor wafers; discrete bare die; power transistor switching devices; electric switches; electric controllers; electric circuitry, namely, electric circuits, electric circuit closers, and electric circuit openers; Electric converters; DC/DC power converters; DC/AC power converters; battery chargers; renewable battery system to provide backup power; wireless chargers; inverters; power inverters; solar power inverters; batteries, electric for vehicles; charging stations for charging electric vehicles; semiconductor materials and devices, namely, silicon carbide and gallium nitride power systems; metal oxide semiconductor field effect transistors; electric circuit boards; amplifiers; power amplifiers; electrical power supplies; voltage stabilizing power supply; high-voltage power supplies; low-voltage power supplies; electronic power supplies for powering electric motors; solar panels for the production of electricity; energy storage systems for storing energy by using silicon carbide semiconductor power modules, transistors, and diodes; energy storage systems for managing power grids by using silicon carbide semiconductor power modules, transistors, and diodes; optical apparatus and instruments; virtual reality headsets; smartglasses. Jewelry, precious and semi-precious stones; Silicon Carbide (SiC) crystals sold as an integral component of jewelry; Silicon carbide (SiC) crystals for use in the manufacture of jewelry. Video game apparatus; amusement and game apparatus in the nature of electronic gaming equipment.
100.
DEVICE HAVING A RATE OF CURRENT CHANGE LIMITER AND PROCESS OF IMPLEMENTING THE SAME
A device may include at least one power device; a gate driver; a control and sensing circuit; and a current sensor. Also, the device may include a current limiter that includes a parasitic inductance component. The parasitic inductance component is configured, structured, and/or implemented to limit a rate of current change (di/dt) during a fault. In addition, the device may be configured to be implemented in a system that includes a load and a power source.
H02H 3/08 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current
H02H 1/00 - Details of emergency protective circuit arrangements
