Various techniques are provided for efficiently mapping synthesized components to physical hardware components of a PLD. In one example, a method includes receiving a design identifying operations to be performed by a programmable logic device (PLD). The method also includes converting the operations to a plurality of synthesized components. The method also includes mapping a selected one of the synthesized components to a model associated with first and second types of hardware components of the PLD. The selected synthesized component is compatible with first and second specifications of the first and second types of hardware components, respectively. The method also includes assigning the selected synthesized component to a physical location of the PLD comprising either the first type of hardware component or the second type of hardware component to improve a performance metric of the PLD configured with the design. Additional devices, systems and methods are also provided.
Various techniques are provided to emulate an ambient light sensor and determine an ambient color temperature. A programmable logic device includes an image processing pipeline with hardware components configured to process an image frame received from an image capture device, ambient light sensing hardware coupled to the image processing pipeline and configured to generate an ambient light value from the image frame, and a memory configured to store the ambient light value for use by a host system processor. The host system processor may be configured to selectively adjust a brightness and/or display color settings based on the ambient light value. The programmable logic device may be configured to operate in accordance with a polling interval. User presence data comprising audio, video, and/or user input data may be collected and fused with the ambient light value for use by the host processor.
Systems and methods for controlling the operation of an electronic system are disclosed. An example electronic system includes an edge PLD including programmable logic blocks (PLBs) configured to implement an image engine preprocessor and an image engine. The edge PLD is configured to receive raw imagery provided by an imaging module of the electronic system via a raw image pathway of the electronic system; to generate, via the image engine preprocessor, engine-quality imagery corresponding to the received raw imagery; and to generate, via the image engine of the edge PLD, one or more image tags associated with the generated engine-quality imagery. The one or more image tags and/or the associated engine-quality imagery is used to control operation of the electronic system.
Various techniques are provided for configuring clients of a programmable logic device (PLD). In one embodiment, a method includes passing, from a configuration engine of a PLD, a plurality of transactions to clients of the PLD over a pipeline of the PLD. The method also includes executing each of the transactions by one or more of the clients. A first one of the transactions is a read transaction that causes at least a first one of the clients to retrieve read data and pass the read data over the pipeline. The method also includes passing the read data over the pipeline to the configuration engine. Additional systems and methods are also provided.
Various techniques are provided to implement context switching systems and methods. In one example, a system includes a plurality of programmable logic devices (PLDs) each configured to be in an active state or an inactive state. At most one of the plurality of PLDs is in the active state to provide PLD functionality. The system further includes an instance controller configured to communicate with each of the plurality of PLDs and control context switch aspects to set each of the plurality of PLDs to the active state or the inactive state. Related methods and devices are provided.
Systems and methods for asset tamper detection management for secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine. The secure PLD is configured to detect an asset tamper attempt on a targeted asset of the secure PLD, and to lock a securable asset associated with the detected asset tamper attempt, where the securable asset includes the targeted asset, the configuration I/O, and/or a communication bus of the secure PLD.
Various techniques are provided for selectively operating a memory block in full power or half power modes. In one example, a system comprises a memory block configured to be selectively operated in a full power mode or a half power mode. The memory block comprises an input/output port. The memory block further comprises a first sub-block configured to be powered on during the full power mode and during the half power mode. The memory block further comprises a second sub-block configured to be powered on during the full power mode and powered off during the half power mode. The memory block further comprises routing hardware configured to pass data between the input/output port and the first and second sub-blocks. Additional systems and methods are also provided.
Various techniques are provided to implement dual power supplied memory cells and deterministic reset thereof for programmable logic devices. In one example, a programmable logic device (PLD) includes a configuration memory including an array of memory cells arranged in rows and columns. The PLD further includes a power supply circuit coupled to the configuration memory and configured to selectively couple, based on a reset control signal, a power supply to a first power supply line coupled to the array of memory cells. The array of memory cells is reset if the power supply is coupled to the first power supply line. The power supply circuit is further configured to provide power on a second power supply line to the array of memory cells. Related methods and devices are provided.
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4072 - Circuits for initialization, powering up or down, clearing memory or presetting
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
9.
CRYPTOGRAPHIC HARDWARE SHARING SYSTEMS AND METHODS
Various techniques are provided to implement cryptographic hardware sharing systems and methods. In one example, a programmable logic device (PLD) includes a configuration engine configured to provide configuration data for processing using a first set of security functions. The PLD further includes a PLD fabric including an array of memory cells configured to operate upon being programmed using the configuration data and provide user data for processing using a second set of security functions. The PLD further includes a security engine including a cryptographic circuit and an interface integration logic circuit. The logic circuit is configured to selectively couple, based on an indicator, the configuration engine or PLD fabric to the cryptographic circuit. The cryptographic circuit is configured to perform the first set or second set of security functions when coupled to the configuration engine or PLD fabric, respectively, by the logic circuit. Related systems and methods are provided.
H03K 19/17768 - Structural details of configuration resources for security
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
10.
CONFIGURABLE CLOCK ENABLE AND RESET SIGNAL FOR PROGRAMMABLE LOGIC DEVICES SYSTEMS AND METHODS
Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a PLD comprises a plurality of slices. Each slice comprises a plurality a lookup tables (LUT) and flip-flops configured to operate in response to a plurality of control signals. The PLD further comprises routing logic configured to selectively route the control signals to each of the plurality of slices. The control signals comprise at least a signal selectively configurable as a clock enable signal or a local set-reset signal. Additional systems and methods are also provided.
Various techniques are provided to efficiently synchronize clock and data signals in programmable logic devices (PLDs). In one example, a method comprises configuring an intellectual property (IP) block of the PLD to receive a first clock signal and a first data signal at a first component of the IP block, determining a delay associated with the first clock signal between a first input and the first component, configuring a programmable logic cell (PLC) to receive a second clock signal and output the first data signal to the IP block, determining a delay period to synchronize the first clock signal and the first data signal at the first component of the IP block, and configuring an adjustable delay element to apply the delay period to the second clock signal to synchronize the first clock signal and the first data signal at the first component of the IP block.
Various techniques are provided to implement information leakage mitigation associated with data communications. In one example, a method includes receiving a bitstream including a plurality of bits. The method further includes, for each bit of the plurality of bits, transitioning between two states of a plurality of states in response to the bit; inverting a differential pair of data signals associated with the bit in response to the transitioning to obtain differentially transitioned data signals; maintaining a third data signal associated with the bit in response to the transitioning; and transmitting each data signal of the differentially transitioned data signals and the third data signal over a respective wire. Related systems and devices are provided.
09 - Scientific and electric apparatus and instruments
Goods & Services
Integrated circuits; integrated circuits in the nature of
field programmable gate arrays; programmable logic devices;
semiconductors; semiconductor devices.
14.
PROGRAMMABLE LINEAR-FEEDBACK SHIFT REGISTER SYSTEMS AND METHODS
Various techniques are provided to implement programmable linear-feedback shift register (LFSR) circuits. In one example, the LFSR circuit includes state storage elements. Each state storage element is configured to store a state signal. The LFSR circuit further includes programmable logic stage circuits each configured to selectively receive an input signal and a set of state signals, determine an output signal based at least on the set of state signals, and provide the output signal. Each programmable logic stage circuit is connected to at least one other programmable logic stage circuit. The LFSR circuit further includes pipeline elements. Each pipeline element is configured to selectively connect at least two programmable logic stage circuits. The LFSR circuit further includes sets of latency balance elements. Related systems and methods are provided.
09 - Scientific and electric apparatus and instruments
Goods & Services
Integrated circuits; integrated circuits in the nature of
field programmable gate arrays; programmable logic devices;
semiconductors; semiconductor devices; recorded software and
firmware to be programmed into integrated circuits for
programming programmable gate arrays consisting primarily of
silicon chips; downloadable software and firmware for
programming logic, computational and arithmetic functions
into integrated circuits; recorded software and firmware to
be programmed into integrated circuits for programming
programmable gate arrays consisting primarily of silicon
chips for land vehicle applications; downloadable software
and firmware for programming logic, computational and
arithmetic functions into integrated circuits for use in
land vehicles.
16.
IMAGE TAGGING ENGINE SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
Systems and methods for controlling the operation of an electronic system are disclosed. An example electronic system includes an edge PLD including programmable logic blocks (PLBs) configured to implement an image engine preprocessor and an image engine. The edge PLD is configured to receive raw imagery provided by an imaging module of the electronic system via a raw image pathway of the electronic system; to generate, via the image engine preprocessor, engine-quality imagery corresponding to the received raw imagery; and to generate, via the image engine of the edge PLD, one or more image tags associated with the generated engine-quality imagery. The one or more image tags and/or the associated engine-quality imagery is used to control operation of the electronic system.
Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes performing a read operation on a non-volatile memory to obtain a first value. The method further includes comparing the value to a predetermined value to obtain a comparison result. The method further includes determining whether a boot image stored on the non-volatile memory is to be read based at least on the first comparison result. The method further includes performing, based on the determining, a read operation on the boot image to obtain data associated with booting of a device. The method further includes booting the device based at least on the data. Related systems and devices are provided.
Various techniques are provided to implement multi-chip secure and programmable systems and methods. In one example, a multi-chip module system for providing an integrated programmable logic functionality and security functionality. The multi-chip module system includes a first die including a programmable logic device (PLD) configured to provide at least a portion of the programmable logic functionality. The multi-chip system further includes a second die including a security engine configured to perform at least a portion of the security functionality. The security engine is further configured to receive, from the first die, data associated with a first and second configuration image; perform a read operation on a memory for the second configuration image based on the data; and authenticate the second configuration image. The multi-chip system further includes a configuration engine configured to program the PLD according to the first configuration image. Related devices and methods are provided.
G06F 21/64 - Protecting data integrity, e.g. using checksums, certificates or signatures
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
19.
BACK-END PROCESSING SYSTEMS AND METHODS FOR DEVICE IDENTIFICATION
Various techniques are provided to implement back-end processing systems and methods for device identification. In one example, a method includes receiving fabrication data associated with a die element. The die element has an integrated circuit fabricated according to a design defined by a mask set. The method further includes creating, by the integrated circuit, a seed value based on a characteristic of the integrated circuit. The method further includes producing, by the integrated circuit, an identifier for the die element based on the fabrication data and the seed value. Related devices and systems are provided.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
09 - Scientific and electric apparatus and instruments
Goods & Services
Integrated circuits; integrated circuits in the nature of field programmable gate arrays; programmable logic devices; semiconductors; semiconductor devices
Various techniques are provided to implement look-up table (LUT) circuits. In one example, a LUT circuit includes a first LUT configured to selectively receive a first input signal and each input signal of a set of input signals and determine a first output signal based on the first input signal and/or an input signal(s) of the set. The LUT circuit also includes a second LUT configured to selectively receive a second input signal and each input signal of the set and determine a second output signal based on the second input signal and/or an input signal(s) of the set. The LUT circuit also includes a multiplexer configured to selectively receive the first and second output signals and a third input signal, and selectively provide, based on the third input signal, the first or second output signal as an output of the LUT circuit. Related systems and methods are also provided.
09 - Scientific and electric apparatus and instruments
Goods & Services
Integrated circuits; integrated circuits in the nature of field programmable gate arrays; programmable logic devices; semiconductors; semiconductor devices; recorded software and firmware to be programmed into integrated circuits for programming programmable gate arrays consisting primarily of silicon chips; downloadable software and firmware for programming logic, computational and arithmetic functions into integrated circuits; recorded software and firmware to be programmed into integrated circuits for programming programmable gate arrays consisting primarily of silicon chips for land vehicle applications; downloadable software and firmware for programming logic, computational and arithmetic functions into integrated circuits for use in land vehicles
23.
INFORMATION LEAKAGE MITIGATION ASSOCIATED WITH ELLIPTIC CURVE OPERATIONS
Various techniques are provided to implement information leakage mitigation associated with elliptic curve operations. In one example, a method includes generating second data based on first data. The first data is associated with a message. The second data is associated with a decoy message. The method further includes performing a first elliptic curve operation based on the first data. The method further includes performing a second elliptic curve operation based on the second data. The first elliptic curve operation and the second elliptic curve operation are performed in a random order. Related systems and devices are provided.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
Various techniques are provided to implement information leakage mitigation associated with data communications. In one example, a method includes receiving a bitstream including a plurality of bits. The method further includes, for each bit of the plurality of bits, transitioning between two states of a plurality of states in response to the bit; inverting a differential pair of data signals associated with the bit in response to the transitioning to obtain differentially transitioned data signals; maintaining a third data signal associated with the bit in response to the transitioning; and transmitting each data signal of the differentially transitioned data signals and the third data signal over a respective wire. Related systems and devices are provided.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
25.
Programmable linear-feedback shift register systems and methods
Various techniques are provided to implement programmable linear-feedback shift register (LFSR) circuits. In one example, the LFSR circuit includes state storage elements. Each state storage element is configured to store a state signal. The LFSR circuit further includes programmable logic stage circuits each configured to selectively receive an input signal and a set of state signals, determine an output signal based at least on the set of state signals, and provide the output signal. Each programmable logic stage circuit is connected to at least one other programmable logic stage circuit. The LFSR circuit further includes pipeline elements. Each pipeline element is configured to selectively connect at least two programmable logic stage circuits. The LFSR circuit further includes sets of latency balance elements. Related systems and methods are provided.
Various techniques are provided to implement programmable linear-feedback shift register (LFSR) circuits. In one example, the LFSR circuit includes state storage elements. Each state storage element is configured to store a state signal. The LFSR circuit further includes programmable logic stage circuits each configured to selectively receive an input signal and a set of state signals, determine an output signal based at least on the set of state signals, and provide the output signal. Each programmable logic stage circuit is connected to at least one other programmable logic stage circuit. The LFSR circuit further includes pipeline elements. Each pipeline element is configured to selectively connect at least two programmable logic stage circuits. The LFSR circuit further includes sets of latency balance elements. Related systems and methods are provided.
G06F 7/58 - Random or pseudo-random number generators
G06F 5/06 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
27.
Adaptive power-on-reset generator systems and methods for programmable logic devices
Systems and methods for providing adaptive power on reset (POR) signals for use with programmable logic devices (PLDs) and/or other semiconductor devices are disclosed. An example adaptive POR signal generator includes a logic device configured to detect a first supply voltage ramp traversal across a first threshold ramp voltage, detect a second supply voltage ramp traversal across a second threshold ramp voltage, and generate a POR signal based, at least in part, on a nominal operating voltage associated with the power supply and/or the supply voltage and/or on a ramp time associated with the first and second supply voltage ramp traversals. The second threshold ramp voltage is higher than the first threshold ramp voltage and the first and second threshold ramp voltages are lower than the nominal operating voltage.
Systems and methods for controlling the operation of an electronic system are disclosed. An example electronic system includes an edge PLD including programmable logic blocks (PLBs) configured to implement an image engine preprocessor and an image engine. The edge PLD is configured to receive raw imagery provided by an imaging module of the electronic system via a raw image pathway of the electronic system; to generate, via the image engine preprocessor, engine-quality imagery corresponding to the received raw imagery; and to generate, via the image engine of the edge PLD, one or more image tags associated with the generated engine-quality imagery. The one or more image tags and/or the associated engine-quality imagery is used to control operation of the electronic system.
Systems and methods for management of remotely programmable, programmable logic devices (remote PLDs) are disclosed. An example system includes a remote PLD including a plurality of programmable logic blocks (PLBs) arranged in a PLD fabric and a programmable input/output (I/O) coupled to the PLD fabric. The remote PLD is configured to form a communications link between the remote PLD and a remote PLD management system node over a communications network via a communication module of the remote PLD or a host device configured to interface with the remote PLD over the programmable I/O. The remote PLD is configured to receive a protected configuration image from the remote PLD management system node over the communications link and programs the PLD fabric according to the protected configuration image.
Various techniques are provided to implement multi-chip secure and programmable systems and methods. In one example, a multi-chip module system for providing an integrated programmable logic functionality and security functionality. The multi-chip module system includes a first die including a programmable logic device (PLD) configured to provide at least a portion of the programmable logic functionality. The multi-chip system further includes a second die including a security engine configured to perform at least a portion of the security functionality. The security engine is further configured to receive, from the first die, data associated with a first and second configuration image; perform a read operation on a memory for the second configuration image based on the data; and authenticate the second configuration image. The multi-chip system further includes a configuration engine configured to program the PLD according to the first configuration image. Related devices and methods are provided.
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
31.
Adaptive processing of video streams with reduced color resolution
A solution for adaptively processing a digital image with reduced color resolution is described herein. A source device pre-processes a video frame with reduce color resolution by remapping luma components and chroma components of the video frame, and encodes the pre-processed video frame. The source device remaps a half of luma components on a scan line of the video frame onto a data channel of a source line to an encoder and remaps the other half of the luma components on the scan line to another data channel of the source line. The source device remaps the corresponding chroma components onto a third data channel of a source line. By using a data channel conventionally configured to transmit chroma components, the solution enables a video codec to adaptively encode a digital image with reduced color resolution without converting the digital image to full color resolution before the encoding.
H04N 19/00 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
H04N 19/196 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters
H04N 19/85 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
H04N 19/136 - Incoming video signal characteristics or properties
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
32.
Fast boot systems and methods for programmable logic devices
Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
33.
INFORMATION LEAKAGE MITIGATION ASSOCIATED WITH ELLIPTIC CURVE OPERATIONS
Various techniques are provided to implement information leakage mitigation associated with elliptic curve operations. In one example, a method includes generating second data based on first data. The first data is associated with a message. The second data is associated with a decoy message. The method further includes performing a first elliptic curve operation based on the first data. The method further includes performing a second elliptic curve operation based on the second data. The first elliptic curve operation and the second elliptic curve operation are performed in a random order. Related systems and devices are provided.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
34.
Input/output bus protection systems and methods for programmable logic devices
Systems and methods for providing external bus protection for programmable logic devices (PLDs) are disclosed. An example system includes a programmable I/O bus configured to interface with a user device over an external bus interface coupled to a PLD; a bus protection circuit arrangement integrated with the programmable I/O interface and configured to provide I/O bus supply voltage protection for the programmable I/O interface; and a bus protection control signal generator. The bus protection control signal generator generates a default bus protection control signal for the bus protection circuit arrangement of the PLD prior to completion of a power ramp performed by the user device; an intermediate bus protection control signal for the PLD prior to completion of loading a PLD configuration into a PLD fabric of the PLD; and an operational bus protection control signal for the PLD.
A solution for adaptively processing a digital image with reduced color resolution is described herein. A source device pre-processes a video frame with reduce color resolution by remapping luma components and chroma components of the video frame, and encodes the pre-processed video frame. The source device remaps a half of luma components on a scan line of the video frame onto a data channel of a source line to an encoder and remaps the other half of the luma components on the scan line to another data channel of the source line. The source device remaps the corresponding chroma components onto a third data channel of a source line. By using a data channel conventionally configured to transmit chroma components, the solution enables a video codec to adaptively encode a digital image with reduced color resolution without converting the digital image to full color resolution before the encoding.
H04N 19/00 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
H04N 19/196 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters
H04N 19/85 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
H04N 19/136 - Incoming video signal characteristics or properties
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
36.
Memory circuit having non-volatile memory cell and methods of using
One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.
G11C 7/16 - Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
Systems and methods for providing external bus protection for programmable logic devices (PLDs) are disclosed. An example system includes a programmable I/O bus configured to interface with a user device over an external bus interface coupled to a PLD; a bus protection circuit arrangement integrated with the programmable I/O interface and configured to provide I/O bus supply voltage protection for the programmable I/O interface; and a bus protection control signal generator. The bus protection control signal generator generates a default bus protection control signal for the bus protection circuit arrangement of the PLD prior to completion of a power ramp performed by the user device; an intermediate bus protection control signal for the PLD prior to completion of loading a PLD configuration into a PLD fabric of the PLD; and an operational bus protection control signal for the PLD.
Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes performing a read operation on a non-volatile memory to obtain a first value. The method further includes comparing the value to a predetermined value to obtain a comparison result. The method further includes determining whether a boot image stored on the non-volatile memory is to be read based at least on the first comparison result. The method further includes performing, based on the determining, a read operation on the boot image to obtain data associated with booting of a device. The method further includes booting the device based at least on the data. Related systems and devices are provided.
Various techniques are provided to implement power supply regulation for programmable logic devices (PLDs). In one example, a method includes powering configuration memory cells of a PLD with a first voltage. The method further includes configuring the configuration memory cells while the configuration memory cells are powered by the first voltage. The method further includes operating the PLD while the configuration memory cells are powered with a second voltage higher than the first voltage. The method further includes powering the configuration memory cells with a third voltage lower than the first voltage in response to an indication to transition the PLD to a sleep mode of the PLD. Related systems and devices are provided.
Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes performing a read operation on a non-volatile memory to obtain a first value. The method further includes comparing the value to a predetermined value to obtain a comparison result. The method further includes determining whether a boot image stored on the non-volatile memory is to be read based at least on the first comparison result. The method further includes performing, based on the determining, a read operation on the boot image to obtain data associated with booting of a device. The method further includes booting the device based at least on the data. Related systems and devices are provided.
Systems and methods for providing adaptive power on reset (POR) signals for use with programmable logic devices (PLDs) and/or other semiconductor devices are disclosed. An example adaptive POR signal generator includes a logic device configured to detect a first supply voltage ramp traversal across a first threshold ramp voltage, detect a second supply voltage ramp traversal across a second threshold ramp voltage, and generate a POR signal based, at least in part, on a nominal operating voltage associated with the power supply and/or the supply voltage and/or on a ramp time associated with the first and second supply voltage ramp traversals. The second threshold ramp voltage is higher than the first threshold ramp voltage and the first and second threshold ramp voltages are lower than the nominal operating voltage.
One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.
G11C 7/16 - Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
43.
Transmitting common mode control data over audio return channel
A source device and a sink device may be connected using an interface cable comprising at least first and second physical channels. The first physical channel may be used to transmit video data unidirectionally from the source device to the sink device. In addition, the second physical channel may comprise an audio return channel wherein audio data can be transmitted unidirectionally from the sink device to the source device at a first rate. In addition, the second physical channel may also transmit bidirectional control data between the source and sink devices at a second rate slower than the first rate. The audio data may be overlaid on the control data, wherein the audio data is transmitted using differential signaling, while the control data is transmitted using common mode signaling.
H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
H04N 21/4363 - Adapting the video stream to a specific local network, e.g. a Bluetooth® network
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 1/16 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
H04N 21/439 - Processing of audio elementary streams
H04L 1/18 - Automatic repetition systems, e.g. Van Duuren systems
44.
Failure characterization systems and methods for erasing and debugging programmable logic devices
Systems and methods for failure characterization of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a failure characterization (FC) command from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to execute the FC command to, at least in part, erase and/or nullify portions of the NVM. The secure PLD may also be configured to boot a debug configuration for the PLD fabric that identifies and/or characterizes operational failures of the secure PLD.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
G06F 21/85 - Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
H03K 19/17768 - Structural details of configuration resources for security
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
G06F 21/10 - Protecting distributed programs or content, e.g. vending or licensing of copyrighted material
45.
Secure boot systems and methods for programmable logic devices
Systems and methods for secure booting of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine. The secure PLD is configured to retrieve a pre-authentication status associated with the configuration image from the NVM, determine or verify the retrieved pre-authentication status associated with the configuration image includes a valid status, and boot the PLD fabric of the secure PLD using the configuration image.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
G06F 21/85 - Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
H03K 19/17768 - Structural details of configuration resources for security
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
G06F 21/10 - Protecting distributed programs or content, e.g. vending or licensing of copyrighted material
46.
Key provisioning systems and methods for programmable logic devices
Systems and methods for provisioning secure programmable logic devices (PLDs) are disclosed. An example secure PLD provisioning system includes an external system comprising a processor and a memory and configured to be coupled to a secure PLD through a configuration input/output (I/O) of the secure PLD. The external system is configured to generate a locked PLD comprising the secure PLD based, at least in part, on a request from a secure PLD customer, wherein the request from the secure PLD customer comprises a customer public key; and to provide a secured unlock package for the locked secure PLD. The external system may also be configured to provide an authenticatable key manifest comprising a customer programming key token and a corresponding programming public key associated with the locked secure PLD, wherein the authenticatable key manifest is signed using a programming private key generated by the locked secure PLD.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
G06F 21/85 - Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
H03K 19/17768 - Structural details of configuration resources for security
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
47.
Asset management systems and methods for programmable logic devices
Systems and methods for asset management for secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a secure PLD asset access request from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to perform a secure PLD asset update process corresponding to the secure PLD asset access request, where the performing the asset update process is based on a lock status associated with a secure PLD asset corresponding to the secure PLD asset access request.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
G06F 21/85 - Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
H03K 19/17768 - Structural details of configuration resources for security
Systems and methods for management of remotely programmable, programmable logic devices (remote PLDs) are disclosed. An example system includes a remote PLD including a plurality of programmable logic blocks (PLBs) arranged in a PLD fabric and a programmable input/output (I/O) coupled to the PLD fabric. The remote PLD is configured to form a communications link between the remote PLD and a remote PLD management system node over a communications network via a communication module of the remote PLD or a host device configured to interface with the remote PLD over the programmable I/O. The remote PLD is configured to receive a protected configuration image from the remote PLD management system node over the communications link and programs the PLD fabric according to the protected configuration image.
41 - Education, entertainment, sporting and cultural services
42 - Scientific, technological and industrial services, research and design
Goods & Services
Business management analysis and business consultancy,
namely, consultancy regarding integrated circuit supply
chain security; conducting and administering a program to
establish standards and protocols for supply chain integrity
in the semiconductor industry and distribution of data used
to configure or program programmable logic devices;
conducting and administering a program featuring tools and
information to increase awareness of semiconductor supply
chain vulnerabilities and technologies available to address
those vulnerabilities. Educational and instructional services, namely, providing,
conducting and organizing classes and seminars relating to
threats to integrity and security of semiconductor supply
chains and technical measures and services that can be used
to combat those threats. Software as a service (SaaS) services featuring software for
programming security keys into semiconductor devices;
scientific and technological services and research and
design relating thereto, all in the field of protecting the
supply chain for integrated circuits and for programmable
logic devices; software as a service (SaaS) services
featuring software for receiving security keys from
third-parties through an Internet portal; scientific and
technological services and research and design relating
thereto in the field of creating locked programmable logic
devices that can be unlocked using a customer-provided
security key; software as a service (SaaS) services
featuring software for protecting, destroying, or
obfuscating sensitive data during change of custody, or
through a chain of custody, of an integrated circuit;
providing online non-downloadable computer software for
programming security keys into semiconductor devices;
technical consultation services in the fields of supply
chain security for integrated circuits and for distribution
and control of content that can be programmed into or onto
integrated circuits.
41 - Education, entertainment, sporting and cultural services
42 - Scientific, technological and industrial services, research and design
Goods & Services
Business management analysis and business consultancy,
namely, consultancy regarding integrated circuit supply
chain security; administration of programs to establish
standards and protocols for supply chain integrity in the
semiconductor industry and distribution of data used to
configure or program programmable logic devices;
administration of programs featuring tools and information
to increase awareness of semiconductor supply chain
vulnerabilities and technologies available to address those
vulnerabilities. Educational and instructional services, namely, providing,
conducting and organizing classes and seminars relating to
threats to integrity and security of semiconductor supply
chains and technical measures and services that can be used
to combat those threats. Software as a service (SaaS) services featuring software for
programming security keys into semiconductor devices;
scientific and technological services and research and
design relating thereto, all in the field of protecting the
supply chain for integrated circuits and for programmable
logic devices; software as a service (SaaS) services
featuring software for receiving security keys from
third-parties through an internet portal; scientific and
technological services and research and design relating
thereto in the field of creating locked programmable logic
devices that can be unlocked using a customer-provided
security key; software as a service (SaaS) services
featuring software for protecting, destroying, or
obfuscating sensitive data during change of custody, or
through a chain of custody, of an integrated circuit;
providing temporary use of online applications and software
tools for use in programming security keys into
semiconductor devices; technical consultation services in
the fields of supply chain security for integrated circuits
and for distribution and control of content that can be
programmed into or onto integrated circuits.
09 - Scientific and electric apparatus and instruments
Goods & Services
Integrated circuits; integrated circuits in the nature of field programmable gate arrays; programmable logic devices; semiconductors; semiconductor devices.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Artificial-intelligence-based software and software
development platforms, computer hardware, integrated
circuits in the nature of field programmable gate arrays,
and downloadable electronic data files for configuring field
programmable gate arrays to do pattern discovery,
recognition, classification, segmentation, regression,
decision support and visualization; downloadable software
for algorithm-based machine learning in the field of
biometric recognition, facial, iris, retina recognition, 3D
sensing, object classification, and object recognition. Providing temporary use of on-line non-downloadable software
development tools for use in developing
artificial-intelligence based software; platform as a
service (PAAS) featuring computer software platforms for
providing a platform for artificial-intelligence software
development; providing temporary use of on-line
non-downloadable software for use in designing and
developing machine learning algorithms, and deep neural
networks, and for data analysis; providing temporary use of
on-line non-downloadable software libraries in the nature of
computer application software for use in designing and
developing machine learning algorithms and neural networks.
A bridge chip receives a first data stream compliant with the first multimedia communication standard. The first data stream includes first video data of a first incoming video frame, second video data of a second incoming video frame, and information describing a transfer function for the second video data, the information included in a video blanking interval of the first incoming video frame. The bridge chip extracts information describing a transfer function for the second video data. The bridge chip then generates a second data stream compliant with the second multimedia communication standard. The second data stream includes the first video data in a first outbound video frame, the second video data in a second outbound video frame, and the extracted information describing the transfer function for the second video data. Finally, the generated second data stream is transmitted to a destination device.
Embodiments of the invention are generally directed to transmission and detection of multi-channel signals in reduced channel format. An embodiment of a method for transmitting data includes determining whether a first type or a second type of content data is to be transmitted, where the first type of content data is to be transmitted at a first multiple of a base frequency and the second type of data is to be transmitted at a second multiple of the base frequency. The method further includes selecting one or more channels from a plurality of channels based on the type of content data, clocking a frequency on the first or second multiple of the base frequency according to the type of content data in the selected channels, modifying the content data to fit within a single output channel, and transmitting the modified data via a single output channel at the chosen multiple of the base frequency.
H04N 19/90 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups , e.g. fractals
09 - Scientific and electric apparatus and instruments
Goods & Services
Integrated circuits; integrated circuits in the nature of field programmable gate arrays; programmable logic devices; semiconductors; semiconductor devices
58.
Memory circuit having non-volatile memory cell and methods of using
One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first magnetic tunnel junction (MTJ) device, a first select device connected in series with the first MTJ device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
H03K 19/1776 - Structural details of configuration resources for memories
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
09 - Scientific and electric apparatus and instruments
Goods & Services
Integrated circuits; integrated circuits in the nature of field programmable gate arrays; programmable logic devices; software and firmware to be programmed into integrated circuits for performing a function therein; software and firmware for programming functions into integrated circuits.
Methods and circuitry for low-speed bus time stamping and triggering are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that comprises a data line and a clock line. The master device generates and controls a clock signal on the clock line, and sends a synchronization command over the data line to the slave devices. In response to the synchronization command, the master device receives timestamp information of an event detected at each slave device. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can further send to each slave device delay setting information for generating a trigger signal at that slave device based on transitions of the clock signal, the synchronization command and the delay setting information.
41 - Education, entertainment, sporting and cultural services
42 - Scientific, technological and industrial services, research and design
45 - Legal and security services; personal services for individuals.
Goods & Services
Educational and instructional services, namely, providing, conducting and organizing classes and seminars relating to threats to integrity and security of semiconductor supply chains and technical measures and services that can be used to combat those threats Software as a service (SaaS) services featuring software for programming security keys into semiconductor devices; Scientific and technological services, namely, research and design in the field of protecting the supply chain for integrated circuits and for programmable logic devices; Software as a service (SaaS) services featuring software for receiving security keys from third-parties through an Internet portal; Scientific and technological services, namely, research and design in the field of creating locked programmable logic devices that can be unlocked using a customer-provided security key; Software as a service (SaaS) services featuring software for protecting, destroying, or obfuscating sensitive data during change of custody, or through a chain of custody, of an integrated circuit; Providing online non-downloadable computer programs for programming security keys into semiconductor devices; Technical consultation services in the field of engineering for supply chain security for integrated circuits and for distribution and control of content that can be programmed into or onto integrated circuits; Development of voluntary standards and protocols for supply chain integrity in the semiconductor industry and for distribution of data used to configure or program programmable logic devices Consultancy regarding integrated circuit supply chain security
41 - Education, entertainment, sporting and cultural services
42 - Scientific, technological and industrial services, research and design
45 - Legal and security services; personal services for individuals.
Goods & Services
Educational and instructional services, namely, providing, conducting and organizing classes and seminars relating to threats to integrity and security of semiconductor supply chains and technical measures and services that can be used to combat those threats Software as a service (SaaS) services featuring software for programming security keys into semiconductor devices; Scientific and technological services, namely, research and design in the field of protecting the supply chain for integrated circuits and for programmable logic devices; Software as a service (SaaS) services featuring software for receiving security keys from third-parties through an Internet portal; Scientific and technological services, namely, research and design in the field of creating locked programmable logic devices that can be unlocked using a customer-provided security key; Software as a service (SaaS) services featuring software for protecting, destroying, or obfuscating sensitive data during change of custody, or through a chain of custody, of an integrated circuit; Providing online non-downloadable computer programs for programming security keys into semiconductor devices; Technical consultation services in the field of engineering for supply chain security for integrated circuits and for distribution and control of content that can be programmed into or onto integrated circuits; Development of voluntary standards and protocols for supply chain integrity in the semiconductor industry and for distribution of data used to configure or program programmable logic devices Consultancy regarding integrated circuit supply chain security
Some aspects of the present disclosure relate to an apparatus, a PLL and an electronic device. The apparatus comprises a voltage-to-current (V2I) converter, a current controlled oscillator and a compensation current. The V2I converter is operable to receive a first voltage and generate a first current based on the first voltage. The current controlled oscillator is coupled to the V2I converter and operable to generate an oscillation signal based on a second current from or to the V2I converter. The compensation circuit is coupled to the V2I converter and operable to receive a third current from or to the V2I converter. The second and third currents vary in response to at least one of temperature variation and supply voltage variation of the apparatus. Variation direction of the third current is opposite to variation direction of the second current and different frequencies may be provided for a low supply voltage domain.
H03B 5/04 - Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
H03L 7/183 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
09 - Scientific and electric apparatus and instruments
Goods & Services
Integrated circuits; integrated circuits in the nature of field programmable gate arrays; programmable logic devices, namely, programmable gate arrays consisting primarily of silicon chips; recorded software and firmware to be programmed into integrated circuits for programming programmable gate arrays consisting primarily of silicon chips; downloadable software and firmware for programming logic, computational and arithmetic functions into integrated circuits
Systems and methods for dual channel polarization filter structures are disclosed. An example wireless communication system includes a first transceiver module of a wireless communication system configured to form one or more linearly polarized communication links with a second transceiver module of the wireless communication system, and a dual channel polarization filter structure positioned between the first and second transceiver modules and configured to filter the one or more linearly polarized communication links to produce corresponding one or more filtered linearly polarized communication links. The dual channel polarization filter structure includes first and second filter channels each formed from three structural layers including at least one metalized layer printed circuit board (PCB) disposed between the remaining two structural layers, and each filter channel includes an array of filter elements each comprising at least one metamaterial absorber arrangement.
Systems and methods for polarization converters are disclosed. An example wireless communication system includes a first transceiver module of a wireless communication system configured to form one or more linearly polarized communication links with a second transceiver module of the wireless communication system, and a polarization converter positioned between the first and second transceiver modules and configured to convert the one or more linearly polarized communication links to circularly polarized communication links. The polarization converter includes first and second frequency selective surfaces (FSSs) formed from respective first and second metalized layers of a printed circuit board (PCB), each FSS includes an array of capacitive patches and inductive traces forming an array of unit cells, and each unit cell of the second FSS is aligned with each unit cell of the first FSS.
H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
G01S 7/00 - Details of systems according to groups , ,
68.
ASSET MANAGEMENT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
Systems and methods for asset management for secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a secure PLD asset access request from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to perform a secure PLD asset update process corresponding to the secure PLD asset access request, where the performing the asset update process is based on a lock status associated with a secure PLD asset corresponding to the secure PLD asset access request.
G06F 21/85 - Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
Systems and methods for provisioning secure programmable logic devices (PLDs) are disclosed. An example secure PLD provisioning system includes an external system comprising a processor and a memory and configured to be coupled to a secure PLD through a configuration input/output (I/O) of the secure PLD. The external system is configured to generate a locked PLD comprising the secure PLD based, at least in part, on a request from a secure PLD customer, wherein the request from the secure PLD customer comprises a customer public key; and to provide a secured unlock package for the locked secure PLD. The external system may also be configured to provide an authenticatable key manifest comprising a customer programming key token and a corresponding programming public key associated with the locked secure PLD, wherein the authenticatable key manifest is signed using a programming private key generated by the locked secure PLD.
G06F 21/85 - Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
Systems and methods for failure characterization of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a failure characterization (FC) command from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to execute the FC command to, at least in part, erase and/or nullify portions of the NVM. The secure PLD may also be configured to boot a debug configuration for the PLD fabric that identifies and/or characterizes operational failures of the secure PLD.
Systems and methods for secure booting of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine. The secure PLD is configured to retrieve a pre-authentication status associated with the configuration image from the NVM, determine or verify the retrieved pre-authentication status associated with the configuration image includes a valid status, and boot the PLD fabric of the secure PLD using the configuration image.
G06F 21/85 - Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
downloadable application programming interface (API) software for programming integrated circuits to perform tasks using Artificial Intelligence (AI); recorded application programming interface for programming integrated circuits to perform tasks using Artificial Intelligence (AI); computer hardware; integrated circuits for use with field programmable gate arrays and downloadable electronic data files featuring configuration data for configuring field programmable gate arrays to do pattern discovery, recognition, classification, segmentation, regression, decision support and visualization; downloadable computer software using artificial intelligence for algorithm-based machine learning in the field of biometric recognition, facial, iris, retina recognition, 3D sensing, object classification, and object recognition Providing temporary use of on-line non-downloadable software development tools for programming integrated circuits for use in
developing artificial-intelligence based software; platform as a service (PAAS) featuring computer software platforms for
programming integrated circuits for providing a platform for artificial-intelligence software development; providing temporary use of
on-line non-downloadable software for programming integrated circuits for use in designing and developing machine learning
algorithms, and deep neural networks, and for data analysis; providing temporary use of on-line non-downloadable software
libraries in the nature of computer application software for programming integrated circuits for use in designing and developing
machine learning algorithms and neural networks implemented through field programmable gate arrays
73.
LOW LATENCY INTERRUPT ALERTS FOR ARTIFICIAL NEURAL NETWORK SYSTEMS AND METHODS
Various techniques are provided for providing neural networks with increased efficiency. In one example, a system includes a first artificial neural network (ANN), a second ANN, and a logic device. The first ANN is configured to receive a first plurality of data inputs associated with a data stream and process the first data inputs to generate a first inference output after a first latency. The second ANN is configured to receive a second plurality of data inputs associated with the data stream and process the second data inputs to generate a second inference output after a second latency less than the first latency. The logic device is configured to receive the second inference output before the first inference output is generated. Additional systems and methods are also provided.
Various techniques are provided for providing neural networks with increased efficiency. In one example, a system includes a first artificial neural network (ANN), a second ANN, and a logic device. The first ANN is configured to receive a first plurality of data inputs associated with a data stream and process the first data inputs to generate a first inference output after a first latency. The second ANN is configured to receive a second plurality of data inputs associated with the data stream and process the second data inputs to generate a second inference output after a second latency less than the first latency. The logic device is configured to receive the second inference output before the first inference output is generated. Additional systems and methods are also provided.
In one embodiment, a reconfigurable and scalable hardware management architecture includes a digital controller for controlling two or more analog sense-and-control (ASC) circuits, where each ASC monitors voltage, current, and temperature of one or more power supplies, ICs, or a circuit board. The controller and ASCs are connected in a star architecture, where each ASC is connected to the controller via a different, dedicated interface to communicate regarding the power supplies being monitored. The controller and the ASCs are also connected in a bus architecture via a shared interface. The architecture can be re-configured by adding one or more additional ASCs or by removing one or more existing ASCs, where each additional ASC is (i) connected to a different I/O interface of the digital controller via a different, dedicated interface and (ii) connected to the digital controller and the two or more existing ASCs via the shared interface.
Example embodiments herein relate to methods of transmitting and receiving audio signals. A method of transmitting an audio signal includes: receiving the audio signal including frames having left and right subframes containing audio data of a first number of bits; encoding the left and right subframes into a parity code of a second number of bits; generating serial data by combining the parity code and audio data; and transmitting the serial data over an audio transmission media having a bandwidth of a third number of bits, a sum of the first and second number being below the third number. A method of receiving an audio signal includes: receiving a serial signal combining a parity code; decoding the serial signal by calculating a syndrome based on the parity code; detecting an error by comparing the syndrome with the audio data; and generating a corrected audio signal by correcting the detected error.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
A bridge chip receives a first data stream compliant with the first multimedia communication standard. The first data stream includes first video data of a first incoming video frame, second video data of a second incoming video frame, and information describing a transfer function for the second video data, the information included in a video blanking interval of the first incoming video frame. The bridge chip extracts information describing a transfer function for the second video data. The bridge chip then generates a second data stream compliant with the second multimedia communication standard. The second data stream includes the first video data in a first outbound video frame, the second video data in a second outbound video frame, and the extracted information describing the transfer function for the second video data. Finally, the generated second data stream is transmitted to a destination device.
A bridge chip receives a first data stream compliant with the first multimedia communication standard. The first data stream includes first video data of a first incoming video frame, second video data of a second incoming video frame, and information describing a transfer function for the second video data, the information included in a video blanking interval of the first incoming video frame. The bridge chip extracts information describing a transfer function for the second video data. The bridge chip then generates a second data stream compliant with the second multimedia communication standard. The second data stream includes the first video data in a first outbound video frame, the second video data in a second outbound video frame, and the extracted information describing the transfer function for the second video data. Finally, the generated second data stream is transmitted to a destination device.
H04N 21/4363 - Adapting the video stream to a specific local network, e.g. a Bluetooth® network
H04N 21/436 - Interfacing a local distribution network, e.g. communicating with another STB or inside the home
H04N 21/434 - Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams or extraction of additional data from a video streamRemultiplexing of multiplex streamsExtraction or processing of SIDisassembling of packetised elementary stream
H04N 21/435 - Processing of additional data, e.g. decrypting of additional data or reconstructing software from modules extracted from the transport stream
79.
Fast boot systems and methods for programmable logic devices
Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
H03K 19/17756 - Structural details of configuration resources for partial configuration or partial reconfiguration
H03K 19/17758 - Structural details of configuration resources for speeding up configuration or reconfiguration
A non-volatile programmable bitcell has a read enable device with a source coupled with a bitline, an anti-fuse device with a gate coupled with a first write line, a drain coupled with a supply voltage and a source coupled with a drain of the read enable device. The bitcell has a fuse device coupled between a second write line and the drain of the read enable device. A magnitude of current flowing in the bitline, when the read enable device is enabled for reading, is dependent both on (1) a voltage level applied to the first write line and anti-fuse device state and on (2) a voltage level applied to the second write line and fuse device state. Usages include in a memory array, such as for FPGA configuration memory. The bitcell can be used as a multi-time programmable element, or to store multiple bit values.
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.
H03K 3/3562 - Bistable circuits of the primary-secondary type
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
H03K 19/17728 - Reconfigurable logic blocks, e.g. lookup tables
A direct digital synthesizer (DDS) is controlled by a suitably configured programmable logic device (PLD). The DDS includes a digital analog converter (DAC), and a coupled driver/buffer configured to drive relatively high capacitive loads with substantially rail to rail sinusoidal driver output signals and with little to no waveform distortion. The DAC includes a PMOS and NMOS DACs, and a switch configured to select the PMOS DAC for negative portions and the NMOS DAC for positive portions of an output analog signal generated by the DAC. The driver includes a pair of input differential amplifiers, PMOS and NMOS structures, which may be variable, and a pair of variable current sources. The PLD controls variable elements of the DDS to adjust the achievable positive and negative slew rates of the DDS, independently of one another, to reduce or eliminate risk of signal distortion while maintaining substantially stable rail to rail output.
Various techniques are provided to implement hysteresis control for programmable logic devices (PLDs). In one example, a PLD includes a hysteresis control circuit configured to generate a hysteresis control signal based on a core voltage and an input/output (I/O) voltage. The PLD further includes an I/O cell associated with an I/O fabric of the PLD and powered by the I/O voltage. The I/O cell includes a first buffer circuit configured to receive an input voltage and generate a first buffer voltage based on the input voltage. The I/O cell further includes a hysteresis generator configured to generate a hysteresis voltage based on the hysteresis control signal and the I/O voltage. The I/O cell further includes a second buffer circuit configured to generate a second buffer voltage based on the first buffer voltage and the hysteresis voltage. Related methods and systems are provided.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
G05B 19/05 - Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
84.
TRANSMITTING COMMON MODE CONTROL DATA OVER AUDIO RETURN CHANNEL
A source device and a sink device may be connected using an interface cable comprising at least first and second physical channels. The first physical channel may be used to transmit video data unidirectionally from the source device to the sink device. In addition, the second physical channel may comprise an audio return channel wherein audio data can be transmitted unidirectionally from the sink device to the source device at a first rate. In addition, the second physical channel may also transmit bidirectional control data between the source and sink devices at a second rate slower than the first rate. The audio data may be overlaid on the control data, wherein the audio data is transmitted using differential signaling, while the control data is transmitted using common mode signaling.
A source device and a sink device may be connected using an interface cable comprising at least first and second physical channels. The first physical channel may be used to transmit video data unidirectionally from the source device to the sink device. In addition, the second physical channel may comprise an audio return channel wherein audio data can be transmitted unidirectionally from the sink device to the source device at a first rate. In addition, the second physical channel may also transmit bidirectional control data between the source and sink devices at a second rate slower than the first rate. The audio data may be overlaid on the control data, wherein the audio data is transmitted using differential signaling, while the control data is transmitted using common mode signaling.
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
H04N 21/4363 - Adapting the video stream to a specific local network, e.g. a Bluetooth® network
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 1/16 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
H04N 21/439 - Processing of audio elementary streams
H04L 1/18 - Automatic repetition systems, e.g. Van Duuren systems
86.
Selective power gating of routing resource configuration memory bits for programmable logic devices
Various techniques are provided to efficiently implement selective power gating of routing resource configuration memory bits for programmable logic devices (PLDs). In one example, a PLD includes a routing circuit configured to selectively route input nodes to an output node. The PLD further includes configuration memory cells configured to store configuration bit values to control the routing circuit. The PLD further includes a power circuit configured to power the configuration memory cells while storing the configuration bit values. The PLD further includes an enable bit memory cell configured to store an enable bit value to interrupt at least one connection of the power circuit to the configuration memory cells. The configuration memory cells are configured to provide, in response to an interruption of the connection, default configuration bit values to the routing circuit to prevent routing the input nodes to the output node. Additional systems and related methods are provided.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
G11C 11/413 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
G11C 8/14 - Word line organisationWord line lay-out
Methods and circuitry for low-speed bus time stamping and triggering are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that comprises a data line and a clock line. The master device generates and controls a clock signal on the clock line, and sends a synchronization command over the data line to the slave devices. In response to the synchronization command, the master device receives timestamp information of an event detected at each slave device. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can further send to each slave device delay setting information for generating a trigger signal at that slave device based on transitions of the clock signal, the synchronization command and the delay setting information.
A voltage controlled oscillator (VCO) is disclosed. The VCO includes an amplifier that receives a control signal and a feedback signal and generates an amplified output signal based on the difference between the control signal and the feedback signal. The VCO also includes circuitry to generate an oscillating output signal based on the amplifier output signal. Additionally, the VCO includes a feedback amplifier that generates the feedback signal based on the output of the amplifier. The feedback amplifier includes a first resistor connected in parallel with a second resistor, the second resistor having an adjustable resistance.
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
89.
CLOCK RECOVERY AND DATA RECOVERY FOR PROGRAMMABLE LOGIC DEVICES
Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
90.
Transmitter circuit harvesting power from power supply of a receiver circuit
A transmitter (TX) circuit harvesting power from a power supply of a receiver (RX) circuit is disclosed herein. The TX circuit for data transmission over a differential channel comprises a driver circuit coupled with the differential channel across a first pair of resistors. One terminal of each resistor of the first pair coupled together at a common mode voltage node. The differential channel is series terminated at the RX circuit by a second pair of resistors to a power supply node of the RX circuit. The driver circuit includes a differential pair and a current source drawing current from the power supply node of the RX circuit. A pre-driver circuit coupled with the driver circuit provides an output of the pre-driver circuit as an input to the driver circuit. At least the pre-driver circuit is powered from the common mode voltage node of the driver circuit.
Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.
Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.
A method and apparatus for a network repository for metadata. Embodiments of a data repository include a memory to store data including one or more data content items, where each data content item is associated with zero or more metadata items, and where each data content item is associated with a handle and each metadata item is associated with an attribute name. The data repository further includes a network interface configured to communicate with a client device, and a control unit configured to control the storage of data in the memory, where the control unit provides functions for writing data to and reading data from the memory and where the control unit is to transfer the data without interpretation.
G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
G06F 16/13 - File access structures, e.g. distributed indices
G06F 16/48 - Retrieval characterised by using metadata, e.g. metadata not derived from the content or metadata generated manually
94.
Compressed blanking period transfer over a multimedia link
A transmitting device for communicating via a multimedia communication link includes a compression circuitry that receives blanking period data corresponding to blanking states of video blanking periods. The compression circuitry compresses the blanking period data into compressed blanking period data. The transmitting device also includes an interface that transmits signals corresponding to the compressed blanking period data via one or more multimedia channels of the multimedia communication link.
H04N 7/088 - Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band with signal insertion during the vertical blanking interval the inserted signal being digital
H04N 19/463 - Embedding additional information in the video signal during the compression process by compressing encoding parameters before transmission
H04N 21/4402 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
H04N 21/4363 - Adapting the video stream to a specific local network, e.g. a Bluetooth® network
H04N 19/85 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
H04N 7/083 - Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band with signal insertion during the vertical and the horizontal blanking interval
H04N 21/2343 - Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
H04N 19/00 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04N 21/2662 - Controlling the complexity of the video stream, e.g. by scaling the resolution or bitrate of the video stream based on the client capabilities
H04N 7/085 - Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band with signal insertion during the horizontal blanking interval the inserted signal being digital
H04N 7/084 - Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band with signal insertion during the horizontal blanking interval
H04N 7/087 - Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band with signal insertion during the vertical blanking interval
H04N 7/025 - Systems for transmission of digital non-picture data, e.g. of text during the active part of a television frame
09 - Scientific and electric apparatus and instruments
Goods & Services
Computer software for use in the design of programming for programmable integrated circuits; computer software for electronic design automation; computer software for designing integrated circuits; computer software for configuring programmable integrated circuits; computer software for use in the design, programming, and operation of programmable gate arrays
A non-volatile programmable bitcell has a read enable device with a source coupled with a bitline, an anti-fuse device with a gate coupled with a first write line, a drain coupled with a supply voltage and a source coupled with a drain of the read enable device. The bitcell has a fuse device coupled between a second write line and the drain of the read enable device. A magnitude of current flowing in the bitline, when the read enable device is enabled for reading, is dependent both on (1) a voltage level applied to the first write line and anti-fuse device state and on (2) a voltage level applied to the second write line and fuse device state. Usages include in a memory array, such as for FPGA configuration memory. The bitcell can be used as a multi-time programmable element, or to store multiple bit values.
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Various techniques are provided for implementing a hybrid electrical-optical interface. In one example, the hybrid electrical-optical interface includes a connector body configured to mate with an universal serial bus (USB) component in accordance with a predetermined mechanical misalignment tolerance, a plurality of electrical conduits disposed within the connector body and configured to pass electrical signals, and an optical conduit disposed within the connector body between at least two of the electrical conduits, wherein the optical conduit is configured to pass optical signals through a free space gap formed while the connector body is mated with the USB component, and configured to maintain communication of the optical signals through the free space gap while the connector body and the USB component are within the misalignment tolerance. Additional implementations and related methods are also provided.
Various techniques are provided for implementing a hybrid electrical-optical interface. In one example, the hybrid electrical-optical interface includes a connector body configured to mate with a high-definition multimedia interface (HDMI) component in accordance with a predetermined mechanical misalignment tolerance, a plurality of electrical conduits at least partially disposed within a central region of the connector body and configured to pass electrical signals, and first and second optical conduits at least partially disposed within first and second peripheral regions of the connector body adjacent to the central region, wherein the optical conduits are configured to pass optical signals through a free space gap formed while the connector body is mated with the HDMI component and configured to maintain communication of the optical signals through the free space gap while the connector body and the HDMI component are within the misalignment tolerance. Additional implementations and related methods are also provided.
In one embodiment, an integrated circuit has one or more multi-channel transmitters, each transmitter having synchronization circuitry that synchronizes different copies of a reset signal used to reset different sets of TX channel circuitry used to generate the multiple TX signals, to reduce the skew between the different TX signals. Each set of synchronization circuitry has (at least) two synchronization stages that re-time different copies of the reset signal to a selected clock signal. In one implementation, the integrated circuit has (at least) two quads, each of which can generate four different TX signals, where both quads can be configured to use the same clock signal to re-time different copies of the reset signal such that the eight different TX signals are all synchronized to one another.
Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.
H03K 3/3562 - Bistable circuits of the primary-secondary type
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
