A method of manufacturing a packaging substrate according to the present disclosure manufactures a packaging substrate by including a preparation step of providing a base substrate including a core layer and an insulating layer disposed on the core layer and a plasma step of plasma-treating an upper surface of the insulating layer. In the plasma step, an inert gas is applied as a process gas, and a plasma process condition index (Ipp value) defined by the following Equation 1 is 80 seconds or greater. A developed interfacial area ratio (Sdr value) of the upper surface of the insulating layer after completion of the plasma step is 50% or less. [Equation 1] Ipp=Rsb*H In Equation 1, Rsb is a ratio of bias power to source power applied during the plasma step, and His a processing time of the plasma step. In such a case, a redistribution layer having a fine pitch on the core layer may be more precisely implemented.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
C23C 14/02 - Pretreatment of the material to be coated
An embodiment relates to an automatic carrier slot scanning apparatus for glass substrate semiconductor packages for automation of a glass substrate semiconductor package factory, and more particularly, to an automatic carrier slot scanning apparatus for glass substrate semiconductor packages configured to automatically scan positions and the number of glass substrates for slots of a carrier, compare the scanned information with related information of a manufacturing execution system, and thereby achieve synchronization.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
3.
PACKAGING SUBSTRATE AND SEMICONDUCTOR PACKAGE COMPRISING THE SAME
A packaging substrate according to the present disclosure comprises a core layer and an insulating layer disposed on the core layer. The insulating layer comprises an insulating resin. The insulating layer comprises a first insulating layer and a second insulating layer disposed on the first insulating layer. A hydroxyl peak intensity of the second insulating layer measured by FT-IR is smaller than a hydroxyl peak intensity of the first insulating layer measured by FT-IR. A moisture absorption amount of the packaging substrate measured after being left to stand for 7 days under an atmosphere of 23° C. and 50% RH is 500 ppm to 1200 ppm.
A packaging substrate according to the present disclosure comprises a core layer and an insulating layer disposed on the core layer. The insulating layer comprises an insulating resin. The insulating layer comprises a first insulating layer and a second insulating layer disposed on the first insulating layer. A hydroxyl peak intensity of the second insulating layer measured by FT-IR is smaller than a hydroxyl peak intensity of the first insulating layer measured by FT-IR. A moisture absorption amount of the packaging substrate measured after being left to stand for 7 days under an atmosphere of 23° C. and 50% RH is 500 ppm to 1200 ppm.
In such a case, a packaging substrate and the like capable of stably maintaining long-term durability and electrical reliability may be provided.
G01N 21/35 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light
G01N 21/3563 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light for analysing solidsPreparation of samples therefor
According to the present disclosure, a substrate comprises a glass core. The glass core comprises a through via penetrating the glass core in a thickness direction. A diameter of the through via is 50 μm to 100 μm. A sum of a sulfur content (atomic %) and a nitrogen content (atomic %) of the glass core is 0.2 atomic % to 8 atomic %.
According to the present disclosure, a substrate comprises a glass core. The glass core comprises a through via penetrating the glass core in a thickness direction. A diameter of the through via is 50 μm to 100 μm. A sum of a sulfur content (atomic %) and a nitrogen content (atomic %) of the glass core is 0.2 atomic % to 8 atomic %.
In this case, it may be possible to provide a substrate that achieves more stable electrical connection through the glass core and exhibits stable durability and electrical reliability even under a high-humidity environment.
An embodiment relates to a packaging substrate comprises: a glass core; a wiring layer; and an insulating layer, wherein the glass core is a plate-shaped glass in which vias are disposed, the wiring layer is an electrically conductive layer disposed on a surface of the glass core, the insulating layer is a layer disposed in a space between the electrically conductive layers and comprising a mixture of a polymer resin and an insulating filler, the packaging substrate has an upper surface on which a semiconductor element is mounted and a lower surface facing the upper surface, the insulating layer disposed on an upper portion of the glass core is an upper insulating layer, a cover layer is further disposed on the upper insulating layer, the insulating layer disposed on a lower portion of the glass core is a lower insulating layer, and a solder resist layer is further disposed on the lower insulating layer.
The embodiment relates to a packaging substrate comprising: a glass wafer 20; a plurality of vias 25 disposed in the glass wafer 20; copper electrodes 40 disposed on the vias 25 or on the surface of the glass wafer 20; and an insulating layer 30 surrounding the vias 25 or the copper electrodes 40. The packaging substrate 100 comprises P and Zn as eluted impurities, and the content of the eluted impurities is based on an analysis value obtained by preparing an analytical solution through pretreatment at 200°C for 16 hours in a graphite block after adding 70 mol% nitric acid to the packaging substrate 100, and analyzing the solution using an ICP-MS device (Nexlon2000 model manufactured by PerkinElmer) in accordance with KS M 0025:2008 test method. The content of P (by weight) is 1,500 ppb or less, and the content of Zn (by weight) is 500 ppb or less.
A substrate according to the present disclosure comprises a glass core having an upper surface. A maximum height roughness (Rmax) value of the upper surface of the glass core is 3 nm to 7 nm. A surface energy of the upper surface of the glass core is 50 mN/m to 63 mN/m. In such a case, an insulating layer having improved peel resistance may be implemented on the glass core, and electrical reliability of the substrate may be further improved.
A packaging substrate comprising a glass core, an upper redistribution layer, and a lower redistribution layer is provided. The glass core is a plate-shaped glass in which vias are arranged, the upper redistribution layer is disposed above the glass core, and the lower redistribution layer is disposed below the glass core. The redistribution layer comprises a wiring layer being a patterned copper layer having grains. C is an area ratio of grains having a major axis to minor axis ratio of 3:1 or greater in the wiring layer disposed in the upper redistribution layer, and D is an area ratio of grains having a major axis to minor axis ratio of 3:1 or greater in the wiring layer disposed in the lower redistribution layer. A value obtained by dividing C by D in the packaging substrate is 0.85 or more and 0.99 or less.
A packaging substrate according to the embodiment comprises: a glass core; a wiring layer; and an insulating layer. A measurement point is a point on the surface of the packaging substrate, and ten different measurement points are disposed on the surface. The measurement points are spaced apart by at least 0.05 times the surface length. Er is a value of extreme surface reduced modulus (unit: GPa) measured at the measurement point using a nanoindentation method, Er_av is the average of the extreme surface reduced modulus values measured at the measurement points, and Er_stdev is the standard deviation thereof. The ratio of Er_stdev to Er_av may be 7% or less. The packaging substrate according to the embodiment can reduce overall stress by adjusting variations in the extreme surface modulus according to in-plane location within a certain range.
The present invention relates to a method of pre-adjusting a glass substrate for a glass substrate semiconductor package to significantly shorten manufacturing time and improve manufacturing efficiency includes selecting one material group from among a plurality of material groups, each of which has a plurality of glass substrates, collecting processing process information by a processing equipment for performing a processing process on the plurality of glass substrates belonging to the one material group according to identification codes, checking according to the processing process information, whether a transfer equipment associated with the processing equipment for performing a current processing process and a transfer equipment associated with the processing equipment for performing a next processing process are each provided with a flipper, and pre-adjusting each of the plurality of glass substrates by rotating the each of the plurality of plurality of glass substrates using the processing equipment for the current processing process.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
A method of manufacturing a packaging substrate according to the present disclosure comprises a preparation step of preparing a preliminary substrate including a glass core on which a device portion including a device is mounted; and an encapsulation layer forming step of manufacturing the packaging substrate by forming an encapsulation layer surrounding at least a portion of the device portion with an encapsulation layer-forming composition. The glass core comprises a cavity portion that is a space formed by being recessed on an upper surface side of the glass core. The device portion is disposed in the cavity portion. A viscosity of the encapsulation layer-forming composition at 25° C. is 12,000 cps to 38,000 cps.
A method of manufacturing a packaging substrate according to the present disclosure comprises a preparation step of preparing a preliminary substrate including a glass core on which a device portion including a device is mounted; and an encapsulation layer forming step of manufacturing the packaging substrate by forming an encapsulation layer surrounding at least a portion of the device portion with an encapsulation layer-forming composition. The glass core comprises a cavity portion that is a space formed by being recessed on an upper surface side of the glass core. The device portion is disposed in the cavity portion. A viscosity of the encapsulation layer-forming composition at 25° C. is 12,000 cps to 38,000 cps.
In this case, it is possible to suppress occurrence of voids in the encapsulation layer, and it is possible to suppress occurrence of defects such as the glass core and the encapsulation layer which may occur in the manufacturing process.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
An embodiment relates to a packaging substrate having an embedded bridge, and comprises: a glass core having a cavity and through-electrodes; a bridge disposed in the cavity; an integrated electrode disposed on one surface of the bridge and on one surface of the glass core; and an insulating material disposed between the glass core and the bridge and between the integrated electrode. The bridge comprises: a bridge core, which is a support; and a bridge electrode disposed inside the bridge core, electrically interconnecting at least two points on one face of the bridge, with both ends exposed to a surface of the bridge core. The integrated electrode is an electrically conductive layer electrically connected to at least one of the through-electrodes and the bridge electrode.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
According to an embodiment, a method for manufacturing a packaging substrate comprises: a preparation step to comprise a base substrate including a core layer, a first conductive layer disposed on the core layer, and an insulating layer disposed on the first conductive layer; and a desmear step to comprise desmearing the base substrate, thereby providing a packaging substrate. The insulating layer comprises a contact hole penetrating the insulating layer in a thickness direction. An upper surface of the first conductive layer comprises an exposed region exposed by the contact hole. In the desmear step, the base substrate is plasma-desmeared using a reactive gas comprising oxygen gas and a fluorine-based gas. In the desmear step, a ratio of a flow rate of the fluorine-based gas to a flow rate of the oxygen gas introduced into an atmosphere in which the base substrate is placed is 4.5 or more.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
14.
PACKAGING SUBSTRATE AND MANUFACTURING METHOD THEREOF
A packaging substrate according to the present disclosure comprises a core layer; a first conductive layer, which is a conductive layer disposed in contact with an upper surface of the core layer; and an adhesion reinforcement layer disposed on the core layer and surrounding at least a portion of the first conductive layer. The adhesion reinforcement layer comprises any one selected from the group consisting of a silicon-based compound, an acrylic-based compound, and a combination thereof. An arithmetic average roughness (Ra) value of the upper surface of the first conductive layer is 150 nm or less.
A packaging substrate according to the present disclosure comprises a core layer; a first conductive layer, which is a conductive layer disposed in contact with an upper surface of the core layer; and an adhesion reinforcement layer disposed on the core layer and surrounding at least a portion of the first conductive layer. The adhesion reinforcement layer comprises any one selected from the group consisting of a silicon-based compound, an acrylic-based compound, and a combination thereof. An arithmetic average roughness (Ra) value of the upper surface of the first conductive layer is 150 nm or less.
In this case, it is possible to effectively improve the adhesion strength of the insulating layer to the first conductive layer without excessively roughening the first conductive layer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
According to the present disclosure, a packaging substrate includes a glass core and an adhesion reinforcement layer disposed on the glass core. The adhesion reinforcement layer includes a first adhesion reinforcement layer and a second adhesion reinforcement layer disposed on the first adhesion reinforcement layer. The first adhesion reinforcement layer includes a transition metal and silicon. The second adhesion reinforcement layer includes a transition metal.
In such a case, it is possible to improve the bonding strength of the conductive layer with respect to the glass core, while effectively suppressing damage to the packaging substrate caused by the difference in thermal expansion properties between the glass core and the conductive layer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A method for manufacturing a packaging substrate includes a preparation step of preparing a base substrate comprising a core substrate and an insulating layer disposed on the core substrate, an etching step of selectively etching the insulating layer using an etching mask, and a manufacturing step of manufacturing the packaging substrate from the base substrate after the etching step. The etching mask is disposed on the insulating layer and includes a metal pattern film and a resist pattern film disposed on the metal pattern film.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
Disclosed is a substrate loading cassette including an upper frame, a lower frame disposed to face the upper frame, a support frame configured to connect the upper frame and the lower frame to each other at an edge side of the substrate loading cassette, a transfer device coupling unit disposed on the upper frame, the transfer device coupling unit being coupled to a transfer device configured to transfer the substrate loading cassette, wherein the transfer device coupling unit includes a transfer device coupling frame and a vibration damping portion disposed under the transfer device coupling frame, the support frame includes a first support frame disposed on each of left and right sides of the substrate loading cassette and a second support frame disposed on a rear side of the substrate loading cassette, and the substrate loading cassette includes a support bar connected to the second support frame.
B23Q 7/10 - Arrangements for handling work specially combined with or arranged in, or specially adapted for use in connection with, machine tools, e.g. for conveying, loading, positioning, discharging, sorting by means of magazines
18.
PACKAGING SUBSTRATE AND SEMICONDUCTOR PACKAGE COMPRISING SAME
A packaging substrate according to the present disclosure includes a glass core and an insulating layer disposed on the glass core. The glass core has a thickness of 100 μm or more. The insulating layer has an HEI value, which is the heat-resistant elasticity index of Equation 1 below, of 1.2 or more.
A packaging substrate according to the present disclosure includes a glass core and an insulating layer disposed on the glass core. The glass core has a thickness of 100 μm or more. The insulating layer has an HEI value, which is the heat-resistant elasticity index of Equation 1 below, of 1.2 or more.
HEI
=
Tg
E
×
CTE
[
Equation
1
]
in Equation 1,
Tg is the glass transition temperature (unit: ° C.), E is the elastic modulus (unit: GPa) measured at 23° C., and CTE is the coefficient of thermal expansion (ppm/° C.).
A packaging substrate according to the present disclosure includes a glass core and an insulating layer disposed on the glass core. The glass core has a thickness of 100 μm or more. The insulating layer has an HEI value, which is the heat-resistant elasticity index of Equation 1 below, of 1.2 or more.
HEI
=
Tg
E
×
CTE
[
Equation
1
]
in Equation 1,
Tg is the glass transition temperature (unit: ° C.), E is the elastic modulus (unit: GPa) measured at 23° C., and CTE is the coefficient of thermal expansion (ppm/° C.).
In this case, damage to the glass core during a process of forming a redistribution layer can be effectively suppressed.
A manufacturing method for a packaging substrate is provided. The manufacturing method includes a preparation step of preparing a base substrate including a core layer including an upper surface and a through-hole formed in a thickness direction of the core layer, a via insulating portion forming step of forming a via insulating portion in the through-hole to prepare a via-plugged substrate, and a fabrication step of fabricating a packaging substrate from the via-plugged substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
20.
METHOD OF MANUFACTURING SUBSTRATE INCLUDING PACKAGING SUBSTRATE
Disclosed is a method of manufacturing a substrate including a packaging substrate. The method includes an operation of preparing a glass core having core vias, a 1-1st operation of forming a first metal layer on the glass core, a 1-2nd operation of laminating a first insulative material layer on the first metal layer, a 1-3rd operation of curing the first insulative material layer to prepare a first insulating layer, a 2-1st operation of forming a second metal layer on the first insulative material layer so as to be electrically connected to the first metal layer, and a 2-2nd operation of laminating a second insulative material layer on the second metal layer. The 1-3rd operation includes pre-curing the first insulative material layer at a temperature of 80° C. or higher but lower than 175° C. and post-curing the first insulative material layer at a temperature of 175° C. to 230° C.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
21.
PACKAGING SUBSTRATE AND MANUFACTURING METHOD THEREOF
A packaging substrate and a manufacturing method of a packaging substrate are provided. A packaging substrate according to the present disclosure includes a glass substrate having first and second sides facing each other; a cavity part formed in the glass substrate; and a cavity element disposed in the cavity part. The cavity part includes a cavity space in which at least a portion of the cavity element is inserted, a sidewall surrounding the cavity space, and a gap disposed between a first side of the cavity element and the sidewall, the gap being filled with one or more types of filling material.
A substrate and a packaging substrate are provided. A substrate according to the present disclosure is a plate-shaped substrate included in a packaging substrate, including a glass substrate having a first face and a second face facing each other, the glass substrate having a cavity portion; and a cavity extension portion; disposed thereon, the cavity portion having an accommodation space therein and having at least one corner, the corner being a virtual line where extensions of two adjacent sides of the accommodation space meet, the cavity extension portion being disposed at the corner and having a corner space connected with the accommodation space.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
23.
PACKAGING SUBSTRATE AND MANUFACTURING METHOD OF PACKAGING SUBSTRATE
The present disclosure relates to a packaging substrate and a method for manufacturing a packaging substrate. The packaging substrate according to the present disclosure includes a core layer comprising a glass core having first and second surfaces opposite each other and a cavity portion penetrating the glass core; a cavity module and a second insulating layer disposed in the cavity portion. The cavity module comprises: a plurality of electronic elements, a first insulating layer and a third insulating layer. The first insulating layer covers each of the electronic elements with a coating material. The first insulating layer is disposed on an entire surface or an entire surface except one surface of each of the electronic elements. The third insulating layer disposes to cover the electronic elements with a molding material. The second insulating layer is embedded in a portion of the cavity portion excluding the cavity module.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
A method of manufacturing a packaging substrate according to an embodiment includes a preparation step of preparing a base substrate comprising a core layer and an insulating layer formed on the core layer, a patterning step of selectively plasma etching the insulating layer with an etching mask to form a patterned insulating layer, and a manufacturing step of manufacturing a packaging substrate from the base substrate on which the patterned insulating layer is formed. The etching mask includes an organic compound. The atmosphere temperature of the patterning step is 120° C. or less. In this case, packaging substrates may be manufactured with an improved convenience of manufacturing process and improved electrical reliability.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
B08B 7/02 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass by distortion, beating, or vibration of the surface to be cleaned
A packaging substrate according to a present disclosure includes a silica-based core. The silica-based core includes a through via portion passing through the silica-based core in a thickness direction of the silica-based core. The through via portion includes a via space which is a space where an electrode is disposed and a via inner diameter surface surrounding the via space. The packaging substrate includes a through electrode disposed in the via space. The through electrode includes metal grain having a preferential orientation in the thickness direction of the silica-based core. In this case, a packaging substrate having excellent electrical reliability, and in which misalignment of an electrically conductive layer pattern is suppressed when a redistribution layer is formed may be provided.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
An embodiment relates to a manufacturing method of a packaging substrate and a packaging substrate utilizing the same. A packaging substrate according to the present disclosure includes a core layer, the core layer comprising: a glass core having first and second surfaces facing each other; a cavity portion having a surface recessed to open in the direction of the first surface; and a plurality of core vias penetrating the glass core in a thickness direction, the glass core comprising a first glass and a second glass laminated up and down, the first glass and the second glass having a bonding interface disposed between them, and the tapered angle of the cavity portion may be from 86 degrees to 90 degrees.
H01L 23/08 - ContainersSeals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
Embodiments of a substrate and a manufacturing method of the substrate are directed to a substrate comprising a packaging substrate on which one or more electronic elements are disposed, the substrate comprising a glass core having a first and second surfaces facing each other; and a side surface the first and second surfaces; a upper layer laminated on the first surface or a lower layer laminated under the second surface; and a side protection layer covering a side surface of the glass core with a protective material, characterized in that defect is formed in an inward direction of the glass core on the side of the glass core, and the protective material fills the defect.
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A packaging substrate and a semiconductor package are provided. The packaging substrate according to a present disclosure includes a glass core. The glass core includes a through via passing through the glass core in a thickness direction of the glass core. The glass core has a surface. The packaging substrate includes a crack prevention layer surrounding at least a portion of the surface. In the packaging substrate, a ratio of a thickness of the crack prevention layer to a thickness of the glass core is 0.0001 to 0.05.
A packaging substrate and a semiconductor package are provided. The packaging substrate according to a present disclosure includes a glass core. The glass core includes a through via passing through the glass core in a thickness direction of the glass core. The glass core has a surface. The packaging substrate includes a crack prevention layer surrounding at least a portion of the surface. In the packaging substrate, a ratio of a thickness of the crack prevention layer to a thickness of the glass core is 0.0001 to 0.05.
In this case, a packaging substrate having excellent durability against a thermal impact and a mechanical impact may be provided.
This specification relates to a packaging substrate and a manufacturing method for the packaging substrate. The packaging substrate according to this specification includes a core layer comprising a glass core having a first surface and a second surface facing each other, as well as a cavity portion penetrating through the glass core. An element module is arranged in the cavity portion, which includes a cavity element and a distribution layer formed on upper side of the cavity element. The cavity distribution layer includes a redistribution circuit layer and a cavity heat dissipation pattern, where the redistribution circuit layer includes i) a cavity bump layer; or ii) vias and circuit layers. The cavity heat dissipation pattern facilitates the movement of heat generated by the cavity element.
H01L 23/367 - Cooling facilitated by shape of device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
30.
PACKAGING SUBSTRATE AND MANUFACTURING METHOD OF PACKAGING SUBSTRATE
The present disclosure relates to a manufacturing method for a packaging substrate and a packaging substrate utilizing the method. The packaging substrate according to the present disclosure may comprise a core layer comprising a glass core having a first surface and a second surface facing each other, a cavity portion opening recessed in the direction of the first surface or the second surface, and a plurality of core vias penetrating the glass core in the thickness direction, wherein the internal space of the cavity includes a first section recessed space within glasses at regular depths in the thickness direction and a second section recessed space within at increasingly smaller widths in the thickness direction. Through it, the effect of strengthening the bonding force of the glasses forming the glass core with the half-cavity can be achieved to prevent delamination of the glasses forming the glass core even after multiple high-temperature processes.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
This specification relates to a packaging substrate and a manufacturing method for the packaging substrate. The packaging substrate according to this specification includes a core layer comprising a glass core having a first surface and a second surface facing each other, as well as a cavity portion penetrating through the glass core. An element module is disposed of the cavity portion. The element module comprises one or more cavity elements and a cavity distribution layer that are modularized into a capsule layer, wherein the cavity distribution layer is disposed above the cavity element, and the cavity distribution layer comprises a redistribution distribution circuit layer. A manufacturing method of a packaging substrate comprises preparing operation of a glass core with a cavity portion and an element module; and arranging operation of the element module in the cavity portion.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
32.
MANUFACTURING METHOD OF PACKAGING SUBSTRATE AND PACKAGING SUBSTRATE USING THE SAME
A method for manufacturing a packaging substrate and a packaging substrate using the method are provided. A packaging substrate includes a core layer and an upper layer disposed on the core layer. The core layer includes a glass core having a first face and a second face facing each other. The upper layer includes a first distribution layer formed on the core layer, and a dummy layer formed on the first distribution layer. The dummy layer may include a material having a lower coefficient of thermal expansion (CTE) than a CTE of an insulating material of the first distribution layer.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
The present specification relates to a method of manufacturing a packaging substrate and a packaging substrate manufactured thereby. The packaging substrate according to the present specification includes a core layer comprising a glass core and a cavity portion, wherein the glass core is a glass substrate having a first surface and a second surface facing each other, the cavity portion has an accommodation space for accommodating an electronic element as a part of the glass core is recessed or penetrated, and the element package is placed in the accommodation space of the cavity portion, wherein the element package comprises i) a plurality of arranged electronic elements; and ii) a molding portion containing a molding material and the molding portion arranges for the molding material to surround the electronic elements, and a concave portion having arranged dimples is disposed in some of the molding portion at the element package.
An embodiment relates to a packaging substrate and a manufacturing method of the same. The packaging substrate according to an embodiment includes a glass core including a first surface and a second surface facing each other; and an upper layer stacked on the first surface or a lower layer stacked on the second surface, and the corners of the packaging substrate may be treated as curved surfaces or chamfered. Through this, it is possible to protect the glass core from external impact and minimize damage and damage to the glass core.
B24B 7/24 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfacesAccessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding or polishing glass
C03B 33/07 - Cutting armoured or laminated glass products
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
35.
MANUFACTURING METHOD OF PACKAGING SUBSTRATE AND PACKAGING SUBSTRATE USING THE SAME
The present disclosure relates to a manufacturing method for a packaging substrate and a packaging substrate utilizing the method. The packaging substrate according to the present disclosure includes; a core layer including a glass substrate having first and second surfaces facing each other and a cavity portion; an insulating layer formed on the first surface; and a light transmitting portion formed on an upper surface of the insulating layer, wherein a light receiving portion is disposed in the cavity portion, the insulating layer includes a via penetrating in a thickness direction, and a portion of a lower surface of the light transmitting portion may abut on the via. Though it, the packaging substrate may be compactly manufactured by reducing the space for the configuration of electrically connecting the conventional photoelectric elements, and the effect of improving the sensing efficiency and performance of the photoelectric sensor relative to the space may occur.
Embodiments relate to packaging substrates and methods of manufacturing the same. A substrate with embedded elements according to the embodiments comprises a glass substrate comprising a first surface and a second surface facing each other; and an upper layer stacked on the first surface, or a lower layer stacked on the second surface; wherein the glass substrate may have an edge region that protrudes from the upper layer or the lower layer. A manufacturing method of a packaging substrate, comprises a forming operation of an upper layer on a first surface of a glass substrate comprising the first surface and a second surface facing each other; a removing operation of the upper layer by a predetermined width along a predetermined cutting line; a forming operation of a filamentation along the cutting line on the glass substrate from which the upper layer has been removed; and a cutting operation of the glass substrate using the filamentation. Through this, defects occurring on the surface and cross section of the substrate can be easily detected.
A packaging substrate includes a glass substrate comprising a first surface and a second surface facing each other, a plurality of core vias passing through the glass substrate in a thickness direction, and a core layer having a core seed layer as a seed for forming an electrically conductive layer on a surface of the core vias. The packaging substrate further includes an upper layer disposed on one surface of the core layer. The core layer includes a core distribution layer disposed on a surface of the glass substrate or a surface of the core via. The core distribution layer includes an electrically conductive layer at least a part of which electrically connects an electrically conductive layer of the first surface and an electrically conductive layer of the second surface through the core via.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
The present specification relates to a method of manufacturing a packaging substrate and a packaging substrate manufactured thereby. The packaging substrate according to the present specification includes a core layer including a glass substrate having a first surface and a second surface facing each other and a cavity portion passing through the glass substrate, wherein a cavity module is disposed in the cavity portion, the cavity module comprise a cavity element and a first insulating layer is formed on some surfaces other than one surface or on all the surface of the cavity element, and a second insulating layer is incorporated into the remaining portion of the cavity portion other than the cavity module, and the first insulating layer and the second insulating layer have different dielectric constants. Accordingly, an undulation phenomenon due to a gap between elements, a gap between the cavity portion and an element, and/or the like may be prevented, and a leakage current may be prevented from occurring.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
39.
METHOD OF MANUFACTURING PACKAGING SUBSTRATE AND PACKAGING SUBSTRATE MANUFACTURED THEREBY
The present disclosure relates to a method of manufacturing a packaging substrate and a packaging substrate manufactured thereby. The method of manufacturing a packaging substrate according to the present disclosure includes: generating a glass structure that is a core via, a cavity portion, or both on a glass core including a first surface and a second surface facing each other; forming an insulating layer on the first surface or second surface using an insulating film; and forming an upper layer including an upper distribution layer and an upper surface connection layer on the insulating layer. The forming of the insulating layer May include a primary curing operation of laminating a first insulating film on the first surface and primarily curing the first insulating film, and a secondary curing operation of laminating a second insulating film on the primarily cured first insulating film and secondarily curing the second insulating film. Accordingly, warpage may be improved, and separation of an electronic element may be prevented.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
A substrate according to a present disclosure comprises a glass core having a top surface. The glass core top surface has Rs/z, a ratio value of skewness to maximum height roughness of Equation 1 below, between −5 nm−2 and 50 nm−2.
A substrate according to a present disclosure comprises a glass core having a top surface. The glass core top surface has Rs/z, a ratio value of skewness to maximum height roughness of Equation 1 below, between −5 nm−2 and 50 nm−2.
R
s
/
z
=
R
s
k
Rz
2
×
1
0
0
0
[
Equation
l
]
A substrate according to a present disclosure comprises a glass core having a top surface. The glass core top surface has Rs/z, a ratio value of skewness to maximum height roughness of Equation 1 below, between −5 nm−2 and 50 nm−2.
R
s
/
z
=
R
s
k
Rz
2
×
1
0
0
0
[
Equation
l
]
In Equation 1 above, the Rsk value is skewness, and the Rz value is maximum height roughness (in nm).
A substrate according to a present disclosure comprises a glass core having a top surface. The glass core top surface has Rs/z, a ratio value of skewness to maximum height roughness of Equation 1 below, between −5 nm−2 and 50 nm−2.
R
s
/
z
=
R
s
k
Rz
2
×
1
0
0
0
[
Equation
l
]
In Equation 1 above, the Rsk value is skewness, and the Rz value is maximum height roughness (in nm).
For such a substrate, an electrically conductive layer with substantially uniformly improved adhesion to the glass core can be implemented. The electrically conductive layer can efficiently transmit signals even when high frequency power is applied.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
An embodiment relates to a packaging substrate and a method of manufacturing the same. The packaging substrate according to the embodiment includes a core layer, wherein the core layer may include a glass substrate including a first surface and a second surface facing each other, and at least two or more cavity portions each having an opening open in a direction toward the first surface or a direction toward the second surface and having different depths. Accordingly, various types of cavity elements may be mounted without undulation.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A substrate according to an embodiment includes a glass core having a top surface. The top surface of the glass core has a value of Rq*k, bond roughness index of Equation 1 below, from 3.5 nm to 150 nm.
A substrate according to an embodiment includes a glass core having a top surface. The top surface of the glass core has a value of Rq*k, bond roughness index of Equation 1 below, from 3.5 nm to 150 nm.
R
q
*
k
=
R
q
×
R
k
u
2
[
Equation
l
]
A substrate according to an embodiment includes a glass core having a top surface. The top surface of the glass core has a value of Rq*k, bond roughness index of Equation 1 below, from 3.5 nm to 150 nm.
R
q
*
k
=
R
q
×
R
k
u
2
[
Equation
l
]
In Equation 1 above, the value of Rq is root mean square deviation (in nm) and the value of Rku is kurtosis.
A substrate according to an embodiment includes a glass core having a top surface. The top surface of the glass core has a value of Rq*k, bond roughness index of Equation 1 below, from 3.5 nm to 150 nm.
R
q
*
k
=
R
q
×
R
k
u
2
[
Equation
l
]
In Equation 1 above, the value of Rq is root mean square deviation (in nm) and the value of Rku is kurtosis.
For these substrates, an electrically conductive layer can be implemented that has substantially uniformly improved adhesion to the glass core and can efficiently transmit signals even when high-frequency power is applied.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
09 - Scientific and electric apparatus and instruments
21 - HouseHold or kitchen utensils, containers and materials; glassware; porcelain; earthenware
35 - Advertising and business services
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Printed circuit boards; Electronic circuit boards; Electronic integrated circuits; Integrated circuit modules; 3D semiconductor integrated circuits; Large-scale integrated circuits; Electronic memory circuit cards; Circuit boards provided with integrated circuits; Semiconductor chip sets; Computer daughter boards; Digital circuit boards; Motherboards; Printed circuit boards (PCBs); Mother boards Unworked or semi-worked glass incorporating fine electrical conductors, not for building; Semi-worked glass, not for building; Glass incorporating fine electrical conductors, not for building; Substrates primarily of glass incorporating fine electrical conductors for the manufacture of integrated circuits; Substrates primarily of glass incorporating fine electrical conductors for the manufacture of micro-electromechanical systems; Semi-worked glass not for building in the nature of glass used in the manufacture of electronic devices Providing commercial information related to semiconductor packages; Providing commercial information related to semiconductor packages via the Internet; Providing commercial information related to substrates comprised of glass incorporating fine electrical conductors Custom manufacture of finished semiconductors, semiconductor chip and integrated circuit products for others; Custom manufacture of circuit boards and semiconductors for others; Custom manufacturing of semi-conductor parts and integrated circuits for others; Etching of semiconductors for others; Custom manufacturing of semiconductor parts for others Scientific and technical services, namely, design in the field of product engineering mechanical apparatus for manufacturing semiconductors; Providing consulting services in the field of technology and research relating to integrated circuits; Engineering services in the field of semiconductor and integrated circuit design; Engineering services in the field of semiconductor design; Product research, design and development in the field of semiconductors; Testing of semiconductors to determine conformity with certification standards; Product development; Providing consulting services relating to semiconductor product design; Engineering services in the field of semiconductor manufacture; Conducting research in the field of semiconductor manufacture; Providing new product design services to others relating to integrated circuits; Product development, namely, designing electronic circuit substrates for others
09 - Scientific and electric apparatus and instruments
21 - HouseHold or kitchen utensils, containers and materials; glassware; porcelain; earthenware
Goods & Services
Components for electric circuits in the nature of electric circuit boards, electric circuit closers, and electric circuit switches; Printed circuit boards; Electronic circuit boards; Electronic integrated circuits; Large-scale integrated circuits; Circuit boards provided with integrated circuits; Electrical conductors for use in semiconductors made from glass substrates Glass products, namely, glass incorporating fine electrical conductors, not for building; Semi-worked glass, not for building; Unworked or semi-worked glass, not for building, incorporating fine electrical conductors; Substrates primarily of glass incorporating fine electrical conductors for the manufacture of integrated circuits; Modified sheet glass, not for building; Substrates primarily of glass for manufacture of microelectromechanical systems; Modified sheet glass, not for building; Substrates primarily of glass with holes for manufacture of semiconductor packages
45.
SUBSTRATE GRIPPER AND METHOD FOR MOVING A SUBSTRATE USING THE SAME
Disclosed herein are a substrate gripper and a method of transferring a substrate using the same, which include a frame, a plurality of pad holes connected to the frame, and a plurality of suction pads disposed on the frame and connected to the pad holes, wherein the suction pad has a contact surface which comes into contact with one surface of a target substrate when the target substrate is mounted, the suction pad includes a first suction pad having a contact surface at a first height, without supporting the target substrate, and a second suction pad having a contact surface at a second height in a state of not supporting the target substrate, and the first height is greater than the second height based on the frame. In this way, the substrate gripper can stably suction and support the target substrate even when warpage occurs. In addition, the substrate gripper has a strong vertical gripping force and a strong horizontal gripping force and is capable of stably suctioning and supporting the target substrate.
A substrate with an embedded element includes a core substrate having one surface and a cavity recessed from the one surface in a thickness direction; an element package disposed in the cavity, the element package comprising one or more elements; and a substrate insulating material surrounding at least part of the element package. When observed from a side surface of the substrate with the embedded element, the substrate with the embedded element includes a cavity area in which the cavity is disposed and a substrate area outside of the cavity area. An absolute value of difference between an average thickness of the substrate area and an average thickness of the cavity area is 50 μm or less.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
A substrate comprising a glass substrate is provided. The glass substrate includes a first surface, a second surface, and an edge area connecting the first surface and the second surface; a groove part formed toward the inside direction of a glass substrate from a portion of the edge area; and a protecting device formed on the groove part, wherein the groove part penetrates the first surface and the second surface.
C03C 17/30 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with organic material with silicon-containing compounds
48.
Packaging substrate having electric power transmitting elements on non-circular core via of core vias and semiconductor device comprising the same
A packaging substrate includes a core layer including a glass substrate with a first surface and a second surface facing each other, and a plurality of core vias. The plurality of core vias penetrating through the glass substrate in a thickness direction, each comprising a circular core via having a circular opening part and a non-circular core via having an aspect ratio of 2 to 25 in the x-y direction of an opening part. One or more electric power transmitting elements are disposed on the non-circular core via.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
49.
SEMICONDUCTOR PACKAGING SUBSTRATE, SEMICONDUCTOR PACKAGES, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR PACKAGING SUBSTRATE
Embodiments relate to a semiconductor packaging substrate, a semiconductor packages, and a method for manufacturing the semiconductor packaging substrate, wherein a substrate comprising a one surface, other surface facing the one surface, a recessed surface that the one surface recessed, and a side wall connecting the one surface and the recessed surface; and plurality of first vias that penetrating the recessed surface and the other surface; wherein the plurality of first vias include a thermally conductive material. Embodiments have an excellent heat dissipation effect and can prevent warpage on the surface of the substrate due to thermal expansion.
A packaging substrate according to an embodiment includes a cavity region in which an element is accommodated, and a core substrate in which the cavity region is disposed. The cavity region includes an accommodation portion that is a space formed by recessing a portion of the core substrate, a side surface that is formed on an inner side in a thickness direction of the core substrate and forms an outer periphery of the accommodation portion, and an elastic layer disposed adjacent to the side surface.
A packaging substrate according to an embodiment includes a cavity region in which an element is accommodated, and a core substrate in which the cavity region is disposed. The cavity region includes an accommodation portion that is a space formed by recessing a portion of the core substrate, a side surface that is formed on an inner side in a thickness direction of the core substrate and forms an outer periphery of the accommodation portion, and an elastic layer disposed adjacent to the side surface.
An elastic modulus of the elastic layer is 2 GPa to 15 GPa. The packaging substrate may have excellent thermomechanical reliability and long-term durability.
A packaging substrate according to an embodiment has an upper surface and a lower surface. The packaging substrate includes a mounting region in which an element is accommodated and a core substrate in which the mounting region is disposed.
A packaging substrate according to an embodiment has an upper surface and a lower surface. The packaging substrate includes a mounting region in which an element is accommodated and a core substrate in which the mounting region is disposed.
The mounting region includes a cavity portion formed by recessing a portion of the core substrate, a cavity portion side surface formed inside the core substrate in a thickness direction of the core substrate to form an outer periphery of the cavity portion, and a first heat dissipation portion disposed adjacent to the outer periphery of the cavity portion.
A packaging substrate according to an embodiment has an upper surface and a lower surface. The packaging substrate includes a mounting region in which an element is accommodated and a core substrate in which the mounting region is disposed.
The mounting region includes a cavity portion formed by recessing a portion of the core substrate, a cavity portion side surface formed inside the core substrate in a thickness direction of the core substrate to form an outer periphery of the cavity portion, and a first heat dissipation portion disposed adjacent to the outer periphery of the cavity portion.
The first heat dissipation portion is a thermal path through which heat of the packaging substrate is transmitted to the outside.
A packaging substrate according to an embodiment has an upper surface and a lower surface. The packaging substrate includes a mounting region in which an element is accommodated and a core substrate in which the mounting region is disposed.
The mounting region includes a cavity portion formed by recessing a portion of the core substrate, a cavity portion side surface formed inside the core substrate in a thickness direction of the core substrate to form an outer periphery of the cavity portion, and a first heat dissipation portion disposed adjacent to the outer periphery of the cavity portion.
The first heat dissipation portion is a thermal path through which heat of the packaging substrate is transmitted to the outside.
The first heat dissipation portion includes one or more heat dissipation vias each having an area of 5,000 μm2 to 75 mm2 when viewed from the upper surface of the packaging substrate.
A packaging substrate according to an embodiment has an upper surface and a lower surface. The packaging substrate includes a mounting region in which an element is accommodated and a core substrate in which the mounting region is disposed.
The mounting region includes a cavity portion formed by recessing a portion of the core substrate, a cavity portion side surface formed inside the core substrate in a thickness direction of the core substrate to form an outer periphery of the cavity portion, and a first heat dissipation portion disposed adjacent to the outer periphery of the cavity portion.
The first heat dissipation portion is a thermal path through which heat of the packaging substrate is transmitted to the outside.
The first heat dissipation portion includes one or more heat dissipation vias each having an area of 5,000 μm2 to 75 mm2 when viewed from the upper surface of the packaging substrate.
The packaging substrate may effectively emit heat generated during an element driving process, and may have excellent long-term durability and reliability.
An embodiment relates to a substrate and a semiconductor module. A substrate capable of manufacturing a substrate for packaging, which is an individual product, with excellent yield despite cracks that may occur at edges or side surfaces of a core is provided. The substrate comprises a core as a glass or ceramic support, wherein the substrate is divided into a product region and a dummy region, the product region is a region where one or more individual products are disposed, the dummy region is a region of the substrate other than the product region, a breakage prevention portion is disposed in the product region or the dummy region, wherein the breakage prevention portion is a region in which one or more crack stopping structures are disposed, and the crack stopping structure is grooves or vias who stops cracks generated from the side of the core from growing toward the center of the individual product, and wherein the groove is a depression in a surface of the core, and the via is a through hole that has been removed so that a portion of the core being penetrate in a thickness direction.
The embodiment relates to a packaging substrate and a semiconductor apparatus, including an element unit including a semiconductor element; and a packaging substrate electrically connected to the element unit; and it applies a glass substrate as a core of the packaging substrate, thereby can significantly improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a motherboard to be closer to each other so that electrical signals are transmitted through as short a path as possible. Therefore, it can significantly improve electrical properties such a signal transmission rate, substantially prevent generating of parasitic element, and simplify a process of treatment for an insulating layer, and thus provides a packaging substrate applicable to a high-speed circuit.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A packaging substrate is provided. The packaging substrate includes a first area without a cavity and a second area with a cavity. The first area has first and second surfaces facing each other, and a cavity structure of the second area includes a cavity space; a contact surface; and a side wall. The contact surface is disposed opposite to the opening of the cavity structure. A value of a surface roughness of the contact surface is approximately three times or less of a value of a surface roughness of the first surface of the first area.
The present disclosure relates to a core-substrate, a substrate, a use of the substrate, and a semiconductor device comprising the same, wherein the core-substrate is a core-substrate applied to the manufacture of a semiconductor packaging substrate, and the core-substrate distinguished into a product area where a product utilized as a substrate of an individual semiconductor is disposed; and a blank area excepting for the product area, wherein the blank area comprises a protective area disposed between the product area and the substrate, and the protective area comprises a concave or a via. The embodiment can substantially suppress the occurrence of damage in the product area utilized as a substrate for semiconductor packaging, even though a core-substrate which may be easily broken by external impact.
A connection structure of vias is provided. The connection structure includes multiple vias which are disposed within an insulting layer to connect electrical signals in upward and downward directions, the multiple vias comprise a first via and a second via disposed in a vertically stacked relationship with each other, the first via and the second via are configured to meet at a same surface, and the second via and the first via are disposed in respectively different numbers.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
57.
DEVICE PACKAGING SUBSTRATE, MANUFACTURING METHOD FOR THE SAME, AND DEVICE PACKAGE COMPRISING THE SAME
An electronic element packaging substrate and manufacturing method are provided. The substrate includes finer wire widths, transmits signals with low resistance, and provides a compact electronic element package. The substrate may be driven with high efficiency even when high frequency power is applied thereto.
A substrate carrier and a substrate assembly comprising the same are provided. The substrate carrier comprises an accommodation space; a guide unit disposed adjacent to the accommodation space; and a supporting unit disposed under the accommodation space and the guide unit. The guide unit comprises a circular shape or an arc shape in the circumference when viewed from an upper position.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
59.
CLEANED PACKAGING SUBSTRATE AND CLEANED PACKAGING SUBSTRATE MANUFACTURING METHOD
A manufacturing method for a cleaned packaging substrate is provided. The method is applied to a manufacturing process for a glass substrate or a packaging substrate comprising the same, and comprises a preparing process of disposing a target substrate inside a chamber; and a removing process of jetting ionized air on at least one surface of the target substrate to separate particle impurities, and manufacturing a cleaned packaging substrate. The target substrate is a glass packaging substrate, or a packaging substrate, and the packaging substrate comprises the glass packaging substrate and a redistribution layer disposed on at least one surface of the glass packaging substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
B08B 5/02 - Cleaning by the force of jets, e.g. blowing-out cavities
60.
Packaging substrate and semiconductor device comprising the same
Disclosed are a packaging substrate comprising a glass substrate comprising a first surface and a second surface which is the opposite surface of the first surface; a cavity unit forming a space inside the glass substrate; a cavity frame dividing the space into plural districts; and a cavity element comprised in at least some of the cavity unit, wherein the cavity frame comprises plural frame through holes penetrating in a direction from the one side to the other side.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
61.
Packaging substrate having element group in cavity unit and semiconductor device comprising the same
An embodiment relates to a packaging substrate and a semiconductor device. The semiconductor device includes an element unit having a semiconductor element and a packaging substrate electrically connected to the element unit. A glass substrate is applied as a core of the packaging substrate to improve electrical performance, such as signal transmission rate, by reducing the connection distance between the semiconductor element and a motherboard. The structure enables shorter signal transmission paths, suppresses the generation of parasitic elements, and simplifies processing of the insulating layer. As a result, the packaging substrate is suitable for high-speed circuit applications.
A manufacturing method for a cleaned packaging substrate is provided. The method is applied to a manufacturing process for a glass substrate or a packaging substrate comprising the same, and comprises a preparing process of disposing a target substrate inside a chamber; and a removing process of jetting ionized air on at least one surface of the target substrate to separate particle impurities, and manufacturing a cleaned packaging substrate. The target substrate is a glass packaging substrate, or a packaging substrate, and the packaging substrate comprises the glass packaging substrate and a redistribution layer disposed on at least one surface of the glass packaging substrate.
A connection structure of vias is provided. The connection structure includes multiple vias which are disposed within an insulting layer to connect electrical signals in upward and downward directions, the multiple vias comprise a first via and a second via disposed in a vertically stacked relationship with each other, the first via and the second via are configured to meet at a same surface, and the second via and the first via are disposed in respectively different numbers.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A packaging substrate is provided. The packaging substrate includes a first area without a cavity and a second area with a cavity. The first area has first and second surfaces facing each other, and a cavity structure of the second area includes a cavity space; a contact surface; and a side wall. The contact surface is disposed opposite to the opening of the cavity structure. A value of a surface roughness of the contact surface is approximately three times a value of a surface roughness of the first surface of the first area.
H01L 23/055 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body the leads having a passage through the base
H01L 23/04 - ContainersSeals characterised by the shape
H01L 23/08 - ContainersSeals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
65.
SUBSTRATE CARRIER AND SUBSTRATE ASSEMBLY COMPRISING THE SAME
A substrate carrier and a substrate assembly comprising the same are provided. The substrate carrier comprises an accommodation space; a guide unit disposed adjacent to the accommodation space; and a supporting unit disposed under the accommodation space and the guide unit. The guide unit comprises a circular shape or an arc shape in the circumference when viewed from an upper position.
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
B65G 49/07 - Conveying systems characterised by their application for specified purposes not otherwise provided for for fragile or damageable materials or articles for semiconductor wafers
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
B65G 49/06 - Conveying systems characterised by their application for specified purposes not otherwise provided for for fragile or damageable materials or articles for fragile sheets, e.g. glass
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
66.
SUBSTRATE AND PACKAGE SUBSTRATE COMPRISING THE SAME
A substrate comprising a glass substrate is provided. The glass substrate includes a first surface, a second surface, and an edge area connecting the first surface and the second surface; a groove part formed toward the inside direction of a glass substrate from a portion of the edge area; and a protecting device formed on the groove part, wherein the groove part penetrates the first surface and the second surface.
B65D 81/02 - Containers, packaging elements, or packages, for contents presenting particular transport or storage problems, or adapted to be used for non-packaging purposes after removal of contents specially adapted to protect contents from mechanical damage
B65D 85/48 - Containers, packaging elements or packages, specially adapted for particular articles or materials for articles particularly sensitive to damage by shock or pressure for glass sheets
B65D 81/05 - Containers, packaging elements, or packages, for contents presenting particular transport or storage problems, or adapted to be used for non-packaging purposes after removal of contents specially adapted to protect contents from mechanical damage maintaining contents at spaced relation from package walls, or from other contents
B65D 85/30 - Containers, packaging elements or packages, specially adapted for particular articles or materials for articles particularly sensitive to damage by shock or pressure
B62B 3/04 - Hand carts having more than one axis carrying transport wheelsSteering devices thereforEquipment therefor involving means for grappling or securing in place objects to be carriedLoad handling equipment
67.
DEVICE PACKAGING SUBSTRATE, MANUFACTURING METHOD, AND DEVICE PACKAGE
An electronic element packaging substrate and manufacturing method are provided. The substrate includes finer wire widths, transmits signals with low resistance, and provides a compact electronic element package. The substrate may be driven with high efficiency even when high frequency power is applied thereto.
Example embodiments provide a package substrate including a lid structure. The package substrate includes a substrate, a semiconductor element arranged on one surface of the substrate, and a lid surrounding at least a portion of the semiconductor element. The lid includes a region extending outwardly beyond the outer periphery of the substrate.
Example embodiments provide a package substrate including a lid structure. The package substrate includes a substrate, a semiconductor element arranged on one surface of the substrate, and a lid surrounding at least a portion of the semiconductor element with an accommodation space for housing the element and a frame surrounding a portion of the accommodation space. The lid includes an inner and outer region. The outer region of the lid extends outwardly beyond the outer periphery of the substrate.
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H01L 23/053 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
H01L 23/08 - ContainersSeals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
C03C 3/087 - Glass compositions containing silica with 40% to 90% silica by weight containing aluminium oxide or an iron compound containing an oxide of a divalent metal containing calcium oxide, e.g. common sheet or container glass
C03C 3/091 - Glass compositions containing silica with 40% to 90% silica by weight containing boron containing aluminium
70.
Packaging substrate having electric power transmitting elements on non-circular core via of core vias and semiconductor device comprising the same
A packaging substrate includes a core layer including a glass substrate with a first surface and a second surface facing each other, and a plurality of core vias. The plurality of core vias penetrating through the glass substrate in a thickness direction, each comprising a circular core via having a circular opening part and a non-circular core via having an aspect ratio of 2 to 25 in the x-y direction of an opening part. One or more electric power transmitting elements are disposed on the non-circular core via.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
71.
PACKAGING SUBSTRATE AND SEMICONDUCTOR DEVICE COMPRISING THE SAME
Disclosed are a packaging substrate comprising a glass substrate comprising a first surface and a second surface which is the opposite surface of the first surface; a cavity unit forming a space inside the glass substrate; a cavity frame dividing the space into plural districts; and a cavity element comprised in at least some of the cavity unit, wherein the cavity frame comprises plural frame through holes penetrating in a direction from the one side to the other side.
H01L 23/053 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
H01L 23/043 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
H01L 23/08 - ContainersSeals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
01 - Chemical and biological materials for industrial, scientific and agricultural use
09 - Scientific and electric apparatus and instruments
21 - HouseHold or kitchen utensils, containers and materials; glassware; porcelain; earthenware
35 - Advertising and business services
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Chemicals for industrial purposes; chemicals for use in metal plating; chemical compositions for metal plating; copper material for glass penetrating electrode (chemicals) for electronic devices; copper material for electronic devices; chemicals for electronic devices; stripper for manufacture of semiconductor packages (delamination agent); electronic metal plating for manufacture of semiconductor packages; developer for manufacture of semiconductor packages (developing solution); photoresist for manufacture of semiconductor packages. Components for electric circuits; semiconductor package; printed circuit board; electronic circuit board; flexible circuit boards; electronic integrated circuits; integrated circuit package; integrated circuit module; 3D integrated circuit; large scale integrated circuits (LSI); electronic memory circuits; circuit boards provided with integrated circuits; semiconductor package and packaging shaped integrated circuit module; glass substrate for semiconductor; daughterboards; digital boards; motherboards; lead frames for semiconductors; memory modules; random access memory (RAM) module. Glass incorporating fine electrical conductors; semi-worked glass; glass incorporating fine electrical conductors [not for building]; Glass substrates incorporating fine electrical conductors [semi-worked glass not for building]; Glass substrates incorporating fine electrical conductors for use in micro-electro-mechanical systems (MEMS) [semi-worked glass not for building]; glass feedthrough for devices [semi-worked glass not for building]. Providing commercial information related to semiconductor packages; providing commercial information related to semiconductor packages through on-line media such as internet; providing commercial information related to substrate using glass incorporating fine electrical conductors; providing commercial information related to substrate using glass incorporating fine electrical conductors through on-line media such as internet; wholesale service of semiconductor packages; retail service of semiconductor packages; intermediary service of semiconductor packages; sales agency services for semiconductor packages; sales arranging of semiconductor packages; purchasing agency services for semiconductor packages; wholesale service of substrate using glass incorporating fine electrical conductors [semi-worked glass not for building]; retail service of substrate using glass incorporating fine electrical conductors [semi-worked glass not for building]. Service for providing finished products comprising customised semiconductors, semiconductor chips and integrated circuits; custom assembling service of circuit substrates and semiconductors; processing service of semiconductor equipment and components; processing of semiconductors; processing of semiconductor treatment; custom manufacture and assembling related to semiconductor components and integrated circuit; processing of semiconductor elements; processing of semiconductor etching; processing of components for manufacture of semiconductor. Designing of mechanic apparatus for manufacturing semiconductor; developing of fine pitch solder bumping technology; providing of semiconductor wafer bumping technology; providing of semiconductor packaging technology; consultancy related to integrated circuits; designing of semiconductors or integrated circuits; designing of semiconductors; designing of integrated circuits; research in the field of semiconductor design; research/design and testing related to semiconductor development; research related to semiconductors; consultancy related to semiconductor technology; consultancy related to semiconductor design; research in the field of semiconductor manufacture; service of designing integrated circuits; designing of electronic circuit substrates.
73.
Packaging substrate, and semiconductor device comprising same
The embodiment relates to a packaging substrate and a semiconductor device, including an element unit including a semiconductor element; and a packaging substrate electrically connected to the element unit; and it applies a glass substrate as a core of the packaging substrate, thereby can significantly improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a motherboard to be closer to each other so that electrical signals are transmitted through as short a path as possible. Therefore, it can significantly improve electrical properties such a signal transmission rate, substantially prevent generating of parasitic element, and simplify a process of treatment for an insulating layer, and thus provides a packaging substrate applicable to a high-speed circuit.
An embodiment relates to a packaging substrate and a semiconductor device, the semiconductor device comprising: an element unit including a semiconductor element; and a packaging substrate electrically connected to the element unit, wherein a glass substrate is used as the core of the packaging substrate so as to achieve a closer connection between the semiconductor element and a motherboard, thereby allowing an electrical signal to be transmitted over as short a distance as possible. Accordingly, provided is a packaging substrate which can significantly improve electrical characteristics such as signal transmission speed, can substantially prevent the occurrence of a parasitic element and thus more simplify the insulation layer treatment process, and can be applied to a high-speed circuit.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
An embodiment relates to a loading cassette and a target substrate loading method to which same is applied. The loading cassette according to the embodiment comprises: an upper plate; a lower plate facing the upper plate while having a space therebetween; an edge support part for connecting the upper plate to the lower plate and supporting the left and right edges of a target substrate; and a rear surface support part for connecting the upper plate to the lower plate and supporting the center and the rear surface-edge of the target substrate.
B65D 85/48 - Containers, packaging elements or packages, specially adapted for particular articles or materials for articles particularly sensitive to damage by shock or pressure for glass sheets
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
76.
Packaging substrate with core layer and cavity structure and semiconductor device comprising the same
A packaging substrate and a semiconductor device comprising a semiconductor element, include a core layer and an upper layer disposed on the core layer, and the core layer includes a glass substrate as a core of the packaging substrate to improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a mother board to be closer to each other so that electrical signals are transmitted through as short a path as possible.
A packaging glass substrate for semiconductor includes a glass substrate with a first surface and a second surface facing each other, and a plurality of core vias penetrating through the glass substrate in a thickness direction, wherein a plain line is a line linking places where the core vias are not formed, a via line is a line linking places where the core vias are formed, a stress difference value (P) is a value according to Equation (1), and the stress difference value (P) is 1.5 MPa or less, Equation (1): P=Vp−Np where P is a stress difference value measured at the same glass substrate, Vp is a difference between the maximum value and the minimum value of stress measured at the via line, and Np is a difference between the maximum value and the minimum value of stress measured at the plain line.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
80.
Packaging substrate having electric power transmitting elements on non-circular core via of core vias and semiconductor device comprising the same
A packaging substrate includes a core layer including a glass substrate with a first surface and a second surface facing each other, and a plurality of core vias. The plurality of core vias penetrating through the glass substrate in a thickness direction, each comprising a circular core via having a circular opening part and a non-circular core via having a 1.2 or more aspect ratio in the x-y direction of an opening part. One or more electric power transmitting elements are disposed on the non-circular core via.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
81.
Packaging substrate and semiconductor apparatus comprising same
A semiconductor apparatus includes a semiconductor element unit comprising one or more semiconductor elements, a packaging substrate, and a motherboard. The packaging substrate, connected to the semiconductor elements, includes a core layer and an upper layer disposed on the core layer. The core layer includes a glass substrate, a core via, and a core distribution layer. The glass substrate having a first surface and a second surface facing each other. A part of the core distribution layer connects electrically conductive layers of the first surface and an electrically conductive layer of the second surface through the core via penetrating through the glass substrate. A thickness of a thinner one among electrically conductive layers of the core distribution layer is the same as or greater than a width of a thinner one among the electrically conductive layers of the upper layer.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
82.
Semiconductor device having a glass substrate core layer
Disclosed are a packaging substrate and a semiconductor device. The semiconductor device includes an element unit including a semiconductor element and a packaging substrate electrically connected to the element unit. By applying a glass substrate to the packaging substrate as a core substrate, connecting the semiconductor element and a motherboard can be closer to each other, so that electrical signals are transferred through as short a path, and significantly improved electrical properties such as a signal transfer rate could be achieved. Also, it is possible to prevent an occurrence of a parasitic element effect and to apply to a high-speed circuit device without additional insulating process.
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
