The present invention relates to a method of manufacturing a backside illumination (BSI) CMOS optical sensor and more specifically to a method of reducing the cross talk and enhance the photon detection efficiency (PDE) in a backside illumination (BSI) CMOS optical sensor. In particular the claimed method comprises the step of creating an isolation structure between the adjacent sensing elements of the pixel-array of said BSI CMOS optical sensor, so as to isolate all the adjacent sensing elements from each other, and the step of creating a common voltage backside applying structure to all the sensing elements of said pixel-array, so as to connect all the sensing elements to a common voltage bias.
An integrated Hall sensor is provided with: a main wafer (10) of semiconductor material having a substrate (101) with a first surface (101a) and a second surface (101b), opposite to the first surface (101a) along a vertical axis (y); Hall sensor terminals (1, 2, 3, 4; 1′, 2′, 3′, 4′) arranged at least one of the first and second surfaces (101a, 101b) of the substrate (101); an isolation structure (109) in the substrate (101) defining a Hall sensor plate (103) of the integrated Hall sensor, the Hall sensor terminals being arranged in the isolation structure (109). The integrated Hall sensor moreover has a test or calibration coil integrated in the wafer (10), having a plurality of windings formed, at least in part, by metal portions (130b, 170b; 130a, 170a) arranged above the first and second surfaces (101a, 101b) of the substrate (101) and defining an inner volume (1001) entirely enclosing the Hall sensor plate (103).
H01L 43/04 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details of Hall-effect devices
H01L 43/14 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof for Hall-effect devices
A Hall integrated circuit including a vertical Hall element, having a first wafer and a second wafer, the second wafer including a CMOS substrate integrating a CMOS processing circuit coupled to the vertical Hall element and a stack of dielectric layers, and the first wafer including a Hall-sensor layer having a first surface and a second surface, the first and second wafers being bonded with the interposition of a dielectric layer arranged above the first surface of the Hall-sensor layer. The vertical Hall element has: at least a first Hall terminal; at least a second Hall terminal; a deep trench isolation ring extending through the Hall-sensor layer from the first surface to the second surface and enclosing and isolating a Hall sensor region of the Hall-sensor layer; and a first and a second conductive structures electrically connected to respective contact pads embedded in the stack of the second wafer.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A semiconductor vertical Schottky diode device, having: a substrate of semiconductor material, with a front surface and a back surface; a lightly doped region formed in a surface portion of the substrate facing the front surface, having a first conductivity type; a first electrode formed on the lightly doped region on the front surface of the substrate, to establish a Schottky contact; a highly doped region at the back surface of the substrate, in contact with the lightly doped region and having the first conductivity type; and a second electrode electrically in contact with the highly doped region, on the back surface of the substrate, to establish an Ohmic contact.
After finishing of the front side CMOS manufacturing process, the silicon wafer is permanently bonded with its front side onto a carrier wafer. The carrier wafer is a high resistivity silicon wafer or a wafer of a dielectric or of a ceramic material. The silicon substrate of the device wafer is thinned from the back side such that the remaining silicon thickness is only a few micrometers. In the area dedicated to a spiral inductor, the substrate material is entirely removed by a masked etching process and the resulting gap is filled with a dielectric material. A spiral inductor coil is formed on the backside of the wafer on top of the dielectric material. The inductor coil is connected to the CMOS circuits on the front side by through-silicon vias.
b) layers. UV conversion regions (10) are arranged above a number of first photodetector active areas (4) to convert UV light radiation into visible light radiation towards the first photodetector active areas (4), so that the first photodetector active areas (4) are designed to detect UV light radiation. In particular, the first photodetector active areas (4) are alternated to a number of second photodetector active areas (4), designed to detect visible light radiation, in an array (15) of photodetection units (16) of the optical sensor (1), defining a single image detection area (15′), sensitive to both UV and visible light radiation with a same spatial resolution.
The present invention relates to a method of manufacturing a backside illumination (BSI) CMOS optical sensor and more specifically to a method of reducing the cross talk and enhance the photon detection efficiency (PDE) in a backside illumination (BSI) CMOS optical sensor. In particular the claimed method comprises the step of creating an isolation structure between the adjacent sensing elements of the pixel-array of said BSI CMOS optical sensor, so as to isolate all the adjacent sensing elements from each other, and the step of creating a common voltage backside applying structure to all the sensing elements of said pixel-array, so as to connect all the sensing elements to a common voltage bias.
An integrated Hall sensor is provided with: a main wafer (10) of semiconductor material having a substrate (101) with a first surface (101a) and a second surface (101b), opposite to the first surface (101a) along a vertical axis (y); Hall sensor terminals (1, 2, 3, 4; 1', 2', 3', 4') arranged at at least one of the first and second surfaces (101a, 101b) of the substrate (101); an isolation structure (109) in the substrate (101) defining a Hall sensor plate (103) of the integrated Hall sensor, the Hall sensor terminals being arranged in the isolation structure (109). The integrated Hall sensor moreover has a test or calibration coil integrated in the wafer (10), having a plurality of windings formed, at least in part, by metal portions (130b, 170b; 130a, 170a) arranged above the first and second surfaces (101a, 101b) of the substrate (101) and defining an inner volume (1001) entirely enclosing the Hall sensor plate (103).
ISTITUTO NAZIONALE DI FISICA NUCLEARE (INFN) (Italy)
LFOUNDRY SRL (Italy)
ISTITUTO NAZIONALE DI FISICA NUCLEARE (INFN) (Italy)
Inventor
Rivetti, Angelo
Pancheri, Lucio
Giubilato, Piero
Da Rocha Rolo, Manuel Dionisio
Margutti, Giovanni
Di Cola, Onorato
Abstract
This disclosure provides a semiconductor sensor of ionizing radiation and/or ionizing particles with a backside bias electrode and a backside junction for completely depleting the semiconductor substrate up to carrier collection regions each connected to a respective collection electrode of carriers generated by ionization in the substrate. Differently from prior sensors, the sensor of this disclosure has an intermediate semiconductor layer formed upon the substrate, having a greater doping concentration than the doping concentration of the substrate and a doping of a same type. In this intermediate layer, buried doped regions of opposite type one separated from the other are formed for shielding superficial regions in which readout circuits are defined.
H01L 31/115 - Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation
H01L 31/117 - Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation of the bulk effect radiation detector type, e.g. Ge-Li compensated PIN gamma-ray detectors
H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
A method to perform hybrid bonding of two semiconductor wafers without using a dedicated tool for thermo-compression is disclosed. According to the herein disclosed technique, the semiconductor wafers to be bonded together may be placed in an oven simply staying one upon the other without applying any additional compression between them besides their own weight. This outstanding result has been attained using of a particular type of thermosetting materials, namely siloxane polymers of the type that shrink when cured. Among these siloxane polymers, the siloxane polymers of the type SC-480, siloxane polymers of the series SC-200, SC-300, SC-400, SC-500, SC-700, SC-800 and mixtures thereof are particularly suitable.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
11.
HALL INTEGRATED CIRCUIT AND CORRESPONDING METHOD OF MANUFACTURING OF A HALL INTEGRATED CIRCUIT USING WAFER STACKING
A Hall integrated circuit including a vertical Hall element (100), having a first wafer (10) and a second wafer (20) stacked in a vertical direction (z), the second wafer (20) including a CMOS substrate (201) integrating a CMOS processing circuit coupled to the vertical Hall element (100) and a stack (204) of dielectric layers arranged on the CMOS substrate (201), and the first wafer (10) including a Hall-sensor layer (102) having a first surface (10b) and a second surface (10d) opposed along the vertical direction (z) and extending in a horizontal plane (xy), orthogonal to the vertical direction (z), the first and second wafers (10, 20) being bonded with the interposition of a dielectric layer (105) arranged above the first surface (10b) of the Hall-sensor layer (102). The vertical Hall element (100) has: at least a first Hall terminal (1), being a first doped region arranged at the first surface (10b) of the Hall-sensor layer (102); at least a second Hall terminal (4), being a second doped region arranged at the second surface (10d) of the Hall-sensor layer (102) aligned to the first doped region along the vertical direction (z) and separated therefrom by the thickness of the Hall-sensor layer (102); a deep trench isolation ring (107) extending through the Hall-sensor layer (102) from the first surface (10b) to the second surface (10d) and enclosing and isolating a Hall sensor region of the Hall-sensor layer (102), wherein the first and second Hall terminals (1, 4) are arranged; and a first and a second conductive structures (111, 114) coupled to the first, respectively, the second Hall terminal (1, 4) and electrically connected to respective contact pads (221, 224) embedded in the stack (204) of the second wafer (20).
H01L 43/14 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof for Hall-effect devices
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
Method for the alignment of photolithographic masks and corresponding process for manufacturing integrated circuits in a wafer of semiconductor material
A semiconductor vertical Schottky diode device (300; 400; 500; 600; 700), having: a substrate (101) of semiconductor material, with a front surface (101a) and a back surface (101b'); a lightly doped region (102) formed in a surface portion of the substrate (101) facing the front surface (101a), having a first conductivity type; a first electrode (111) formed on the lightly doped region (102) on the front surface (101a) of the substrate (101), to establish a Schottky contact; a highly doped region (140) at the back surface (101b') of the substrate (101), in contact with the lightly doped region (102) and having the first conductivity type; and a second electrode (160a) electrically in contact with the highly doped region (140), on the back surface (101b') of the substrate (101), to establish an Ohmic contact.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 21/329 - Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors the devices comprising one or two electrodes, e.g. diodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
14.
METHOD OF FABRICATION OF AN INTEGRATED SPIRAL INDUCTOR HAVING LOW SUBSTRATE LOSS
After finishing of the front side CMOS manufacturing process, the silicon wafer is permanently bonded with its front side onto a carrier wafer. The carrier wafer is a high resistivity silicon wafer or a wafer of a dielectric or of a ceramic material. The silicon substrate of the device wafer is thinned from the back side such that the remaining silicon0thickness is only a few micrometers. In the area dedicated to a spiral inductor, the substrate material is entirely removed by a masked etching process and the resulting gap is filled with a dielectric material. A spiral inductor coil is formed on the backside of the wafer on top of the dielectric material. The inductor coil is connected to the CMOS circuits on the front side by through-silicon vias.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 27/13 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
15.
VERTICAL HALL ELEMENTS HAVING REDUCED OFFSET AND METHOD OF MANUFACTURING THEREOF
Vertical Hall elements are disclosed which comprise a substrate (101) of a first conductivity type having a first surface (101a) and a second surface (101b), a well (102) of a second conductivity type disposed in and exposed on both surfaces of the substrate, and at least four terminals, preferably comprising highly doped regions of the second conductivity type, in contact with the well. At least two terminals (1, 2) are arranged on the first surface, and at least two terminals (3, 4) are arranged on the second surface such that one terminal (1) on the first surface and one terminal (4) on the second surface have the same but opposite location in a cross-section orthogonal to the substrate surfaces. Alternatively, an element comprises one central pair of opposite surface terminals, whereas the other two terminals comprise lateral buried doped regions (151a, 151c) connecting to the first surface.
H01L 43/14 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof for Hall-effect devices
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
16.
SEMICONDUCTOR OPTICAL SENSOR FOR VISIBLE AND ULTRAVIOLET LIGHT DETECTION AND CORRESPONDING MANUFACTURING PROCESS
A semiconductor optical sensor (1) is provided with: a substrate (2) integrating a plurality of photodetector active areas (4); and a CMOS layer stack (6) arranged on the substrate (2) and including a number of dielectric (6a) and conductive (6b) layers. UV conversion regions (10) are arranged above a number of first photodetector active areas (4) to convert UV light radiation into visible light radiation towards the first photodetector active areas (4), so that the first photodetector active areas (4) are designed to detect UV light radiation. In particular, the first photodetector active areas (4) are alternated to a number of second photodetector active areas (4), designed to detect visible light radiation, in an array (15) of photodetection units (16) of the optical sensor (1), defining a single image detection area (15'), sensitive to both UV and visible light radiation with a same spatial resolution.
This disclosure provides a semiconductor sensor of ionizing radiation and/or ionizing particles with a backside bias electrode and a backside junction for completely depleting the semiconductor substrate up to carrier collection regions each connected to a respective collection electrode of carriers generated by ionization in the substrate. Differently from prior sensors, the sensor of this disclosure has an intermediate semiconductor layer formed upon the substrate, having a greater doping concentration than the doping concentration of the substrate and a doping of a same type. In this intermediate layer, buried doped regions of opposite type one separated from the other are formed for shielding superficial regions in which readout circuits are defined.
H01L 31/117 - Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation of the bulk effect radiation detector type, e.g. Ge-Li compensated PIN gamma-ray detectors
18.
Method for manufacturing improved NIR CMOS sensors
A method for manufacturing a CMOS image sensor for near infrared detection. The method includes: a) providing a silicon wafer; b) performing a germanium implantation in a portion of a front side of the silicon wafer; c) performing an annealing so as to cause thermal diffusion of implanted germanium species, thereby forming silicon-germanium alloy lattice in a first silicon-germanium region exposed on the front side of the silicon wafer; d) carrying out the steps b) and c) one or more times; and e) forming first photodetector active areas in portions of the first silicon-germanium region downwards extending from the front side of the silicon wafer, wherein said first photodetector active areas are sensitive to both near infrared and visible radiations. The first photodetector active areas are formed also in portions of the silicon wafer extending below said portions of the first silicon-germanium region.
METHOD FOR THE ALIGNMENT OF PHOTOLITHOGRAPHIC MASKS AND CORRESPONDING PROCESS FOR MANUFACTURING INTEGRATED CIRCUITS IN A WAFER OF SEMICONDUCTOR MATERIAL
A photomask alignment method for a manufacturing process of an integrated circuit in a semiconductor material wafer (20), the method envisaging: at a first level, defining, by means of a single photolithography process, at least one alignment structure (10; 10') on the wafer (20), the alignment structure (10; 10') having at least a first (4a) and a second (4b) reference mark; and, at an upper level, higher than the first one, aligning a first field mask (11a) relative to the at least one first reference mark (4a); and aligning a second field mask (11b), which is used, together with the first field mask (11a), for the photolithography formation of the integrated circuit inside a respective die (22) in the wafer (20), relative to the at least one second reference mark (4b), so that the first and second field masks (11a, 11b) are arranged on the wafer (20) adjacent to one another in a first coupling direction, without any mutual overlapping.
A method to perform hybrid bonding of two semiconductor wafers without using a dedicated tool for thermo-compression is disclosed. According to the herein disclosed technique, the semiconductor wafers to be bonded together may be placed in an oven simply staying one upon the other without applying any additional compression between them besides their own weight. This outstanding result has been attained using of a particular type of thermosetting materials, namely siloxane polymers of the type that shrink when cured. Among these siloxane polymers, the siloxane polymers of the type SC-480, siloxane polymers of the series SC-200, SC-300, SC-400, SC-500, SC-700, SC-800 and mixtures thereof are particularly suitable.
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
21.
METHOD FOR MANUFACTURING IMPROVED NIR CMOS SENSORS
The present invention concerns a method (1) for manufacturing a CMOS image sensor (2; 3) for near infrared detection. Said method (1) includes: a) providing a silicon wafer (20); b) performing a germanium implantation in a portion of a front side of the silicon wafer (24); c) performing an annealing so as to cause thermal diffusion of implanted germanium species, thereby forming silicon-germanium alloy lattice in a first silicon-germanium region (27) exposed on the front side of the silicon wafer (24); d) carrying out the steps b) and c) one or more times; and e) forming first photodetector active areas (28) in portions of the first silicon-germanium region (27) downwards extending from the front side of the silicon wafer (24), wherein said first photodetector active areas (28) are sensitive to both near infrared and visible radiations. The method is characterized in that said first photodetector active areas (28) are formed also in portions of the silicon wafer (24) extending below said portions of the first silicon-germanium region (27).
The present invention relates to an optical sensor based on CMOS technology and comprising: a semiconductor substrate (21,31); an array of photocells (2,3), each of which includes a respective photodetector active area (11,12,22,32) that is formed in the semiconductor substrate (21,31) and is exposed on a given planar surface (13) of said semiconductor substrate (21,31), each photocell (2,3) being designed to provide a respective output electrical signal related to incident light impinging on the respective photodetector active area (11,12,22,32); a multilayer structure (23,33), that includes metal and dielectric layers and is formed on the given planar surface (13) of the semiconductor substrate (21,31); and light shielding means (14,15,24,35), that are formed in or on the multilayer structure (23,33) and are made of one or more materials reflecting and/or absorbing incident light impinging on said light shielding means (14,15,24,35); wherein each photodetector active area (11,12,22,32) is associated with a corresponding optical path (26,36) extending through the light shielding means (14,15,24,35) and directed towards said photodetector active area (11,12,22,32) to allow incident light with incident direction falling within a given direction range to reach said photodetector active area (11,12,22,32). The optical sensor is characterized in that: all the photocells (2,3) are connected in parallel to provide an overall output electrical signal related to incident light impinging on all the photodetector active areas (11,12,22,32); and all the optical paths (26,36) are parallel to a given direction thereby causing all the photodetector active areas (11,12,22,32) to be reached by incident light with incident direction parallel to said given direction.
A method of fabricating a semiconductor product including processing of a semiconductor wafer from a front surface including structures disposed in the substrate of the wafer adjacent to the front surface and forming a wiring embedded in a dielectric layer disposed on the front surface. The wafer is mounted to a carrier wafer at its front surface so that material can be removed from the backside of the wafer to thin the wafer. Backside processing of the wafer includes forming implantations from the backside, forming deep trenches to isolate the structures from other structures within the wafer, forming a through-silicon via to contact features on the frontside of the wafer, and forming a body contact. Several devices can be generated within the same wafer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
09 - Scientific and electric apparatus and instruments
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Electronic components; semi-conductors; elements for the
construction of semi-conductors; electrical circuits;
integrated circuit chips; semi-conductors chips;
microprocessors. Processing and assembling of electronic components,
semi-conductors, electrical circuits. Research and development services of new products for
semiconductors technology; technological consultancy in
relation to the production of semiconductors and electrical
circuits.
25.
CMOS PROCESS FOR MANUFACTURING AN INTEGRATED GAS SENSOR AND CORRESPONDING CMOS INTEGRATED GAS SENSOR
A CMOS process for manufacturing an integrated gas sensor (35) with fully CMOS-compatible process steps, envisages: providing a supporting layer assembly (11) having semiconductor material and a top surface (11a); forming a first (13a) and a second (13b) electrode portions above the top surface (11a) of the supporting layer assembly (11); forming a dielectric layer (16) covering the first (13a) and second (13b) electrode portions; forming a first (18a) and a second (18b) contact vias, through the dielectric layer (16), reaching the first (13a) and, respectively, second (13b) electrode portion; and forming a gas sensing element (20) on the dielectric layer (16), having a first (20a) and a second (20b) end portions in contact with the first (18a) and, respectively, second (18b) contact vias.
G01N 27/12 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon reaction with a fluid
G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
26.
RECTIFIER FOR A THZ BAND RADIATION SENSOR, IN PARTICULAR FOR IMAGING, AND CHARGE COLLECTING SYSTEM COMPRISING SAID RECTIFIER
UNIVERSITA' DEGLI STUDI DI ROMA "LA SAPIENZA" (Italy)
LFOUNDRY S.R.L. (Italy)
Inventor
Palma, Fabrizio
Del Monte, Andrea
Abstract
The present invention relates to a rectifier for a sensor of electromagnetic signal, said electromagnetic signal having a frequency between 300Ghz and 10THz. Said rectifier comprising: - a semiconductor substrate (1 ) doped p/n comprising a electrons/holes gathering well (2) for gathering electrons/holes; said electrons/holes gathering well (2) being arranged inside said semiconductor substrate (1 ) and comprising at least a first zone doped n/p (21 ); said first zone doped n/p (21 ) having an end surface (21 A); - a metal end surface (41 ) of an antenna (4), said antenna being capable of receiving and concentrating said electromagnetic signal; - a layer doped p/n (3) having a first surface (31) and a second surface (32), opposite to said first surface (31 ). In particular, a first portion of said first surface (31) of said layer doped p/n (3) is in contact with said end surface (21 A) of said first zone doped n/p (21 ) of the electrons/holes gathering well (2), so as to form a first metallurgical junction (G1 ), and a first portion of said second surface (32) of said layer doped p/n (3) is in contact with said metal end surface (41 ), so as to form a second metallurgical junction (G2). The concentration of the doping of said layer doped p/n (3) and the concentration of the doping of said first zone doped n/p (21) of said electrons/holes gathering well (2) are such that said first metallurgical junction (G1) has a first potential barrier (VZ1) inside and the work function of the metal of said metal end surface (41 ) is selected such that it is equal to that of a semiconductor doped n/p and such that said second metallurgical junction (G2) has a second potential barrier (Vzz) inside. Said first metallurgical junction (G1 ) and said second metallurgical junction (G2) form a double metallurgical junction n-p-n/p-n-p with a double potential barrier composed of said first potential barrier (Vz1) and said second potential barrier (Vz2), where said double metallurgical junction n-p-n/p-n-p comprises a first depletion zone (Z1 ), and a second depletion zone (Z2), in contact with said first depletion zone (Z1 ) along a line of contact (A), disposed within said layer doped p/n (3), said first depletion zone (Z1 ) having a thickness greater than the thickness of the second depletion zone (Z2); said first potential barrier (Vzi) being associated with said first depletion zone (Z 1 ), and said second potential barrier (Vz2) being associated with said second depletion zone (Z2). Said layer doped p/n (3) is dimensioned in such a way that said double potential barrier has a value such as to allow said layer doped p/n (3) being completely deprived of holes/electrons, so that, when a variable electric field is induced by said electromagnetic signal received by said antenna (4), said double metallurgical junction n-p-n/p-n-p is subjected to said variable electric field, and a first potential difference (AV^) and a second potential difference (AVZ2) are generated, through the first depletion zone (Z1 ) and through the second depletion zone (Z2) respectively, where each potential difference (ΔVzi, ΔVz2) is proportional to the thickness of the respective depletion zone (Z1, Z2) and is added algebraically to the respective potential barrier (Vz1, Vz2). The present invention relates also to a charge gathering system comprising said rectifier.
A method of fabricating a semiconductor product includes the processing of a semiconductor wafer(10)from a front surface including structures disposed in the substrate (100) of the wafer adjacent to the front surface and the forming of at least one wiring (110) embedded in a dielectric layer (111) disposed on the front surface of the wafer. The semiconductor wafer is mounted to a carrier wafer (120) at its front surface so that material can be removed from the backside of the wafer to thin the semiconductor wafer. Backside processing of the semiconductor wafer includes the forming of implantations from the backside of the wafer, the forming of deep trenches (132a, 132b) to isolate the structures from other structures within the wafer, the forming of a through silicon via (134) to contact features on the front side of the wafer and the forming of a body contact (131). Several devices can be generated within the same wafer.
An integrated gas sensor (1) having a tungsten/tungsten oxide gas sensing element (21), is provided with: a substrate (2) of semiconductor material; and a structure of interconnection layers (8), arranged above the substrate (2) and made of a number of stacked conductive layers (9, 10, 11) and dielectric layers (13). The gas sensing element (21) is integrated within the structure of interconnection layers (8) and at least one electrode (22a, 22b) is provided within the structure of interconnection layers (8), electrically connected to the gas sensing element (21), designed to provide an electric current (lox) to the gas sensing element (21) in order to cause heating thereof.
G01N 27/12 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon reaction with a fluid
