A non-volatile memory structure includes a semiconductor substrate and first and second memory devices on the semiconductor substrate. Each of the first and second memory devices includes a floating gate, a tunnelling insulator under the floating gate, an isolation layer over the floating gate, and at least one of a select gate and a control gate over the isolation layer. The non-volatile memory structure further includes an erase gate shared by the first and second memory devices, a source region under the erase gate, and a shallow trench isolation structure between the erase gate and the source region. The shallow trench isolation structure increases the number of write/erase cycles that can be performed by the non-volatile memory structure.
According to various embodiments, there may be provided an interposer. The interposer including: a substrate; a dielectric layer disposed on the substrate; a via disposed entirely within the dielectric layer; a resistive film layer disposed to line the via; a metal interconnect disposed in the resistive layer lined via; and a plurality of metal lines disposed in the dielectric layer, the plurality of metal lines including a first metal line connected to the metal interconnect, a second metal line connected to the resistive film layer at a first point, and a third metal line connected to the resistive film layer at a second point.
A semiconductor device includes an insulating layer, a first semiconductor layer over the insulating layer, a diffusion break structure between a first active region and a second active region and including a first insulating pattern over the insulating layer and an opening over the first insulating pattern, and a conductive gate material over the opening.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
The present disclosure relates to semiconductor structures and, more particularly, to silicon controlled rectifiers and methods of manufacture. The structure includes: a plurality of wells of a first conductivity type; a well of a second conductivity type which is different than the first conductivity type; an intrinsic semiconductor region between the well and the plurality of wells; and contacts within the plurality of wells.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A temperature-adaptive gate driver for a GaN switch includes a gate-to-source voltage adjustment unit and a driver for outputting an on-state gate-to-source voltage to a gate terminal of the switch. The on-state gate-to-source voltage is adjusted based, in part, on temperature of the switch. The amount of adjustment of the on-state gate-to-source voltage with rise in temperature is based, in part, on high-temperature gate-bias reliability data of the switch and is chosen for a favorable trade-off between performance and life-time. The gate-to-source voltage adjustment unit includes a temperature sense element for sensing temperature of the switch and outputs to the driver an output signal based, in part, on temperature. The gate-to-source voltage adjustment unit includes a regulator for receiving a feedback signal based in part, on resistance of the temperature sense element, and for causing a value of the output signal to be responsive to a value of the feedback signal.
The disclosure provides bipolar transistor structures with a cavity below an extrinsic base, and methods to form the same. A structure of the disclosure provides a bipolar transistor structure including an extrinsic base protruding from an intrinsic base of a bipolar transistor. The extrinsic base extends over a cavity. An insulator is horizontally adjacent the cavity and below a portion of the extrinsic base. A collector extension region of the bipolar transistor structure extends laterally below the insulator and the cavity.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Disclosed is a fully depleted semiconductor-on-insulator structure including a buried Nwell in a substrate below P-type and N-type well regions, an insulator layer on the substrate, and mixed threshold voltage transistors on the insulator layer above at least one of the well regions. An Nwell can be connected to receive a positive bias voltage with any NFET and any PFET above being a FBB LVT/SLVT NFET and a RBB RVT/HVT PFET, respectively. A Pwell can be connected to receive another positive bias voltage less than the positive bias voltage on the Nwell with any NFET and any PFET above being a FBB RVT/HVT NFET and a RBB LVT/SLVT PFET, respectively. Additionally, or alternatively, a Pwell can be connected to receive a negative bias voltage with any NFET and any PFET above being a RBB RVT/HVT NFET and a FBB LVT/SLVT PFET, respectively.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a semiconductor substrate; at least one insulator film over the semiconductor substrate, the at least one insulator film including a recess; and a field plate extending into the at least one recess and over the at least one insulator film.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Structures including multiple magnetic-tunnel-junction layer stacks and methods of forming such structures. The structure comprises a first magnetic-tunneling-junction layer stack, a second magnetic-tunneling-junction layer stack connected in a series connection to the first magnetic-tunneling-junction layer stack, and a pulsed power supply connected to the first and second magnetic-tunneling-junction layer stacks.
Structures including an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate having a top surface, an electrostatic discharge protection device including a base in the semiconductor substrate, and first and second trench isolation regions disposed in the base of the electrostatic discharge protection device. The first trench isolation region extends from the top surface of the semiconductor substrate to a first depth in the base, the second trench isolation region extends from the top surface of the semiconductor substrate to a second depth in the base, and the second depth greater than the first depth.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/082 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
Structures for an optical switch and methods of forming such structures. The structure comprises a first waveguide core including a first portion and a second portion, a second waveguide core including a first portion and a second portion, a ring resonator having a first portion adjacent to the first portion of the first waveguide core and a second portion adjacent to the first portion of the second waveguide core, and an optical coupler coupled to the second portion of first waveguide core and the second portion of the second waveguide core. The first portion of the ring resonator is spaced from the first portion of the first waveguide core by a first gap over a first light coupling region, and the second portion of the ring resonator is spaced from the first portion of the second waveguide core by a second gap over a second light coupling region.
The present disclosure relates to semiconductor structures and, more particularly, to high electron mobility transistors and methods of manufacture. The structure includes: a semiconductor substrate; a gate structure on the semiconductor substrate; a gate metal connecting to the gate structure; and a field plate connected to a source region of the gate structure. The gate metal and the field plate include a same material.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Disclosed are a pixel and a compact memory-in-pixel display (e.g., implemented in a fully-depleted semiconductor-on-insulator processing technology platform). A block of electronic components for a pixel includes a memory cell array, a driving circuit for an LED, and a logic circuit connected between the memory cell array and driving circuit. The memory cell array is above a Pwell, the driving circuit is above an adjacent Nwell, and the logic circuit includes P-type transistors on the Nwell and N-type transistors on the Pwell. A pixel array is above alternating P and N wells with a single buried Nwell below. Specifically, each column of pixels is above adjacent elongated P and N wells and, within each column, adjacent pixels have mirrored layouts. Furthermore, adjacent columns of pixels are above two elongated wells of one type and a shared elongated well of the opposite type therebetween and the adjacent columns have mirrored layouts.
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
A disclosed structure includes a power amplifier and circuitry for implementing a biasing scheme that enables high power operation. The power amplifier includes parallel transistor chains connected to input and output transformers. Each chain includes series-connected first, second, and third n-type field effect transistors (NFETs) having front and back gates. The output transformer receives a variable positive power supply voltage generated using average power tracking. Front and back gates of each third NFET receive a positive bias voltage greater than or equal to the variable positive power supply voltage and a negative bias voltage, respectively. By negative back biasing the third NFETs, threshold voltages thereof are raised so a high positive bias voltage can be applied to the front gates to increase power output without violating reliability specifications. Optionally, by making the negative bias voltage temperature dependent, voltages at source regions of the third NFETs are held constant.
The embodiments herein relate to antifuses capable of forming localized conductive links and methods of forming the same. An antifuse is provided. The antifuse includes a substrate, a dielectric liner, and an electrode. The substrate includes a conductor layer, and a trench is in the conductor layer. The trench includes a first conductor surface and a second conductor surface. The dielectric liner is in the trench. The electrode is on the dielectric liner in the trench, and the electrode includes a first electrode surface and a second electrode surface converging to the first electrode surface.
The disclosure provides a structure including a silicon carbide (SiC) channel horizontally between a source and a drain drift region. The SiC channel has opposite doping from the source and the drain drift region. A capping semiconductor is on the SiC channel and is horizontally between the source and the drain drift region. The capping semiconductor includes a semiconductor having a higher charge carrier mobility than the SiC channel. A gate structure is on the capping semiconductor.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A device includes an antifuse structure. The antifuse structure includes a first contact structure and a second contact structure in a first interlevel dielectric (ILD) layer, an opening arranged between the first contact structure and the second contact structure in the first ILD layer, and a dielectric capping layer lining at least sidewalls of the opening. A second ILD layer is arranged over the first ILD layer and in the opening. The second ILD layer lines the dielectric capping layer on at least the sidewalls of the opening. A third contact structure is arranged between the first contact structure and the second contact structure. The third contact structure includes a first portion in the opening.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
A differential power amplifier circuit, including: a first differential power amplifier including first and second cross-coupled neutralization capacitors; and a second differential power amplifier, coupled in parallel with the first differential power amplifier, including a plurality of multi-gate transistors.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
The present disclosure relates to semiconductor structures and, more particularly, to quantum dot structures and methods of manufacture. The structure includes: a plurality of barrier gates; a plurality of spin qubit gates interdigitated with the plurality of barrier gates; and access gates on opposing sides of the plurality of barrier gates.
Khalifa University of Science and Technology (United Arab Emirates)
Inventor
Rakowski, Michal
Bian, Yusheng
Augur, Roderick A.
Taha, Ayat M.
Papadovasilakis, Marios
Gebregiorgis, Yonas Hadush
Viegas, Jaime
Abstract
Structures for a power splitter that include a multimode interference coupler and methods of forming such structures. The structure comprises a multimode interference coupler including a grating having a plurality of grating lines, an input waveguide core, and an output waveguide core. The grating lines are disposed between the input waveguide core and the output waveguide core. The structure further comprises a resistive heating element adjacent to the grating lines.
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
21.
HIERARCHICAL MEMORY ARCHITECTURE INCLUDING ON-CHIP MULTI-BANK NON-VOLATILE MEMORY WITH LOW LEAKAGE AND LOW LATENCY
A disclosed non-volatile memory (NVM) structure is implemented in a fully depleted semiconductor-on-insulator technology processing platform and includes multiple NVM banks with NVM cells including transistors. NVM banks have well regions in a substrate. Transistors of NVM cells of each NVM bank are on an insulator layer above a corresponding well region for that bank. A bias control circuit causes well regions for NVM banks in a standby state to be biased with a reverse back biasing voltage and causes a well region for an NVM bank in an operational state to be biased with a forward back biasing voltage. The bias control circuit can initiate forward back biasing during a cache data retrieval process (before NVM bank access) to ensure that the corresponding well region of an NVM bank at issue is fully biased when, following the cache data retrieval process, access to the NVM bank is still required.
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
22.
ELECTRO-OPTIC BRIDGE CHIPS FOR CHIP-TO-CHIP COMMUNICATION
Structures including an electro-optic bridge chip and methods of forming such structures. The structure comprises a photonics chip and an electro-optic bridge chip on a package substrate. The electro-optic bridge chip includes a waveguide core and an electrical trace line. A portion of the waveguide core is coupled to an optical coupler of the photonics chip.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: a collector; a base region above the collector; an emitter laterally connecting to the base region; and an extrinsic base connecting to the base region.
H01L 29/201 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds
The present disclosure generally relates to trench isolation structures for semiconductor devices. More particularly, the present disclosure relates to semiconductor devices having trench isolation structures with varying depths for electrically isolating integrated circuit (IC) components in the semiconductor devices. The present disclosure also relates to method of forming the trench isolation structures.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A system and computerized method verify product custody along a product manufacturing chain. The method may include verifying a first machine-readable (MR) code for a product level N is valid by comparing the first MR code to a database of valid MR codes. Where the first MR code for the product level N is verified as valid, a second, valid MR code is generated for a next product level N+1 in the database of valid MR codes. In addition, the first MR code for the product level N in the database of valid MR codes is invalidated, so it cannot be used again. The second MR code is formed for use with the next product level N+1, e.g., by the downstream product manufacturer. Custody of product levels along a manufacturing chain can be verified and secured, avoiding bad actors from inserting and profiting from fake parts into the manufacturing chain.
G06K 7/14 - Methods or arrangements for sensing record carriers by electromagnetic radiation, e.g. optical sensingMethods or arrangements for sensing record carriers by corpuscular radiation using light without selection of wavelength, e.g. sensing reflected white light
26.
PHOTONIC STRUCTURES INCLUDING MULTIPLE INPUT/OUTPUT OPTICAL COUPLERS
Photonic structures including multiple input/output optical couplers and methods of forming such photonic structures. The photonic structure comprises a light source and a photonics chip including a semiconductor substrate. The photonic structure further comprises a first mirror disposed at a first height relative to a top surface of the semiconductor substrate and a second mirror disposed at a second height relative to the top surface of the semiconductor substrate. The first mirror is configured to reflect first light from the light source to the photonics chip, and the second mirror is configured to reflect second light from the light source to the photonics chip. The first mirror is disposed between the second mirror and the light source, and the second height is different from the first height.
A structure according to the disclosure includes a dielectric layer over a substrate and horizontally between a gate terminal and a source/drain (S/D) terminal. The dielectric layer has a first surface proximal to the substrate and a second surface opposite the first surface. The dielectric layer has a plurality of recesses in the second surface. At least some of the plurality of recesses have different depths. A conductive field plate includes a metal layer on the second surface and within the plurality of recesses. The conductive field plate is electrically isolated from the gate terminal and the S/D terminal.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
An assembly is provided. The assembly includes a packaged semiconductor device and an outer enclosure enclosing the packaged semiconductor device. The assembly includes a packaged semiconductor device having a semiconductor chip and an outer enclosure enclosing the packaged semiconductor device. The packaged semiconductor device includes at least four opposing sides. The outer enclosure includes a magnetic material and further includes a lower section embedding the packaged semiconductor device, an upper section over the lower section, and a non-magnetic region arranged between the upper section and the lower section adjacent to the at least four opposing sides of the packaged semiconductor device.
An electrostatic discharge (ESD) protection circuit includes a silicon controlled rectifier. The silicon controlled rectifier includes a first well of a first conductivity type in a substrate, and a first doped region of a second conductivity type and a first tap region of the first conductivity type in the first well. The second conductivity type has an opposite polarity to the first conductivity type. The first doped region is coupled to a first pad. The first tap region is coupled to a second pad through a resistor external to the silicon controlled rectifier.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/87 - Thyristor diodes, e.g. Shockley diodes, break-over diodes
30.
NANOSHEET STRUCTURES WITH BOTTOM SEMICONDUCTOR MATERIAL
The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures with a bottom epitaxial semiconductor material and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets; a plurality of gate structures surrounding individual semiconductor nanosheets of the plurality of semiconductor nanosheets; a first semiconductor material of a first conductivity type at source/drain regions of the plurality of gate structures; and a second semiconductor material of a second conductivity type above the first semiconductor material, the first conductivity type being different than the second conductivity type.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
H03B 5/04 - Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
32.
STRUCTURE WITH GATE OVER NON-ALIGNED SEMICONDUCTOR REGIONS
Embodiments of the disclosure provide a structure and related method for a gate over semiconductor regions that are not aligned. Structures according to the disclosure include a first semiconductor region extending from a first widthwise end to a second widthwise end within a substrate. A second semiconductor region is adjacent the first semiconductor region and extends from a first widthwise end to a second widthwise end within the substrate. The second widthwise end of the second semiconductor region is non-aligned with the second widthwise end of the first semiconductor region. A gate structure is over the substrate and extends widthwise over the first semiconductor region and the second semiconductor region.
Structures for a co-packaged photonics chip and electronic chip, and associated methods. The structure comprises a layer comprising a molding compound, an electronic chip and a photonics chip affixed in the layer, and a waveguiding structure including a waveguide core adjacent to the photonics chip. The photonics chip includes an optical coupler, the waveguide core includes a portion that overlaps with the optical coupler, and the waveguide core comprises a polymer.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
Photonics chip structures including a reflector and methods of forming such structures. The photonics chip structure comprises a first waveguide core, a second waveguide core adjacent to the first waveguide core, and a reflector including a plurality of metal contacts over a portion of the first waveguide core. The second waveguide core is configured to couple light to the first waveguide core, and the metal contacts are configured to reflect the light.
A disclosed flip-flop includes primary and secondary sections connected to switchable and continuous power supplies, respectively. The primary section includes logic outputting first control signals, a primary latch controlled by the first control signals, and a data output device connected to an output terminal of the primary latch. The secondary section includes logic outputting second control signals and a secondary latch. A first transmission gate controlled by the second control signals is connected between the output terminal of the primary latch and an input terminal of the secondary latch. A second transmission gate controlled by the first and second control signals is connected between output and input terminals of the secondary latch. In a normal mode, both sections receive power and the first transmission gate is conductive. In a retention mode, the primary section is powered down, the first transmission gate is non-conductive and the second transmission gate is conductive.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
36.
STATIC RANDOM ACCESS MEMORY (SRAM) CELL WITH VARIABLE TOGGLE THRESHOLD VOLTAGE AND MEMORY CIRCUIT INCLUDING SRAM CELLS
A static random access memory (SRAM) cell includes P-type and N-type transistors having secondary gates. A node connected to all secondary gates receives a write enable signal (WEN). A low WEN forward biases the P-type transistors and increases the toggle threshold voltage (Vtth) of the SRAM cell to avoid data switching during a read. A high WEN forward biases the N-type transistors and decreases Vtth during a write. The SRAM cell can be implemented using a fully depleted semiconductor-on-insulator technology, where the secondary gates include corresponding portions of a well region below. In this case, an array of SRAM cells can be above a single well region. Alternatively, the array can be sectioned into sub-arrays above different well regions and a decoder can output sub-array-specific WENs to the different well regions (e.g., with only one WEN being high at a given time to reduce capacitance).
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises one or more semiconductor layers, a gate on the one or more semiconductor layers, a source/drain region including a first portion in the one or more semiconductor layers and a second portion in the one or more semiconductor layers, and a defect region in the one or more semiconductor layers. The defect region is disposed adjacent to the first portion of the source/drain region.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
Structures including a wide band-gap semiconductor layer stack and methods of forming such structures. The structure comprises a layer stack on a substrate and a first dielectric layer on the layer stack. The layer stack includes semiconductor layers that comprise a wide band-gap semiconductor material. A seal ring includes a trench that penetrates through the first dielectric layer and the layer stack to the substrate, a second dielectric layer that lines the trench, and a conductor layer including first and second portions inside the trench. The trench surrounds portions of the layer stack and the first dielectric layer. The second dielectric layer includes a first portion disposed between the first portion of the conductor layer and the portion of the layer stack, and the second dielectric layer includes a second portion disposed between the second portion of the conductor layer and the portion of the first dielectric layer.
GlobalFoundries Dresden Module One Limited Liability Company & Co. KG (Germany)
Inventor
Kammler, Thorsten Erich
Zier, Manfred Michael
Dhulla, Vinit
Hauser, Julia
Dreiner, Stefan
Ewering, Johannes
Abstract
Embodiments of the disclosure provide a structure with a guard ring between the terminals of a single photon avalanche diode photodetector (SPAD), and related methods. A structure according to the disclosure includes a SPAD with an anode within a doped well and a cathode within the doped well. A guard ring includes a semiconductor material within the doped well. The semiconductor material and the doped well have opposite doping polarities.
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
The present disclosure relates to semiconductor structures and, more particularly, to a transistor with a thermal plug and methods of manufacture. The structure includes: a semiconductor substrate; a gate structure over the semiconductor substrate; a source region on a first side of the gate structure; a drain region on a second side of the gate structure; and a thermal plug extending from a top side of the semiconductor substrate into an active region of the semiconductor substrate.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A photodiode device includes a layer of semiconductor material, a plurality of pixels, each of the pixels including a diode structure on a first side of the layer of semiconductor material and a conductive layer on a second side of the layer of semiconductor material, deep trench isolation (DTI) structures isolating adjacent pixels from one another, a first vertical conductive layer over a first side of each DTI structure, and a second vertical conductive layer over a second side of each DTI structure. The first vertical conductive layer extends from the conductive layer to a first contact on the first side of each DTI structure, and the second vertical conductive layer extends from the conductive layer to a second contact on the second side of each DTI structure.
Disclosed circuit structure embodiments include an enhancement mode transistor and a turn-off slew rate controller for automatically adding drain-source capacitance to the transistors when the transistor is transitioning to an off state. The added drain-source capacitance slows the turn-off slew rate (dV/dt_off) of the transistor without also increasing the turn-off energy loss (E_off). In some embodiments, the slew rate controller includes: sensors connected to the drain region for sensing both the drain voltage and the slew rate, respectively; a logic circuit for generating and outputting an enable signal based on output voltages from the sensors; and a capacitance adder for adding to the drain-source capacitance only when the logic value of the enable signal indicates that the drain voltage is at or above a predetermined positive drain voltage level and the slew rate is positive.
H03K 19/003 - Modifications for increasing the reliability
H03K 17/0412 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
43.
PHOTONICS CHIP PACKAGE STRUCTURES INCLUDING A CONTROLLED UNDERFILL FILLET
Structures for a packaged photonics chip and associated methods. The structure comprises a photonics chip, a packaging substrate, a plurality of electrical connections disposed in a gap between the photonics chip and the packaging substrate, and a fillet comprising an underfill material. The fillet is disposed to overlap with a portion of the photonics chip adjacent to the gap, the fillet has a width dimension and a height dimension transverse to the width dimension, and a ratio of the width dimension to the height dimension is greater than or equal to 1.5.
Structures for a random number generator that include magnetic-tunnel-junction layer stacks and methods of forming such structures. The structure comprises a write line, first and source lines, a first transistor connected by the first source line to a first end of the write line, and a second transistor connected by the second source line to a second end of the write line. The structure further comprises a plurality of magnetic-tunneling-junction layer stacks disposed on the write line between the first and second ends of the write line.
Structures for an insulated-gate bipolar transistor and methods of forming a structure for an insulated-gate bipolar transistor. The structure comprises a semiconductor substrate having a front surface and a back surface opposite from the front surface. The semiconductor substrate comprises a wide bandgap semiconductor material. The structure further comprises a gate electrode at the front surface of the semiconductor substrate, and a diode at the back surface of the semiconductor substrate.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
Structures including a single-photon avalanche diode and methods of forming such structures. The structure comprises a semiconductor substrate including a trench. The trench surrounds a portion of the semiconductor substrate. The structure further comprises a deep trench isolation region that includes a dielectric layer and a semiconductor layer inside the trench. The dielectric layer is disposed between a sidewall of the trench and the semiconductor layer. The structure further comprises an active device that includes a doped region in the semiconductor layer.
H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
H01L 21/763 - Polycrystalline semiconductor regions
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
47.
SEMICONDUCTOR FIN WITH DIVOTS, TRANSISTOR INCLUDING THE SEMICONDUCTOR FIN, MEMORY CELL INCLUDING THE TRANSISTOR, AND ASSOCIATED METHODS
Disclosed semiconductor structures include semiconductor fin(s), each extending from a semiconductor substrate and having opposing sidewalls. Each fin has a lower portion and an upper portion above the lower portion. The lower portion has a base proximal to the semiconductor substrate and divots within the opposing sidewalls at the base. An isolation region is on the semiconductor substrate adjacent to the opposing sidewalls of each fin (e.g., including within the divots). The upper portion of each fin extends above the level of the top surface of the isolation region and can be incorporated into a single-fin or multi-fin fin-type device (e.g., a fin-type field effect transistor (FINFET)). In some embodiments, multiple single-fin and/or multi-fin FINFETs incorporating the upper portions of such fins can be incorporated into a memory cell, such as a static random access memory (SRAM) cell. Also disclosed herein are associated method embodiments.
H10B 10/00 - Static random access memory [SRAM] devices
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
The present disclosure relates to semiconductor structures and, more particularly, to asymmetric junctionless fin field effect transistor (FINFET) structures and methods of manufacture. The structure includes: a nanowire fin comprising a first width adjacent to a source region and a second width adjacent to a drain region, the first width and the second width being different dimensions; and a gate structure over the nanowire fin, the gate structure spanning over the first width and the second width and being between the source region and the drain region.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Structures for a resistive memory element and methods of forming a structure for a resistive memory element. The structure comprises a resistive memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. The first electrode includes a first metal feature and a second metal feature inside the first metal feature. The first metal feature comprising a first metal, and the second metal feature comprises a second metal with a different composition than the first metal. The first metal feature adjoins a first portion of the switching layer, and the second metal feature adjoins a second portion of the switching layer.
Structures including a compound semiconductor layer stack and methods of forming such structures. The structure comprises a device region on a substrate. The device region includes a first section of a layer stack that has a plurality of semiconductor layers, and each semiconductor layer comprises a compound semiconductor material. The structure further comprises an isolation structure disposed about the section of the layer stack, and a device in the device region. The isolation structure penetrates through the layer stack to the substrate.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
51.
Optoelectronic device including photodiode having buried layer with different thicknesses
The present disclosure generally relates to semiconductor devices for use in optoelectronic/photonic applications and integrated circuit (IC) chips. More particularly, the present disclosure relates to devices containing photodiodes such as avalanche photodiodes (APDs) and single photon avalanche diodes (SPADs). The present disclosure may provide a device including a substrate, a first well of a first conductivity type in the substrate, a second well of a second conductivity type in the substrate, and a buried layer of the second conductivity type in the substrate. The buried layer may be below the first well and the second well. The buried layer may have a first section and a second section, in which the first section has a larger thickness than the second section.
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
52.
ELECTRONIC FUSES WITH A SILICIDE LAYER HAVING MULTIPLE THICKNESSES
Structures for an electronic fuse and methods of forming an electronic fuse. The structure includes a first terminal, a second terminal, and a fuse link extending from the first terminal to the second terminal. The structure further includes a silicide layer having a first portion included in the fuse link and a second portion included in the first terminal and the second terminal. The first portion of the silicide layer has a first thickness, the second portion of the silicide layer has a second thickness, and the first thickness is less than the second thickness.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
Disclosed are a structure, including a junction field effect transistor (JFET), and a method of forming the structure. The JFET includes a channel region and source and drain regions above the channel region. The JFET also includes a first gate region below the channel region and a second gate region above the channel region positioned laterally between and isolated from the source and drain regions. The first gate region underlies the drain region and is offset from the source region and at least that portion of the second gate region adjacent to the source region. Specifically, the first gate region is either completely offset from both the source region and the second gate region or is completely offset from the source region and only partially underlies the second gate region. In the JFET, resistance on is reduced and saturation drain current is increased without significantly impacting breakdown or pinch-off voltages.
The disclosed subject matter relates generally to inductor structures integrated in semiconductor devices. More particularly, the present disclosure relates to a semiconductor device having a semiconductor chip, a redistribution layer on the semiconductor chip, and an inductor structure having an upper section in the redistribution layer and a lower section in the semiconductor chip. The upper section and the lower section are concentric about a center region of the inductor structure. The lower section is connected to the upper section.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
55.
SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS
A semiconductor device including a semiconductor substrate. A first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. A CA layer forms a local interconnect layer electrically connected to one of the source and the drain of the first transistor. A CB layer forms a local interconnect layer electrically connected to the gate of one of the first transistor and the second transistor. An end of the CB layer is disposed at a center of the CA layer
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A test tray system for electronics, like photonics integrated circuit (PIC) structures, and a related method are disclosed. The test tray system includes at least one test tray. Each test tray includes a first section exposing a first electrical component to a high temperature, and a second section covered by a thermal protection element configured to prevent a second component from being exposed to the high temperature at the same time that the first electrical component is being exposed to the high temperature. The test tray system allows testing of the first component at a high temperature, e.g., 125° C., while protecting the second component from the high temperatures.
An integrated circuit includes a fin having a height and a width under a gate of a selected fin-type field effect transistor (FinFET) that is less than the height and width along a remainder of the fin including under gates and for source/drain regions of other FinFETs. The IC includes a first FinFET having a first gate over a fin having a first height and a first width under the first gate, and a second FinFET in the fin adjacent to the first FinFET. The second FinFET has a second gate over the fin, and the fin has, under the second gate only, a second height less than the first height and a second width less than the first width. The resulting reduced channel height and width for the second FinFET increases gate control and reduces gate leakage, which is beneficial for ultra-low current leakage (ULL) devices.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes a transistor including a gate and a dielectric layer over the gate. A cavity is in the dielectric layer above the gate and a portion of the cavity over the gate has a negative sloped sidewall in the dielectric layer. The negative sloped sidewall provides a portion of the cavity having a trapezoidal cross-section having a first width at a lower end adjacent the gate and a second width smaller than the first width at an upper end. The negative sloped sidewall thus places a wider portion of the cavity closer to the gate, which decreases gate-contact capacitance.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
Structures for a photonics chip that include a photonic component and methods of forming such structures. The structure may comprise a photodetector on a substrate and a waveguide core. The photodetector includes a light-absorbing layer having a longitudinal axis, a first sidewall, and a second sidewall adjoined to the first sidewall at an interior angle. The first sidewall is slanted relative to the longitudinal axis, and the second sidewall is oriented transverse to the longitudinal axis. The waveguide core includes a tapered section adjacent to the first sidewall and the second sidewall of the light-absorbing layer.
The present disclosure relates to semiconductor structures and, more particularly, to gate-all-around field effect transistors and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding the plurality of semiconductor nanosheets; a conductive material between the plurality of semiconductor nanosheets and the plurality of gate structures; an inner sidewall spacer adjacent to each of the plurality of gate structures and conductive material; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a gate structure; a first field plate on a first side of the gate structure; and a second field plate on a second side of the gate structure, independent from the first field plate.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Structures including an inductor and methods of forming such structures. The structure comprises a semiconductor substrate including a first plurality of sealed cavities and a back-end-of-line stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the scaled cavities.
Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate including a well, a field-effect transistor including a gate, a source having a doped region in the well, and a drain, and a silicon-controlled rectifier including a doped region in the well.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
65.
ISOLATION STRUCTURE HAVING DIFFERENT LINERS ON UPPER AND LOWER PORTIONS
An isolation structure for a substrate is disclosed. The isolation structure includes a lower portion having a first liner, and an upper portion having a second liner vertically over the first liner. A first dielectric material is surrounded by the second liner from above and by the first liner from below and laterally. The second liner may include a second dielectric material in at least part thereof. The second liner prevents exposure of end surfaces of a semiconductor layer of the substrate during subsequent processing, which prevents damage such as thinning, agglomeration and/or oxidation that can negatively affect performance of a transistor formed using the semiconductor layer. The second liner also reduces an overall step height of the isolation structure.
A disclosed structure includes a semiconductor fin on a substrate and an isolation region on the substrate laterally surrounding a lower portion of the fin. A fin-type field effect transistor (FINFET) includes an upper portion of the fin and an isolation structure, and a gate structure are on the isolation region and positioned laterally adjacent to the upper portion of the fin. The gate structure also extends over the top of the fin and abuts the isolation structure. The FINFET also includes an independently biasable supplementary gate structure integrated into the isolation structure. Specifically, an opening extends into the isolation structure adjacent to, but separated from, the fin. The supplementary gate structure includes a conductor layer within the opening and that portion of the isolation structure between the conductor layer and the semiconductor fin. Also disclosed are associated methods.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets; an inner sidewall spacer adjacent each of the plurality of gate structures; and corner spacers under the plurality of stacked semiconductor nanosheets.
Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure comprises a semiconductor layer, a source region, a drain region, and a gate positioned between the source region and the drain region. The gate includes a gate conductor layer, a first gate dielectric layer having a first thickness, and a second gate dielectric layer having a second thickness greater than the first thickness. The first gate dielectric layer is disposed on a top surface of the semiconductor layer, and the second gate dielectric layer includes a first section on the top surface of the semiconductor layer and a second section adjacent to a sidewall of the semiconductor layer. The gate conductor layer has an overlapping relationship with the first gate dielectric layer, the first section of the second gate dielectric layer, and the second section of the second gate dielectric layer.
Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a semiconductor substrate and a layer stack including a first dielectric layer and a second dielectric layer. The first dielectric layer is positioned between the second dielectric layer and the semiconductor substrate. The structure further comprises a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, and a metal gate on the layer stack laterally between the first source/drain region and the second source/drain region. The second dielectric layer is positioned between the metal gate and the first dielectric layer. A contact extends through the layer stack to the first source/drain region.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
The present disclosure relates to semiconductor structures and, more particularly, to a device with a vertical nanowire channel region and methods of manufacture. The structure includes: a bottom source/drain region; a top source/drain region; a gate structure extending between the bottom source/drain region and the top source/drain region; and a vertical nanowire in a channel region of the gate structure.
A disclosed charge pump includes first and second stages and, optionally, additional stage(s). The first stage receives a voltage input (Vin) at a first voltage (V1), CLK1 (GND, V1), and CLK1B (V1, GND), and outputs a first stage voltage output (Vout1) at a second voltage (V2) double V1. A second stage receives Vout1, CLK2 (V1, V2), and CLK2B (V2, V1, and outputs a second stage voltage output (Vout2) at a third voltage (V3) essentially triple V1, and so on. A clock driver supplies CLK1-CLK1B to the first stage and to a clock generator. The clock generator includes: a voltage level shifter, which receives CLK1 and CLK1B and outputs multiple level-shifted voltage output pulses; and a driving circuit, which receives specific ones of the output voltage pulses and outputs CLK2 and CLK2B to the second stage and, if needed, additional voltage level-shifted clock signal-inverted clock signal pairs to any additional stages.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
72.
FEEDBACK CURRENT DEPENDED RAMP GENERATOR FOR SWITCHED MODE POWER SUPPLY
To reduce sub-harmonic oscillations in a Switched-Mode Power Supply (SMPS). a ramp generator circuit of the SMPS produces a ramp signal having an amplitude corresponding to a sensed current through an energy storage device, such as an inductor, of the SMPS. The ramp signal is used to control a duty cycle of the SMPS. The ramp generator circuit may include a reference current circuit, a ramp capacitor, and a discharge circuit to periodically discharge the ramp capacitor. The ramp capacitor may be charged using a charging current produced by combining a feedback current corresponding to the sensed current with a reference current produced by the reference current circuit and may be periodically discharged at a fixed frequency, or may be charged using the reference current and discharged at a time determined according to the feedback current.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Disclosed structures include a single-stage and a multi-stage voltage level shifter. Each structure includes multiple transistors, which are optionally all symmetric low-voltage transistors, and the structures are configured to avoid operation outside the safe operating area (SOA) of such transistors. The single-stage voltage level shifter and the first stage of the multi-stage voltage level shifter can be essentially identical. In operation, input voltage pulses (including an input voltage pulse transitioning between a first positive voltage (V1) equal to the voltage rating of the transistors and ground) can be received at source nodes of N-type transistors and, in response, output voltage pulses (including an intermediate output voltage pulse transitioning between V1 and a second positive voltage (V2) that is higher than (e.g., double) V1 and an output voltage pulse that transitions between ground and V2) can be output.
A disclosed circuit structure includes a voltage level shifter connected to a variable voltage generator for receiving a low supply voltage and to a programmable voltage generator for receiving a high supply voltage that is higher than the low supply voltage. The high supply voltage is programmable to one of multiple different voltage levels. The variable voltage generator tracks the voltage level of the high supply voltage and outputs the low supply voltage based thereon. The high supply voltage is tracked either directly or using the trim bit signal employed by the programmable voltage generator to program the high supply voltage. The low supply voltage is high when the high supply voltage is high to ensure operation within the safe operating area and is low when the high supply voltage drops below some threshold level to ensure operability and, optionally, improve operating speed.
A structure includes a level shifter, first and second variable voltage generators, and a programmable voltage generator. The level shifter includes low and high supply voltage nodes and two parallel branches, including multiple transistors, connected between the nodes. The programmable voltage generator generates and applies a high supply voltage (VH) to the high supply voltage node. VH is programmable to one of multiple possible VH levels. Based on the voltage level of VH, the first variable voltage generator generates and applies a low supply voltage (VL) to the low supply voltage node and the second variable voltage generator generates and applies a gate bias voltage (VGB) to gates of some transistors. By tracking VH and adjusting VL and VGB based on thereon, the voltage level shifter operates within the SOA at high VHs, remains operable at low VHs, and maintains operating speed at mid-level VHs.
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
76.
High-electron-mobility transistors with inactive gate blocks
Structures for a high-electron-mobility transistor and methods of forming such structures. The structure comprises a device structure including a gate and an ohmic contact, and one or more inactive blocks laterally positioned between the gate and the ohmic contact.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
The present disclosure relates to semiconductor structures and, more particularly, to metal-oxide semiconductor transistors and methods of manufacture. The structure includes: a substrate comprising a drift region and a body region; a gate structure between the drift region and the body region; an insulator material over the gate structure, the drift region and the body region; and an air gap within the insulator material and extending into the drift region.
The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked diode-trigger silicon controlled rectifiers and methods of manufacture. The structure includes: a silicon controlled rectifier in a trap rich region of a semiconductor substrate; and at least one diode built in polysilicon (gate material) and isolated by a gate-dielectric.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/763 - Polycrystalline semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming same. The structure comprises a semiconductor substrate including a trench, a source and a drain in the semiconductor substrate, a dielectric layer inside the trench, and a gate in the dielectric layer. The trench has a first sidewall and a second sidewall, the source is adjacent to the first sidewall of the trench, the drain is adjacent to the second sidewall of the trench, and the gate is laterally between the first sidewall of the trench and the second sidewall of the trench. The structure further comprises an air gap in the dielectric layer. The air gap is below the gate, and the air gap is laterally between the first sidewall of the trench and the second sidewall of the trench.
The present disclosure relates to semiconductor structures and, more particularly, to multi-channel transistors and methods of manufacture. The structure includes: a gate structure; a single channel layer in a channel region under the gate structure; a drift region adjacent to the gate structure; and multiple channel layers in the drift region coupled to the single channel layer under the gate structure.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Plasmonic photonic structures that include a layer that exhibits an electric-field-induced Pockels effect and methods of forming such structures. The structure comprises a waveguide core on a substrate, a first layer that has an overlapping relationship with the first waveguide core, and a second layer that has an overlapping relationship with the first waveguide core and the first layer. The first layer comprises a metal, and the second layer comprising a material that exhibits an electric-field-induced Pockels effect.
G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
G02F 1/035 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect in an optical waveguide structure
83.
STRUCTURES FOR AN ELECTROSTATIC DISCHARGE PROTECTION DEVICE
Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises adjacent first and second gates over a semiconductor substrate, a source adjacent to the first gate, and a drain adjacent to the second gate. The source includes a first well in the semiconductor substrate, a second well in the semiconductor substrate, and a doped region. The first well and the doped region have a first conductivity type, and the second well has a second conductivity type opposite from the first conductivity type. The doped region has a first portion that overlaps with the first well, and the doped region has a second portion that overlaps with the second well.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
84.
MULTI-SUBSTRATE COUPLING FOR PHOTONIC INTEGRATED CIRCUITS
Embodiments of the disclosure provide a multi-substrate coupling for photonic integrated circuits (PICs). Structures of the disclosure may include a first substrate having a first surface. The first surface includes a groove therein. A second substrate has a second surface coupled to the first surface. The second substrate includes a cavity substantially aligned with the groove of the first surface, and a photonic integrated circuit (PIC) structure horizontally distal to the cavity.
A structure includes a through semiconductor via (TSV) in a semiconductor substrate. The structure also includes a cavity including a first cavity portion in the semiconductor substrate and surrounding a middle section of the TSV and in direct contact with the TSV. The cavity also includes a plurality of second cavity portions in the semiconductor substrate and surrounding an upper section of the TSV. The semiconductor substrate is between adjacent second cavity portions, creating a bridge portion that provides structural support. The cavity reduces parasitic capacitance.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
86.
THREE-DIMENSIONAL INTEGRATED CIRCUIT WITH TOP CHIP INCLUDING LOCAL INTERCONNECT FOR BODY-SOURCE COUPLING
Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions; a body region on a channel region between the source and drain regions; and a gate structure adjacent to and between the channel region and the dielectric material layers. Alternatively, the transistor includes: a source region between drain regions; a body region on a channel region between the source region and each drain region; and gate structures adjacent to and between the channel regions and the dielectric material layers. The first chip also includes an insulator layer on the transistor opposite the dielectric material layers, a trench in the insulator layer extending to the source and body regions, and a local interconnect at the bottom of the trench.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Structures including a calibration marker adjacent to a photonic structure and methods of forming such structures. The structure comprises a semiconductor substrate, a photonic structure, and a back-end-of-line stack over the semiconductor substrate. The back-end-of-line stack includes a plurality of fill features, an exclusion area surrounded by the plurality of fill features, and a calibration marker in the exclusion area. The calibration marker is disposed adjacent to the photonic structure, and the calibration marker includes a feature having a predetermined dimension.
Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions, a body region on a channel region between the source and drain regions, and a gate structure adjacent to and between the channel region and the dielectric material layers. An insulator layer is on the transistor opposite the dielectric material layers and includes an opening extending to the body region. Optionally, a semiconductor layer is at the bottom of the opening. A contact extends into the opening to the body region (or to the semiconductor layer thereon, if applicable).
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
89.
SEMICONDUCTOR DEVICE INCLUDING DIFFUSION BREAK STRUCTURE AND METHOD OF FORMING SEMICONDUCTOR DEVICE
A semiconductor device includes an insulating layer, a first semiconductor layer over the insulating layer, a diffusion break structure between a first active region and a second active region and including a first insulating pattern over the insulating layer and an opening over the first insulating pattern, and a conductive gate material over the opening.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor layer, a first raised source/drain region on the semiconductor layer, a second raised source/drain region on the semiconductor layer, a gate electrode laterally between the first raised source/drain region and the second raised source/drain region, a first airgap laterally between the first raised source/drain region and the gate electrode, and a second airgap laterally between the second raised source/drain region and the gate electrode. The gate electrode includes a first section and a second section between the first section and the semiconductor layer, the first section of the gate electrode has a first width, the second section of the gate electrode has a second width, and the first width is greater than the second width.
Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure comprises a drain and a source in a semiconductor substrate. The source includes a source region having a first terminating end, a second terminating end, and a length between the first terminating end and the second terminating end. The structure further comprises a shallow trench isolation region in the semiconductor substrate. The shallow trench isolation region surrounds the drain. The structure further comprises a gate that surrounds the shallow trench isolation region and the drain. The gate has a side section between the drain and the source region, the side section of the gate has a width, and the gate has a length in a direction transverse to the width. The length of the source region is substantially equal to the length of the gate.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
The present disclosure relates to semiconductor structures and, more particularly, to gated body transistors and methods of manufacture. The structure includes: at least one fin structure composed of semiconductor material and including a channel region between a source region and a drain region; and a gated body under the channel region of the at least one fin structure.
H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Photonics chip structures including an edge coupler and a layer that exhibits an electric-field-induced Pockels effect and methods of forming such structures. The structure comprises a substrate, an edge coupler on the substrate, and a layer including a portion that has an overlapping relationship with the edge coupler. The layer comprises a material that exhibits an electric-field-induced Pockels effect.
G02F 1/035 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect in an optical waveguide structure
94.
STRUCTURES INCLUDING A GRATING COUPLER AND A LAYER EXHIBITING AN ELECTRIC-FIELD-INDUCED POCKELS EFFECT
Structures including a grating coupler and a layer that exhibits an electric-field-induced Pockels effect and methods of forming such structures. The structure comprises a first grating coupler on a substrate, a second grating coupler having an overlapping relationship with the first grating coupler, and a layer including a portion having an overlapping relationship with the second grating coupler. The layer comprises a material that exhibits an electric-field-induced Pockels effect.
G02F 1/03 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect
G02F 1/035 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect in an optical waveguide structure
95.
BROADBAND OPTICAL SWITCHES BASED ON A RING-ASSISTED MACH-ZHENDER INTERFEROMETER
Structures for a broadband optical switch and methods of forming such structures. The structure comprises a Mach-Zehnder interferometer including first and second arms. The first arm comprises a first waveguide core, and the second arm comprises a second waveguide core. The structure further comprises a ring resonator comprising a third waveguide core that has a first thickness. A portion of the third waveguide core is adjacent to a portion of the first waveguide core over a light coupling region. A slab layer connects the portion of the first waveguide core to the portion of the third waveguide core. The slab layer has a second thickness that is less than the first thickness of the first waveguide core.
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference
96.
THIN FILM RESISTOR, THERMISTOR AND METHOD OF PRODUCING THE SAME
An apparatus includes a resistor structure within a back end of line (BEOL) via level. The resistor structure includes a lower resistor film, a first insulating layer over the lower resistor film, an upper resistor film over the first insulating layer, and a second insulating layer over the upper resistor film. First and second upper metal lines are above the second insulating layer, a first end of the upper resistor film is coupled to the first upper metal line by a first upper via or contact, and a second end of the upper resistor film is coupled to the second upper metal line by a second upper via or contact. The apparatus may be a resistor or a thermistor of a semiconductor device.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
97.
CAVITY WITH BOTTOM HAVING DIELECTRIC LAYER PORTION OVER GATE BODY WITHOUT ETCH STOP LAYER AND RELATED METHOD
A semiconductor device includes a transistor including source/drain regions and a gate, the gate having a gate body. An etch stop layer is over the source/drain regions but not over the gate body. An interconnect layer is over the transistor and includes a dielectric layer. A cavity extends partially through the interconnect layer above the gate, and a portion of the dielectric layer is over the gate body and defines a bottom of the cavity. The cavity provides a mechanism to reduce both on-resistance and off-capacitance for applications such as radio frequency switches.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 - Layout of the interconnection structure
98.
METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS
An integrated circuit product including a first layer of insulating material that includes a first insulating material, a metallization blocking structure positioned in an opening in the first layer of insulating material, a second layer of insulating material including a second insulating material positioned below the metallization blocking structure, a metallization trench defined in the first layer of insulating material on opposite sides of the metallization blocking structure, and a conductive metallization line positioned in the metallization trench on opposite sides of the metallization blocking structure.
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Structures including a photonics chip and a cavity-mounted laser chip, and methods of forming and using such structures. The structure comprises a photonics chip including a substrate and a cavity in the substrate. The structure further comprises a laser chip inside the cavity, and a lead frame comprising a first section attached to a portion of the laser chip and a second section attached to a portion of the photonics chip.
A structure includes a first gate structure spaced from a second gate structure in a field effect transistor (FET) area of a substrate. A polysilicon resistor is in a space between the first gate structure and the second gate structure. The polysilicon resistor has a lower surface that is farther from the substrate than lower surfaces of the polysilicon bodies of the first and second gate structures. The polysilicon resistor may have a different polarity dopant compared to at least one of the polysilicon bodies of the first and second gate structures.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
