SEAKR Engineering LLC

United States of America

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        United States 20
        Canada 3
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Date
2026 April 1
2026 (YTD) 2
2024 1
2023 1
2022 5
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IPC Class
H04B 7/185 - Space-based or airborne stations 11
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission 7
H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station 7
H04B 1/44 - Transmit/receive switching 5
H04B 7/212 - Time-division multiple access 5
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NICE Class
09 - Scientific and electric apparatus and instruments 5
40 - Treatment of materials; recycling, air and water treatment, 2
42 - Scientific, technological and industrial services, research and design 2
Status
Pending 3
Registered / In Force 21

1.

SCALABLE PARTITIONING OF FUNCTIONS WITHIN APPLICATION SPECIFIC INTEGRATED CIRCUIT OR MICROELECTRONICS DEVICE

      
Document Number 03284526
Status Pending
Filing Date 2025-08-29
Open to Public Date 2026-04-10
Owner SEAKR ENGINEERING, LLC (USA)
Inventor Lowry, Anthony

Abstract

A semiconductor wafer is provided including: processing cores; and die structures each including at least one processing core. Each processing core includes a set of first input output (I/O) interfaces configured for communication between the processing core and a second processing core, wherein the processing core and the second processing core are included in a first die structure of the die structures. Each processing core includes a second input output (I/O) interface configured for communication between the processing core and a third processing core, wherein the third processing core is included in a second die structure of the die structures. The processing cores are spaced apart by a target distance associated with separating one or more processing cores or one or more die structures from the semiconductor wafer.

IPC Classes  ?

  • G06F 15/00 - Digital computers in generalData processing equipment in general
  • H10D 80/00 - Assemblies of multiple devices comprising at least one device covered by this subclass
  • H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
  • H10P 54/00 -
  • H10P 58/00 -
  • H10W 90/10 -

2.

SCALABLE PARTITIONING OF FUNCTIONS WITHIN APPLICATION SPECIFIC INTEGRATED CIRCUIT OR MICROELECTRONICS DEVICE

      
Application Number 18885177
Status Pending
Filing Date 2024-09-13
First Publication Date 2026-03-19
Owner SEAKR Engineering, LLC (USA)
Inventor Lowry, Anthony

Abstract

A semiconductor wafer is provided including: processing cores; and die structures each including at least one processing core. Each processing core includes a set of first input output (I/O) interfaces configured for communication between the processing core and a second processing core, wherein the processing core and the second processing core are included in a first die structure of the die structures. Each processing core includes a second input output (I/O) interface configured for communication between the processing core and a third processing core, wherein the third processing core is included in a second die structure of the die structures. The processing cores are spaced apart by a target distance associated with separating one or more processing cores or one or more die structures from the semiconductor wafer.

IPC Classes  ?

  • G06F 13/20 - Handling requests for interconnection or transfer for access to input/output bus

3.

Integrated mixed-signal ASIC with ADC, DAC, and DSP

      
Application Number 18201821
Grant Number 12255729
Status In Force
Filing Date 2023-05-25
First Publication Date 2024-05-02
Grant Date 2025-03-18
Owner Seakr Engineering, LLC (USA)
Inventor
  • Rutt, Paul
  • Buehler, Erik
  • Van Buren, Damon

Abstract

An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.

IPC Classes  ?

  • H04B 7/185 - Space-based or airborne stations
  • H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
  • H04B 1/40 - Circuits

4.

ADDA

      
Application Number 1717021
Status Registered
Filing Date 2022-11-30
Registration Date 2022-11-30
Owner SEAKR Engineering LLC (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Satellite processors; satellite-based electronic circuits; satellite components, namely, payload components in the nature of satellite-based RF transceivers and satellite-based integrated circuits; integrated circuits and integrated circuit cores for use in wireless communications and wireless communication equipment and apparatus and digital signal processors (DSP); satellite transceivers; satellite radios; radiation-tolerant or radiation-hardened components for integrated circuits provided in payloads for space-borne assets, namely, satellites and other spacecraft, and payloads for other vehicles operating at or above 15km of the surface of the earth. Custom design and engineering of satellite-based electronic circuits to improve the processing capacity of satellites; design of integrated circuits for use in wireless communications, wireless communication equipment, or digital signal processors (DSP) and which are radiation-tolerant, radiation-hardened, or otherwise designed for use in high-radiation environments, namely, space and high-altitude environments above 15km of the surface earth.

5.

ADDA

      
Application Number 224417500
Status Registered
Filing Date 2022-11-30
Registration Date 2024-09-30
Owner SEAKR Engineering LLC (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

(1) Satellite processors; satellite-based electronic circuits; satellite components, namely, payload components in the nature of satellite-based RF transceivers and satellite-based integrated circuits; integrated circuits and integrated circuit cores for use in wireless communications and wireless communication equipment and apparatus and digital signal processors (DSP); satellite transceivers; satellite radios; radiation-tolerant or radiation-hardened components for integrated circuits provided in payloads for space-borne assets, namely, satellites and other spacecraft, and payloads for other vehicles operating at or above 15km of the surface of the earth. (1) Custom design and engineering of satellite-based electronic circuits to improve the processing capacity of satellites; design of integrated circuits for use in wireless communications, wireless communication equipment, or digital signal processors (DSP) and which are radiation-tolerant, radiation-hardened, or otherwise designed for use in high-radiation environments, namely, space and high-altitude environments above 15km of the surface earth.

6.

ADDA

      
Serial Number 97610656
Status Registered
Filing Date 2022-09-28
Registration Date 2025-02-18
Owner SEAKR Engineering LLC ()
NICE Classes  ? 09 - Scientific and electric apparatus and instruments

Goods & Services

Satellite processors; satellite-based electronic circuits; Satellite components, namely, payload components in the nature of satellite-based RF transceivers and satellite-based integrated circuits; Integrated circuits and integrated circuit cores for use in wireless communications and wireless communication equipment and apparati and digital signal processors (DSP); Satellite transceivers; Satellite radios; Radiation-tolerant and radiation-hardened components in the nature of integrated circuits provided in payloads for space-borne assets, namely, satellites and other spacecraft, and integrated circuits provided in payloads for other vehicles operating at or above 15km of the surface of the Earth

7.

Integrated mixed-signal ASIC with ADC, DAC, and DSP

      
Application Number 17668177
Grant Number 11711139
Status In Force
Filing Date 2022-02-09
First Publication Date 2022-08-25
Grant Date 2023-07-25
Owner SEAKR ENGINEERING, LLC (USA)
Inventor
  • Rutt, Paul
  • Buehler, Erik
  • Van Buren, Damon

Abstract

An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.

IPC Classes  ?

  • H04B 7/185 - Space-based or airborne stations
  • H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
  • H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
  • H04B 7/212 - Time-division multiple access
  • H04B 1/44 - Transmit/receive switching
  • H04B 1/40 - Circuits

8.

SYSTEM AND METHOD FOR MEASURING SMALL FREQUENCY DIFFERENCES

      
Document Number 03210050
Status Pending
Filing Date 2021-11-16
Open to Public Date 2022-08-04
Owner SEAKR ENGINEERING, LLC (USA)
Inventor Smith, John Eric

Abstract

The present disclosure is directed to a system and method for measuring small frequency differences between two signals quickly and with high precision. In particular examples, an offset between two clock signals on a satellite can be accurately determined in a time period enabling rapid clock synchronization useful in position, navigation, and tracking (PNT) and satellite communications applications. The system and method may also be implemented in constellation of cooperative satellites or other space-borne and high-altitude assets, wherein a plurality of such assets are accurately time-synchronized and more accurate ensemble average calculations are enabled using two-way time transfer (TWTT) protocols. A particular application presently disclosed measurement and correction of very small frequency differences between an atomic clock signal and a tunable clock signal.

IPC Classes  ?

  • G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • G06F 1/12 - Synchronisation of different clock signals
  • H04H 20/74 - Wireless systems of satellite networks

9.

System and method for measuring small frequency differences

      
Application Number 17528085
Grant Number 12200093
Status In Force
Filing Date 2021-11-16
First Publication Date 2022-07-28
Grant Date 2025-01-14
Owner SEAKR Engineering, LLC (USA)
Inventor Smith, John Eric

Abstract

The present disclosure is directed to a system and method for measuring small frequency differences between two signals quickly and with high precision. In particular examples, an offset between two clock signals on a satellite can be accurately determined in a time period enabling rapid clock synchronization useful in position, navigation, and tracking (PNT) and satellite communications applications. The system and method may also be implemented in constellation of cooperative satellites or other space-borne and high-altitude assets, wherein a plurality of such assets are accurately time-synchronized and more accurate ensemble average calculations are enabled using two-way time transfer (TWTT) protocols. A particular application presently disclosed measurement and correction of very small frequency differences between an atomic clock signal and a tunable clock signal.

IPC Classes  ?

  • H04L 7/027 - Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
  • H04B 7/185 - Space-based or airborne stations
  • H04L 27/26 - Systems using multi-frequency codes

10.

Integrated mixed-signal ASIC with ADC, DAC, and DSP

      
Application Number 17142778
Grant Number 11329718
Status In Force
Filing Date 2021-01-06
First Publication Date 2021-07-29
Grant Date 2022-05-10
Owner SEAKR ENGINEERING, LLC (USA)
Inventor
  • Rutt, Paul
  • Buehler, Erik
  • Van Buren, Damon

Abstract

An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications capable of flexibly processing high-bandwidth and low-bandwidth RF input signal(s). The RF transceiver may selectively distribute high-bandwidth RF input signals among one or more DSP pipelines for parallel processing of the RF input signals, and the RF transceiver may coherently recombine the processed signals from the one or more DSP pipelines to generate an RF output signal. The ADDA RF transceiver includes one or more ADCs, DSPs, and DACs, all on one or more ASICs, FPGAs, or modular electronic devices in a single semiconductor package. Further, the RF transceiver is radiation tolerant at the module, circuit, and/or system level for high availability and reliability in the ionizing radiation environment present in the space environment.

IPC Classes  ?

  • H04B 7/185 - Space-based or airborne stations
  • H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
  • H04B 7/212 - Time-division multiple access
  • H04B 1/40 - Circuits
  • H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
  • H04B 1/44 - Transmit/receive switching

11.

Integrated mixed-signal RF transceiver with ADC, DAC, and DSP and high-bandwidth coherent recombination

      
Application Number 16286567
Grant Number 10917163
Status In Force
Filing Date 2019-02-26
First Publication Date 2020-07-09
Grant Date 2021-02-09
Owner SEAKR ENGINEERING, LLC (USA)
Inventor
  • Rutt, Paul
  • Hobart, Jesse D.
  • Perego, Richard E.

Abstract

An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications capable of flexibly processing high-bandwidth and low-bandwidth RF input signal(s). The RF transceiver may selectively distribute high-bandwidth RF input signals among one or more DSP pipelines for parallel processing of the RF input signals, and the RF transceiver may coherently recombine the processed signals from the one or more DSP pipelines to generate an RF output signal. The ADDA RF transceiver includes one or more ADCs, DSPs, and DACs, all on one or more ASICs, FPGAs, or modular electronic devices in a single semiconductor package. Further, the RF transceiver is radiation tolerant at the module, circuit, and/or system level for high availability and reliability in the ionizing radiation environment present in the space environment.

IPC Classes  ?

  • H04B 7/185 - Space-based or airborne stations
  • H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
  • H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
  • H04B 7/212 - Time-division multiple access
  • H04B 1/44 - Transmit/receive switching
  • H04B 1/40 - Circuits

12.

Pulse-based synchronization training for synchronous digital and mixed-signal systems

      
Application Number 15978017
Grant Number 10461753
Status In Force
Filing Date 2018-05-11
First Publication Date 2019-10-29
Grant Date 2019-10-29
Owner SEAKR ENGINEERING, LLC (USA)
Inventor
  • Pritchard, Jeff
  • Highley, Jeff
  • Randolph, Iii, James

Abstract

Systems and methods for synchronizing the clocks of a central device and one or more destination devices are disclosed. In some embodiments the central device and destination devices are implemented in a space-based or high-altitude asset. The central device provides a series of synchronization pulses to the one or more destination devices. In response to detecting, at the destination device, the synchronization pulse, a sample of the destination device clock is stored in a register. The sample is provided to the central device. The sequence is repeated at least once. A phase offset between the central device clock and the destination device clock may be determined based on the returned samples and the position of the samples within the register.

IPC Classes  ?

  • H03L 7/00 - Automatic control of frequency or phaseSynchronisation

13.

Flexible beamforming, channelization, and routing folded processing architecture for digital satellite payloads

      
Application Number 15945624
Grant Number 10594385
Status In Force
Filing Date 2018-04-04
First Publication Date 2018-10-04
Grant Date 2020-03-17
Owner SEAKR ENGINEERING, LLC (USA)
Inventor
  • Buehler, Erik
  • Perego, Richard E.

Abstract

An electronic device for a communications satellite for beamforming, channelization, and/or routing is implemented using a digital folded architecture to reduce the number of serial communication paths and provide more flexible routing and network configurability and scalability. A method for configuring the switching network of a system comprising multiple electronic devices allows the system to be dynamically reconfigured to implement different types of networks.

IPC Classes  ?

  • H04B 7/0408 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas using two or more beams, i.e. beam diversity
  • H04B 7/185 - Space-based or airborne stations
  • H04L 12/70 - Packet switching systems
  • H04L 12/933 - Switch core, e.g. crossbar, shared memory or shared medium
  • H04W 16/28 - Cell structures using beam steering
  • H04W 84/06 - Airborne or Satellite Networks

14.

Power efficiency in beamforming RF systems

      
Application Number 15456086
Grant Number 10771145
Status In Force
Filing Date 2017-03-10
First Publication Date 2017-09-14
Grant Date 2020-09-08
Owner SEAKR ENGINEERING, LLC (USA)
Inventor Buehler, Erik

Abstract

A satellite communication system processes a plurality of input signals to generate beamformed signals, drives a plurality of nonlinear power amplifiers with the beamformed input signals to produce RF signals for transmission; and transmits the RF signals with a plurality of Tx antenna elements. Conversion to and from linear signals to and from nonlinear or digitized signals is performed. Temporal or spatial decorrelation of the beamformed signals is employed to reduce the impact of intermodulation products. In some cases the power amplifiers are nonlinear, and can be one-sided or two-sided and produce two or three distinct output levels.

IPC Classes  ?

  • H03K 11/00 - Transforming types of modulation, e.g. position-modulated pulses into duration-modulated pulses
  • H04L 25/60 - Regenerative repeaters with electromagnetic switches
  • H04L 25/64 - Start-stop regenerative repeaters using discharge tubes or semiconductor devices
  • H04B 7/185 - Space-based or airborne stations
  • H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
  • H04B 1/04 - Circuits
  • H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
  • H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages

15.

Integrated mixed-signal ASIC with DAC and DSP

      
Application Number 15351224
Grant Number 10218430
Status In Force
Filing Date 2016-11-14
First Publication Date 2017-03-02
Grant Date 2019-02-26
Owner SEAKR ENGINEERING, LLC (USA)
Inventor
  • Buehler, Erik
  • Van Buren, Damon
  • Rutt, Paul

Abstract

An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuity is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.

IPC Classes  ?

  • H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
  • H04B 7/185 - Space-based or airborne stations
  • H04B 7/212 - Time-division multiple access
  • H04B 1/44 - Transmit/receive switching
  • H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station

16.

Integrated mixed-signal ASIC with ADC and DSP

      
Application Number 15263134
Grant Number 10243650
Status In Force
Filing Date 2016-09-12
First Publication Date 2017-02-23
Grant Date 2019-03-26
Owner SEAKR ENGINEERING, LLC (USA)
Inventor
  • Buehler, Erik
  • Van Buren, Damon
  • Rutt, Paul

Abstract

An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.

IPC Classes  ?

  • H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
  • H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
  • H04B 7/185 - Space-based or airborne stations
  • H04B 7/212 - Time-division multiple access
  • H04B 1/44 - Transmit/receive switching

17.

LEO flexible single axis beamforming

      
Application Number 15178441
Grant Number 09900072
Status In Force
Filing Date 2016-06-09
First Publication Date 2016-12-15
Grant Date 2018-02-20
Owner SEAKR ENGINEERING, LLC (USA)
Inventor Van Buren, Damon

Abstract

A hybrid system of satellite-based beamforming that includes digitally beamforming in one axis and physically beamforming in an orthogonal axis. Based on the orientation of the satellite, the digital beamforming axis may be the in-track axis, the cross-track axis, or anywhere in between those two axes. In the digitally beamformed axis, the beam pattern can be steered to different positions along the axis and it can be compressed or expanded, as desired.

IPC Classes  ?

  • H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
  • H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
  • H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
  • H04B 7/185 - Space-based or airborne stations
  • H04B 7/0408 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas using two or more beams, i.e. beam diversity

18.

Robust SerDes wrapper

      
Application Number 14812871
Grant Number 09690646
Status In Force
Filing Date 2015-07-29
First Publication Date 2016-06-30
Grant Date 2017-06-27
Owner SEAKR ENGINEERING, LLC (USA)
Inventor Buehler, Erik

Abstract

Light-weight, configurable error detection in a satellite communication system that detects invalid SerDes lanes via hash codes appended to packets of data in the lanes. An indication can be passed back upstream about the invalid lane so that the lane can be reset. Error correction can be provided by reconstructing the bit data in the invalid SerDes lane based on parity information in an optional parity lane.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
  • H03M 9/00 - Parallel/series conversion or vice versa
  • H03M 13/03 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
  • H04L 1/16 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
  • H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability

19.

Centralized configuration control of reconfigurable computing devices

      
Application Number 13835338
Grant Number 09612900
Status In Force
Filing Date 2013-03-15
First Publication Date 2016-06-02
Grant Date 2017-04-04
Owner SEAKR ENGINEERING, LLC (USA)
Inventor
  • Anderson, Scott
  • Murray, Paul

Abstract

Methods, systems, and devices for configuration and upset recovery of reconfigurable devices are provided. A central program/recovery manager (CPRM) is coupled with each of a number of reconfigurable devices. The reconfigurable devices are programmed/configured by the CPRM, which then periodically monitors each of the reconfigurable devices to detect if one or more of the devices has experienced an upset. In the event of an upset, the CPRM may attempt to reset the reconfigurable device, scrub a memory of the reconfigurable device, or reprogram the reconfigurable device. A memory module is coupled with the CPRM and each of the reconfigurable devices that stores bit or programming files that may be used to program and/or reprogram the reconfigurable devices.

IPC Classes  ?

  • G06F 11/00 - Error detectionError correctionMonitoring
  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance

20.

Integrated mixed-signal ASIC with ADC, DAC, and DSP

      
Application Number 14828126
Grant Number 09461732
Status In Force
Filing Date 2015-08-17
First Publication Date 2016-02-18
Grant Date 2016-10-04
Owner SEAKR ENGINEERING, LLC (USA)
Inventor
  • Buehler, Erik
  • Van Buren, Damon
  • Rutt, Paul

Abstract

An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.

IPC Classes  ?

  • H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
  • H04B 7/185 - Space-based or airborne stations

21.

System and method for dissipating thermal energy

      
Application Number 14455668
Grant Number 09498858
Status In Force
Filing Date 2014-08-08
First Publication Date 2016-02-11
Grant Date 2016-11-22
Owner SEAKR ENGINEERING, LLC (USA)
Inventor
  • Schwartz, Tim
  • Torline, Steve

Abstract

A system for dissipating thermal energy from an enclosure includes a gusset having a base engagement face and an enclosure engagement face that may be removably coupled with the enclosure. In some embodiments, a heat pipe extends along a gusset frame between portions of the base engagement face and the enclosure engagement face. The heat pipe is angularly shaped in various embodiments and is thermally coupled with the base engagement face and the enclosure engagement face. In some embodiments, the heat pipe is coupled within a heat pipe channel that extends along a length of the gusset.

IPC Classes  ?

  • F24H 3/00 - Air heaters
  • B23P 15/26 - Making specific metal objects by operations not covered by a single other subclass or a group in this subclass heat exchangers
  • H05K 7/14 - Mounting supporting structure in casing or on frame or rack
  • H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

22.

Distributed mesh-based memory and computing architecture

      
Application Number 13461618
Grant Number 09104639
Status In Force
Filing Date 2012-05-01
First Publication Date 2013-11-07
Grant Date 2015-08-11
Owner SEAKR ENGINEERING, LLC (USA)
Inventor
  • Koritnik, Brett
  • Sprague, Kirk

Abstract

Methods, systems, and devices for distributed computing are provided. Clusters of nodes are provided, each node have a communication link to a primary I/O switch as well as to two other nodes, thereby providing redundant alternative communication paths between different components of the system. Primary and redundant I/O switching modules may provide further redundancy for high availability and high reliability applications, such as applications that may be subjected to the environment as would be found in space, including radiation effects. Nodes in a cluster may provide data storage, processing, and/or input/output functions, as well as one or more alternate communications paths between system components. Multiple clusters of nodes may be coupled together to provide enhanced performance and/or reliability.

IPC Classes  ?

  • G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake
  • G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
  • H04L 12/939 - Provisions for redundant switching, e.g. using parallel switching planes
  • G06F 11/30 - Monitoring
  • H04L 12/933 - Switch core, e.g. crossbar, shared memory or shared medium
  • G06F 13/14 - Handling requests for interconnection or transfer

23.

SEAKR

      
Serial Number 85502571
Status Registered
Filing Date 2011-12-22
Registration Date 2013-04-02
Owner SEAKR ENGINEERING, LLC ()
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 40 - Treatment of materials; recycling, air and water treatment,

Goods & Services

Computer hardware, software and firmware for processing and storage of data; Solid state drives; Power supplies Manufacturing services for others in the field of electronics; Contract manufacturing in the field of electronics; Custom manufacturing in the field of electronics

24.

SE

      
Serial Number 85502567
Status Registered
Filing Date 2011-12-22
Registration Date 2013-04-02
Owner SEAKR ENGINEERING, LLC ()
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 40 - Treatment of materials; recycling, air and water treatment,

Goods & Services

Computer hardware, software and firmware for processing and storage of data; Solid state drives; Power supplies Manufacturing services for others in the field of electronics; Contract manufacturing in the field of electronics; Custom manufacturing in the field of electronics