The invention relates to an electronic device, and more particularly, to systems, devices and methods of authenticating the electronic device using a challenge-response process that is based on a physically unclonable function (PUF). The electronic device comprises a PUF element, a processor and a communication interface. The PUF element generates an input signal based on at least one PUF that has unique physical features affected by manufacturing variability. A challenge-response database, comprising a plurality of challenges and a plurality of corresponding responses, is set forth by the processor based on the PUF-based input and further provided to a trusted entity. During the trusted transaction, the processor generates a response in response to a challenge sent by the trusted entity based on the PUF-based input, and thereby, the trusted entity authenticates the electronic device by comparing the response with the challenge-response database.
G06F 21/73 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
G06Q 20/02 - Payment architectures, schemes or protocols involving a neutral third party, e.g. certification authority, notary or trusted third party [TTP]
G06Q 20/32 - Payment architectures, schemes or protocols characterised by the use of specific devices using wireless devices
G06Q 20/40 - Authorisation, e.g. identification of payer or payee, verification of customer or shop credentialsReview and approval of payers, e.g. check of credit lines or negative lists
G07C 9/00 - Individual registration on entry or exit
G07C 9/27 - Individual registration on entry or exit involving the use of a pass with central registration
G09C 1/00 - Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
2.
INDUCTORS INCLUDING ELECTRICALLY CONDUCTIVE STANDOFFS
An inductor includes a magnetic core, a first winding, a first electrically conductive standoff, and a second electrically conductive standoff. The magnetic core includes opposing first and second outer surfaces separated from each other in a first direction. The first winding has first and second ends, and the first winding is wound around at least a portion of the magnetic core. The first electrically conductive standoff is connected to the first end of the first winding, and the first electrically conductive standoff extends along the magnetic core in the first direction from the first outer surface to the second outer surface. The second electrically conductive standoff is connected to the second end of the first winding, and the second electrically conductive standoff extends along the magnetic core in the first direction from the first outer surface to the second outer surface.
A method for providing an analog output signal includes (a) amplifying a digital first internal signal using a first Class-D amplifier to generate a digital first output signal, (b) filtering the digital first output signal to generate an analog first output signal, (c) providing the analog first output signal to a first load, (d) sensing the analog first output signal to generate an analog first feedback signal, (e) converting the analog first feedback signal to a digital first feedback signal, and (f) configuring the first Class-D amplifier for an impedance of the first load by generating the digital first internal signal at least partially based on the digital first feedback signal.
Dynamic error-quantizer tuning systems and methods prevent misconvergence to local minima by using a dynamic quantizer circuit that controls reference voltages of three or more comparators that are independently adjusted to modify the transfer function of the dynamic quantizer circuit. A weighted sum of the comparator outputs is subtracted from the input to form an error signal in a control loop. The ratio of the reference voltages is chosen to reduce or eliminate local minima during a convergence of the control loop and is set to values that minimize a mean squared error signal with respect to discrete modulation states of the input after the convergence of the control loop is complete.
H04B 10/035 - Arrangements for fault recovery using loopbacks
H04B 10/077 - Arrangements for monitoring or testing transmission systemsArrangements for fault measurement of transmission systems using an in-service signal using a supervisory or additional signal
A method for providing an analog output signal includes (a) amplifying an analog first internal signal using a first Class-G amplifier to generate an analog first output signal, (b) providing the analog first output signal to a first load, and (c) configuring the first Class-G amplifier for an impedance of the first load by selecting one of a plurality of power supply rails to power the first Class-G amplifier at least partially based on a voltage across the first load. In some embodiments, an impedance of the first load may range from zero to 1,000 ohms.
A switching power converter includes (i) a plurality of power stages including respective power transfer windings, (ii) an injection stage including a plurality of injection windings electrically coupled in series, (iii) a magnetic core, and (iv) a controller. The magnetic core includes a plurality of power transfer rungs and a plurality of injection rungs disposed between a first rail and a second rail in a first direction. Each power transfer winding is wound around a respective one of the plurality of power transfer rungs, and each injection winding is wound around a respective one of the plurality of injection rungs. The controller is configured to (i) control duty cycle of the power stages to regulate at least one parameter of the switching power converter and (ii) control the injection stage to reduce voltage across a respective leakage inductance of each power transfer winding.
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
7.
SWITCHING POWER CONVERTERS CONFIGURED TO INJECT CURRENT INTO AN OUTPUT NODE
A switching power converter includes a plurality of power stages and a blocking capacitor. Each power stage includes a respective power transformer. The blocking capacitor and a respective secondary winding of each power transformer are electrically coupled in series between an output power node of the switching power converter and a reference node of the switching power converter. Another switching power converter includes a plurality of power stages, a boost winding, and a blocking capacitor. Each power stage includes a respective power transfer winding, and the boost winding forms at least one turn around a respective leakage magnetic flux path of each power transfer winding. The blocking capacitor and the boost winding are electrically coupled in series between an output power node of switching power converter and a reference node of the switching power converter.
H02M 1/14 - Arrangements for reducing ripples from DC input or output
H02M 1/44 - Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
8.
ULTRA-LOW POWER INSTANT LOCK PHASE LOCK LOOP (PLL)
Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
9.
SYSTEMS AND METHODS FOR PERFORMING IN-FLIGHT COMPUTATIONS
In-flight operations in an inbound data path from a source memory to a convolution hardware circuit increase computational throughput when performing convolution calculations, such as pooling and element-wise operations. Various operations may be performed in-line within an outbound data path to a target memory. Advantageously, this drastically reduces extraneous memory access and associated read-write operations, thereby, significantly reducing overall power consumption in a computing system.
A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H04L 7/00 - Arrangements for synchronising receiver with transmitter
11.
TWO-STAGE SWITCHING POWER CONVERTERS WITH RIPPLE CURRENT CANCELATION, AND ASSOCIATED METHODS
A two-stage switching power converter includes a first power stage, a second power stage electrically coupled in series with the first power stage, and a controller. The first power stage includes a first power transfer winding, and the second power stage includes a second power transfer winding that is magnetically coupled to the first power transfer winding. The controller is configured to (a) control switching of the second power stage to regulate at least one parameter of the two-stage switching power converter and (b) control switching of the first power stage such that the first power stage switches in a complementary manner with respect to the second power stage.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A serial communication link includes a waveguide having a first end and a second end, a serializer communicatively coupled to the first end of the waveguide, a deserializer communicatively coupled to the second end of the waveguide, a first power over cable (PoC) filter, and a second PoC filter. The first PoC filter is electrically coupled between to first end of the waveguide, and the first PoC filter includes two inductors that are configured to collectively present an impedance of at least one thousand ohms over an entire operating frequency range of the serial communication link. The second PoC filter is electrically coupled to the second end of the waveguide, and the second PoC filter includes two inductors that are configured to collectively present an impedance of at least one thousand ohms over the entire operating frequency range of the serial communication link.
A powered device interface assembly includes an optocoupler and a powered device interface. The opto-coupler is electrically coupled with a microcontroller of the power device interface. The powered device interface includes a telemetry circuit coupled with the opto-coupler and configured to generate encoded telemetry information for output via a single pin of the powered device interface for transmission to the microcontroller of the powered device, wherein the opto-coupler is coupled with the single pin and is configured to electrically isolate the single pin from the microcontroller.
G06F 1/3203 - Power management, i.e. event-based initiation of a power-saving mode
H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water
14.
SYSTEM AND METHOD FOR DUAL-PORT COMMUNICATION AND POWER DELIVERY
Described herein are embodiments for dual-port communication and power delivery for one-wire applications. Embodiments of one-wire bridge devices are disclosed to provide a dual-port link for two one-wire masters to communicate with one another in a multi-voltage system while intermittently allowing charging voltage. The configuration may be used to set a bidirectional pass through mode that allows level shifted fast logic signals to pass through the two one-wire links. A timer may also be configurable to time-out the pass through mode from edge in-activity. Power may be derived for operation directly from one of the links, eliminating the need for an external power supply when local power is not available. When local power is available, the other one-wire link provides local access and the pass through mode. Such configurations make it easy for a two-contact solution to be both a communication channel and a power supply for battery charging.
Systems and methods herein use a sensing circuit to detect an overvoltage at a voltage node as a drain current. A current-mode comparator converts the detected current into a control signal, which is provided to a control circuit. The control circuit uses the control signal cut of a bias current to turn off switches in a protection circuit to create a high-impedance electrical path between the voltage node and the to-be-protected voltage node.
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
G01D 3/08 - Measuring arrangements with provision for the special purposes referred to in the subgroups of this group with provision for safeguarding the apparatus, e.g. against abnormal operation, against breakdown
16.
SOLENOID SYSTEM WITH POSITION AND TEMPERATURE DETECTION
A solenoid system and method can include: providing an energizing voltage to a coil of a solenoid; providing an AC signal superimposed onto the energizing voltage; detecting current through the coil including an AC current amplitude induced by the AC signal and including a DC offset current amplitude; determining the AC current amplitude is a low AC current amplitude based on an armature within the solenoid being in a retracted position or determining the AC current amplitude is a high AC current amplitude based on the armature being in an extended position with the control logic, and where the AC current amplitude is determined utilizing the AC signal for synchronous demodulation; and determining a temperature fault based on the DC offset current amplitude falling below a DC offset current amplitude threshold.
A canal dynamic photodiode includes a gate structure forming a plurality of apertures, at least one anode region within the gate structure, and a plurality of cathode regions. Each cathode region of the plurality of cathode regions is within a respective aperture of the plurality of apertures. The canal dynamic photodiode may further include a plurality of field regions, where each cathode region of the plurality of cathode regions is separated from the gate structure by a respective field region of the plurality of field regions. Each field region optionally includes a respective doped surface region.
H01L 31/103 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN homojunction type
A canal dynamic photodiode includes a gate structure forming a plurality of apertures, at least one anode region within the gate structure, and a plurality of cathode regions. Each cathode region of the plurality of cathode regions is within a respective aperture of the plurality of apertures. The canal dynamic photodiode may further include a plurality of field regions, where each cathode region of the plurality of cathode regions is separated from the gate structure by a respective field region of the plurality of field regions. Each field region optionally includes a respective doped surface region.
H01L 27/14 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
G01S 17/04 - Systems determining the presence of a target
A method for sensing current includes (a) generating a first current signal representing magnitude of current flowing through a sensing element while a first switching device is in its on-state and a second switching device is in its off-state, each of the first switching device and the second switching device being electrically coupled to the sensing element, (b) generating a second current signal representing magnitude of current flowing through the sensing element while the first switching device is in its off-state and the second switching device is in its on-state, and (c) generating a composite current signal from the first current signal and the second current signal, the composite current signal representing magnitude of current flowing through the sensing element.
A voltage converter includes: first and second switches having a first voltage rating, the first switch connected between an input voltage and a first node, and the second switch connected between the first node and a potential; a bypass switch connected between the input voltage and a second node; a first inductor connected between the first node and the second node; a first capacitor connected between the second node and the potential; third and fourth switches having a second voltage rating that is less than the first voltage rating, the third switch connected between the second node and a third node, and the fourth switch connected between the third node and the potential; and a switch control module configured to, in response to the input voltage becoming greater than a predetermined voltage: switch the first and second switches and adjust the voltage at the second node toward a target voltage.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
A current based resonant frequency tracking system and methods can include: providing a haptic pattern with a processor, the haptic pattern including both a haptic pattern start time and a haptic pattern stop time; driving a linear resonant actuator according to the haptic pattern with an amplifier coupled to the processor, and the amplifier having an output coupled to the linear resonant actuator; detecting a current sense signal having a back electromotive force current after the haptic pattern stop time with a current frequency tracker coupled to the output of the amplifier; measuring a frequency of the back electromotive force current as a resonant frequency of the linear resonant actuator; and detecting cycles in the back electromotive force current after the haptic pattern stop time.
H02P 6/182 - Circuit arrangements for detecting position without separate position detecting elements using back-emf in windings
H02P 6/00 - Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor positionElectronic commutators therefor
This disclosure describes a magnetic-field image sensor and method of use. In accordance with implementations of the magnetic-field image sensor, a sample can be placed on top of the magnetic field image sensor. An image of the magnetic nanoparticles or superparamagnetic nanoparticles can be created immediately afterwards based upon detection of a change in magnetic field caused by the magnetic nanoparticles or superparamagnetic nanoparticles. From this image, computer imaging algorithms can determine attributes (e.g., size, shape, type, quantity, distribution, etc.) of the target entity.
Systems and methods reduce unwanted effects caused by mismatch in amplifier circuits having components that are trimmable during and post-production to minimize DC offset. Various embodiments of the invention trim out amplifier mismatch by determining trim codes for two or more phases of operation of an amplifier circuit and use those trim codes to determine a final trim code for use in regular operation.
A method for operating a switching power converter to reduce ripple current magnitude includes (a) controlling duty cycle of a plurality power stages of the switching power converter to regulate at least one parameter of the switching power converter, each power stage including a respective power transformer, and (b) controlling an injection stage of the switching power converter to reduce voltage across leakage inductance of each power transformer, the injection stage including an injection transformer that is electrically coupled to a respective secondary winding of each power transformer.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/14 - Arrangements for reducing ripples from DC input or output
25.
SWITCHING POWER CONVERTERS INCLUDING BOOSTED COUPLED INDUCTORS AND INJECTION STAGES, AND ASSOCIATED METHODS
A method for operating a switching power converter to reduce ripple current magnitude includes (1) controlling duty cycle of a plurality power stages of the switching power converter to regulate at least one parameter of the switching power converter, each power stage including a respective power transfer winding, and (2) controlling an injection stage of the switching power converter to reduce voltage across leakage inductance of each power transfer winding, the injection stage of the switching power converter including a boost winding forming at least one turn around a respective leakage magnetic flux path of each power transfer winding.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
The invention relates to an electronic device, and more particularly, to systems, devices and methods of authenticating the electronic device using a challenge-response process that is based on a physically unclonable function (PUF). The electronic device comprises a PUF element, a processor and a communication interface. The PUF element generates an input signal based on at least one PUF that has unique physical features affected by manufacturing variability. A challenge-response database, comprising a plurality of challenges and a plurality of corresponding responses, is set forth by the processor based on the PUF-based input and further provided to a trusted entity. During the trusted transaction, the processor generates a response in response to a challenge sent by the trusted entity based on the PUF-based input, and thereby, the trusted entity authenticates the electronic device by comparing the response with the challenge-response database.
G06Q 20/00 - Payment architectures, schemes or protocols
G06F 21/73 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
G06Q 20/02 - Payment architectures, schemes or protocols involving a neutral third party, e.g. certification authority, notary or trusted third party [TTP]
G06Q 20/32 - Payment architectures, schemes or protocols characterised by the use of specific devices using wireless devices
G06Q 20/40 - Authorisation, e.g. identification of payer or payee, verification of customer or shop credentialsReview and approval of payers, e.g. check of credit lines or negative lists
G07C 9/27 - Individual registration on entry or exit involving the use of a pass with central registration
G09C 1/00 - Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
Presented are average current mode control systems and methods for driving a load with a constant current. In embodiments, this is accomplished when, in response to a zero-current detection circuit detecting a zero current condition in the load current, a compensation circuit is disconnected from a first error amplifier to enable that error amplifier to provide a first voltage to a second error amplifier. The second error amplifier increases a charging current in a capacitor to reduce a dead time in the load current. Similarly, in response to an overcurrent detection circuit detecting an overcurrent condition in the load current, the compensation circuit is disconnected from the first error amplifier to enable the first error amplifier to provide a second voltage to the second error amplifier to decrease the charging current and reduce an overshoot condition.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H05B 45/36 - Circuits for reducing or suppressing harmonics, ripples or electromagnetic interferences [EMI]
Presented are systems and methods for controlling a compensation circuit. In embodiments, a detection circuit receives a set of control signals that have been generated by a control circuit to drive a set of light emitting diode (LED) switches. The switches control a set of LEDs driven by a DC-DC converter that is coupled to a feedback loop to which the compensation circuit is removably coupled. In embodiments, the detection circuit determines whether the status of an LED is about to change and, in response, uses the compensation circuit to control the feedback loop in a manner such as to reduce a current overshoot or current undershoot in the LED current.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H05B 45/36 - Circuits for reducing or suppressing harmonics, ripples or electromagnetic interferences [EMI]
Presented are systems and methods for improving transient response in buck-boost circuits avoid circuit instabilities in both boost mode and buck mode. In embodiments, this is accomplished when, in response to determining that the circuit operates in buck mode, a compensation circuit is adjusted to operate at a first bandwidth. In response to determining that the circuit operates in boost mode, the compensation circuit may then be adjusted to decrease a boost mode crossover frequency and operate at a second, lower bandwidth.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H05B 45/36 - Circuits for reducing or suppressing harmonics, ripples or electromagnetic interferences [EMI]
Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
31.
Power control systems and methods for machine learning computing resources
Described are context-aware low-power systems and methods that reduce power consumption in compute circuits such as commonly available machine learning hardware accelerators that carry out a large number of arithmetic operations when performing convolution operations and related computations. Various embodiments exploit the fact that power demand for a series of computation steps and many other functions a hardware accelerator performs is highly deterministic, thus, allowing for energy needs to be anticipated or even calculated to a certain degree. Accordingly, power supply output may be optimized according to actual energy needs of compute circuits. In certain embodiments this is accomplished by proactively and dynamically adjusting power-related parameters according to high-power and low-power operations to benefit a machine learning circuit and to avoid wasting valuable power resources, especially in embedded computing systems.
A method for controlling a power supply includes (1) generating a current error signal representing a difference between (a) magnitude of an output current of the power supply and (b) magnitude of a reference current value and (2) providing the current error signal for injection into a voltage feedback node of the power supply. A controller for a power supply includes (1) a current control subsystem configured to regulate a magnitude of an output current of the power supply and (2) a voltage control subsystem configured to regulate a magnitude of an output voltage of the power supply, the voltage control subsystem being logically coupled in series with the current control subsystem.
A measurement system and method of manufacture can include: a pressure resistant structure; a pressure inducer coupled to the pressure resistant structure, the pressure inducer having an engaged configuration, the engaged configuration of the pressure inducer increasing pressure exerted on a portion of a user in contact with the pressure resistant structure; a light source coupled to the pressure resistant structure; an optical sensor coupled to the pressure resistant structure and configured to detect a signal from the light source; a pressure sensor coupled to the pressure resistant structure, the pressure sensor configured to detect the pressure exerted on the portion of the user in contact with the pressure inducer; and a processor coupled to the optical sensor and the pressure sensor, the processor configured to correlate volumetric data from the optical sensor with pressure data from the pressure sensor and to provide a blood pressure measurement.
A61B 5/021 - Measuring pressure in heart or blood vessels
A61B 5/00 - Measuring for diagnostic purposes Identification of persons
A61B 5/0225 - Measuring pressure in heart or blood vessels by applying pressure to close blood vessels, e.g. against the skinOphthaldynamometers the pressure being controlled by electric signals, e.g. derived from Korotkoff sounds
34.
Systems and methods to cable shield fault detection and protection
Described are system and method embodiments for establishing a weak ground path, comprising: disabling a first ground path for a shield pin of a cable connection interface, the first ground path including a first switch; enabling a second ground path for the shield pin, the second ground path comprises a second switch, and the second ground path having a higher resistance than the first ground path; determining a connection of a device to the cable connection interface with the second ground path; and enabling the first ground path based on the connection of the device being determined.
H02H 7/22 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for distribution gear, e.g. bus-bar systemsEmergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for switching devices
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
G01R 31/12 - Testing dielectric strength or breakdown voltage
H02H 1/00 - Details of emergency protective circuit arrangements
35.
H-BRIDGE BUCK-BOOST FOR ADAPTIVE DRIVING BEAM HEADLAMPS
Described are light emitting diode (LED) and non-LED driver systems and methods that reduce current overshoot and, deadtime, and other undesirable effects in applications such as adaptive driving beam headlamp application that negatively impact circuit parameters, including efficiency. In certain embodiments, this is accomplished by using a current clamp circuit that is controlled such as to limit an overshoot in load current, e.g., when a number of LEDs that are turned on changes.
H05B 45/54 - Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDsCircuit arrangements for operating light-emitting diodes [LED] responsive to LED lifeProtective circuits in a series array of LEDs
H05B 45/375 - Switched mode power supply [SMPS] using buck topology
H05B 45/38 - Switched mode power supply [SMPS] using boost topology
H05B 45/345 - Current stabilisationMaintaining constant current
An energy-efficient sequencer comprising inline multipliers and adders causes a read source that contains matching values to output an enable signal to enable a data item prior to using a multiplier to multiply the data item with a weight to obtain a product for use in a matrix-multiplication in hardware. A second enable signal causes the output to be written to the data item.
A method for powering driver circuitry for an upper transistor of a half-bridge switching stage includes (1) selectively charging a boot-strap capacitor via a first voltage source such that a voltage at the boot-strap capacitor remains within a predetermined voltage range, (2) clamping the voltage at the boot-strap capacitor to prevent the voltage at the boot-strap capacitor from exceeding a predetermined maximum value, and (3) electrically powering the driver circuitry at least partially via the boot-strap capacitor.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
Systems and methods provide secure, end-to-end high-speed data encoding and communication. In certain embodiments, this is accomplished by modifying a header portion of a data packet received from a first device and complying with a one Mobile Industry Processor Interface (MIPI) protocol to create a modified data packet that complies with a faster MIPI protocol. The header portion of the modified data packet is validated during a tunnel mode operation using an error detection process to validate the modified data packet, which can then be securely transmitted to a second device that complies with the faster MIPI protocol.
An integrated circuit device includes a controller, a voltage source coupled to the controller, a voltage sampler coupled to the controller, a to current detector coupled to the controller and memory coupled to the controller, where memory includes code segments executable by the controller for: (a) measuring a cell voltage to determine an initial voltage; (b) holding the cell voltage at the initial voltage using a power source; and (c) determining the leakage current of the cell by the current provided by the current power source with a low current detector. The power source can be one or both of a voltage source and a current source.
Various embodiments of the invention provide for an AC-coupling method and systems that utilize a nested loop circuit to generate a differential mode output that facilitates an offset compensation and a common mode output that facilitates DC-biasing of an active circuit. In embodiments, the nested loop circuit comprises a differential amplifier and a differential mode loop that generates a differential mode output and a common mode loop that uses a common mode voltage and a reference voltage to generate the common mode output.
Described herein are systems and methods that provide for asymmetric image splitter image stream applications. In one embodiment, a system supporting image multi-streaming comprises an asymmetric image splitter engine that splits super-frame image streams into two or more image streams and a fractional clock divider circuit. The fractional clock divider may comprise a digital feedback control loop and a one-bit sigma delta modulator. The fractional clock divider circuit may provide compatible display clock frequencies for each of the two or more image streams. When a multi-image stream comprises the two image streams, the asymmetric image splitter engine adjusts a vertical asymmetry of a first image stream with a shortest height to same height as a second image stream by adding vertical padding to the first image stream. The super-frame image streams may comprise image streams from video, LIDAR, radar, or other sensors.
H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
H03M 3/00 - Conversion of analogue values to or from differential modulation
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04N 7/10 - Adaptations for transmission by electrical cable
H04N 21/234 - Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
H04N 21/2365 - Multiplexing of several video streams
H04N 21/414 - Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
H03L 7/193 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
42.
Electrical switching systems including constant-power controllers and associated methods
An electrical switching system includes a constant-power controller and a switching device electrically coupled between a first node and a second node. The constant-power controller is configured to (a) generate a digital control signal to control the switching device, (b) control a duration of an active phase of the digital control signal at least partially based on a voltage across the switching device, and (c) control a peak value of the digital control signal to regulate a peak magnitude of current flowing through the switching device.
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
H03K 17/0412 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
43.
VARIABLE INDUCTANCE SYSTEMS AND METHODS FOR HIGH FREQUENCY GAIN CONTROL
Various embodiments of the invention provide amplifier control systems and methods for adjusting a high frequency gain of an amplifier circuit. In certain embodiments, this is accomplished by varying an effective inductance of an amplifier circuit that comprises a first path, which comprises a first cascoded transistor in series with a first inductor and a second cascoded transistor in parallel with the first cascoded transistor. A second path to carry a second current in parallel with the first path comprises a third cascoded transistor that is coupled in series with a second inductor, wherein adjusting comprises maintaining the sum of the first and second currents to be substantively constant when alternating current between the second and third transistors.
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
An angle-of-arrival antenna system uses two orthogonal arrays of patch antenna elements to measure the angle of arrival of a wireless signal irrespective of its polarization. Each antenna element has an antenna patch located over a corresponding ground patch. A shorting wall directly electrically connects one edge of the antenna patch to a corresponding edge of the underlying ground patch. The edge of the ground patch is also directly connected to a system ground plane. No other edges of the ground patch are connected to the system ground plane. The shorting wall acts as an impedance that isolates the ground patch from the system ground plane, and therefore improves isolation between the antenna elements. The antenna system may be constructed using conventional circuit-board fabrication techniques by implementing each shorting wall as an array of plated through-holes or slots.
H01Q 21/24 - Combinations of antenna units polarised in different directions for transmitting or receiving circularly and elliptically polarised waves or waves linearly polarised in any direction
G01S 3/04 - Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic, or electromagnetic waves, or particle emission, not having a directional significance, are being received using radio waves Details
Low-power systems and methods increase computational efficiency in neural network processing by allowing hardware accelerators to perform processing steps on large amounts of data at reduced execution times without significantly increasing hardware cost. In various embodiments, this is accomplished by accessing locations in a source memory coupled to a hardware accelerator and using a resource optimizer that based on storage availability and network parameters determines target locations in a number of distributed memory elements. The target storage locations are selected according to one or more memory access metrics to reduce power consumption. A read/write synchronizer then schedules simultaneous read and write operations to reduce idle time and further increase computational efficiency.
Dynamic data-dependent neural network processing systems and methods increase computational efficiency in neural network processing by uniquely processing data based on the data itself and/or configuration parameters for processing the data. In embodiments, this is accomplished by receiving, at a controller, input data that is to be processed by a first device in a first layer of a sequence of processing layers of a neural network using a first set of parameters. The input data is analyzed to determine whether to modify it, whether processing the (modified) data in a second layer would conserve at least one computational resource, or whether to apply a different set of parameters. Depending on the determination, the sequence of processing layers is modified, and the (modified) data are processed according to the modified sequence to reduce data movements and transitions, thereby, conserving computational resources.
Non-intrusive, low-cost systems and methods allow designers to reduce headroom and safety margin requirements in the context of compute circuits, such as machine learning circuits, without increasing footprint or having to sacrifice computing capacity and other valuable resources. Various embodiments accomplish this by taking advantage of certain properties of machine learning circuits and using a CNN as a diagnostic tool for evaluating circuit behavior and adjusting circuit parameters to fully exploit available computing resources.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G06N 3/04 - Architecture, e.g. interconnection topology
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
48.
Transmitting clock reference over reverse channel in a bidirectional serial link
A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H04L 7/00 - Arrangements for synchronising receiver with transmitter
49.
Narrow pulse widths in h-bridge buck-boost drivers
Described herein are systems and methods for generating short load current pulses using an H-bridge. In various embodiments, this is accomplished by controlling, in a shunting mode, a low-side switch of the H-bridge to drive a first average current and controlling, in a non-shunting mode, a high-side switch of the H-bridge to drive a second average current such that the first and second average currents are substantially the same and reduce a current pulse width of the load current.
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H05B 45/10 - Controlling the intensity of the light
Systems and methods increase computational efficiency in machine learning accelerators. In embodiments, this is accomplished by evaluating, partitioning, and selecting computational resources to uniquely process, accumulate, and store data based on the type of the data and configuration parameters that are used to process the data. Various embodiments, take advantage of the zeroing feature of a Built-In Self-Test (BIST) controller to cause a BIST circuit to create a known state for a hardware accelerator, e.g., during a startup and/or wakeup phase, thereby, reducing data movements and transitions to save both time and energy.
A tracking power supply includes a power conversion subsystem and one or more tracking subsystems. The power conversion subsystem is configured to generate N power rails, where N is an integer greater than one. Each tracking subsystem includes a switching network and a controller. The switching network is electrically coupled between each of the N power rails and a tracking power rail of the tracking power supply. The controller is configured to control operation of the switching network according to a tracking signal associated with a load powered by the tracking power supply, such that a voltage at the tracking power rail is one of two or more values, as determined at least partially based on the tracking signal. The controller is further configured to adjust voltage of at least one of the N power rails.
A digital communication station includes a coupled inductor, driver circuitry, and a digital transceiver. The coupled inductor includes (1) a first winding connected between a first digital communication node and a first power node, (2) a second winding connected between a second digital communication node and a second power node, and (3) a third winding. The driver circuitry is configured to drive the third winding to increase respective inductance values of the first and second windings, and the digital transceiver is communicatively coupled to the first digital communication node and the second digital communication node.
H03H 1/00 - Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
H01F 27/42 - Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors or choke coils
Systems and methods increase power efficiency in communication systems by examining a digital signal to determine whether a threshold corresponding to an increase in a power requirement is likely to be exceeded. The signal is encoded with information indicating the likely change and communicated to a driver that, upon extracting the information, uses it to cause instruct an amplifier to increase a power output to accommodate the increase in power requirement. Once the threshold is no longer exceeded, the driver circuit, advantageously, decreases the power output to conserve energy. In various embodiments, an amplifier may increase power efficiency by switching from a low-power circuit configuration to a high-circuit configuration.
Described are context-aware low-power systems and methods that reduce power consumption in compute circuits such as commonly available machine learning hardware accelerators that carry out a large number of arithmetic operations when performing convolution operations and related computations. Various embodiments exploit the fact that power demand for a series of computation steps and many other functions a hardware accelerator performs is highly deterministic, thus, allowing for energy needs to be anticipated or even calculated to a certain degree. Accordingly, power supply output may be optimized according to actual energy needs of compute circuits. In certain embodiments this is accomplished by proactively and dynamically adjusting power-related parameters according to high-power and low-power operations to benefit a machine learning circuit and to avoid wasting valuable power resources, especially in embedded computing systems.
Circuitry, systems, and methods for fault detection and reporting comprise a fault detection circuit configured to detect one or more fault conditions that cause a state change in a fault pin voltage representative of a transceiver failure. Once the state of the fault pin voltage changes, a transceiver input generates a fault detection code. In embodiments, in response to the transceiver input receiving a first signal, the fault detection code is shifted to a transceiver output that may communicate the fault detection code to a controller. Once the transceiver input receives a second signal, the fault pin voltage may be reset to clear the fault detection code before resuming operations, including detecting additional fault conditions as they arise.
Systems and methods herein use a sensing circuit to detect an overvoltage at a voltage node as a drain current. A current-mode comparator converts the detected current into a control signal, which is provided to a control circuit. The control circuit uses the control signal cut of a bias current to turn off switches in a protection circuit to create a high-impedance electrical path between the voltage node and the to-be-protected voltage node.
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
G01D 3/08 - Measuring arrangements with provision for the special purposes referred to in the subgroups of this group with provision for safeguarding the apparatus, e.g. against abnormal operation, against breakdown
58.
Systems and methods for performing in-flight computations
In-flight operations in an inbound data path from a source memory to a convolution hardware circuit increase computational throughput when performing convolution calculations, such as pooling and element-wise operations. Various operations may be performed in-line within an outbound data path to a target memory. Advantageously, this drastically reduces extraneous memory access and associated read-write operations, thereby, significantly reducing overall power consumption in a computing system.
Storage-efficient, low-cost systems and methods provide embedded systems with the ability to dynamically perform on-device learning to modify or customize a trained model to improve computing and detection accuracy in small-scale devices. In certain embodiments, this is accomplished by repurposing storage elements from inference to training and performing partial back-propagation in embedded devices in the final layers of an existing network. In various embodiments replacing weights in final layers, while using hardware components to iteratively performing forward-propagation calculation, advantageously, reduces the need to store intermediate results, thus, allowing for on-device training without significantly increasing hardware requirements or requiring excessive computational memory resources when compared to conventional machine learning methods.
A method for operating a switching power converter to reduce ripple current magnitude includes controlling duty cycle of a plurality power stages of the switching power converter to regulate at least one parameter of the switching power converter. Each power stage includes a respective power transfer winding that is magnetically coupled to the respective power transfer winding of each other power stage. The method further includes controlling an injection stage of the switching power converter to reduce voltage across a respective leakage inductance of each power transfer winding. The injection stage includes an injection winding that is magnetically coupled to each power transfer winding.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/14 - Arrangements for reducing ripples from DC input or output
61.
SYSTEMS AND METHODS FOR REDUCING POWER CONSUMPTION IN COMPUTE CIRCUITS
Systems and methods allow existing hardware, such as commonly available hardware accelerators to process fully connected network (FCN) layers in an energy-efficient manner and without having to implement additional expensive hardware. Various embodiments, accomplish this by using a “flattening” method that converts a channel associated with a number of pixels into a number of channels that equals the number pixels.
A time of flight sensor includes a time of flight (TOF) processor having a digital TOF port, a digital input port, and a digital output port, the TOF processor comprising a phase detector including cyclically rotating demultiplexer (DEMUX), a first summer coupled to a first DEMUX output, a second summer coupled to a second DEMUX output, a third summer coupled to a third DEMUX output, a fourth summer coupled to a fourth DEMUX output, and a phase estimator coupled to outputs of the first summer, the second summer, the third summer and the fourth summer and having a phase estimate output; a driver having a digital driver port coupled to the digital TOF port and a driver output port; and an analog-to-digital converter (ADC) having an output port coupled to the digital input port of the digital TOF processor.
G01S 7/4913 - Circuits for detection, sampling, integration or read-out
G01S 7/4915 - Time delay measurement, e.g. operational details for pixel componentsPhase measurement
G01S 17/36 - Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated with phase comparison between the received signal and the contemporaneously transmitted signal
A system and method for performing diagnostics of a link capable of measuring a signal pulse having a pulse width that is narrower than a sampling period of a clock signal used for data sampling. The system incorporates a phase interpolator that shifts a phase of the clock signal while preserving the sampling period of the clock signal. The method includes generating and transmitting a plurality of pulses to a link, where then each pulse is sampled according to the clock signal. After each pulse is sampled, the phase interpolator shifts the phase of the clock signal so that each pulse is sampled according to a unique phase, thereby increasing signal measurement accuracy without decreasing the sampling period.
Systems and methods reduce power consumption in embedded machine learning hardware accelerators and enable cost-effective embedded at-the-edge machine-learning and related applications. In various embodiments this may be accomplished by using hardware accelerators that comprise a programmable pre-processing circuit that operates in the same clock domain as the accelerator. In some embodiments, tightly coupled data loading first-in-first-out registers (FIFOs) eliminate clock synchronization issues and reduce unnecessary address writes. In other embodiments, a data transformation may gather source data bits in a manner that allows loading full words of native bus width to reduce the number of writes and, thus, overall power consumption.
Described are context-aware low-power systems and methods that reduce power consumption in compute circuits such as commonly available machine learning hardware accelerators that carry out a large number of arithmetic operations when performing convolution operations and related computations. Various embodiments exploit the fact that power demand for a series of computation steps and many other functions a hardware accelerator performs is highly deterministic, thus, allowing for energy needs to be anticipated or even calculated to a certain degree. Accordingly, power supply output may be optimized according to actual energy needs of compute circuits. In certain embodiments this is accomplished by proactively and dynamically adjusting power-related parameters according to high-power and low-power operations to benefit a machine learning circuit and to avoid wasting valuable power resources, especially in embedded computing systems.
Described herein are systems and methods that prevent against fault injection attacks. In various embodiments this is accomplished by taking advantage of the fact that an attacker cannot utilize a result that has been faulted to recover a secret. By using infective computation, an error is propagated in a loop such that the faulted value will provide to the attacker no useful information or information from which useful information may be extracted. Faults from a fault attack will be so large that a relatively large number of bits will change. As a result, practically no secret information can be extracted by restoring bits.
A system for monitoring and controlling an IC testing machine includes a vibration sensor, a sensor interface, and a processor coupled to the sensor interface. The vibration sensor is in mechanical communication with an IC testing machine to develop an electrical vibration signal representing mechanical vibrations generated by the operation of the IC testing machine. The sensor interface processes the vibration signal to develop vibration data that can be processed by the processor to determine whether the vibration data is indicative of an operational anomaly and, if so, to generate a machine control signal to correct an operation of the IC testing machine. Multiple vibration sensors can be used to increase the amount of vibration data available for analysis.
A current sensing line fault detector includes a unity gain buffer coupling a reference voltage to an IC pin, a current controlled current source coupled to the buffer, a current mode A/D converter developing a digital signal representative of the IC pin current, and logic for determining the state of a transmission line coupled to the IC pin. An alternative current sensing line fault detector includes an OPAMP having a first input coupled to an input node and to a reference current source and having a second input coupled to a reference voltage source. A voltage controlled current source (VCCS) is coupled between the first input of the OPAMP and ground and is controlled by an output of the OPAMP. An A/D converter is coupled to the output of the OPAMP to develop a digital output signal representative of the current flowing through the current sensor.
Described herein are systems and methods for operating DC-DC regulators such as LED drivers. Various embodiments herein allow a DC-DC regulator to switch between buck mode and buck-boost mode without suffering effects otherwise resulting from transient currents when switching between modes. In certain embodiments, this is accomplished by operating the DC-DC regulator in a buck-boost mode to charge a boost capacitor with a substantially constant inductor current. The inductor current is also used to control a set of switches to operate the DC-DC regulator in a buck mode to drive a load by using the capacitor as a power source.
Described herein are systems and methods that perform coarse chromatic dispersion (CD) compensation by applying precomputed coarse front-end equalizer (FEE) tap weights to a receiver based on an assumed propagation distance. After a waiting period, the FEE tap weights are applied, and it is determined whether the FEE tap weights cause a decision-directed tracking of channel rotations to satisfy a stability metric. In response to the stability metric not being satisfied, the assumed propagation distance is adjusted and used to obtain updated FEE tap weights. Conversely, if the stability metric is satisfied, a fine CD compensation is performed that comprises maintaining the updated FEE tap weights; performing an iterative least-mean-squared (LMS) error adaption to adjust Back-End Equalizer (BEE) tap weights and obtain updated BEE tap weights; and using the updated BEE tap weights to adjust the FEE tap weights to, ultimately, have the BEE output an equalized data bit stream.
A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
72.
Resonant power converters including coupled inductors
A resonant power converter includes a capacitive divider circuit, a coupled inductor, and N switching stages, where N is an integer greater than two. The coupled inductor includes N windings, and total leakage inductance of the coupled inductor and equivalent capacitance of the capacitive divider circuit collectively form a resonant tank circuit of the resonant power converter. Each switching stage is electrically coupled between a respective one of the N windings of the coupled inductor and the capacitive divider circuit. The capacitive divider circuit may include one or more resonant capacitors.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 3/00 - Conversion of DC power input into DC power output
H02M 1/36 - Means for starting or stopping converters
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/44 - Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
73.
Solenoid system with position and temperature detection
A solenoid system and method can include: providing an energizing voltage to a coil of a solenoid; providing an AC signal superimposed onto the energizing voltage; detecting current through the coil including an AC current amplitude induced by the AC signal and including a DC offset current amplitude; determining the AC current amplitude is a low AC current amplitude based on an armature within the solenoid being in a retracted position or determining the AC current amplitude is a high AC current amplitude based on the armature being in an extended position with the control logic, and where the AC current amplitude is determined utilizing the AC signal for synchronous demodulation; and determining a temperature fault based on the DC offset current amplitude falling below a DC offset current amplitude threshold.
A sensor offset voltage compensation circuit includes a programmable gain amplifier (PGA) having an input loop configured to receive the signal output by a sensor (e.g., a voltage generated a sensor resistive bridge of a pressure sensor) and an output loop configured to furnish an output signal having a voltage that is greater than the input voltage. An offset compensation voltage is applied to at least one of the input loop or the output loop of the PGA to at least substantially cancel the zero-quantity offset voltage of the sensor from the output voltage.
H03G 3/30 - Automatic control in amplifiers having semiconductor devices
G01L 9/06 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elementsTransmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers of piezo-resistive devices
H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
75.
TWO STAGE VOLTAGE CONVERTER FOR HIGH EFFICIENCY OPERATION
A voltage converter includes: first and second switches having a first voltage rating, the first switch connected between an input voltage and a first node, and the second switch connected between the first node and a potential; a bypass switch connected between the input voltage and a second node; a first inductor connected between the first node and the second node; a first capacitor connected between the second node and the potential; third and fourth switches having a second voltage rating that is less than the first voltage rating, the third switch connected between the second node and a third node, and the fourth switch connected between the third node and the potential; and a switch control module configured to, in response to the input voltage becoming greater than a predetermined voltage: switch the first and second switches and adjust the voltage at the second node toward a target voltage.
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
A power converter is disclosed. The power converter includes a Single-Input-Multiple-Output (SIMO) device includes a first transistor connected to an input and a first end of an inductor, a second transistor connected to a second end of the inductor and a first output, and a third transistor connected to the second end of the inductor and a second output. The power converter also includes a controller connected to the SIMO device and is configured to maintain a minimum inductor current through the inductor between charging cycles and to cause the minimum inductor current to transition to a charging inductor current during a charging cycle. The charging inductor current is based on a difference between an output voltage signal and a target voltage signal.
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
An integrated circuit device includes a controller, an optional current source coupled to the controller, a voltage sampler coupled to the controller, a current detector coupled to the controller, and memory coupled to the controller, where memory includes code segments executable by the controller to: (a) apply a current pulse to a cell; (b) measure a voltage of the cell during the current pulse; (c) calculate an impedance of the cell from the measured voltage; and (d) determine an operational state of the cell from the impedance.
A switching power converter includes an integrated inductor assembly, a first switching stage, and a second switching stage. The integrated inductor assembly includes a magnetic core and first and second windings disposed at least partially in the magnetic core. The second winding is separated from the first winding by a separation portion of the magnetic core. The first switching stage is configured such that a first current flowing from the first switching stage to the first winding induces first magnetic flux flowing through the separation portion of the magnetic core. The second switching stage is configured such that a second current flowing from the second switching stage to the second winding induces second magnetic flux flowing through the separation portion of the magnetic core that opposes the first magnetic flux in the separation portion of the magnetic core.
An angle-of-arrival antenna system uses two orthogonal arrays of patch antenna elements to measure the angle of arrival of a wireless signal irrespective of its polarization. Each antenna element has an antenna patch located over a corresponding ground patch. A shorting wall directly electrically connects one edge of the antenna patch to a corresponding edge of the underlying ground patch. The edge of the ground patch is also directly connected to a system ground plane. No other edges of the ground patch are connected to the system ground plane. The shorting wall acts as an impedance that isolates the ground patch from the system ground plane, and therefore improves isolation between the antenna elements. The antenna system may be constructed using conventional circuit-board fabrication techniques by implementing each shorting wall as an array of plated through-holes or slots.
G01S 3/46 - Systems for determining direction or deviation from predetermined direction using antennas spaced apart and measuring phase or time difference between signals therefrom, i.e. path-difference systems
H01Q 21/08 - Arrays of individually energised antenna units similarly polarised and spaced apart the units being spaced along, or adjacent to, a rectilinear path
H01Q 25/00 - Antennas or antenna systems providing at least two radiating patterns
80.
Switching power converter assemblies including coupled inductors, and associated methods
A coupled inductor includes first and second magnetic rails, a plurality of connecting magnetic elements, and a plurality of windings. The first and second magnetic rails are separated from each other in a first direction, and the first magnetic rail has a first cross-sectional area A1 as seen when viewed in the first direction. Each connecting magnetic element is disposed between the first and second magnetic rails in the first direction. The plurality of connecting magnetic elements collectively have a second cross-sectional area A2 as seen when viewed in the first direction, and a ratio of A2/(A1−A2) is at least 1.5. A respective winding is wound at least partially around each connecting magnetic element.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H01F 17/04 - Fixed inductances of the signal type with magnetic core
Real-time systems and methods prevent duplication of independent signal streams in a coherent receiver subject to source separation controlled by multiplicative coefficients under adaptive feedback control. In various embodiments, this is achieved by first obtaining a first set of coefficients associated with a first signal stream and a second set of coefficients associated with a second signal stream. In response to the sets of coefficients satisfying a condition, the first set modified into a set of coefficients that is mutually orthogonal with respect to and replaces the second set of coefficients. The resulting series of coefficient values may then be used to perform source separation of independent signal streams without duplicating independent signal streams.
Described herein are systems and methods that allow for correcting a residual frequency offset in the GHz frequency range by using low-complexity analog circuit implementations of a broad-band frequency detector that comprises two analog polyphase filters in a dual configuration. Each filter comprises an RC network of cross-coupled capacitors that facilitate filters with opposite passbands and opposite stop-bands. In various embodiments, the outputs of the two filters are combined to obtain power metrics that when subtracted from each other, deliver a measure of the imbalance between the positive and negative halves of a frequency spectrum. Since the measure is substantially proportional to a frequency offset within a linear range spanning 5 GHz or more, the polyphase filters may be used in a broad-band frequency detector that, based on the measure, adjusts the frequency offset.
Dynamic error-quantizer tuning systems and methods prevent misconvergence to local minima by using a dynamic quantizer circuit that controls reference voltages of three or more comparators that are independently adjusted to modify the transfer function of the dynamic quantizer circuit. A weighted sum of the comparator outputs is subtracted from the input to form an error signal in a control loop. The ratio of the reference voltages is chosen to reduce or eliminate local minima during a convergence of the control loop and is set to values that minimize a mean squared error signal with respect to discrete modulation states of the input after the convergence of the control loop is complete.
H04B 10/035 - Arrangements for fault recovery using loopbacks
H04B 10/077 - Arrangements for monitoring or testing transmission systemsArrangements for fault measurement of transmission systems using an in-service signal using a supervisory or additional signal
A method for quickly shutting down a transistor in a switching circuit includes (a) generating a feedback signal associated with current flowing through the transistor, (b) transmitting the feedback signal through an isolating device to a controller, (c) detecting an over-current condition in the switching circuit without transmitting information through the isolating device, and (d) shutting-down the transistor in response to detecting the over-current condition, without transmitting information through the isolating device. A transistor driver includes logic circuitry, an isolating device, driver circuitry configured to drive a transistor according to a control signal received from the logic circuitry via the isolating device, and over-current circuitry configured to (a) detect an over-current condition without receiving information via the isolating device and (b) cause the driver circuitry to shut-down the transistor in response to detection of the over-current condition, without receiving information via the isolating device.
H02H 7/00 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
H02H 9/02 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
85.
Method and circuit assembly for sensorless load detection in stepper motors
A method and a circuit assembly are described with which, in a stepper motor, a mechanical load applied to the motor shaft of which can be detected without a sensor in a voltage-based operating mode in which a nominal coil current is generated by applying a predetermined coil voltage (Us) to the coil. The coil is connected in a bridge branch of a bridge circuit formed from a first to fourth semiconductor switch (S1, . . . S4), wherein the predetermined coil voltage (Us) is applied to the coil with a variable duty cycle (T) by switching the semiconductor switch in the form of at least one PWM voltage (U(A1), U(A2)). The motor load is detected in the form of a load indicator signal (L) which represents a phase shift between a zero crossing of the predefined coil voltage (Us) and the next zero crossing of the coil current (Icoil) generated thereby, wherein a zero crossing of the coil current (Icoil) is defined when, in those time intervals (tm) in which the PWM voltage (U(A1), U(A2)) applied to the coil is zero, a polarity change occurs in a voltage dropping across the internal resistances of the semiconductor switches due to the coil current.
A vertically structured pad system and method can include: a platform having etch attributes, a platform top surface, and a platform side surface; a structure on the platform, the structure including a structure side surface extended up from the platform top surface terminating in a structure top surface, the structure including a structure interior surface defining a cavity within the structure, and the platform top surface exposed from within the cavity; and an interconnect structure adhered to the platform and the structure, the interconnect structure conforming with an exterior shape of the platform side surface in combination with the structure for locking the interconnect structure onto the platform and the structure.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
87.
Power control of powered devices in a system with power over the ethernet
A powered device interface includes a supply sensing circuit, a demand sensing circuit, and a control circuit. The supply sensing circuit is configured to sense an amount of power received by the powered device from at least one power source equipment over an ethernet cable. The demand sensing circuit is configured to sense a power demand requested by the powered device. The control circuit is coupled with the supply sensing circuit and the demand sensing circuit and is configured to cause the power demand requested by the powered device to be reduced when the power demand requested by the powered device exceeds the amount of power allowed by the power source equipment for the powered device.
A powered device interface assembly includes an optocoupler and a powered device interface. The opto-coupler is electrically coupled with a microcontroller of the power device interface. The powered device interface includes a telemetry circuit coupled with the opto-coupler and configured to generate encoded telemetry information for output via a single pin of the powered device interface for transmission to the microcontroller of the powered device, wherein the opto-coupler is coupled with the single pin and is configured to electrically isolate the single pin from the microcontroller.
G06F 1/26 - Power supply means, e.g. regulation thereof
H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water
A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor including a breakdown voltage clamp includes a drain n+ region, a source n+ region, a gate, and a p-type reduced surface field (PRSF) layer including one or more bridge portions. Each of the one or more bridge portions extends below the drain n+ region in a thickness direction. Another LDMOS transistor includes a drain n+ region, a source n+ region, a gate, an n-type reduced surface field (NRSF) layer disposed between the source n+ region and the drain n+ region in a lateral direction, a PRSF layer disposed below the NRSF layer in a thickness direction orthogonal to the lateral direction, and a p-type buried layer (PBL) disposed below the PRSF layer in the thickness direction. The drain n+ region is disposed over the PBL in the thickness direction.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
90.
COUPLED INDUCTORS FOR LOW ELECTROMAGNETIC INTERFERENCE
A coupled inductor for low electromagnetic interference includes a plurality of windings and a composite magnetic core including a coupling magnetic structure formed of a first magnetic material and a leakage magnetic structure formed of a second magnetic material having a distributed gap. The coupling magnetic structure magnetically couples together the plurality of windings, and the leakage magnetic structure provides leakage magnetic flux paths for the plurality of windings.
H01F 27/34 - Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
H01F 38/08 - High-leakage transformers or inductances
H01F 3/10 - Composite arrangements of magnetic circuits
H01F 1/147 - Alloys characterised by their composition
H01F 1/34 - Magnets or magnetic bodies characterised by the magnetic materials thereforSelection of materials for their magnetic properties of inorganic materials characterised by their coercivity of soft-magnetic materials non-metallic substances, e.g. ferrites
Described herein are system and method embodiments for adaptive noise control for headphones, specifically for open-ear headphones. A leakage detection module in an ambient sound control (ASC) circuit implements leakage detection to determine a leakage mode. Based on the determined leakage mode, an ASC profile may create, select or modify an ASC profile for the ASC circuit to operate. Pilot tone, ambient noise, or audio playback may be used respectively or in combination for leakage detection. Experimental results show that embodiments of adaptive ASC approach may achieve improved performance compared to a default ASC, especially under loose fitting of an earphone.
G10K 11/178 - Methods or devices for protecting against, or for damping, noise or other acoustic waves in general using interference effectsMasking sound by electro-acoustically regenerating the original acoustic waves in anti-phase
A charger device includes a Single-Input-Multiple-Output (SIMO) device and a controller. The SIMO device includes a first transistor connected to an input and a first end of an inductor, a second transistor connected to ground and the first end of the inductor, a third transistor connected to a second end of the inductor and a first output, and a fourth transistor connected to the second end of the inductor and a second output. The controller is connected to the SIMO device and is configured to cause the SIMO device to charge the inductor using a first power source coupled to the input during a first time period and discharge the inductor to charge a second power source coupled to the first output during a second time period.
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
The present disclosure relates generally to systems and methods for transient response improvements in electrical circuits. More particularly, the present disclosure relates to systems and methods for suppressing overshoot currents and overshoot durations in circuits using switching regulators, such as driver circuits for LED applications. Embodiments of the invention relate to an LED driver that utilizes transient suppression systems and method for LED applications.
H05B 45/50 - Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDsCircuit arrangements for operating light-emitting diodes [LED] responsive to LED lifeProtective circuits
H05B 45/38 - Switched mode power supply [SMPS] using boost topology
H05B 45/375 - Switched mode power supply [SMPS] using buck topology
Systems and methods provide secure, end-to-end high-speed data encoding and communication. In certain embodiments, this is accomplished by modifying a header portion of a data packet received from a first device and complying with a one Mobile Industry Processor Interface (MIPI) protocol to create a modified data packet that complies with a faster MIPI protocol. The header portion of the modified data packet is validated during a tunnel mode operation using an error detection process to validate the modified data packet, which can then be securely transmitted to a second device that complies with the faster MIPI protocol.
A flux-corrected switching power converter includes a first transformer, a first switching stage, a controller, and a flux correction current source. The first transformer includes a first magnetic core, a first primary winding, and a first secondary winding, and the first switching stage is electrically coupled to the first secondary winding. The controller is configured to control switching of at least the first switching stage. The flux correction current source is electrically coupled to the first primary winding, and the flux correction current source is configured to inject current into the first primary winding to at least partially cancel magnetic flux in the first magnetic core that is generated by current flowing through the first secondary winding.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H01F 27/38 - Auxiliary core membersAuxiliary coils or windings
A switching power converter includes a first switching stage, a second switching stage, a coupled inductor, and a boost winding. The coupled inductor includes a first phase winding, a second phase winding, and a magnetic core. The first phase winding is wound at least partially around a first portion of the magnetic core, and the first phase winding is electrically coupled to the first switching stage. The second phase winding is wound at least partially around a second portion of the magnetic core, and the second phase winding is electrically coupled to the second switching stage. The boost winding forms at least one turn such that mutual magnetic flux associated with each of the first and second phase windings flows through the at least one turn.
H02M 3/04 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
H01F 27/34 - Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
An inductor includes a magnetic core, a first winding, a first electrically conductive standoff, and a second electrically conductive standoff. The magnetic core includes opposing first and second outer surfaces separated from each other in a first direction. The first winding has first and second ends, and the first winding is wound around at least a portion of the magnetic core. The first electrically conductive standoff is connected to the first end of the first winding, and the first electrically conductive standoff extends along the magnetic core in the first direction from the first outer surface to the second outer surface. The second electrically conductive standoff is connected to the second end of the first winding, and the second electrically conductive standoff extends along the magnetic core in the first direction from the first outer surface to the second outer surface.
A controller for a SIMO DC-DC converter operable in CCM and DCM receives a signal representative of an inductor current, and signals representative of a first and a second DC-DC converter output. The controller has a first and second output adapted to control electronic switches coupled to a first and second output filter, and a third and fourth output adapted to control current in an inductor. The controller controls the outputs based upon the inputs by determining a desired PWL inductor current and current waveform, and determines pulsewidths of the outputs, to match the inductor current to the desired PWL. A timer controls pulsewidths of the outputs and the controller dynamically selects DCM or CCM to maintain the first and second DC-DC converter outputs at predetermined levels. In embodiments, the desired PWL inductor current is one or both of a desired valley current and a desired peak current.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/14 - Arrangements for reducing ripples from DC input or output
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
A circuit assembly includes a first substrate including a first outer surface, a first capacitor disposed on the first outer surface, and a first metallic bar. The first capacitor has a first capacitor thickness in a first direction orthogonal to the first outer surface. The first metallic bar has a first bar thickness in the first direction, the first bar thickness being greater than the first capacitor thickness. An electrical load is optionally disposed on a second outer surface of the first substrate over the first metallic bar, in the first direction. The electrical load may be electrically coupled to the first metallic bar.
An audio amplifier employs an idle mode to reduce power consumption and improve efficiency of the amplifier. The audio amplifier comprises a modulator configured to receive an analog input signal. The modulator is operable to convert the analog input signal to differential first and second quantized signals, each having a common mode duty cycle. The modulator causes the common mode duty cycle of each of the first and second quantized signals to be shifted when the level of the analog input signal is below a threshold level so that the common mode duty cycle is one of greater than or less than fifty percent (50%). The amplifier further includes a power stage that receives the first and second quantized signals and generates corresponding first and second output signals configured to drive a load, wherein the first and second output signals switched between a supply voltage and a second voltage based on the respective first and second quantized signals.
H03F 3/217 - Class D power amplifiersSwitching amplifiers
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
