A system may include a sound sensor that may monitor a sound; a camera that may capture one or more of an image or a video; and a device including a processing device. The processing device may classify the sound based on one or more of a security condition or a safety condition using one or more of artificial intelligence (AI) or machine learning (ML), in which the sound may be an intrusion-indicating sound. The processing device may perform analysis of one or more of the image or the video to verify the one or more of the security condition or the safety condition using one or more of AI or ML to detect an object, in which the object may be an intrusion-indicating object. The device may include one or more of an internet gateway or an access point (AP).
An access point (AP) may include a processing device. The processing device may detect, at the AP, a failure of a first network link. The processing device may determine, at the AP, a path to a second network link. The processing device may activate, at the AP, a backup long-range wireless communication device when the failure of the first network link is detected, in which the backup long-range wireless communication device facilitates a connection to the second network link. The processing device may connect, at the AP, to the second network link using the backup long-range wireless communication device.
A device may include a processing device. The processing device may receive, at the device from an internet of things (IoT) device, one or more of an artificial intelligence (AI) task or a machine learning (ML) task. The processing device may receive, at the device from an IoT device, input data related to the one or more of the AI task or the ML task. The processing device may perform, at the device, the one or more of the AI task or the ML task using the input data to generate output data. The processing device may send, from the device to the IoT device, the output data.
A method may include obtaining input symbols and a hash table. The method may also include storing the input symbols in a first buffer at a current coding position, and processed input symbols in a second buffer. The method may further include defining a plurality of delayed match window (DMW) offsets, comprising a highest DMW offset and at least one lower DMW offset. The method may also include performing a substring match search using the input symbols, the processed input symbols, and the highest DMW offset, to determine one or more candidate matches. The method may further include outputting a result from the substring match search corresponding to a determination associated with the one or more candidate matches.
A system and method for selectively retiming signals in a high-performance network. The system includes a smart repeater circuit with input and output crossbars and retimers configured to recondition high-loss channels while bypassing low-loss channels. A sniffing mechanism dynamically assesses channel quality and adjusts routing configurations. In an advanced electrical circuit switch (AECS) system, the smart repeater integrates digital signal processors (DSPs) and analog crossbars, utilizing out-of-band (OOB) signaling for configuration, channel routing, and fault-tolerant operations. A method for channel assessment includes sequentially connecting a sniffer to input channels in a round-robin manner, evaluating channel metrics, and routing signals based on the assessments. Feedback from output channels, via in-band (IB) or OOB signaling, is used to refine routing configurations. These features support high-performance applications, providing selective retiming and dynamic signal management.
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
A system and method for selectively retiming signals in a high-performance network. The system includes a smart repeater circuit with input and output crossbars and retimers configured to recondition high-loss channels while bypassing low-loss channels. A sniffing mechanism dynamically assesses channel quality and adjusts routing configurations. In an advanced electrical circuit switch (AECS) system, the smart repeater integrates digital signal processors (DSPs) and analog crossbars, utilizing out-of-band (OOB) signaling for configuration, channel routing, and fault-tolerant operations. A method for channel assessment includes sequentially connecting a sniffer to input channels in a round-robin manner, evaluating channel metrics, and routing signals based on the assessments. Feedback from output channels, via in-band (IB) or OOB signaling, is used to refine routing configurations. These features support high-performance applications, providing selective retiming and dynamic signal management.
A system may include a first access point (AP), a second AP, one or more first stations (STAs), and one or more second STAs. The first AP may be operable to transmit a first NDP. The second AP may be operable to transmit a second NDP. The first STAs may be associated with the first AP, and may be operable to transmit first channel state information (CSI) to the first AP and the second AP in response to obtaining a first beamforming report poll (BFRP) from the first AP. The second STAs may be associated with the second AP, and may be operable to transmit second CSI to the first AP and the second AP in response to obtaining a second BFRP from the second AP. The first NDP and the second NDP may be transmitted at non-overlapping time intervals.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04B 7/024 - Co-operative use of antennas at several sites, e.g. in co-ordinated multipoint or co-operative multiple-input multiple-output [MIMO] systems
8.
BROADCASTING AND MULTICASTING MECHANISMS IN A SWITCH DEVICE
A switch device may include: a first electronic device including a plurality of ports to facilitate communication via a plurality of lanes; a plurality of second electronic devices comprising a second plurality of ports, wherein the second electronic devices are operable to communicate with the first electronic device via the plurality of lanes; and a switch controller. The switch controller may: dynamically map the plurality of lanes from at least one port of the first electronic device to one or more ports of the second plurality of ports of the plurality of second electronic devices; facilitate simultaneous broadcasting of data from the at least one port of the first electronic device to a plurality of ports of the second electronic devices; and enable multicasting by selectively mapping data from the at least one port of the first electronic device to a predefined subset of ports in the second electronic devices.
A system may include a first access point (AP), a second AP, one or more first stations (STAs), and one or more second STAs. The first AP may be operable to transmit a first NDP. The second AP may be operable to transmit a second NDP. The first STAs may be associated with the first AP, and may be operable to transmit first channel state information (CSI) to the first AP and the second AP in response to obtaining a first beamforming report poll (BFRP) from the first AP. The second STAs may be associated with the second AP, and may be operable to transmit second CSI to the first AP and the second AP in response to obtaining a second BFRP from the second AP. The first NDP and the second NDP may be transmitted at non-overlapping time intervals.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
A method includes obtaining, by a data transform accelerator, a first command and first source data associated with the first command. The method also includes generating, by the data transform accelerator, one or more containers using the first command. Each of the one or more containers may have a container size and may be operable to store compressed source data. The method further includes obtaining a mode of operation for a data compression operation. The method also includes performing the data compression operation to a first portion of the first source data using the mode of operation to obtain the compressed source data. The method further includes storing the compressed source data in a first container of the one or more containers.
A device includes a plurality of digital signal processors (DSPs), analog crossbars in communication with the DSPs, and a switch controller. The switch controller facilitates control signals using in-band signaling within payload traffic or out-of-band signaling over a dedicated management interface. The system supports dynamic traffic prioritization based on real-time metrics, such as latency and traffic load, ensuring efficient resource allocation and seamless operation during congestion or reconfiguration. Redundant crossbars and failover mechanisms enhance fault tolerance, while granular backpressure selectively throttles traffic flows to prevent bottlenecks. Integrated diagnostic tools monitor performance and optimize traffic flow, enabling high-speed and reliable communication.
Systems and methods for seamless network communication reconfiguration, comprising a device that includes physical media dependent (PMD) devices, incorporating a digital signal processor (DSP) configured to handle both in-band and out-of-band communication traffic, a plurality of primary analog crossbars connected to the DSPs for routing operational data, and a set of redundant analog crossbars configured to establish auxiliary communication channels. The system includes a controller operable to dynamically activate the auxiliary communication channels during reconfiguration events, enabling a make-before-break protocol by transitioning traffic from primary channels to auxiliary channels. The redundant crossbars support out-of-band signaling to coordinate transitions and maintain system integrity. The auxiliary channels remain in a low-power state during steady operation, ensuring resource efficiency, while the controller monitors signal integrity and initiates reconfiguration upon detecting a fault or network event, maintaining uninterrupted traffic flow.
A device includes a plurality of digital signal processors (DSPs) and analog crossbars in communication with the DSPs. The DSPs and crossbars dynamically adjust power consumption based on traffic load and/or a signal quality, leveraging traffic prediction models to optimize resource allocation. The system supports features such as powering down unused lanes, asymmetrically deactivating transmission or receiving lanes, and preemptively scaling resources during predicted traffic increases. Dynamic voltage and frequency scaling (DVFS) optimizes power usage based on link utilization and traffic priority, minimizing latency impacts during transitions. The switch controller integrates traffic prioritization algorithms, including weighted round-robin (WRR), to allocate power and bandwidth efficiently to high-priority traffic flows. Redundant crossbars handle overflow traffic or failover scenarios, transitioning between standby and active states dynamically.
A device includes digital signal processors (DSPs) and analog crossbars in communication with the DSPs. The analog crossbars are operable to dynamically adjust equalization settings based on real-time feedback from DSPs, physical media-dependent (PMD) devices, or environmental sensors. Equalization adjustments optimize signal quality by compensating for traffic conditions, environmental changes, or signal degradation. The crossbars support predictive equalization using machine learning algorithms to preemptively adjust signal properties, ensuring performance across dynamic network environments. Diagnostics and logging capabilities monitor and refine equalization performance, while auxiliary in-band channels provide low-power pathways to reduce energy consumption. These features enable efficient, high-speed data transmission with enhanced reliability and adaptability in modern networking systems.
H04L 49/101 - Packet switching elements characterised by the switching fabric construction using crossbar or matrix
H04L 41/0816 - Configuration setting characterised by the conditions triggering a change of settings the condition being an adaptation, e.g. in response to network events
Technology for a device includes a plurality of digital signal processors (DSPs) and a plurality of analog crossbars in communication with the DSPs. The DSPs dynamically adjust queues to optimize data flow based on traffic conditions, latency, and resource availability. Queues may include input queues, output queues, virtual output queues, or hybrid configurations, supporting techniques such as priority scheduling and time-division multiplexing (TDM). The DSPs facilitate flow control through granular backpressure signaling, managing congestion between DSPs and endpoints. Synchronization of queues during crossbar reconfiguration ensures seamless traffic flow and prevents data loss. Advanced mechanisms, such as dynamic queue depth adjustment and adaptive prioritization, enable efficient resource sharing while maintaining high throughput. The device leverages these features to provide scalable, energy-efficient networking solutions for complex environments, such as data centers and telecommunication system
A device may include a die-to-die (D2D) interconnect. The D2D interconnect may receive first data at a first port and transmit second data from a second port. One or more of a voltage or a bias of the D2D interconnect may be dynamically adapted based on target link performance.
A device includes a plurality of digital signal processors (DSPs) and analog crossbars in communication with the DSPs. The analog crossbars dynamically switch between multiple inputs and outputs and adjust configurations based on real-time feedback from the DSPs. The crossbars use amplification to enhance signal strength at input and output stages, ensuring signal integrity across long transmission paths or during multicasting and broadcasting operations. Real-time adaptive equalization optimizes performance in response to environmental changes or signal degradation. The crossbars facilitate system management traffic through out-of-band signaling and support failover with redundant paths to maintain communication during failures. Synchronization with DSPs or a switch controller is achieved through shared clock signals or IEEE 1588. These features enable efficient, high-speed data transmission while maintaining robust performance and reliability in dynamic network environments.
A device may include a plurality of digital signal processors (DSPs) and a plurality of analog crossbars connected to the DSPs. A microcontroller unit may be operable to facilitate network isolation.
Technology for a device may include a plurality of digital signal processors (DSPs); and a plurality of analog crossbars operable to be connected to the plurality of DSPs. The timing between the plurality of DSPs may be synchronized.
A digital signal processors (DSPs) and analog crossbars operatively connected to the DSPs includes a method for synchronization and distributed processing. The DSPs are configured to coordinate traffic among themselves, enabling efficient data flow and resource allocation. This coordination may involve synchronization, traffic management, and resource arbitration to optimize performance and minimize latency. The device facilitates seamless communication and supports dynamic reconfiguration, making it suitable for high-speed networking and scalable systems.
A device includes a plurality of digital signal processors (DSPs) and analog crossbars operable to connect with the DSPs. A switch controller facilitates control signaling between the DSPs and the crossbars, enabling dynamic coordination of traffic flow, resource allocation, and crossbar configurations. The device supports integrated in-band (IB) and out-of-band (OOB) communication, proactive monitoring of signal metrics for failover prediction, and synchronization techniques to minimize latency and ensure system coherence. The architecture further incorporates load balancing, fault tolerance, and distributed control mechanisms to optimize performance in high-speed network environments.
A multi-channel decoder circuit associated with a multi-channel decoder system is disclosed. The multi-channel decoder circuit comprises a distributed decoder circuit comprising a set of unit decoder circuits, each unit decoder circuit configured to receive one or more codewords of a plurality of codewords associated with a plurality of input channels, and decode the one or more codewords. The multi-channel decoder circuit further comprises a distribution controller circuit configured to distribute each incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits within the distributed decoder circuit, based on determining a currently available unit decoder circuit within the set of unit decoder circuits.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
H04L 12/28 - Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Downloadable computer software for vector quantization and data compression in the field of machine learning and artificial intelligence (AI); Downloadable data compression software; Computer hardware Digital compression of data for use in the field of neural network models, memory, storage as related to machine learning and artificial intelligence (AI); Software as a service (SAAS) services featuring software for vector quantization and data compression in the field of machine learning and artificial intelligence (AI); Digital compression of computer data
An access point (AP) may include a processing device. The processing device may receive, at the AP, a video performance capture. The processing device may identify, at the AP, metadata relating to the video performance capture. The processing device may determine, at the AP, a gateway setting based on the video performance capture and the metadata.
A modem may include a processing device. The processing device may monitor, at the modem, a downstream spectrum for performance data. The processing device may determine, at the modem, when the performance data is greater than a threshold. The processing device may send, from the modem to a converged cable access platform (CCAP) core, the performance data when the performance data is greater than the threshold.
An access point (AP) may include a transceiver and a processing device. The transceiver may be operable to facilitate communications with a station (STA). The processing device may be operable to allocate first bandwidth in a first operating band and second bandwidth in a second operating band to the STA. The processing device may also be operable to switch traffic to the STA between the first operating band and the second operating band. The first operating band may be one or more of a 2.4 GHz band, a 5 GHz band, or a 6 GHz band. The second operating band may be one or more of a 2.4 GHz band, a 5 GHz band, or a 6 GHz band. The first operating band may be different from the second operating band.
An access point (AP) may include a transceiver and a processing device. The transceiver may be operable to facilitate communications with a station (STA). The processing device may be operable to allocate first bandwidth in a first operating band and second bandwidth in a second operating band to the STA. The processing device may also be operable to switch traffic to the STA between the first operating band and the second operating band. The first operating band may be one or more of a 2.4 GHz band, a 5 GHz band, or a 6 GHz band. The second operating band may be one or more of a 2.4 GHz band, a 5 GHz band, or a 6 GHz band. The first operating band may be different from the second operating band.
An access point (AP) may include a transceiver and a processing device. The processing device may be operable to obtain, from the transceiver, multiple received signal strength indicators (RSSIs) from multiple devices in an area. The processing device may also be operable to generate a mapping of wireless local area network (WLAN) performance across the area using the multiple RSSIs. The processing device may further be operable to generate a user instruction based on the mapping.
Device, Apparatus, Method and Computer Programs for a Network Gateway, Server, Server Apparatus, Server Method, System, Router, Mobile Device, Vehicular Gateway and Cloud Server
A device for controlling a network gateway comprises at least one network interface configured to communicate in at least one computer network. The device further comprises a processing module configured to at least partially execute at least a first software module and a second software module. The first software module is configured to provide a gateway functionality of the network gateway via the at least one network interface. A functionality of the second software module is different from the gateway functionality of the first software module. The second software module is encapsulated from the first software module.
H04L 67/00 - Network arrangements or protocols for supporting network services or applications
G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
An example method may include determining a multi-user packet error rate associated with communications from a client device to a host device, the multi-user packet error rate based on a number of packets in a multi-user communication frame with an error. The method may also include sending a trigger from the host device to the client device to communicate via a second multi-user communication frame, the trigger identifying a transfer rate based on the multi-user packet error rate.
Technology is disclosed for an optical receiver. The optical receiver may include an optical and digital signal processing (ODSP) device. The ODSP device may include a photodiode operable to convert an optical signal to an electrical signal; a digital signal processor operable to generate a digital signal based on the electrical signal; a quantization component operable to generate a quantized output signal based on the digital signal; and a processing device. The processing device may be operable to measure one or more signal statistics of the digital signal; and identify one or more quantization thresholds, wherein the one or more quantization thresholds are computed based on the one or more signal statistics.
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04B 17/309 - Measuring or estimating channel quality parameters
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
32.
AUGMENTED SWITCH CAPACITY, REDUNDANT CROSSBARS, AND FAILOVER MECHANISMS IN CROSSBAR SYSTEMS
Technology for a device is disclosed. The device may include a plurality of digital signal processors (DSPs). The device may include a plurality of analog crossbars operable to be connected to the plurality of DSPs. The device may include a set of redundant analog crossbars operable to be connected to the plurality of DSPs. The set of redundant analog crossbars may be operable to provide one or more of additional input lanes or additional output lanes when failover occurs.
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
33.
DIGITAL SIGNAL PROCESSOR (DSP) INTEGRATION OF LAYER 2/3 PROTOCOLS AND CROSSBAR CONTROL IN NETWORK SWITCHING
A device may include a processor operable to process one or more of layer 2(L2) or layer 3 (L3) protocols in which the processor includes handling of one or more of frame headers, frame boundaries, media access control (MAC) addresses, or internet protocol (IP) addresses. The device may have a MAC address and an IP address associated with the device. The device may be operable to receive and process data packets addressed to the MAC or the IP address of the device. The device may be operable to interface with layer 1(L1) devices, including layer 1 systems and physical transceivers (PHYs).
H04L 61/103 - Mapping addresses of different types across network layers, e.g. resolution of network layer into physical layer addresses or address resolution protocol [ARP]
Technology for a device used for time division multiplexing is disclosed. The device may include a plurality of digital signal processors (DSPs). The device may include a plurality of analog crossbars operable to be connected to the plurality of DSPs. The plurality of analog crossbars may be operable to: receive, at one or more input ports of the plurality of analog crossbars, input data from the plurality of DSPs; and send, from an output port of the plurality of analog crossbars, time-division multiplexed (TDM) output data.
A device may include a first plurality of electronic devices comprising a plurality of ports operable to facilitate communications via a plurality of lanes; a second plurality of electronic devices operable to communicate with the first plurality of electronic devices via the plurality of lanes; and a third plurality of electronic devices operable to communicate with the second plurality of electronics devices via a plurality of connections.
An access point may include a transceiver and a processing device. The transceiver may be operable to communicate with at least on station. The processing device may be operable to determine distributed resource units for the station to use for transmissions with the access point. The processing device may also be operable to estimate a channel between the access point and the at least one station. The processing device may further be operable to determine beamforming coefficients based on the estimated channel. The processing device may also be operable to transmit the beamforming coefficients and an uplink data frame to the at least one station. The processing device may further be operable to obtain a beamforming-triggered distributed resource unit transmission from the at least one station.
An access point (AP) may include a transceiver and a processing device. The transceiver may be operable to communicate with at least a second AP and at least a first station (STA). The processing device may be operable to transmit a null data packet announcement and a joint null data packet from the AP and the second AP. The processing device may also be operable to request a sounding feedback from the first STA. The processing device may further be operable to obtain a channel estimation feedback from the second AP. The processing device may also be operable to perform a precoder calculation using the sounding feedback and the channel estimation feedback. The processing device may further be operable to provide the precoder calculation to the second AP.
H04B 7/0456 - Selection of precoding matrices or codebooks, e.g. using matrices for antenna weighting
H04B 7/024 - Co-operative use of antennas at several sites, e.g. in co-ordinated multipoint or co-operative multiple-input multiple-output [MIMO] systems
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04L 5/00 - Arrangements affording multiple use of the transmission path
38.
FAST TRANSIENT FEED FORWARD RESPONSE FOR AN INTEGRATED CIRCUIT
A system and method for multiphase or single-phase power control is disclosed herein. The system may include a hysteretic window generator. The hysteretic window generator may dynamically set and modulate a lower voltage threshold and an upper voltage threshold for phases of the multiphase power control based on an operating condition. Switching power supply (SPS) stages may correspond to the multiple phases. The SPS stages may be coupled to the hysteretic window generator. A fast transient addition may be coupled to the hysteretic window generator and activated by a transient load condition of one of the plurality of SPS stages. The fast transient addition may output a non-linear step adjustment to a control voltage of one of the plurality of SPS, thereby reducing a settling time and return to a predefined voltage level.
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output voltage with controlled ripple current. The buck converter may include one or more main buck converter stages and one or more suppression buck converter stages coupled with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents to reduce ripple currents generated in the one or main buck converter stages.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H03M 1/14 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
40.
IMON RECONSTRUCTION VIA KALMAN FILTER IN DIGITAL QUAD CONTROLLER
A system for switching power supply is disclosed herein. The system may include a controller and a plurality of switching power supplies. The controller may include a processing device. The processing device may determine a monitored current of at least one switching power supply of the plurality of switching power supply, and determine, based on the monitored current, an induction prediction. The processing device may determine, a voltage input prediction corresponding to the at least one switching power supply, and output, by the controller, the voltage input prediction to the at least one switching power supply.
An access point may include a transceiver and a processing device. The transceiver may be operable to communicate with at least on station. The processing device may be operable to determine distributed resource units for the station to use for transmissions with the access point. The processing device may also be operable to estimate a channel between the access point and the at least one station. The processing device may further be operable to determine beamforming coefficients based on the estimated channel. The processing device may also be operable to transmit the beamforming coefficients and an uplink data frame to the at least one station. The processing device may further be operable to obtain a beamforming-triggered distributed resource unit transmission from the at least one station.
H04W 72/044 - Wireless resource allocation based on the type of the allocated resource
H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
Methods and systems describe herein relate to a reconfigurable multi-radio bridge that may connect a local area network (LAN) with an access point (AP) or other WAP to the backhaul and may dynamically change and/or select transmission methods. An example implementation of a reconfigurable multi-radio bridge performs a method including discovering a topology of a network that includes one or more wireless stations (STAs), evaluating a metric for each of at least two routes discovered in the topology, receiving a packet that identifies a first STA of the one or more STAs as an intended destination of the packet, selecting a route of the at least two routes over which to send the packet based on the metric, and sending the packet from a reconfigurable multi-radio bridge over the selected route toward the first STA.
An access point (AP) may include a transceiver and a processing device. The transceiver may be operable to communicate with at least a second AP and at least a first station (STA). The processing device may be operable to transmit a null data packet announcement and a joint null data packet from the AP and the second AP. The processing device may also be operable to request a sounding feedback from the first STA. The processing device may further be operable to obtain a channel estimation feedback from the second AP. The processing device may also be operable to perform a precoder calculation using the sounding feedback and the channel estimation feedback. The processing device may further be operable to provide the precoder calculation to the second AP.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
A method may include detecting parameter(s) of communication between an AP and a STA. The method may include determining a training configuration for a channel estimation of the communication based on the parameter(s). The method may include transmitting a DL transmission or a trigger frame to the STA. The DL transmission may include a training block configured according to the training configuration. The trigger frame may include the training configuration and instructions for the STA to include a training block configured according to the training configuration in a UL transmission to the AP. The STA may be configured to determine the channel estimation of a channel of the communication using the training block of the DL transmission received at the STA. Alternatively, the method may also include determining the channel estimation of a channel of the communication using the training block of the UL transmission received at the AP.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
An example device may include an antenna node configured to be coupled to an antenna element. The antenna node may be configured to pass wireless communications over multiple frequency bands. The device may also include multiple signal paths coupled to the antenna node. Each of the multiple signal paths may be configured to carry a signal from a different one of the multiple frequency bands. The device may further include a switch element coupled to the antenna node by the multiple signal paths and an amplifier circuit within the multiple signal paths between the switch element and the antenna node. The amplifier circuit may be configured to amplify the signals carried by the multiple signal paths.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
H04B 1/48 - Transmit/receive switching in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter
46.
MULTI-ACCESS POINT (AP) COORDINATED TIME DIVISION MULTIPLE ACCESS (TDMA) RESTRICTED TO SPECIFIC TRAFFIC
An access point (AP) may include a processing device. The processing device may: identify, at the AP, a traffic condition; determine, at the AP, a coordinated time division multiple access (C-TDMA) status based on the traffic condition; and compute, at the AP, a transmission opportunity based on the C-TDMA status. The AP may include a transceiver. The transceiver may transmit, from the AP, a transmission using the transmission opportunity when the C-TDMA status indicates C-TDMA usage.
A method may include determining characteristics associated with a host device and a data transform accelerator. The method may also include adjusting a command field for interrupt management in a command to be transmitted from the host device to the data transform accelerator, which may be based on the characteristics. The method may further include obtaining transformed data from the data transform accelerator based on the command.
Example operations may include initiating wireless transmission of a first data frame of data designated for wireless transmission. The wireless transmission of the first data frame may be via a first wireless signal packet configured to carry the data of the first data frame. The operations include directing termination of the wireless transmission of the first data frame via the first wireless signal packet prior to wireless transmission, via the first wireless signal packet, of all of the data of the first data frame. In addition, the operations include directing, in response to termination of transmission of the first data frame, wireless transmission of a termination signal, the termination signal indicating that transmission of the first data frame via the first wireless signal packet terminated prior to completion of transmission of all of the data of the first data frame via the first wireless signal packet.
Example implementations are directed to methods and systems employing a solicited sounding protocol that includes an efficient communication sequence for operating a wireless transceiver transmitting a sounding trigger to one or more beamformees via a forward channel, receiving at least one dedicated training signal from the one or more beamformees via a reverse channel in response to the sounding trigger, and for each of the received dedicated training signal. The method also includes estimating forward CSI derived based on the dedicated training signal from an associated beamformee; and where subsequent packets are precoded with precoding derived from the forward CSI for transmission to the associated beamformee via the forward channel. Example aspects including scheduling multiple dedicated training signals from one or more beamformees based on a single sounding trigger.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
An access point (AP) may include a processing device. The processing device may: identify, at the AP, a traffic condition; determine, at the AP, a coordinated time division multiple access (C-TDMA) status based on the traffic condition; and compute, at the AP, a transmission opportunity based on the C-TDMA status. The AP may include a transceiver. The transceiver may transmit, from the AP, a transmission using the transmission opportunity when the C-TDMA status indicates C-TDMA usage.
An access point (AP) may include a processing device. The processing device may generate, at the AP, a training set including historical downstream traffic; train, at the AP, a neural network using the training set; receive, at the AP, downstream traffic; and classify, at the AP, the downstream traffic using the neural network.
H04W 28/02 - Traffic management, e.g. flow control or congestion control
H04L 47/2408 - Traffic characterised by specific attributes, e.g. priority or QoS for supporting different services, e.g. a differentiated services [DiffServ] type of service
An access point may include a processing device configured to: identify a puncturing pattern for a channel width of a physical layer protocol data unit (PPDU) of a transmit signal; compute one or more tone rotation patterns using one or more tone rotation pattern parameters; and select a tone rotation pattern of the one or more tone rotation patterns based on the puncturing pattern for the channel width to minimize a peak to average power ratio (PAPR) of the transmit signal. The access point may include a transceiver configured to transmit the transmit signal to a wireless device based on the tone rotation pattern.
A receiver circuit is disclosed and is configured to receive an optical signal. The receiver circuit includes a receiving circuit configured to receive the optical signal and convert the optical signal from a duobinary signal format into a binary signal based on a plurality of decision thresholds. The receiver circuit also includes a clock data recovery circuit configured to sample the binary signal per data period at a first time instant based on a predetermined clock data recovery technique, and sample the binary signal per data period at a second time instant offset from the first instant, as well as determine an intermediate sample based on an offset for decoding a transmitted bit sequence according to soft information based on the samples.
A method may include identifying an application operable to submit one or more commands to a data transform accelerator. The method may also include determining one or more classes of service utilized with at least one bank of data transform engines in the data transform accelerator. The method may further include estimating a workload to be transmitted to the data transform accelerator. In response to the workload satisfying a threshold and interrupt control being enabled in the at least one bank of data transform engines, the method may also include configuring interrupt control for the one or more classes of service.
A method may include obtaining input data to be compressed by a compression operation. The method may also include obtaining metadata associated with the input data to be compressed by the compression operation. The method may further include determining a data threshold of the input data and the metadata to be compressed by the compression operation. The method may also include preprocessing the metadata. The method may further include arranging the input data and the metadata based on the data threshold. The method may also include performing the compression operation on the arranged input data and the arranged metadata.
A method may include obtaining input data to be compressed by a compression operation. The method may also include obtaining metadata associated with the input data to be compressed by the compression operation. The method may further include determining a data threshold of the input data and the metadata to be compressed by the compression operation. The method may also include preprocessing the metadata. The method may further include arranging the input data and the metadata based on the data threshold. The method may also include performing the compression operation on the arranged input data and the arranged metadata.
An access point (AP) for wireless communication may include data processing hardware; and memory hardware in communication with the data processing hardware, the memory hardware storing instructions that when executed on the data processing hardware cause the data processing hardware to perform operations including: identifying, at the AP, one or more transmitting stations having one or more spatial streams; sending, from the AP to the one or more transmitting stations, a sounding request; performing, at the AP, multiple user multiple input multiple output (MU-MIMO) channel estimation based on the sounding request response; computing, at the AP, one or more precoder coefficients for the one or more transmitting stations based on the MU-MIMO channel estimation; and sending, from the AP to the one or more transmitting stations, the one or more precoder coefficients and a transmission trigger.
A station (STA) may include a processing device. The processing device may select, at a STA for transmission to an access point (AP), a long training field (LTF) mode in which the LTF mode is 4×LTF. The processing device may select, at the STA for the transmission to the AP, a first guard interval having a value of less than 3.2 μs in which the first guard interval is used for one or more of training symbols or data symbols. The STA may include a transceiver. The transceiver may transmit, from the STA to the AP, the transmission using the LTF mode and the first guard interval. The transceiver may transmit, from the STA to the AP, the transmission using one or more distributed resource units (DRUs).
A station (STA) may include a processing device. The processing device may select, at a STA for transmission to an access point (AP), a long training field (LTF) mode in which the LTF mode is 4x LTF. The processing device may select, at the STA for the transmission to the AP, a first guard interval having a value of less than 3.2 µs in which the first guard interval is used for one or more of training symbols or data symbols. The STA may include a transceiver. The transceiver may transmit, from the STA to the AP, the transmission using the LTF mode and the first guard interval. The transceiver may transmit, from the STA to the AP, the transmission using one or more distributed resource units (DRUs).
An access point (AP) may include a processing device. The processing device may identify, at the AP, a first portion of a wireless local area network (WLAN) frame and a second portion of a WLAN frame, in which the first portion of the WLAN frame may include a first set of one or more codewords having a first protection level and the second portion of the WLAN frame may include a second set of one or more codewords having a second protection level. The processing device may select, at the AP, a first forward error correction (FEC) setting for the first portion of the WLAN frame to facilitate the first protection level, and select, at the AP, a second FEC setting for the second portion of the WLAN frame to facilitate the second protection level.
According to an aspect of an embodiment, a method may include obtaining a first signal at a first port of a communication system. The first signal may include a combination of an incident signal and a reflected signal. The method may include performing a first processing to the first signal. In response to the first processing, the method may include performing a second processing to the first signal. The method may include estimating a voltage standing wave ratio (VSWR) associated with a transmission line from results of the second processing to the first signal.
For critical path monitoring in an integrated circuit (IC), a system includes a data flip-flop configured to receive a data input and a clock input, and generate a first data output and a first clock output. A data delay path generates a delayed data output. An output flip-flop, coupled to the data delay path generates a second data output and a second clock output. A time-to-digital converter (TDC), coupled to the data delay path, includes a comparator bank that compares the delayed data output against reference levels and generates a code. An encoder, coupled to the comparator bank converts the code into a binary code representing the time delay. A minimum delay search coupled to the TDC includes a control circuit, configured to dynamically adjust the supply voltage and other parameters of the IC based on the timing margins and delay settings identified by the minimum delay search.
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
A gateway may include a processing device. The processing device may: receive, at the gateway, data using a data over cable service interface specification (DOCSIS) protocol in which the data is received using a first quality of service (QoS) operation; identify, at the gateway, the first QoS operation for the DOCSIS protocol; determine, at the gateway, a second QoS operation for a wireless local area network (WLAN) protocol; and send, from the gateway to a station (STA), the data using the WLAN protocol in which the data is sent using the second QoS operation.
H04L 12/28 - Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
H04L 12/66 - Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
H04L 41/5009 - Determining service level performance parameters or violations of service level contracts, e.g. violations of agreed response time or mean time between failures [MTBF]
64.
CANCELLATION OF PASSIVE INTERMODULATION FROM MULTIPLE SOURCES
A system includes a receiver (RX) configured to receive an RX output signal in an RX band, where the RX output signal has a first passive intermodulation (PIM) source in the RX band and a second PIM source in the RX band; and a processing device configured to: receive the RX output signal from the receiver on an RX path, receive a crest factor reduction (CFR) output signal from a CFR on a transmit (TX) path, identify the first PIM source and the second PIM source based on the RX output signal and the CFR output signal, calibrate the CFR output signal based on the first and second PIM sources in the RX output signal to generate a non-linear actuation (NA) input signal, and generate an intermodulation distortion signal by using an NA function on the NA input signal.
H04B 1/525 - Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
A critical path tracking system for an integrated circuit (IC) is described. The system may include a real critical path with a first set of combinatorial logic receiving data and clock inputs, generating a first output. The system may include a replica critical path with a second set of combinatorial logic replicating the first set, generating a second output. Capture flip-flops (CFFs) may be coupled to paths, capturing the first and second outputs at different points. A programmable delay element may introduce adjustable delays to the second output. A multiplexer may select between the first and delayed outputs for the CFFs, and a comparator may generate a path failure signature by comparing the outputs. A control circuit may dynamically adjust the delay settings and the IC's supply voltage based on the path failure signature. A software loop may read the signature, analyze timing margins, and control the circuit.
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A gateway may include a processing device. The processing device may: receive, at the gateway, data using a data over cable service interface specification (DOCSIS) protocol in which the data is received using a first quality of service (QoS) operation; identify, at the gateway, the first QoS operation for the DOCSIS protocol; determine, at the gateway, a second QoS operation for a wireless local area network (WLAN) protocol; and send, from the gateway to a station (STA), the data using the WLAN protocol in which the data is sent using the second QoS operation.
An access point (AP) may include a processing device. The processing device may identify, at the AP, a first portion of a wireless local area network (WLAN) frame and a second portion of a WLAN frame, in which the first portion of the WLAN frame may include a first set of one or more codewords having a first protection level and the second portion of the WLAN frame may include a second set of one or more codewords having a second protection level. The processing device may select, at the AP, a first forward error correction (FEC) setting for the first portion of the WLAN frame to facilitate the first protection level, and select, at the AP, a second FEC setting for the second portion of the WLAN frame to facilitate the second protection level.
H04B 7/0456 - Selection of precoding matrices or codebooks, e.g. using matrices for antenna weighting
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 1/16 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
A critical path tracking system for an integrated circuit (IC) is described. The system may include a real critical path with a first set of combinatorial logic receiving data and clock inputs, generating a first output. The system may include a replica critical path with a second set of combinatorial logic replicating the first set, generating a second output. Capture flip-flops (CFFs) may be coupled to paths, capturing the first and second outputs at different points. A programmable delay element may introduce adjustable delays to the second output. A multiplexer may select between the first and delayed outputs for the CFFs, and a comparator may generate a path_failure_signature by comparing the outputs. A control circuit may dynamically adjust the delay settings and the IC's supply voltage based on the path failure signature. A software loop may read the signature, analyze timing margins, and control the circuit.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H02M 7/5395 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
69.
SYSTEM AND METHODS FOR CRITICAL PATH TRACKING SYSTEM-ON-CHIP
For critical path monitoring in an integrated circuit (IC), a system includes a data flip-flop configured to receive a data input and a clock input, and generate a first data output and a first clock output. A data delay path generates a delayed data output. An output flip-flop, coupled to the data delay path generates a second data output and a second clock output. A time-to-digital converter (TDC), coupled to the data delay path, includes a comparator bank that compares the delayed data output against reference levels and generates a code. An encoder, coupled to the comparator bank converts the code into a binary code representing the time delay. A minimum delay search coupled to the TDC includes a control circuit, configured to dynamically adjust the supply voltage and other parameters of the IC based on the timing margins and delay settings identified by the minimum delay search.
According to an aspect of an embodiment, a base station configured for beamforming estimation in a massive multiple input multiple output (mMIMO) radio access network (RAN) (mMIMO-RAN) may comprise a processing device and a transceiver. The processing device may be configured to obtain a channel estimate for a user equipment (UE). The processing device may be configured to compute a first power level adjustment for a downlink (DL) signal and a second power level adjustment for the DL signal. The second power level adjustment may be based on a power constraint. The transceiver may be configured to transmit the DL signal to the UE.
H04W 52/14 - Separate analysis of uplink or downlink
H04L 5/00 - Arrangements affording multiple use of the transmission path
H04W 52/24 - TPC being performed according to specific parameters using SIR [Signal to Interference Ratio] or other wireless path parameters
H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
71.
DISTORTION-OPTIMIZED TRANSMISSION IN HYBRID FIBER COAX NETWORKS
A node circuit associated with a hybrid fiber coax (HFC) network is disclosed. The node circuit includes an optimizer circuit configured to process a plurality of signal-to-noise ratio (SNR) values associated with a plurality of subcarriers, respectively, associated with a set of cable modem (CM) circuits coupled to the node circuit. In some embodiments, at least one subcarrier is allocated to the set of CM circuits for communication with the node circuit. In some embodiments, the optimizer circuit is further configured to determine an optimal transmit power of the node circuit, based on the plurality of SNR values and a transmitter distortion of a transmitter circuit associated with the node circuit. In some embodiments, the transmitter distortion defines a transmitter distortion associated with the transmitter circuit in terms of a total transmit power of the node circuit.
A coded signal is received via a physical link and decoded. A link loss of the physical link is detected based on at least one of the coded signal and said decoding.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H04B 3/32 - Reducing cross-talk, e.g. by compensating
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04M 11/06 - Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
A method for reducing receive band leakage may include: sensing, at a full duplexer, passive intermodulation distortion and power amplifier distortion; generating, at a processing device, a passive intermodulation distortion and power amplifier distortion cancellation signal; and cancelling, on a receive path, the passive intermodulation distortion and power amplifier distortion using the passive intermodulation distortion and power amplifier distortion cancellation signal.
Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.
A method for reducing receive band leakage may include: sensing, at a full duplexer, passive intermodulation distortion and power amplifier distortion; generating, at a processing device, a passive intermodulation distortion and power amplifier distortion cancellation signal; and cancelling, on a receive path, the passive intermodulation distortion and power amplifier distortion using the passive intermodulation distortion and power amplifier distortion cancellation signal.
H04B 1/525 - Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex
H04B 1/12 - Neutralising, balancing, or compensation arrangements
Technology is disclosed for a system. The system may include a system-on-chip (SoC) including one or more physical media dependent (PMD) devices, in which the one or more PMD devices are associated with one or more digital signal processors (DSPs), in which the one or more DSPs operate one or more crossbar switches; a central crossbar switch facilitating communication between the one or more DSPs; and a control unit operable to manage a configuration of the one or more crossbar switches based on a lookup table, in which the lookup table facilitates data routing between an input and an output.
Technology is disclosed for a system. The system may include a system-on-chip (SoC) including one or more physical media dependent (PMD) devices, in which the one or more PMD devices are associated with one or more digital signal processors (DSPs), in which the one or more DSPs operate one or more crossbar switches; a central crossbar switch facilitating communication between the one or more DSPs; and a control unit operable to manage a configuration of the one or more crossbar switches based on a lookup table, in which the lookup table facilitates data routing between an input and an output.
A method may include obtaining, by a hardware, multiple data packets. The method may also include storing, by the hardware, the multiple data packets in an internal memory. The method may further include allocating, by a firmware, a contiguous portion of external memory. The method may also include determining, by the firmware, a particular flow and a segment number associated with individual data packets of the multiple data packets. The method may further include storing, by the firmware, the individual data packets in the external memory to create an aggregated data packet. The storing may be based on the particular flow and the segment number. The method may also include transmitting, by the firmware, the aggregated data packet to a host CPU for processing.
H04L 41/0853 - Retrieval of network configurationTracking network configuration history by actively collecting configuration information or by backing up configuration information
H04L 43/10 - Active monitoring, e.g. heartbeat, ping or trace-route
A method may include obtaining multiple tunable parameters associated with a data transform accelerator operable to perform data transform operations. The method may also include configuring a resource configuration vector based on the multiple tunable parameters. The method may further include obtaining a target performance metric. The method may also include measuring one or more performance metrics associated with the data transform accelerator. The method may further include automatically tuning at least one tunable parameter of the multiple tunable parameters to obtain tuned parameters in response to a performance metric of the one or more performance metrics failing to satisfy the target performance metric. The method may also include updating the resource configuration vector in view of the tuned parameters.
A method may include obtaining, by a hardware, multiple data packets. The method may also include storing, by the hardware, the multiple data packets in an internal memory. The method may further include allocating, by a firmware, a contiguous portion of external memory. The method may also include determining, by the firmware, a particular flow and a segment number associated with individual data packets of the multiple data packets. The method may further include storing, by the firmware, the individual data packets in the external memory to create an aggregated data packet. The storing may be based on the particular flow and the segment number. The method may also include transmitting, by the firmware, the aggregated data packet to a host CPU for processing.
A method may include obtaining multiple tunable parameters associated with a data transform accelerator operable to perform data transform operations. The method may also include configuring a resource configuration vector based on the multiple tunable parameters. The method may further include obtaining a target performance metric. The method may also include measuring one or more performance metrics associated with the data transform accelerator. The method may further include automatically tuning at least one tunable parameter of the multiple tunable parameters to obtain tuned parameters in response to a performance metric of the one or more performance metrics failing to satisfy the target performance metric. The method may also include updating the resource configuration vector in view of the tuned parameters.
09 - Scientific and electric apparatus and instruments
Goods & Services
Semiconductors; semiconductor chips; Computer hardware and downloadable network configuration software and integrated circuit chips for providing access to the Internet through a wireline broadband access network, wireless mobile network, wireless and wireline networks, wireless LAN, ethernet and power line communications; semiconductors for use in transceivers for broadband communications; semiconductor devices used to enable broadband communications; integrated circuits; cards with integrated circuits; embedded multimedia LAN (local area network) operating software for providing communications and geolocation, sold as an integral component in non-medical sensors and gaming devices; computer hardware with embedded multimedia network configuration software for operating and creating video displays, power management and power regulation sold as an integral component of consumer and infrastructure electronics devices in the nature of receivers and transceivers, computers, automotive electronics in the nature of step down regulators; semiconductors and downloadable software for use in mobile wireless infrastructure for operating wireless communication access, wireless backhaul and user equipment; semiconductors for use in datacenter communications, computation, storage and accelerators; integrated circuit evaluation kits comprised of an integrated circuit, auxiliary computer hardware, power regulators and power managers being step down regulators, receivers and transceivers, external memory cards, I/O computer hardware and interfaces being transceivers and receivers used to interface, control and test the integrated circuit; downloadable computer operating software used for accessing the Internet through a wireline broadband access network
83.
CARRIER SENSE MULTIPLE ACCESS (CSMA) WITH ENHANCED COLLISION AVOIDANCE
A station (STA) may include a processing device. The processing device may perform, at the STA, an arbitration inter-frame spacing (AIFS) backoff. The processing device may perform, at the STA, a carrier-sense multiple access (CSMA) contention window (CW) backoff. The processing device may send, at the STA, a first short signal when reaching a CSMA CW backoff end. The processing device may perform, at the STA, a first short backoff after sending the first short signal. The processing device may send, at the STA, a frame after an nth short signal has been sent and an nth short backoff has occurred in which n is an integer greater than or equal to 2.
H04L 12/413 - Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
H04W 74/0808 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA]
H04W 16/00 - Network planning, e.g. coverage or traffic planning toolsNetwork deployment, e.g. resource partitioning or cell structures
H04B 17/309 - Measuring or estimating channel quality parameters
H04W 24/02 - Arrangements for optimising operational condition
H04J 3/16 - Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
An access point may include a processing device. The processing device may generate, at the AP, a transmission including a preamble including a physical layer (PHY) version identifier (ID) defined by a first Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard. The processing device may generate, at the AP, the transmission including the preamble including one or more signaling bits defined by a second IEEE 802.11 standard. The access point may include a transceiver. The transceiver may send, at the AP to a station (STA), the transmission including the preamble.
A method includes determining an address associated with a data transform command in a container data structure which is in the data transform accelerator. The data transform accelerator is in communication with a host computing unit. In response to a determination that the address is in the container data structure, the method includes accessing the data transform command based on the address. The data transform command is in the host computing unit. The method includes obtaining metadata based on information in the data transform command. The metadata is in the data transform accelerator or spread out in the host computing unit memory and in the memory of data transform accelerator. The method includes configuring a data transform pipeline based on the metadata. The metadata can be shared in its entirety or partially by multiple data transform commands grouped together.
A station (STA) may include a processing device. The processing device may perform, at the STA, an arbitration inter-frame spacing (AIFS) backoff. The processing device may perform, at the STA, a carrier-sense multiple access (CSMA) contention window (CW) backoff. The processing device may send, at the STA, a first short signal when reaching a CSMA CW backoff end. The processing device may perform, at the STA, a first short backoff after sending the first short signal. The processing device may send, at the STA, a frame after an nth short signal has been sent and an nth short backoff has occurred in which n is an integer greater than or equal to 2.
An access point may include a processing device. The processing device may generate, at the AP, a transmission including a preamble including a physical layer (PHY) version identifier (ID) defined by a first Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard. The processing device may generate, at the AP, the transmission including the preamble including one or more signaling bits defined by a second IEEE 802.11 standard. The access point may include a transceiver. The transceiver may send, at the AP to a station (STA), the transmission including the preamble.
System and methods are disclosed for hybrid phase detection and clock recovery in a serializer/deserializer (SerDes) receiver. The system enables a clock recovery unit (CRU) to dynamically operate in either a Mueller-Muller Phase Detection (MMPD) mode or an Alexander Phase Detection (APD) mode using shared circuit components. The CRU includes data and error slicers configured to generate phase error signals based on a received data stream, with the phase detector adapting the recovered clock signal accordingly. The system utilizes adjustable reference voltage levels and signal gating logic to repurpose MMPD hardware to emulate APD functionality without impacting high-speed data paths. Such architecture supports various interleaving configurations, including even-odd and n-way time-interleaved designs, and enables on-the-fly mode switching based on channel conditions or baud rate requirements.
System and methods are disclosed for hybrid phase detection and clock recovery in a serializer/deserializer (SerDes) receiver. The system enables a clock recovery unit (CRU) to dynamically operate in either a Mueller-Muller Phase Detection (MMPD) mode or an Alexander Phase Detection (APD) mode using shared circuit components. The CRU includes data and error slicers configured to generate phase error signals based on a received data stream, with the phase detector adapting the recovered clock signal accordingly. The system utilizes adjustable reference voltage levels and signal gating logic to repurpose MMPD hardware to emulate APD functionality without impacting high-speed data paths. Such architecture supports various interleaving configurations, including even-odd and n-way time-interleaved designs, and enables on-the-fly mode switching based on channel conditions or baud rate requirements.
H03M 13/25 - Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
An access point (AP) may include a processing device. The processing device may identify, at the AP, one or more of sounding data, channel state information (CSI), beamforming matrix, or round trip timing (RTT) for a station (STA). The processing device may compute, at the AP, a location for the STA based on the one or more of the sounding data, the CSI, the beamforming matrix, or the RTT in which the location may be computed relative to a geo-fence. The processing device may compute, at the AP, a network access for the STA based on the location relative to the geo-fence.
H04W 64/00 - Locating users or terminals for network management purposes, e.g. mobility management
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04L 41/16 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using machine learning or artificial intelligence
H04W 4/021 - Services related to particular areas, e.g. point of interest [POI] services, venue services or geofences
An access point (AP) may include a processing device. The processing device may identify, at the AP, one or more of sounding data, channel state information (CSI), beamforming matrix, or round trip timing (RTT) for a station (STA). The processing device may compute, at the AP, a location for the STA based on the one or more of the sounding data, the CSI, the beamforming matrix, or the RTT in which the location may be computed relative to a geo-fence. The processing device may compute, at the AP, a network access for the STA based on the location relative to the geo-fence.
Methods are disclosed for fiber to the room (FTTR). A method may include receiving, at an access point from a station (STA), a modulated signal. The method may include sending, from the access point to a multimedia over coaxial alliance (MoCA) device, the modulated signal. The method may include sending, from the MoCA device to an optical front end, the modulated signal.
Methods are disclosed for fiber to the room (FTTR). A method may include receiving, at an access point from a station (STA), a modulated signal. The method may include sending, from the access point to a multimedia over coaxial alliance (MoCA) device, the modulated signal. The method may include sending, from the MoCA device to an optical front end, the modulated signal.
An access point (AP) may include a processing device. The processing device may send, from the AP to a first-generation station (STA), a first generation beacon in a first duration in a first subset of a first frequency segment. The processing device may send, from the AP to a second-generation STA, a second generation beacon in the first duration in a second subset of a second frequency segment. The processing device may receive, at the AP from the first-generation (STA), a first single user packet in a second duration in the first frequency segment. The processing device may receive, at the AP from the second-generation STA, a second single user packet in a third duration in the second frequency segment.
An access point (AP) may include a processing device. The processing device may send, from the AP to a first-generation station (STA), a first generation beacon in a first duration in a first subset of a first frequency segment. The processing device may send, from the AP to a second-generation STA, a second generation beacon in the first duration in a second subset of a second frequency segment. The processing device may receive, at the AP from the first-generation (STA), a first single user packet in a second duration in the first frequency segment. The processing device may receive, at the AP from the second-generation STA, a second single user packet in a third duration in the second frequency segment.
A device may include one or more of a transmit path, a receive path, or an optical interface receiver. The transmit path may include an electrical-optical interface that may receive an electrical signal and send an optical signal. The receive path may include a trans-impedance amplifier (TIA) that may send a bypass signal. The optical interface receiver may be coupled to the receive path. The optical interface receiver may sense the bypass signal.
H03F 3/08 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
H04B 10/69 - Electrical arrangements in the receiver
A system may include a first link including a first digital signal processor (DSP), a first optical receiver, and a first optical transmitter. The system may include a second link including a second DSP, a second optical receiver, and a second optical transmitter. The second DSP may be coupled to the first DSP using one or more of an active electrical cable or an active optical cable. The second DSP may communicate with the first DSP using one or more forward error correction (FEC) padding bits or one or more reserved bits.
A system may include a first link including a first digital signal processor (DSP), a first optical receiver, and a first optical transmitter. The system may include a second link including a second DSP, a second optical receiver, and a second optical transmitter. The second DSP may be coupled to the first DSP using one or more of an active electrical cable or an active optical cable. The second DSP may communicate with the first DSP using one or more forward error correction (FEC) padding bits or one or more reserved bits.
A device may include one or more of a transmit path, a receive path, or an optical interface receiver. The transmit path may include an electrical-optical interface that may receive an electrical signal and send an optical signal. The receive path may include a trans-impedance amplifier (TIA) that may send a bypass signal. The optical interface receiver may be coupled to the receive path. The optical interface receiver may sense the bypass signal.
H04B 10/25 - Arrangements specific to fibre transmission
G02B 6/42 - Coupling light guides with opto-electronic elements
H03F 3/08 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
Technology is disclosed for an access point (AP). The access point may include a processing device. The processing device may identify, at the AP, a peer-to-peer (P2P) group comprising a first station (STA) and a second STA. The processing device may generate, at the AP, a shared gained transmission opportunity (TXOP) for the first STA and the second STA. The processing device may send, from the AP to the first STA and second STA, a trigger frame including the shared gained TXOP.
