Trench-gate MOSFETs use a N+ SiC substrate with a N SiC drift layer. A Si wafer is bonded to the top of the SiC wafer, forming a Si/SiC heterojunction at the interface. Gate trenches are formed in the Si layer, oxidized, and filled with a conductor. Since the gate oxide is only in contact with the Si, and not the SiC, there is no problem with carbon at the gate oxide interface. Also, since the MOSFET is formed in the Si layer, electron mobility near the gates is high. JFET channel regions in the SiC layer pinch off during short circuit, high current conditions to limit drain current and thus achieve a higher short circuit withstand time capability. At the Si/SiC interface, a thin, highly doped n-type layer is formed in the SiC layer that allows tunneling current flowing through the barrier to lower the voltage drop across the heterojunction.
H10D 62/822 - Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
A SiC vertical power switch is formed with planar polysilicon gates. For forming the source metal contact opening over the N+ sources, the large difference in oxidation rates of the planar polysilicon gate and the SiC surface of the N+ source is utilized. A blanket (no mask) oxidation step forms a relatively thick oxide layer over the top of the polysilicon gates and along the side edges of the polysilicon gates, while the oxide formed over the exposed SiC source regions is much thinner. A short blanket etch (no mask) is then used to remove the very thin oxide layer over the source regions. The source metal is then deposited over the insulated gates and the exposed N+ source, where the source metal is self-aligned to the gate so as to have a very repeatable and optimally minimum spacing for a maximum cell density.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
3.
SELF-ALIGNED SOURCE CONTACT FOR SIC SWITCH UTILIZING OXIDATION RATE DIFFERENCE BETWEEN POLY-SI AND SIC
A SiC vertical power switch is formed with planar polysilicon gates. For forming the source metal contact opening over the N+ sources, the large difference in oxidation rates of the planar polysilicon gate and the SiC surface of the N+ source is utilized. A blanket (no mask) oxidation step forms a relatively thick oxide layer over the top of the polysilicon gates and along the side edges of the polysilicon gates, while the oxide formed over the exposed SiC source regions is much thinner. A short blanket etch (no mask) is then used to remove the very thin oxide layer over the source regions. The source metal is then deposited over the insulated gates and the exposed N+ source, where the source metal is self-aligned to the gate so as to have a very repeatable and optimally minimum spacing for a maximum cell density.
A vertical MOSFET has an N-type SiC drift layer connected to a drain electrode. An overlying Si layer creates an n-N heterojunction at the top of the SiC drift layer. A P-well layer and N+ source regions are formed in the Si layer. Trenched gates are formed in the Si layer that invert the P-well to create a conductive path between the Si source regions and the SiC drift region. JFET channel regions and gate regions are formed in the SiC layer for improving reliability of the MOSFET under reverse voltage conditions and under short circuit conditions. The SiC drift layer results in a higher breakdown voltage, lower on-resistance, and improved thermal conductivity, and the upper Si layer retains its higher channel mobility and stability and high gate drive efficiency.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A vertical trench MOSFET is formed with deep P-shield regions below portions of each gate trench. The deep P-shield regions are effectively downward extensions of the P-body/well, and are electrically coupled to the top source electrode. The P-shield regions abut the bottom portions and lower sides of the gate trenches, so that those small portions of the gate trench do not create N-channels and do not conduct current. Accordingly, each trench comprises an active gate portion that creates an N-channel and a small non-active portion that abuts the P-shield regions. The spacing of the P-shield regions along each gate trench is selected to achieve the desired electric field spreading to protect the gate oxide from punch-through. No field plate trenches are needed to be formed in the active area of the MOSFET. The deep P-shield regions may be formed in trench areas that are deeper than the active gate trench areas.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A vertical MOSFET has an N-type drift layer over an N+ substrate. A horizontal JFET layer overlies the drift layer, where the JFET layer has P-type gate regions and N-type channel regions. A first N-type layer overlies the JFET layer. A P-type well layer overlies the first N-type layer. Gate trenches are formed through the P-type well layer and into the first N-type layer. N-type source regions abut the top areas of the gate trenches, and a source electrode contacts the source regions. The JFET N-type channel regions are generally directly below the gate trenches for conducting a vertical current when the MOSFET is in an on state. The source electrode is electrically connected to the JFET P-type gate regions via a deep P-type contact region. The JFET N-type channel regions pinch off during short circuit high current conditions to limit drain current.
A vertical trench MOSFET is formed with deep P-shield regions below portions of each gate trench. The deep P-shield regions are effectively downward extensions of the P-body/well, and are electrically coupled to the top source electrode. The P-shield regions abut the bottom portions and lower sides of the gate trenches, so that those small portions of the gate trench do not create N-channels and do not conduct current. Accordingly, each trench comprises an active gate portion that creates an N-channel and a small non-active portion that abuts the P-shield regions. The spacing of the P-shield regions along each gate trench is selected to achieve the desired electric field spreading to protect the gate oxide from punch-through. No field plate trenches are needed to be formed in the active area of the MOSFET. The deep P-shield regions are formed by implanting P-type dopants through the bottom of the trenches.
A vertical trench MOSFET is formed with deep P-shield regions below portions of each gate trench. The deep P-shield regions are effectively downward extensions of the P-body/well, and are electrically coupled to the top source electrode. The P-shield regions abut the bottom portions and lower sides of the gate trenches, so that those small portions of the gate trench do not create N-channels and do not conduct current. Accordingly, each trench comprises an active gate portion that creates an N-channel and a small non-active portion that abuts the P-shield regions. The spacing of the P-shield regions along each gate trench is selected to achieve the desired electric field spreading to protect the gate oxide from punch-through. No field plate trenches are needed to be formed in the active area of the MOSFET. The deep P-shield regions are formed by implanting P-type dopants through the bottom of the trenches.
A vertical transistor structure in which a recessed field plate trench surrounds multiple adjacent gate electrodes. Thus the specific on-state conductance is increased, since the ratio of recessed field plate area to channel area is reduced. Various versions use two, three, or more distinct gate electrodes within the interior of a single RFP or RSFP trench's layout.
A vertical transistor structure in which a recessed field plate trench surrounds multiple adjacent gate electrodes. Thus the specific on-state conductance is increased, since the ratio of recessed field plate area to channel area is reduced. Various versions use two, three, or more distinct gate electrodes within the interior of a single RFP or RSFP trench's layout.
A split gate power device is disclosed having a trench containing a U-shaped gate that, when biased above a threshold voltage, creates a conductive channel in a p-well. Below the gate is a field plate in the trench, coupled to the source electrode, for spreading the electric field along the trench to improve the breakdown voltage. The top gate poly is initially formed relatively thin so that it can be patterned using non-CMP techniques, such as dry etching or wet etching. As such, the power device can be fabricated in conventional fabs not having CMP capability. In one embodiment, the thin gate has vertical and lateral portions that create conductive vertical and lateral channels in a p-well. In another embodiment, the thin gate has only vertical portions along the trench sidewalls for minimizing surface area and gate capacitance.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/41 - Electrodes characterised by their shape, relative sizes or dispositions
13.
Split gate power device and its method of fabrication
A split gate power device is disclosed having a trench containing a U-shaped gate that, when biased above a threshold voltage, creates a conductive channel in a p-well. Below the gate is a field plate in the trench, coupled to the source electrode, for spreading the electric field along the trench to improve the breakdown voltage. The top gate poly is initially formed relatively thin so that it can be patterned using non-CMP techniques, such as dry etching or wet etching. As such, the power device can be fabricated in conventional fabs not having CMP capability. In one embodiment, the thin gate has vertical and lateral portions that create conductive vertical and lateral channels in a p-well. In another embodiment, the thin gate has only vertical portions along the trench sidewalls for minimizing surface area and gate capacitance.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
15.
Trench transistors and methods with low-voltage-drop shunt to body diode
Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
Structures and fabrication methods for increasing the density of trench transistor devices and the like. During fabrication of a trench transistor device, a vertical protrusion (or hat) of oxide is left in place above the gate trench. This vertical protrusion is self-aligned to the gate trench, and is used to define the positions of sidewall spacers (made e.g. of silicon nitride). These sidewall spacers define a space outward from the edge of the gate trench; by performing a recess etch which is delimited by these sidewall spacers, the resistance of the source contact and the body contact is minimized. The spacing between the gate trench and the recessed-contact field-plate trench can therefore be minimized and well controlled, which improves density without degrading on-resistance nor breakdown voltage.
A new semiconductor rectifier structure. In general, a MOS-transistor-like structure is located above a JFET-like deeper structure. The present application teaches ways to combine and optimize these two structures in a merged device so that the resulting combined structure achieves both a low forward voltage and a high reverse breakdown voltage in a relatively small area. In one class of innovative implementations, an insulated (or partially insulated) trench is used to define a vertical channel in a body region along the sidewall of a trench, so that majority carriers from a “source” region (typically n+) can flow through the channel. An added “pocket” diffusion, of the same conductivity type as the body region (p-type in this example), provides an intermediate region around the bottom of the trench. This intermediate diffusion, and an additional deep region of the same conductivity type, define a deep JFET-like device which is in series with the MOS channel portion of the diode. This advantageously permits the MOS channel portion to be reasonably short, and to have a reasonably low threshold voltage, since the high-voltage withstand characteristics are defined by the deep JFET-like device.
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
A new semiconductor rectifier structure. A MOS-transistor-like structure is generally located above a JFET-like deeper structure. The present application teaches ways to combine and optimize these two structures in a merged device so that the resulting combined structure achieves both low forward voltage and high reverse breakdown voltage in a relatively small area. In one class of innovative implementations, an insulated (or partially insulated) trench is used to define a vertical channel in a body region along the sidewall of a trench, so that majority carriers from a "source" region (typically n+) can flow through the channel. An added "pocket" diffusion, of the same conductivity type as the body region (p-type in this example), provides an intermediate region around the bottom of the trench. This intermediate diffusion, and an additional deep region of the same conductivity type, define a deep JFET-like device which is in series with the MOS channel portion of the diode. This advantageously permits the MOS channel portion to be reasonably short, and to have a reasonably low threshold voltage, since the high-voltage withstand characteristics are defined by the deep JFET-like device.
Heterostructure and double-heterostructure trench-gate devices, in which the substrate and/or the body are constructed of a narrower-bandgap semiconductor material than the uppermost portion of the drift region. Fabrication most preferably uses a process where gate dielectric anneal is performed after all other high-temperature steps have already been done.
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
21.
Lateral transistors and methods with low-voltage-drop shunt to body diode
Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
In one embodiment, a power MOSFET or IGBT cell includes an N-type drift region grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed over the drift region. A P-well is formed over the N-type layer, and an N+ source/emitter region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into a trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction in the N-type layer along the sidewalls of the trench to reduce on-resistance. A vertical shield field plate is also in the trench and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. Floating P-islands in the N-type drift region increase breakdown voltage and reduce the saturation current.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
In one embodiment, a power MOSFET or IGBT cell includes an N-type drift region grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed over the drift region. A P-well is formed over the N-type layer, and an N+ source/emitter region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into a trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction in the N-type layer along the sidewalls of the trench to reduce on-resistance. A vertical shield field plate is also in the trench and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. Floating P-islands in the N-type drift region increase breakdown voltage and reduce the saturation current.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
25.
POWER MOSFET HAVING PLANAR CHANNEL, VERTICAL CURRENT PATH, AND TOP DRAIN ELECTRODE
In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well' s lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
A silicon carbide (or comparable) trench transistor in which gate dielectric anneal, in an oxynitriding atmosphere, is performed after all other high-temperature steps have already been done.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
29.
Power MOSFET having lateral channel, vertical current path, and P-region under gate for increasing breakdown voltage
In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
30.
Vertical power transistor with deep trenches and deep regions surrounding cell array
Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
34.
Vertical power transistor with deep floating termination regions
Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.
Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
In one embodiment, a RESURF structure between a source and a drain in a lateral MOSFET is formed in a trench having a flat bottom surface and angled sidewalls toward the source. Alternating P and N-type layers are epitaxially grown in the trench, and their charges balanced to achieve a high breakdown voltage. In the area of the source, the ends of the P and N-layers angle upward to the surface under the lateral gate and contact the body region. Thus, for an N-channel MOSFET, a positive gate voltage above the threshold forms a channel between the source and the N-layers in the RESURF structure as well as creates an inversion of the ends of the P-layers near the surface for low on- resistance. In another embodiment, the RESURF structure is vertically corrugated by being formed around trenches, thus extending the length of the RESURF structure for a higher breakdown voltage.
In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
39.
Lateral power MOSFET with non-horizontal RESURF structure
In one embodiment, a RESURF structure between a source and a drain in a lateral MOSFET is formed in a trench having a flat bottom surface and angled sidewalls toward the source. Alternating P and N-type layers are epitaxially grown in the trench, and their charges balanced to achieve a high breakdown voltage. In the area of the source, the ends of the P and N-layers angle upward to the surface under the lateral gate and contact the body region. Thus, for an N-channel MOSFET, a positive gate voltage above the threshold forms a channel between the source and the N-layers in the RESURF structure as well as creates an inversion of the ends of the P-layers near the surface for low on-resistance. In another embodiment, the RESURF structure is vertically corrugated by being formed around trenches, thus extending the length of the RESURF structure for a higher breakdown voltage.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
40.
Power device having a polysilicon-filled trench with a tapered oxide thickness
In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
41.
Semiconductor device with electric field relaxation portion in insulating layer between lower and upper trench electrodes
A semiconductor device according to the present invention includes a semiconductor layer having a trench, a first insulating film formed along an inner surface of the trench, and an upper electrode and a lower electrode embedded in the trench via the first insulating film and disposed above and below a second insulating film. An electric field relaxation portion that relaxes an electric field arising between the upper electrode and the semiconductor layer is provided between a side surface of the trench and a lower end portion of the upper electrode.
Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
45.
Methods of operating power semiconductor devices and structures
Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
46.
REVERSE-CONDUCTING GATED-BASE BIPOLAR-CONDUCTION DEVICES AND METHODS WITH REDUCED RISK OF WARPING
Reverse-conducting IGBTs where the collector side includes diode terminal regions, and the semiconductor material is much thicker through the diode terminal regions than it is through the collector regions. This exploits the area fraction which is taken up by the diode terminal regions to provide increased rigidity for the wafer, and thus avoid warping.
A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Semiconductors Research, design, engineering, and development of technology solutions for power management and consumption in semiconductor devices; Consulting services in the field of semiconductor technology development; Design and development services for others in the field of semiconductor devices; Custom design and engineering for new product development of semiconductors; technology consultation services regarding semiconductors; technical consulting services in the field of semiconductor development concerning semiconductor manufacturing technology for production of a uniquely designed semiconductor
N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
54.
Vertical power MOSFET having planar channel and its method of fabrication
A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension next to the top portion of the sidewalls. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and extends virtually the entire length of the sidewalls. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Semiconductors Research, design, engineering and/or development of technology solutions for power management and consumption in semiconductor devices; Consulting services in the field of semiconductor technology development; Design and development services for others in the field of semiconductor devices; Custom design and engineering for new product development of semiconductors; technology consultation services regarding semiconductors; technical consulting services in the field of semiconductor development concerning semiconductor manufacturing technology for production of a uniquely designed semiconductor
56.
Lateral transistors and methods with low-voltage-drop shunt to body diode
Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. Alternating N and P-type columns are formed over the drift layer with a higher dopant concentration. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and next to the sidewalls as a vertical field plate. A source electrode contacts the P-well and source region. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls. Current between the source and drain flows laterally and then vertically through the various N layers. On resistance is reduced and the breakdown voltage is increased.
A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension next to the top portion of the sidewalls. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and extends virtually the entire length of the sidewalls. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
60.
MOS-gated power devices, methods, and integrated circuits
MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
61.
Trench transistors and methods with low-voltage-drop shunt to body diode
Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
62.
Vertical power MOSFET with planar channel and vertical field plate
A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. Alternating N and P-type columns are formed over the drift layer with a higher dopant concentration. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and next to the sidewalls as a vertical field plate. A source electrode contacts the P-well and source region. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls. Current between the source and drain flows laterally and then vertically through the various N layers. On resistance is reduced and the breakdown voltage is increased.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
63.
Power semiconductor devices, structures, and related methods
Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.
Power devices which include trench Schottky barrier diodes and also (preferably) trench-gate transistors. Isolation trenches flank both the gate regions and the diode mesas, and have an additional diffusion below the bottom of the isolation trenches. The additional diffusion helps to reduce the electric field (and leakage), when the device is in the OFF state, at both the Schottky barrier and at the body diode.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
67.
Trench gated power device with multiple trench width and its fabrication process
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor device also includes a body layer extending a first predetermined distance into the semiconductor layer of the second conductivity type and a pair of trenches extending a second predetermined distance into the semiconductor layer of the second conductivity type. Each of the pair of trenches consists essentially of a dielectric material disposed therein and a concentration of doping impurities present in the semiconductor layer of the second conductivity type and a distance between the pair of trenches define an electrical characteristic of the semiconductor device. The semiconductor device further includes a control gate coupled to the semiconductor layer of the second conductivity type and a source region coupled to the semiconductor layer of the second conductivity type.
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A method of manufacturing a semiconductor device includes providing a semiconductor layer of a first conductivity type and forming a semiconductor layer of a second conductivity type thereon. The method also includes forming an insulator layer on the semiconductor layer of the second conductivity type, etching a trench into at least the semiconductor layer of the second conductivity type, and forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type. The method further includes implanting ions into the thermal oxide layer, forming a second insulator layer, removing the second insulator layer from a portion of the trench, and forming an oxide layer in the trench and on the epitaxial layer. Moreover, the method includes forming a material in the trench, forming a second gate oxide layer over the material, and patterning the second gate oxide layer.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
70.
MOS-gated power devices, methods, and integrated circuits
MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
71.
Schottky and MOSFET+Schottky structures, devices, and methods
Power devices which include trench Schottky barrier diodes and also (preferably) trench-gate transistors. Isolation trenches flank both the gate regions and the diode mesas, and have an additional diffusion below the bottom of the isolation trenches. The additional diffusion helps to reduce the electric field (and leakage), when the device is in the OFF state, at both the Schottky barrier and at the body diode.
A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
73.
Power semiconductor devices, methods, and structures with embedded dielectric layers containing permanent charges
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
74.
Devices, components and methods combining trench field plates with immobile electrostatic charge
N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
75.
Power semiconductor devices, structures, and related methods
Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
76.
Trench transistors and methods with low-voltage-drop shunt to body diode
Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
77.
Lateral transistors with low-voltage-drop shunt to body diode
Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS
H01L 31/062 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the metal-insulator-semiconductor type
H01L 31/113 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect photo- transistor being of the conductor-insulator- semiconductor type, e.g. metal- insulator-semiconductor field-effect transistor
H01L 31/119 - Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation characterised by field-effect operation, e.g. MIS type detectors
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.
The present inventors have realized that manufacturability plays into optimization of power semiconductor devices in some surprising new ways. If the process window is too narrow, the maximum breakdown voltage will not be achieved due to doping variations and the like normally seen in device fabrication. Thus, among other teachings, the present application describes some ways to improve the process margin, for a given breakdown voltage specification, by actually reducing the maximum breakdown voltage. In one class of embodiments, this is done by introducing a vertical gradation in the density of fixed electrostatic charge, or in the background doping of the drift region, or both. Several techniques are disclosed for achieving this.
Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.
A method of manufacturing a semiconductor device includes providing a semiconductor layer of a first conductivity type and forming a semiconductor layer of a second conductivity type thereon. The method also includes forming an insulator layer on the semiconductor layer of the second conductivity type, etching a trench into at least the semiconductor layer of the second conductivity type, and forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type. The method further includes implanting ions into the thermal oxide layer, forming a second insulator layer, removing the second insulator layer from a portion of the trench, and forming an oxide layer in the trench and on the epitaxial layer. Moreover, the method includes forming a material in the trench, forming a second gate oxide layer over the material, and patterning the second gate oxide layer.
A semiconductor device includes a semiconductor layer of a first conductivity type having a first surface and a second surface, a source region disposed on the first surface, a gate region disposed on the first surface adjacent the source region, and a drain region disposed on the first surface. The semiconductor device also includes a pair of charge control trenches disposed between the gate region and the drain region. Each of the pair of charge control trenches is characterized by a width and includes a first dielectric material disposed therein and a second material disposed internal to the first dielectric material. Additionally, a concentration of doping impurities present in the semiconductor layer of the first conductivity type and a distance between the pair of charge control trenches define an electrical characteristic of the semiconductor device that is independent of the width of each of the pair of charge control trenches.
Power semiconductor devices in which insulated empty space zones are used for field-shaping regions, in place of dielectric bodies previously used. Optionally permanent charge is added at the interface between the insulated empty space zone and an adjacent semiconductor drift region.
A MOSFET switch which has a low surface electric field at an edge termination area, and also has increased breakdown voltage. The MOSFET switch has a new edge termination structure employing an N-P-N sandwich structure. The MOSFET switch also has a polysilicon field plate configuration operative to enhance any spreading of any depletion layer located at an edge of a main PN junction of the N-P-N sandwich structure.
H01L 27/095 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being Schottky barrier gate field-effect transistors
H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate
H01L 31/07 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the Schottky type
H01L 31/108 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the Schottky type
A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.
Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.
A vertical-current-flow device includes a trench which includes an insulated gate and which extends down into first-conductivity-type semiconductor material. A phosphosilicate glass layer is positioned above the insulated gate and a polysilicon layer is positioned above the polysilicate glass layer. Source and body diffusions of opposite conductivity types are positioned adjacent to a sidewall of the trench. A drift region is positioned to receive majority carriers which have been injected by the source, and which have passed through the body diffusion. A drain region is positioned to receive majority carriers which have passed through the drift region. The gate is capacitively coupled to control inversion of a portion of the body region. As an alternative, a dielectric layer may be used in place of the doped glass where permanent charge is positioned in the dielectric layer.
Improved MOSFET structures and processes, where multiple polysilicon embedded regions are introduced into the n+ source contact area. A top poly Field Plate is used to shield the electric field from penetrating into the channel, so that a very short channel can be used without jeopardizing the device drain-source leakage current. A bottom poly Field Plate is used to modulate the electric field distribution in the drift region such that a more uniform field distribution can be obtained.
Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery.
Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.
Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery.
Semiconductor power devices, and related methods, wherein a recessed contact makes lateral ohmic contact to the source diffusion, but is insulated from the underlying recessed field plate (RFP). Such an insulated RFP is here referred to as an embedded recessed field plate (ERFP).
Semiconductor power devices, and related methods, wherein a recessed contact makes lateral ohmic contact to the source diffusion, but is insulated from the underlying recessed field plate (RFP). Such an insulated RFP is here referred to as an embedded recessed field plate (ERFP).
An edge termination structure includes a final dielectric trench containing permanent charge. The final dielectric trench is surrounded by first conductivity type semiconductor material (doped by lateral outdiffusion from the trenches), which in turn is laterally surrounded by second conductivity type semiconductor material.
Devices, structures, and related methods for IGBTs and the like which include a self-aligned series resistance at the source-body junction to avoid latchup. The series resistance is achieved by using a charged dielectric, and/or by using a dielectric which provides a source of dopant atoms of the same conductivity type as the source region, at a sidewall adjacent to the source region.
N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).
N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).
Devices, structures, and related methods for IGBTs and the like which include a self-aligned series resistance at the source-body junction to avoid latchup. The series resistance is achieved by using a charged dielectric, and/or by using a dielectric which provides a source of dopant atoms of the same conductivity type as the source region, at a sidewall adjacent to the source region.
