Patent Safe, Inc.

United States of America

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2020 2
Before 2020 4
IPC Class
H01S 5/0234 - Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings 3
H01S 5/0237 - Fixing laser chips on mounts by soldering 3
H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers 3
H01S 5/042 - Electrical excitation 3
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] 3
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Found results for  patents

1.

High speed photo detectors with reduced aperture metal contact and method therefor

      
Application Number 16782788
Grant Number 11201251
Status In Force
Filing Date 2020-02-05
First Publication Date 2020-12-31
Grant Date 2021-12-14
Owner PATENT SAFE, INC. (USA)
Inventor
  • Pao, Yi-Ching
  • Riaziat, Majid
  • Wu, Ta-Chung

Abstract

A photodiode has a substrate. A mesa structure is formed on the substrate, wherein the mesa structure has an n region containing an n type dopant formed on the substrate, an intermediate region positioned on the n region and a p region formed on the intermediate region and containing a p type dopant. A contact is formed on a top surface of the mesa and attached to the p region. The contact is formed around an outer perimeter of the mesa. The mesa has a diameter of 30 um or less.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 21/332 - Thyristors
  • H01L 31/0224 - Electrodes
  • H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
  • H01L 31/105 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type

2.

Planarization and flip-chip fabrication process of fine-line-geometry features with high-roughness metal-alloyed surfaces

      
Application Number 16594895
Grant Number 10840106
Status In Force
Filing Date 2019-10-07
First Publication Date 2020-04-16
Grant Date 2020-11-17
Owner PATENT SAFE, INC. (USA)
Inventor
  • Pao, Yi-Ching
  • Pao, James
  • Riaziat, Majid
  • Wu, Ta-Chung

Abstract

A method of semiconductor device fabrication that enables fine-line geometry lithographic definition and small form-factor packaging comprises: forming contacts on a metal layer of the semiconductor device; applying a protective mask layer over active regions and surfaces of the contacts having rough surface morphology; planarizing a surface of the semiconductor device until the protective mask layer is removed and the surfaces of the contacts having rough surface morphology are planarized; and forming contact stacks on the surfaces of the contacts which are planarized.

IPC Classes  ?

  • H01L 21/321 - After-treatment
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/4763 - Deposition of non-insulating-, e.g. conductive-, resistive-, layers on insulating layersAfter-treatment of these layers
  • H01L 21/463 - Mechanical treatment, e.g. grinding, ultrasonic treatment
  • H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation

3.

Planarization of backside emitting VCSEL and method of manufacturing the same for array application

      
Application Number 16258976
Grant Number 11233377
Status In Force
Filing Date 2019-01-28
First Publication Date 2019-08-01
Grant Date 2022-01-25
Owner PATENT SAFE, INC. (USA)
Inventor Pao, Yi-Ching

Abstract

A method of forming a flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package comprising: forming a VCSEL pillar array; applying a dielectric layer to the VCSEL pillar array, the dielectric layer filling trenches in between pillars forming the VCSEL pillar array and covering the pillars; planarizing the VCSEL pillar array to remove the dielectric layer covering the pillars exposing a metal layer on a top surface of the pillars; applying a metal coating on the metal layer on a top surface of the pillars, the metal layer defining a contact pattern of the VCSEL pillar array; and applying solder on the metal coating to flip chip mount the VCSEL pillar array to a substrate package.

IPC Classes  ?

  • H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
  • H01S 5/42 - Arrays of surface emitting lasers
  • H01S 5/0234 - Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
  • H01S 5/042 - Electrical excitation
  • H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers
  • H01S 5/0237 - Fixing laser chips on mounts by soldering
  • H01S 5/02345 - Wire-bonding

4.

Flip chip backside emitting VCSEL package

      
Application Number 16239083
Grant Number 11264780
Status In Force
Filing Date 2019-01-03
First Publication Date 2019-08-01
Grant Date 2022-03-01
Owner PATENT SAFE, INC. (USA)
Inventor Pao, Yi-Ching

Abstract

A flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package has a VCSEL pillar array. A first metal contact is formed over a top section of each pillar of the VCSEL pillar array. A second metal contact is formed on a back surface of the VCEL pillar array. An opening is formed in the second metal contact and aligned with the pillars of the VCSEL pillar array. Solder tip is applied on each pillar of the VCSEL pillar array to flip chip mount the VCSEL pillar array.

IPC Classes  ?

  • H01S 5/0234 - Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
  • H01S 5/042 - Electrical excitation
  • H01S 5/42 - Arrays of surface emitting lasers
  • H01S 5/323 - Structure or shape of the active regionMaterials used for the active region comprising PN junctions, e.g. hetero- or double- hetero-structures in AIIIBV compounds, e.g. AlGaAs-laser
  • H01S 5/024 - Arrangements for thermal management
  • H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
  • H01S 5/0237 - Fixing laser chips on mounts by soldering
  • H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers
  • H01S 5/02345 - Wire-bonding

5.

Pillar confined backside emitting VCSEL

      
Application Number 16208958
Grant Number 11283240
Status In Force
Filing Date 2018-12-04
First Publication Date 2019-07-11
Grant Date 2022-03-22
Owner PATENT SAFE, INC. (USA)
Inventor
  • Pao, Yi-Ching
  • Riaziat, Majid
  • Wu, Ta-Chung
  • Kyi, Wilson
  • Pao, James

Abstract

A backside Vertical Cavity Surface Emitting Laser (VCSEL) has a substrate. A first mirror device is formed on the substrate. An active region is formed on the first mirror device. A second mirror device is formed on the active region. A pillar is formed by directional Inductive Coupled Plasma-Reactive Ion Etcher (ICP-RIE). The pillar exposes a portion of the first mirror device, the active region and the second mirror device. A first metal contact is formed over a top section of the pillar. A second metal contact is formed on the substrate. An opening formed in the second metal contact and aligned with the pillar.

IPC Classes  ?

  • H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
  • H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers
  • H01S 5/0234 - Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
  • H01S 5/0237 - Fixing laser chips on mounts by soldering
  • H01S 5/34 - Structure or shape of the active regionMaterials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
  • H01S 5/02 - Structural details or components not essential to laser action
  • H01S 5/20 - Structure or shape of the semiconductor body to guide the optical wave
  • H01S 5/042 - Electrical excitation
  • H01S 5/42 - Arrays of surface emitting lasers
  • H01S 5/024 - Arrangements for thermal management

6.

Transferring and resizing of epitaxial film arrays and method thereof

      
Application Number 12872609
Grant Number 08546237
Status In Force
Filing Date 2010-08-31
First Publication Date 2012-03-01
Grant Date 2013-10-01
Owner PATENT SAFE, INC. (USA)
Inventor Riaziat, Majid

Abstract

A method of transferring an epitaxial film from an original substrate to a destination substrate comprises: growing an epitaxial film grown with a sacrificial layer on the original substrate; patterning the epitaxial film into a plurality of sections; attaching the plurality of sections to a stretchable film; removing the plurality of sections attached to the stretchable film from the original substrate; stretching the sections apart as needed; and attaching a permanent substrate to the plurality of sections; and trimming the sizes of the sections as needed for precise positioning prior to integrated circuit device fabrication.

IPC Classes  ?

  • H01L 21/76 - Making of isolation regions between components