Systems and methods herein are for one or more processing units to be associated with at least one switch or router and to enable the at least one switch or router to receive a communication from a source host machine, where the communication includes a request associated with memory access protocols of a memory space of a destination host machine, and where the communication is to be provided to the destination host machine to enable subsequent communications from the source host machine that are based in part on the memory access protocols received in response to the request.
A communication system includes at least one send queue, containing send queue entries pointing to packets to be transmitted over a network by packet sending circuitry. A clock work queue contains clock queue entries to synchronize sending times of the packets pointed to by the send queue entries. At least one arming queue contains arming queue entries to arm the clock work queue at selected time intervals.
In one embodiment, a processing device includes a memory to store a plurality of memory pages having corresponding physical memory addresses in the memory, store an active multilevel page table (MPT) mapping virtual to physical memory addresses for corresponding allocated memory pages stored in the memory, and store a floating MPT at least partially mapping virtual to physical memory addresses for corresponding spare memory pages stored in the memory, the floating and active MPT using a common mapping scheme, and a processor to receive a request to add a virtual to physical address mapping for more memory pages of the plurality of memory pages to the active MPT, and in response to receiving the request, adjoin at least part of the floating MPT to the active MPT so that the active MPT provides the virtual to physical address mapping for at least some memory pages of the spare memory pages.
A system includes a network device. The network device is to receive a packet comprising metadata. Responsive to determining that an entry in a match action table matches a match action lookup tuple based on the metadata, identify a debug instruction associated with the entry, the entry in the match action table identifying an action to be performed with respect to the packet. The debug instruction is executed. At least a portion of the debug instruction is executed prior to performing the action identified in the entry of the action table.
System, methods, and devices for initializing a system by loading drivers are provided. In one example, a system includes comprising one or more circuits to initiate a system initiation or a boot of the system, during the system initiation or the boot of the system, read data from a non-volatile memory, based on the data from the non-volatile memory, identify a plurality of hardware components, identify one or more drivers based on the plurality of hardware components, and load the one or more drivers during the system initiation or the boot of the system.
Systems and methods are described herein for an electro-absorption modulator (EAM) device. An example EAM device comprises an optical waveguide comprising a waveguide core configured to facilitate propagation and modulation of an optical signal therethrough; a segmented structure comprising diode segments disposed on the waveguide; and an electrical transmission line operatively coupled to the diode segments. The electrical transmission line is configured to facilitate propagation of an electrical signal therethrough. The electrical transmission line includes a first transmission line rail and a second transmission line, where a first subset of diode segments is operatively coupled to the first transmission line rail and a ground rail, and a second subset of diode segments is operatively coupled to the second transmission line and the ground rail. The diode segments from the first subset are disposed alternately with the diode segments from the second subset.
G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.
Apparatus and method for improved network resource management are described herein. An example computing apparatus comprises a network adapter configured to: receive, via a network connection, a data packet from the communication network; determine, from the first memory block, a value of an extended portion of a local counter associated with the network connection in response to receiving the data packet; capture, from the second memory block, a value of a global counter; compare the value of the extended portion of the local counter with the value of the global counter; and in an instance in which the comparison identifies a mismatch: update the value of the extended portion of the local counter based on the value of the global counter; and set a current value of a bit indicating a status of the network connection, wherein the bit is associated with the plurality of bits.
G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
H04L 67/143 - Termination or inactivation of sessions, e.g. event-controlled end of session
Systems and methods herein are for global bandwidth-aware adaptive routing in a network communication and include at least one switch to determine an event associated with a change in network bandwidth between a local host and a remote host, where the at least one switch is further to provide routing protocols for the network communication, and where the routing protocols is to be used to modify an adaptive routing in the at least one switch for selection from different routes for the network communication between the local host and the remote host.
In one embodiment, a network switch device includes a network interface to receive vectors from endpoint devices, and an aggregation and reduction accelerator to perform elementwise and vector splitting operations with the vectors as input yielding at least two intermediate vector results, wherein the network interface is to send the at least two intermediate vector results to different corresponding network switches in different switch aggregation trees, receive at least two final vector results of an aggregation and reduction process from the different switch aggregation trees, and combine the at least two final vector results to yield a combined final vector result, wherein the network interface is to send the combined final vector result to the endpoint devices.
Systems and methods herein are for a video encoder to be associated with an interface that is to receive, from an application, at least one metric that is associated with a quality preference for video compression to be performed by the video encoder and that is to provide a weight map to enable the video encoder to perform rate-distortion optimization (RDO) for received frames from the application using the weight map to weigh one or more first blocks associated with an individual one of the frames more than one or more second blocks associated with the individual one of the frames.
H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
A system includes one or more processors to trace one or more packets transmitted by an application distributed among a plurality of computing nodes. The one or more processors are to generate tracing data based at least in part on tracing the one or more packets. The tracing data includes temporal information associated with transmission of the one or more packets. The one or more processors are to manage a data allocation associated with the application based on the tracing data.
A datacenter environment having a plurality of servers, leaf switches, and spine switches is presented. A transceiver module facilitates reliable data transmission across network layers. The transceiver module includes a first optical module to facilitate data transmission between a server and a leaf switch, and a second optical module to facilitate data transmission between the leaf switch and a spine switch. An adapter operatively coupled to both optical modules manages data flow under different configurations. In a first configuration, the adapter receives first data from the server via the first optical module and second data from the leaf switch via the second optical module. Upon detecting an operational failure in the first optical module, the adapter terminates reception of second data from the leaf switch and switches to a second configuration, in which it redirects the first data from the server through the second optical module.
In one embodiment, a system, includes a digitally controlled oscillator (DCO) to generate a local clock signal having a local clock frequency, and a hardware clock to maintain a value indicative of a local clock time advancing at a frequency proportional to the local clock frequency of the local clock signal generated by the DCO, and clock synchronization circuitry to receive from a device an indication of a remote clock time, generate a digital control command to at least partially correct for a difference between the remote clock time and the local clock time, and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.
In one embodiment, a system includes a digitally controlled oscillator (DCO) to generate a local clock having a local clock frequency, and clock synchronization circuitry to receive from a device a signal indicative of a remote clock frequency, compare measures of the remote clock frequency and the local clock frequency; generate a digital control command based on the comparison; and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H04L 7/10 - Arrangements for initial synchronisation
A network device, a network interface controller, and a switch are provided. In one example, a shared buffer includes a plurality of cells of memory, one or more ports read data from the shared buffer and write data to the shared buffer, and a controller circuit selectively enables and disables cells of memory of the shared buffer based on an amount of data stored in the shared buffer. Power consumption of the shared buffer is in proportion to a number of enabled cells of memory.
Systems and methods herein are system for efficient network communication in an unreliable transport protocol (UTP) using a first processor to provide communication to a second processor using the UTP, where the communication is associated with a set of sequential messages sent over multiple timepoints, where at least one part of the communication includes a request for acknowledgement from the second processor of a receipt of the set of sequential messages, and where the first processor is to receive a summary of the set of sequential messages in a dense format as the acknowledgement.
A device includes a receiver including a timestamp generator to update timestamps at a first rate. The receiver is to estimate a first time for receiving a signal, wherein the signal is associated with a synchronization operation. The receiver is further to receive the signal at a second time. The receiver is further to determine a difference between the second time and the first time, wherein the difference is associated with an error of the timestamp generator of the receiver. The receiver can also adjust the first rate to a second rate at which to update the timestamps by the timestamp generator, responsive to determining the difference between the first time and the second time.
A system is described which monitors accesses to one or more peers using queue pairs (QPs). Each access is associated with a respective peer of the one or more peers. The system identifies, based on one or more of a rate and a count of the monitored accesses to the one or more QPs, a first peer of the one or more peers. In response to identifying the first peer, a reliable connection QP is established for the first peer of the one or more peers.
A network device includes a plurality of ports, a plurality of optical indicators, two or more packet processing circuits, and synchronization circuitry. The two or more packet processing circuits are to process packets communicated over the ports, each packet processing circuit to control a subset of the optical indicators to display status information relating to a subset of the ports. At least some of the status information is represented by blinking of the optical indicators. The synchronization circuitry is to synchronize at least one operational characteristic of the optical indicators among the two or more packet processing circuits.
A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.
A system, a computing system, and a switch are provided. In one example, a system for routing data to one of a plurality of queues comprises a processor to poll a depth of one or more queues of the plurality of queues, determine a weight for each polled queue based on the depth of each polled queue, and route data received via a port to a first queue of the plurality of queues based on the determined weight for each polled queue.
A device, communication system, and method are provided. In one example, a system for routing traffic is described that includes a plurality of ports to facilitate communication over a network. The system also includes a controller to selectively activate or deactivate ports of the system based on queue depths and additional information to improve power efficiency of the system.
Processes and devices for continuous compositional grading in photodetectors and electro-absorption modulators (EAM) are provided. An example photodetector includes a multi-layered structure comprising a collector region, an absorber region, a grading layer, and a peripheral layer, all aligned along a detection axis. The grading layer, positioned adjacent to the absorber region, includes multiple sub-layers that define a continuous compositional grading to facilitate smooth carrier transport and reduce recombination. Similarly, an example electro-absorption modulator (EAM) device includes a waveguide mesa formed on a semiconductor substrate, comprising a multi-quantum well (MQW) core layer, upper and lower near-core cladding layers, and upper and lower central cladding layers. The EAM device features both upper and lower grading layers, each positioned between the near-core cladding layers and the adjacent central cladding layers. These grading layers include multiple sub-layers that define a continuous compositional grading, facilitating smooth transitions between the MQW core and surrounding cladding layers.
G02F 1/017 - Structures with periodic or quasi periodic potential variation, e.g. superlattices, quantum wells
G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
H01L 31/0232 - Optical elements or arrangements associated with the device
H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 31/109 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN heterojunction type
A system includes multiple processors to communicate with one another at predefined time slots. A given processor among the processors is to (i) hold a predetermined schedule plan that specifies which of the other processors in the system are accessible to the given processor at which of the time slots, the predetermined schedule plan having been determined before receiving data for transmission from the given processors to the other processors, (ii) queue data that is destined to one or more of the other processors, and (iii) transmit the queued data in accordance with the predetermined schedule plan.
A method includes presenting, by a processing device, in a user interface of a display device, a set of menu items associated with a plurality of criteria and detecting one or more input signals from one or more selections of the set of menu items. The method includes creating a command that includes one or more criteria corresponding to selected options of the plurality of criteria derived from the one or more input signals. The method includes sending, by the processing device, the command to a network adapter device to trigger a polling operation to be performed that causes internal logic of the network adapter device to sample event data associated with a latency of data packets sent by a hardware process that is specific to the one or more criteria.
An example method for dynamic packet routing using prioritized groups includes: receiving, by a node, a network packet to be forwarded to a network destination, identifying, based on data stored in a forwarding information data structure of the node, a first path satisfying a first cost criterion to the network destination, determining that a path latency of the first path exceeds a threshold latency, selecting, based on the data stored in the forwarding information data structure of the node, a second path to the network destination, wherein the second path satisfies a second cost criterion and does not satisfy the first cost criterion, and forwarding, by the node, the network packet to the network destination via a local interface associated with the second path.
A peripheral device includes a bus interface, a first processor and a second processor. The bus interface is to communicate over a peripheral bus. The first processor is to manage communication over the peripheral bus by executing bus-maintenance software code, the bus-maintenance software code being executed from one or more first layers of a multi-layer memory. The second processor is to update the bus-maintenance software code from an existing version to an updated version, by (i) loading the updated version to one or more second layers of the multi-layer memory, higher in hierarchy than the or one more first layers, and (ii) invalidating the existing version in the one or more first layers, thereby forcing fetching of the updated version from the one or more second layers to the one or more first layers and to start executing the updated version.
A network adapter including a host interface, a network interface, packet processing circuitry, and Translation-as-a-Service (TaaS) circuitry. The host interface is to communicate with a host over a peripheral bus. The network interface is to send and receive packets to and from a network for the host. The packet processing circuitry is to process the packets. The TaaS circuitry is integrated in the network adapter and is to (i) receive from a requesting device a request to translate an input address into a requested address in a requested address space, (ii) translate the input address into the one or more requested addresses, and (iii) return the one or more requested addresses to the requesting device.
G06F 12/1072 - Decentralised address translation, e.g. in distributed shared memory systems
H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and packet processing circuitry operatively coupled to the network interface. The packet processing circuitry is configured to receive, via the network interface, a plurality of data packets associated with a message; determine, for each data packet, at least one corresponding reserved stride in a strided buffer; store each data packet in the at least one corresponding reserved stride; process the strided buffer upon storing the plurality of data packets in a corresponding plurality of reserved strides; and generate a completion notification indicating that the plurality of data packets in the strided buffer has been processed.
Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.
A network device includes control logic coupled to a receiver. The control logic detects an synchronization packet received via the receiver from a second network device over a network that is precision time protocol unaware. The control logic determines that a portion of the synchronization packet is asserted, indicating that the synchronization packet has incurred congestion traversing the network. The control logic adjusts, based on an assertion of the portion, a weight applied to timestamps associated with sending and receiving the synchronization packet in performing clock synchronization with the second network device.
A baseboard management controller structure includes a microcontroller to provide baseboard management functions, levels of printed circuit board on which the microcontroller and peripheral circuits are mounted. The structure includes an interface to provide electrical communication between the microcontroller and a main board of a computing device.
Electronic devices, electronic modules, and methods for manufacturing electronic devices and/or electronic modules are described herein. In some embodiments, the present invention may be directed to an electronic module that includes a pair of printed circuit boards (PCBs) and a capacitor positioned between the PCBs. Each of the PCBs may include a pair of vias configured to provide electrical connections through the PCB, and the capacitor may include a pair of pins. Each pin of the capacitor may be aligned with a via of one of the PCBs and a corresponding via of the other PCB such that each pin is configured to provide electrical connection between the two PCBs. Additionally, the pair of pins may be configured to support the PCBs with respect to each other.
H05K 1/14 - Structural association of two or more printed circuits
H01G 4/38 - Multiple capacitors, i.e. structural combinations of fixed capacitors
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
35.
BACKSIDE FIBER ATTACHMENT TO SILICON PHOTONICS CHIP
Various embodiments of silicon photonic (SiP) chips are provided that are configured for backside or frontside optical fiber coupling. An SiP chip includes a photonic integrated circuit formed on a first surface of a first substrate. The photonic integrated circuit includes at least one optical component and at least one coupling element. The at least one optical component is configured to propagate an optical signal therethrough in a waveguide propagation direction that is substantially parallel to a plane defined by the first surface. The at least one coupling element is configured to couple an optical signal propagating along an optical path transverse to the waveguide propagation direction into the at least one optical component to enable the backside or frontside coupling of an optical fiber to the SiP chip.
An apparatus includes a memory and control circuitry. The control circuitry is configured to receive packets, which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order, to detect that one or more of the packets deviate from the sequential order, to buffer the one or more deviating packets in the memory, and, using the memory, to reorder the packets and provide the packets in the sequential order to the network device.
In one embodiment, a system including a reference processing device includes a reference hardware clock to maintain a reference clock value, and reference clock synchronization circuitry to discipline the reference hardware clock responsively to a remote clock, which is remote to the system, and a follower processing device including a follower hardware clock to maintain a follower clock value, and follower clock synchronization circuitry to synchronize the follower hardware clock to the reference hardware clock, and provide an indication about the follower clock value to the reference processing device, wherein the reference clock synchronization circuitry is configured to monitor a quality of the synchronization of the follower hardware clock to the reference hardware clock.
In one embodiment, a first network device includes a host interface to receive messages from a host device, packet processing circuitry to send a batch of the messages to a second network device without waiting for an acknowledgement receipt from the second network device after sending each message, one message in the batch having a maximum message sequence number (MSN), receive a given acknowledgement receipt from the second network device indicating that all the messages in the batch have been received and including credit data indicating that there is no space in a receive work queue of the second network device for receiving an additional message, and send the additional message having an MSN greater than the maximum MSN to the second network device responsively to receiving the given acknowledgement receipt and based on the credit data indicating that there is no space in the receive work queue.
A network device, system, and method are provided. An illustrative network device includes a plurality of ports connectable to a communication network, one or more reduction units decoupled from the plurality of ports, and configurable logic to service packet transmission between the one or more reduction units and the plurality of ports.
Networking devices, systems, and methods are provided. In one example, a method includes receiving a packet at a networking device; evaluating the packet; based on the evaluation of the packet, truncating the packet from a first size to a second size that is smaller than the first size; and storing the truncated packet in a buffer prior to transmitting the truncated packet with the networking device.
A system includes tiles arranged in a configurable topology. A first tile includes memory and one or more processing devices to: receive a first message including a coordinate identifier of a target tile, the coordinate identifier reflecting a location of the target tile; update a configuration value associated with the target tile based on the coordinate identifier, and transmit a second message to the target tile based on the configuration value.
An optical interconnect device and the method of fabricating it are described. The device includes an in-plane laser cavity transmitting a light beam along a first direction, a Franz Keldysh (FK) optical modulator transmitting the light beam along the first direction, a mode-transfer module including a tapered structure disposed after the FK optical modulator along the first direction to enlarge the spot size of the light beam to match an external optical fiber and a universal coupler controlling the light direction. The tapered structure can be made linear or non-linear along the first direction. The universal coupler passes the laser light to an in-plane external optical fiber if the fiber is placed along the first direction, or it is a vertical coupler in the case that the external optical fiber is placed perpendicularly to the substrate surface. The coupler is coated with highly reflective material.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/30 - Optical coupling means for use between fibre and thin-film device
G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
43.
Hardware accelerated activation of a processing unit
In one embodiment, a network device includes a network interface to receive first packets from a network and send second packets over the network, and packet processing hardware to process a packet, accelerate activation of a given software program by performing at least one activation task of the given software program in hardware, and generate an interrupt to request a processing unit to execute the given software program to perform processing associated with the packet, and the processing unit to execute the given software program and perform processing associated with the packet, responsively to the at least one activation task performed by the packet processing hardware.
Methods, systems, and computer program products to generate a telemetry pipeline. In embodiments, the system includes a communication interface that receives one or more user-defined functions for the telemetry pipeline. The system also includes control logic that implements programmatically the one or more user-defined functions to collect telemetry data at a plurality of layers in the telemetry pipeline based on the one or more user-defined functions and calculate smart metrics at different layers of the plurality of layers in the telemetry pipeline. The smart metrics may be calculated at a layer closest to where associated telemetry data is collected.
Apparatuses, systems, and techniques for classifying one or more computer programs executed by a host device as being ransomware using a machine learning (ML) detection system. An integrated circuit is coupled to physical memory of a host device via a host interface. The integrated circuit hosts a hardware-accelerated security service to protect one or more computer programs executed by the host device. The security service obtains a series of snapshots of data stored in the physical memory and extracts a set of features from each snapshot of the series of snapshots, each snapshot representing the data at a point in time. The security service classifies a process of the one or more computer programs as ransomware or non-ransomware using the set of features and outputs an indication of ransomware responsive to the process being classified as ransomware.
Apparatuses, systems, and techniques for detecting that one or more computer programs executed by a host device are subject to malicious activity using a machine learning (ML) detection system. An integrated circuit is coupled to physical memory of a host device via a host interface. The integrated circuit hosts a hardware-accelerated security service to protect one or more computer programs executed by the host device. The security service extracts a set of features from data stored in the physical memory, the data being associated with the one or more computer programs. The security service determines, using the ML detection system, whether the one or more computer programs are subject to malicious activity based on the set of features. The security service outputs an indication of the malicious activity responsive to a determination that the one or more computer programs are subject to the malicious activity.
A network device, system-on-a-chip, and method of performing an auto-negotiation for a planarized computing system. In response to a link request, switching hardware determines whether a source of the link request is planarized or non-planarized. If a mismatch between a received link request and a sent link request occurs, a lower-level event is escalated to the operating system which is enabled to respond to continue the auto-negotiation process.
Apparatuses, systems, and techniques for dynamic memory allocation using a shared free list. A user tag is received, and a hashed user tag is generated. A first reference to an entry in a second data structure is identified in a first data structure using the hashed user tag. The entry includes multiple user tags. Responsive to determining that the multiple user tags do not include the user tag, a memory address is identified in a third data structure. The memory address is removed from the third data structure. Memory is allocated for a user context associated with the user tag at the memory address. The user tag is added to the second data structure.
An apparatus includes a crossbar circuit that routes one or more packets between one or more ingress domains and one or more egress domains. The crossbar circuit includes sub-crossbar domains. An ingress control circuit associated with the one or more ingress domains may distribute packet data of the one or more packets to the sub-crossbar domains. An egress control circuit of the apparatus receives data bits associated with the packet data from egresses associated with the plurality of sub-crossbar domains. The egress control circuit may reorder or refrain from reordering the data bits based on an attribute associated with the distribution of the packet data.
In one embodiment, a local networking device includes a host interface to receive packets from a local host device, packet processing hardware to receive cryptographic material offloaded from the local host device over the host interface, perform cryptographic operations on the packets based on the cryptographic material, generate datagram transport layer security (DTLS) headers including respective DTLS sequence numbers in hardware, and encapsulate the packets with the DTLS headers in hardware, and a network interface to send the packets with the DTLS headers to a remote networking device over a packet data network.
In one embodiment, a system includes a networking device including a network interface to receive network packets having headers including datagram transport layer security (DTLS) headers from a remote device over a packet data network, packet processing circuitry to identify first packets of the received packets for DTLS processing in the packet processing circuitry, identify second packets of the received packets to bypass DTLS processing in the packet processing circuitry and to be provided to software to perform DTLS processing on the second packets, and perform DTLS processing on the first packets, and a host interface to provide the DTLS processed first packets to the software, and provide the second packets to the software to perform DTLS processing on the second packets.
An electronic sub-assembly, which may include: a ceramic substrate having a top surface and a bottom surface, a plurality of layers of ceramic material disposed between the top surface and the bottom surface of the substrate, and a plurality of conductive structures passing through the substrate between the top surface and the bottom surface of the substrate; and a ball grid array disposed on the bottom surface of the substrate, the ball grid array comprising a plurality of solder balls, wherein at least a portion of the solder balls are connected to at least a portion of the conductive structures.
Some embodiments of the present invention are directed to an aperture for a laser for high-bandwidth communication. The laser may include an active region configured to emit light parallel to an optical axis and an emission surface spaced from the active region and through which the light is emitted. The laser may also include an aperture positioned along the optical axis between the active region and the emission surface, where the aperture has a cross-sectional area in a plane perpendicular to the optical axis, and where the cross-sectional area defines a non-circular shape. In some embodiments, the non-circular shape may have at most one axis of symmetry. The aperture may be configured to reduce a spectral bandwidth of the light emitted by the laser and a relative intensity noise of the laser.
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
54.
DUAL SOFTWARE INTERFACES FOR MULTIPLANE DEVICES TO SEPARATE NETWORK MANAGEMENT AND COMMUNICATION TRAFFIC
A device, communication system, and method are provided. In one example, a system for routing traffic is described that includes a network device. The network device includes a plurality of ports to facilitate communication over a plurality of planes in a multiplane network. The network device also includes a first interface that presents the plurality of ports as a single plane agnostic port to software, and a second interface that presents each port in the plurality of ports as a separate port to the software.
Apparatuses, systems, and techniques for detecting that a host device is subject to a malicious network attack using a machine learning (ML) detection system are described. A computing system includes a graphics processing unit (GPU) and an integrated circuit with a network interface, and a hardware acceleration engine. The integrated circuit hosts a hardware-accelerated security service to extract features from network data and metadata from the hardware acceleration engine and sends the extracted features to the GPU. Using the ML detection system, the GPU determines whether the host device is subject to a malicious network attack using the extracted features. The GPU can send an enforcement rule to the integrated circuit responsive to a determination that the host device is subject to the malicious network activity.
Methods of forming a graphene integrated core for making a printed circuit board (PCB) having enhanced thermal management properties are disclosed. The methods include providing a core body having a core body length and applying a graphene multi-layer to the core body to form a laminated stack, where the graphene multi-layer has a graphene multi-layer length that is shorter than the core body length. At least one conductive layer may be applied to the laminated stack. The graphene multi-layer may be disposed within the graphene integrated core such that the graphene multi-layer is electrically insulated from the at least one conductive layer. Corresponding graphene integrated cores having a graphene multi-layer that is disposed within the graphene integrated core such that the graphene multi-layer is electrically insulated from the at least one conductive layer are also described.
Methods for integrating copper-graphene laminate (CGL) in a multilayer PCB fabrication process and the resulting lamination stacks are disclosed. The methods include providing a core and applying a first graphene layer to the surface of the core. The methods further include applying a metal layer to the first graphene layer and applying a second graphene layer to the metal layer. Further, the methods include applying a photoresist layer to the second graphene layer and applying a protective layer to the photoresist layer. In some embodiments, the methods include applying a metallic plating to lamination stack. The methods further include drilling through the protective layer and at least one of a photoresist layer, the second graphene layer, the metal layer, the first graphene layer, and/or the core.
H05K 3/00 - Apparatus or processes for manufacturing printed circuits
H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
Technologies for optimizing the spreading of traffic across multiple local output ports while considering both local load and end-to-end (E2E) load are described. One device has multiple outgoing ports and a network adapter that determines, for a first flow of packets, a first end-to-end (E2E) congestion rate of at least some of the outgoing ports. The network adapter determines a port state of at least some of the outgoing ports. The network adapter receives a first packet associated with the first flow of packets. The network adapter determines, using a first desired rate for the first flow, the first E2E congestion rates, and the port states, i) a first time at which the first packet is to be transmitted and ii) a first outgoing port on which the first packet is to be transmitted. The first packet is sent on the first outgoing port at the first time.
A network device includes one or more ports, match-action circuitry, and an action processor. The one or more ports are to exchange packets between the network device and a network. The match-action circuitry is to match at least some of the packets to one or more rules so as to set respective actions to be performed, at least one of the actions including a programmable action. The instruction processor is to perform the programmable action by running user-programmable software code. The instruction processor includes architectural registers, one or more of the architectural registers being accessible by the match-action circuitry, and the match-action circuitry is to write into the architectural registers information for performing the programmable action.
High-bandwidth lasers having a balanced intrinsic response and parasitic response are described herein. For example, the present invention may be directed to a laser having an optimized parasitic transfer function and for which the bandwidth of the intrinsic response of the laser is increased by increasing a differential gain of the laser. The laser may balance increased bandwidth of the intrinsic transfer function due to increased cavity length with reduced bandwidth of the parasitic transfer function due to increased active resistance. For example, embodiments of the present invention may be directed to a laser configured to operate at an operating wavelength selected to maximize the bandwidth of the total response of the laser.
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
61.
HIGH-BANDWIDTH LASER HAVING OPTIMIZED PARASITIC TRANSFER FUNCTION
High-bandwidth lasers having minimized parasitic responses are described herein. In some embodiments, the present invention may be directed to a laser having a minimized parasitic response that is achieved by decreasing the active resistance of the laser's active region and decreasing the active capacitance of the laser. For example, the laser may include an active region having an active resistance as well as mirror regions, where the mirror regions have average dopant densities that decrease the active resistance of the active region and decrease the active capacitance of the laser. By decreasing the active resistance and the active capacitance, the −3 dB frequency of the parasitic response is increased. By increasing the −3 dB frequency of the parasitic response, a total response of the laser (e.g., a combination of an intrinsic response and the parasitic response) has a higher −3 dB frequency, thereby allowing the laser to operate at higher bandwidths.
H01S 3/0941 - Processes or apparatus for excitation, e.g. pumping using optical pumping by coherent light of a semiconductor laser, e.g. of a laser diode
H01S 3/08 - Construction or shape of optical resonators or components thereof
H01S 5/30 - Structure or shape of the active regionMaterials used for the active region
62.
ELECTRONIC MODULES FOR CO-PACKAGED OPTICS AND COPPER PACKAGES
Electronic devices, electronic modules, and methods for manufacturing electronic devices and/or electronic modules are described herein. Some embodiments of the present invention may be directed to an electronic module that includes a multi-chip module (MCM) substrate having a first surface configured to be connected to a system printed circuit board and a second surface defining a central portion and a peripheral portion. The electronic module may include a main die positioned on the central portion of the second surface of the MCM substrate and in electrical communication with electrical traces of the MCM substrate. The electronic module may include MCM sockets positioned on the peripheral portion of the MCM substrate, where each MCM socket is configured to engage and support a mezzanine package substrate such that a main portion of the mezzanine package substrate extends beyond the peripheral portion of the MCM substrate.
Systems and methods enable session sharing for session-based remote direct memory access (RDMA). Multiple queue pairs (QPs) can be added to a single session and/or session group where each of the QPs has a common remote. Systems and methods may query a session ID for an existing session group and then use the session ID with an add QP request to join additional QPs to an existing session. Newly added QPs may share one or more features with existing QPs of the session group, such as encryption parameters. Additionally, newly added QPs may be configured with different performance or quality of service requirements, thereby isolating performance, and permitting true scaling for high performance computing applications.
G06F 15/167 - Interprocessor communication using a common memory, e.g. mailbox
H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
H04L 67/146 - Markers for unambiguous identification of a particular session, e.g. session cookie or URL-encoding
64.
PREDICTING INACTIVITY PATTERNS FOR A SIGNAL CONDUCTOR
Methods, systems, and machine-readable mediums to predict signal conductor traffic and to transition between signal conductor states in accordance with the predictions. In at least one embodiment, a scoring system is used to select a prediction method, which is used to determine when to transition a signal conductor between active and inactive states.
Some embodiments of the present invention are directed to a tunnel junction for a vertical-cavity surface-emitting laser (VCSEL) that controls optical and current confinement within the VCSEL. The tunnel junction may define an electrical current injection area and an optical aperture for the VCSEL and may include a heavily p++ doped p-type material and a heavily n++ doped n-type material disposed on the p-type material. At least a portion of the outer edges of the n-type material are etched such that the n-type material has a cross-sectional area that is less than a cross-sectional area of the p-type material. By removing a portion of n-type material near the outer edge of the tunnel junction, a sloped effective refractive index is formed, and an effective area of the tunnel junction is changed, which increases the overlap of the current density and the optical field of the VCSEL.
H01S 5/30 - Structure or shape of the active regionMaterials used for the active region
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
A system including an interconnect device coupled with one or more devices where the first device of the one or more devices is to transmit a control block for synchronization via a physical layer of a link coupled to the high-speed interconnect device, the control block comprising a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits indicating the control block is associated with time synchronization information. The interconnect device is to receive data, parse the data, determine the data is associated with the control block, determine a delay associated with the physical layer transmitting the control block and transmitting a signal responsive to receiving the control block and determining the delay.
A device includes multiple registers, multiple hardware-implemented Privilege Level Indicators (PLIs), and one or more circuits. The registers are to store respective values. The PLIs are to specify privilege levels for accessing the respective registers. The one or more circuits are to perform a secure memory dump operation including (i) checking the PLIs of one or more of the registers and (ii) outputting the values of the registers that are permitted for outputting according to the respective PLIs.
G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
A device includes one or more ports, one or more bandwidth shapers, and processing logic. The one or more ports are to connect to a communication network. A given bandwidth shaper is to: (i) when disabled, output traffic at an available full data rate, and (ii) when enabled, output the traffic at a specified shaper data rate lower than the available full data rate. The processing logic is to receive or generate notifications, which are indicative of average power that is consumed by the network device while outputting traffic through the one or more bandwidth shapers via the one or more ports, and based on at least some of the notifications, toggle at least one of the one or more bandwidth shapers between being enabled and disabled, to retain the average power consumed below a specified power budget.
Systems and methods to perform per-register bin packing are disclosed. A system may include a memory and one or more processors coupled to the memory. The one or more processors may determine a first live range of a first variable in a source code and a second live range of a second variable in the source code. The first live range and the second live range may overlap in time during execution of an output code. The one or more processors may generate the output code including a first instruction for the first variable and a second instruction for the second variable. The first instruction may include a first register identifier, a first mask, and a first offset. The second instruction may include the first register identifier, a second mask, and a second offset.
Approaches in accordance with various illustrative embodiments provide for the determination and/or optimization the quality of an image or video, such as an image that has been compressed for transmission or storage then decompressed for presentation. Weights can be determined for a set of weight-based quality metrics to produce an overall quality metric that is a weighted combination of these metrics. Because different portions of an image or video frame may have different types of features, an image or video frame can be divided into blocks of pixels, for example, with different weights being assigned to different blocks using quality metrics. Different metrics can be considered as points in a high-dimensional weight space, with each dimension corresponding to a weight of a block. A combination of these points results in an improved quality metric. Compression settings can be updated based in part upon the overall quality metric values.
H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
H04N 19/136 - Incoming video signal characteristics or properties
H04N 19/17 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
71.
MULTIPATHING WITH REMOTE DIRECT MEMORY ACCESS CONNECTIONS
Multipathing for session-based remote direct memory access (SRDMA) may be used for congestion management. A given SRDMA session group may be associated with multiple SRDMA sessions, each having its own unique 5-tuple. A queue pair (QP) associated with the SRDMA session group may provide a packet for transmission using the SRDMA session group. The SRDMA session group may enable the packet to be transmitted using any of the associated SRDMA sessions. Congestion levels for each of the SRDMA sessions may be monitored and weighted. Therefore, when a packet is received, an SRDMA session may be selected based, at least, on the weight to enable routing of packets to reduce latency and improve overall system efficiency.
H04L 47/122 - Avoiding congestionRecovering from congestion by diverting traffic away from congested entities
H04L 47/19 - Flow controlCongestion control at layers above the network layer
H04L 47/2408 - Traffic characterised by specific attributes, e.g. priority or QoS for supporting different services, e.g. a differentiated services [DiffServ] type of service
H04L 47/6295 - Queue scheduling characterised by scheduling criteria using multiple queues, one for each individual QoS, connection, flow or priority
A system includes a device including a transmitter associated with a link coupled to the device. The device is to receive from an application layer of the device, a first bitstream for transmission. The device is to encode the first bitstream into one or more blocks and transmit the one or more data blocks via the link. The device is also to receive a second bitstream to be transmitted. The device is to encode the second bitstream into a control block and transmit the control block via the link. The control block includes a first portion of bits corresponding to a header indicating the control block includes the second bitstream and a second portion of bits including the second bitstream.
A system for transmitting data is described, among other things. An illustrative system is disclosed to include one or more circuits to perform transmitting message-based data over packets. The circuits are capable of identifying a first message, transmitting a first portion of the first message in a first packet, the first packet including a bit indicating the first packet is message-based, and transmitting an end portion of the first message in a second packet, the second packet including a first bit indicating the second packet is message-based and a second bit indicating the second packet comprises the end portion of the first message.
Networking devices and optical communication systems are provided. In one example, a system is described to include a first physical coding sublayer (PCS) block that incorporates auto-negotiation information into a control block. The control block is transmitted to a second PCS block and the auto-negotiation information is used to enable negotiation between the first and the second PCS blocks.
A system including a device coupled with a link and including a transmitter. The device is to generate a first control block for synchronization via a physical layer of the link, the first control block including a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits indicating to perform a synchronization handshake. The device is further to transmit, via the link, the first control block comprising the header portion set of bits and the data portion of bit.
An integrated circuit (IC) includes one or more testable voltage decoupling (DCAP) cells. Each of the testable DCAP cells includes (i) one or more decoupling capacitors connected between supply rails of the IC, and (ii) a decoupling-test active logic (DTAL) circuit, which has a normal input-output response and is configured to deviate from the normal input-output response in response to a fault in the DCAP cell.
Systems and methods herein are for message or data aggregation in computer networks in which at least one processor of a network module receives communication including messages having data, determines destination host machines for the messages, and aggregates a subset of the messages or the data to be transmitted to one of different destination host machines, where the aggregation is based at least in part on a bandwidth and a buffer availability associated with the one destination host machine, and where the buffer availability is determined from a status communication between the one destination host machine and the host machine.
Systems and methods herein are for seamless offload of a workload to data processing units (DPUs), where one or more processing unit receive a selection of a first one of the plurality of DPUs to perform the workload, and perform a background operation to select second ones of the plurality of DPUs based, at least in part, on capabilities associated with the first one of the plurality of DPUs being within a threshold, where the workload is to be performed in a load balancing arrangement of the first one and second ones of the plurality of DPUs.
A receiver including an equalization component to receive a signal comprising a sequence of samples corresponding to symbols and generate an equalized signal with an estimated sequence of symbols corresponding to the signal. The receiver further includes a decision generation component to detect that an aggregate error level associated with the equalized signal exceeds a saturation threshold level. The decision generation component identifies a set of errors including a first error associated with a first symbol having a highest error level and a last error associated with a last symbol. The decision generation component generates, based on the equalized signal, a decision including a sequence of one or more bits that represent each symbol of a first subset of the sequence of symbols and a confidence level corresponding to the decision, where the confidence level is based at least in part on a distance between an error level of each symbol and a level of the first error.
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
80.
Tuning digital pre-distortion for a transmitter to correct non-linear errors in a receiver
A receiver device includes circuitry to measure an error vector of a pulse amplitude modulation (PAM) sequence in a signal received from a transmitter and control logic coupled to the circuitry. The control logic removes estimated linear components from the measured error vector to generate a non-linear error vector. The control logic further determines, with reference to a set of lookup table (LUT) values, one or more tuning parameters for the PAM sequence based on the non-linear error vector and modifies the set of LUT values according to the one or more tuning parameters. The control logic further provides the modified set of LUT values to the transmitter, which when used by the transmitter to add digital pre-distortion to the PAM sequence, causes the non-linear error to be at least partially removed from the signal.
A system, circuit, and method are described, among other things. An illustrative system is disclosed to include a processor and a memory storing data for processing by the processor. The data, when processed, causes the processor to receive an initiator message comprising a request to access one or more registers of a plurality of registers, determine that the initiator message corresponds to an entry of a privilege access table, determine a configured level of access control for the initiator message to access the one or more requested registers based at least in part on a group mapping table, and provide a level of access to the one or more requested registers corresponding to the received initiator message based on the initiator message corresponding to the entry of the privilege access table and based, at least in part, on the determined configured level of access control.
A system including a device coupled with a link and including a transmitter. The device is to generate a control block for synchronization via a physical layer of the link, the control block including a header portion of bits corresponding to a header indicating the message is a control block and a data portion of bits including synchronization information for synchronizing via the physical layer. The device is further to transmit, via the link, the control block comprising the header portion of bits and the data portion of bits.
Some embodiments of the present invention are directed to a multi-layer oxide aperture for a VCSEL. The oxide aperture may include multiple layers having different aluminum fractions that may reduce a spectral width of the VCSEL while maintaining longitudinal confinement. The oxide aperture may be formed from a mirror layer of the VCSEL proximate an active region. The mirror layer may include first epitaxial layers closest to the active region having a first aluminum fraction selected to longitudinally confine the optical field of the VCSEL. The mirror layer may include second epitaxial layers that have a second aluminum fraction low enough to prevent substantial oxidation of the second epitaxial layers. Additionally, the mirror layer may include third epitaxial layers that have a third aluminum fraction greater than the first and second aluminum fractions. The third epitaxial layers may be oxidized to form the oxide aperture.
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
84.
MODE-FILTERED LASER WITH MULTI-LAYER OXIDE APERTURE FOR HIGH-BANDWIDTH AND SIDE-MODE SUPPRESSION
Some embodiments of the present invention are directed to a mode-filtered VCSEL having a multi-layer oxide aperture for high-bandwidth and side-mode suppression. The oxide aperture may include multiple layers having different aluminum fractions configured to increase an SMSR of the VCSEL while maintaining longitudinal confinement. The oxide aperture may be formed from a mirror layer of the VCSEL proximate an active region. The mirror layer may include first epitaxial layers closest to the active region having a first aluminum fraction selected to longitudinally confine the optical field of the VCSEL. The mirror layer may include second epitaxial layers having a second aluminum fraction low enough to prevent substantial oxidation of the second epitaxial layers. Additionally, the mirror layer may include third epitaxial layers having a third aluminum fraction greater than the first and second aluminum fractions. The third epitaxial layers may be oxidized to form the oxide aperture.
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
A system for transmitting data is described, among other things. An illustrative system is disclosed to include one or more circuits to perform receiving a first packet, determining a header of the first packet includes a SYN, FIN, or RST flag, in response, delivering the first packet to a CPU, receiving a second packet, determining a header of the second packet does not include a SYN, FIN, or RST flag, and, in response, deliver the second packet to a GPU.
A network device includes one or more ports, processing circuitry, and a memory-network congestion controller. The one or more ports are to connect to a network. The processing circuitry is to run a plurality of processing tasks that access a shared memory, one or more of the processing tasks including communicating one or more packet flows over the network. The memory-network congestion controller is to identify a memory-access congestion, which occurs in accessing the shared memory by one or more of the processing tasks, and to alleviate the memory-access congestion by causing a reduction in a communication rate of at least one of the packet flows.
A system for bandwidth estimation includes an interface and a processor. The interface communicates with a fat-tree (FT) network including multiple switches including (i) leaf switches belonging to a bottom level, (ii) spine switches belonging to a top level and (iii) intermediate switches belonging to one or more intermediate levels. Links connect between selected ones of the switches. The processor is to calculate, for a given level of the FT network that is divided into multiple groups of switches, oversubscription ratios for the respective groups, an oversubscription ratio of a group being indicative of a ratio between (i) a first available bandwidth on the links connecting the switches in the group to a lower level, and (ii) a second available bandwidth on the links connecting the switches in the group to a higher level, and to report a figure of merit of the FT network based on the oversubscription ratios.
Quantum systems, devices, and methods are described herein that enable quantum metrology. An example quantum device includes a first quantum measurement module operably coupled with a first quantum system. The first quantum measurement module applies one or more measurements to the first quantum system and obtains first information associated with the first quantum system based on the one or more measurements. The quantum device further includes a first quantum memory structure operably coupled with the first quantum measurement module. A coherence time window associated with the first quantum memory structure is greater than a coherence time window time associated with the first quantum system. The quantum devices and associated memory structures provide a new methodology for a quantum metrology system.
A peripheral device includes a bus interface and an Address Translation Service (ATS) controller. The bus interface is to communicate over a peripheral bus. The ATS controller is to communicate over the peripheral bus, including sending address translation requests and receiving address translations in response to the address translation requests, to cache at least some of the address translations in one or more Address Translation Caches (ATCs), to estimate one or more statistical properties of the received address translations, and to configure the one or more ATCs based on the one or more statistical properties.
G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
Network devices and associated methods are provided for synchronization in an optically switched network. The network device includes one or more ports in communication with a plurality of devices via an optical switch. The one or more ports receive a master clock signal having a first frequency from a first device of the plurality of devices. The network device includes a local clock in communication with the one or more ports and operating at a second frequency. The network device includes a synchronization manager in communication with the one or more ports and the local clock and configured to be enabled and disabled. When the synchronization manager is enabled, it receives the master clock signal via the one or more ports and transmits an instruction to the local clock to operate at the first frequency.
A system includes a first device coupled with a link which transmits a signal having a repeating pattern, and a second device coupled with the link. The second device is to receive the signal, generate one or more delayed signals from the signal, determine a first duration of a first portion of the repeating pattern and a second duration of a second portion of the repeating pattern using the one or more delayed signals, and adjust a current duty cycle of the signal based on the first duration and the second duration.
Devices, methods, and systems are provided. In one example, a device is described to include a bandwidth-constrained resource and a controller that dynamically allocates a proportional consumption of storage to the bandwidth-constrained resource thereby enabling the bandwidth-constrained resource to provide bandwidth to a consuming entity. The controller may allocate the proportional consumption of the storage to the bandwidth-constrained resource based on a current state of the bandwidth-constrained resource.
A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.
A system comprises a first processing block configured to receive, from a first local resource, a formatted transaction in a format that is not recognizable by a remote endpoint; determine a first transaction category, from among a plurality of transaction categories, of the formatted transaction based on content of the formatted transaction; perform one or operations on the formatted transaction based on the first transaction category to form a reformatted transaction in a format that is recognizable by the remote endpoint; and place the reformatted transaction in a queue for transmission to the remote endpoint.
Devices and methods to identify malicious usage of a network device. In at least one embodiment, a network device comprises circuitry for performing a networking function and collecting telemetry data indicative of the performance of the networking function. The network device obtains an inference of a network traffic pattern using a machine learning model, and responds to the inference.
A network device for load balancing in a multiplane network comprises a software stack that formats a data flow for transmission, and one or more circuits that identify the formatted data flow as a fixed data flow, and apply software-based load balancing to select a first plane, from among a plurality of planes of the multiplane network, for transmitting one or more data packets of the fixed data flow.
A switching device includes ingress ports, egress ports, and switching circuits that connect the ingress ports with the egress ports. The switching device segments data included in a packet received at an ingress port into a plurality of segments. The switching device transfers the plurality of segments to an egress port via a data path included in the switching circuits, according to a first mode of routing the packet in an absence of reading a descriptor corresponding to the packet. The switching device orders, using port logic associated with the egress port, the segments and provides sequence numbers associated with the ordered segments to port logic associated with the ingress port. The switching device validates the transfer of the plurality of segments according to the first mode based on verifying that the sequence numbers satisfy at least one criterion.
A system for video encoding includes an acceleration device, to select from a video stream a target video frame and one or more reference frames. The target and reference frames are divided into respective first pluralities of first blocks of a first size and into respective second pluralities of second blocks of a second size, larger than the first size. At least a first map and a second map are computed, including respective motion vectors between each first block in the target video frame and corresponding first blocks in the reference frames, and between each second block in the target video frame and corresponding second blocks in the one or more reference frames. A control unit encodes the target video frame based on at least one of the reference frames by selecting motion vectors from among the motion vectors in the first and second maps.
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability
H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
99.
Systems and methods of initiating retransmission requests
A communication system is described, among other things. An illustrative system is disclosed to include one or more decoding circuits to perform forward error correction for a received data block in a physical layer and one or more cyclic redundancy check circuits to perform a cyclic redundancy check based on a first output of the decoding circuits and a cyclic redundancy check code generated in the physical layer based on the received data block. In response to one or more of a second output of the decoding circuits and an output of the cyclic redundancy check circuits, a retransmission request of the data block is initiated.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
100.
PRESERVING CONFIDENTIALITY OF TENANTS IN CLOUD ENVIRONMENT WHEN DEPLOYING SECURITY SERVICES
The technology disclosed herein enables an auxiliary device to run a service that can access and analyze data of a Trusted Execution Environment (TEE). The auxiliary device can determine that a host device comprises a first TEE established by a central processing unit (CPU) of the host device, where CPU executes a first computer program in the first TEE. The auxiliary device can receive data of the first TEE using a trusted communication link between the first TEE and a second TEE established by the DPU, and execute a second computer program in the second TEE to monitor execution of the first computer program.
G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
