Abstract

A system-on-chip (SoC) device is disclosed. According to the disclosure, the system-on-chip device comprises at least one power domain; and at least one power management unit (PMU) respectively corresponding to and controlling the at least one power domain, wherein the power management unit comprises a first region configured to perform processing and control, and a second region configured to physically transmit signals, and the first region and the second region are independently separated and respectively present in different components of the system-on-chip device.

IPC Classes  ?

• G06F 1/3234 - Power saving characterised by the action undertaken

Abstract

Disclosed are a clock divider and a method of controlling the same to ensure that an output clock of the clock divider is in a low level state during a retention signal transition period such that a retention operation can be performed smoothly. The clock divider includes a counter configured to count an input clock and generate a counter output for dividing the input clock, an output clock generator configured to generate clock edges according to the counter output and generate an output clock divided from the input clock, and a state machine configured to control the counter such that the output clock is in a low level during a retention signal transition period according to a clock low request from a power management unit.

IPC Classes  ?

• H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
• H03L 7/08 - Details of the phase-locked loop

Abstract

Disclosed are a system and method for designing a power management controller that performs power control of a plurality of power domains in a system-on-chip (SoC) device using a no-code approach. The system comprises a memory configured to store instructions and a processor configured to execute the instructions. The instructions include operations for generating a root power manager instance based on a root power manager component, generating at least one domain power manager instance based on one or more domain power manager components, establishing connections between output ports of the root power manager instance and input ports of the domain power manager instances, allocating memory storage space for each power manager instance, and generating hardware code of power elements, register code corresponding to the power elements, hardware code corresponding to ports and connections, and binary code corresponding to an operation sequence of the power management controller.

IPC Classes  ?

• G06F 1/26 - Power supply means, e.g. regulation thereof
• G06F 8/35 - Creation or generation of source code model driven
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

Disclosed are a semiconductor system and a method of controlling a reset operation clock of the semiconductor system for easily determining a reset timing by inputting a reference clock slower than a function clock to a clock operation unit by a clock multiplexer during a reset operation or reset release operation. The semiconductor system includes a clock management unit configured to operate according to a function clock to generate and output an output function clock for an operation of the semiconductor system, and a power management unit configured to perform power management of the semiconductor system including a reset operation or a reset release operation. The clock management unit includes a clock operation unit configured to operate according to the function clock in an operation mode to generate and output the output function clock, and a clock multiplexer configured to select different input clocks to be input to the clock operation unit in the operation mode and a reset mode and output the input clocks to the clock operation unit.

IPC Classes  ?

• G06F 1/24 - Resetting means
• G06F 1/08 - Clock generators with changeable or programmable clock frequency

Abstract

A system and method for designing a clock management unit using a no-code approach capable of testing a clock component that configures a clock management unit and generating a test clock along a functional clock generation path. The at least one instruction includes instructions for: generating a clock instance including a clock source block, a clock control signal block, and a test multiplexer block based on clock component information; generating a test mode controller instance including a test mode TDR block and a test control TDR block corresponding to the test multiplexer block; setting a connection between the test multiplexer block and the test mode controller instance; and generating hardware code based on connection information and the hardware code logic of the clock instance and the test mode controller instance.

IPC Classes  ?

• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• G01R 31/317 - Testing of digital circuits

Abstract

A clock divider and a clock division method using the same for maintaining a constant output clock duty regardless of a divide value change timing are provided. The clock divider includes a counter configured to count an input clock to generate a counter output based on a count of a first counter expiration value corresponding to a divide value of the clock, an output clock generator configured to generate an output clock divided from the input clock according to the counter output of the counter, and a state machine configured to update the counter to a second counter expiration value corresponding to a changed divide value depending on whether the first counter expiration value has expired based on the divide value being changed.

IPC Classes  ?

• H03K 21/40 - MonitoringError detectionPreventing or correcting improper counter operation

Abstract

A power test system capable of performing a power test on a power management interface in a test mode and a system-on-chip including the same. The power test system according to an embodiment of the present disclosure includes: a target power test controller that generates a target power test mode signal indicating whether a target is in a test mode and target power test data provided to the target while a target test mode is activated; and a target power controller that receives a pure test mode signal indicating whether the target is in a pure test mode, the target power test mode signal and the target power test data, transmits preset data to the target when the pure test mode is activated, and transmits the target power test data to the target when both the pure test mode and the target test mode are activated.

IPC Classes  ?

• G01R 31/317 - Testing of digital circuits

Abstract

The present disclosure provides a system and method for designing a power management cluster using a no-code approach, enabling test reset delivery through the same path as a functional reset in test mode. The system includes at least one processor executing instructions stored in memory, the instructions comprising: generating a power instance from power component information; generating a reset controller instance upstream of the power instance to transmit a reset output to a target; setting first connection information between the target and the reset controller instance; generating a reset test controller instance including a test mode TDR block and a test control TDR block; setting second connection information between the reset and reset test controller instances; and generating hardware code based on the components and connection information.

IPC Classes  ?

• G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

The present disclosure relates to a test mode control system capable of testing a clock component that configures a clock management unit and generating a test clock by driving the clock component that generates a functional clock and a system-on-chip including the same. The test mode control system according to an embodiment of the present disclosure includes: a test mode controller that transmits a clock control signal to a clock source that configures a high-speed domain of a clock management unit in a test mode; and a test multiplexer that transfers a clock control signal input from the test mode controller to the clock source in the test mode and transfers a clock control signal input from a clock control circuit corresponding to the clock source to the clock source in a functional mode.

IPC Classes  ?

• G01R 31/3187 - Built-in tests
• G01R 31/317 - Testing of digital circuits
• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning

Abstract

A reset test system and a system-on-chip, which enable a test reset to be transmitted through the same path as a functional reset in a reset test mode. The reset test system includes a scan test controller configured to generate a scan test enable signal, a scan reset control signal, and a scan reset deactivation signal; a target reset test controller configured to generate a target reset test mode signal and target reset test data; a leading target reset controller configured to synchronize a leading reset input to a functional clock in a functional mode and to output the target reset test data as a leading reset output in a scan test mode; and a following target reset controller configured to receive the leading reset output as a following reset input, synchronize it to the functional clock in the functional mode, and output the target reset test data.

IPC Classes  ?

• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning

Abstract

The present disclosure relates to a system and method for designing a power management cluster using a no-code approach, which enables data testing on power elements in a test mode. The system includes at least one processor configured to execute at least one instruction stored in a memory. The instruction includes: generating a power instance including a power management block, a power interface block, and a data controller block based on power component information; generating a data test controller instance including a test mode TDR block and a test control TDR block corresponding to the data controller block; setting a connection between the data controller block and the data test controller instance; and generating hardware code based on hardware code logic and the connection information of the power instance and the data test controller instance.

IPC Classes  ?

• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning

Abstract

The present disclosure relates to a system and method for providing a flowchart-based user interface to a user and generating instruction codes of a microcontroller unit based on an operation process of the microcontroller unit designed by the user. The system for generating the instruction codes of the microcontroller unit according to an embodiment of the present disclosure includes: a memory configured to store at least one instruction; a component storage; a code conversion logic storage; and a processor, wherein the at least one instruction includes instructions for: generating a first flowchart instance based on at least one flowchart component; further receiving a target component and at least one of a property, and a value of the first flowchart instance to generate an operation process; and converting the operation process into an instruction code including an instruction, a register address, and data based on the code conversion logic.

IPC Classes  ?

• G06F 8/34 - Graphical or visual programming
• G06F 8/51 - Source to source

Abstract

A reset test system includes: a scan test controller that generates a scan test enable signal indicating whether a scan test mode is activated, a scan reset control signal controlling reset in the scan test mode, and a scan reset deactivation signal controlling the reset to be deactivated in the scan test mode; a target reset test controller that generates a target reset test mode signal indicating whether a target is in a test mode and target reset test data; and a target reset controller that receives the scan test enable signal, the scan reset control signal, the scan reset deactivation signal, the target reset test mode signal, the target reset test data, reset input, and a functional clock of the target, outputs the reset input in synchronization with the functional clock, and outputs the target reset test data when the reset is activated in the scan test mode.

IPC Classes  ?

• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• G01R 31/317 - Testing of digital circuits

Abstract

A system and method for designing a programmable sequencer capable of modifying power up and power down sequences for power control in a power domain using a no-code approach. According to one embodiment, the system includes a memory to store at least one instruction, a component storage configured to store power component information and instruction component information, a code logic storage configured to store software code logic for generating executable code based on an instruction instance, and at least one processor configured to execute the stored instruction(s). The instruction(s) include operations for generating at least one power instance based on a power component, generating a first instruction instance based on an instruction component, determining a target power instance among the generated power instances and setting a value, and generating code including an instruction, a register address, and data based on the instruction instance, the target power instance, and the value.

IPC Classes  ?

• G06F 8/34 - Graphical or visual programming

Abstract

Disclosed are clock management unit design system and method for designing an internal function module of clock elements constituting a clock management unit and connections between the clock elements using a no-code approach. A clock management unit design system using a no-code approach includes: a memory configured to store at least one instruction; a clock component storage configured to store clock component information constituting a clock management unit; a hardware code logic storage configured to store hardware code logic for generating a designed clock management unit as hardware code; and at least one processor configured to execute the at least one instruction stored in the memory

IPC Classes  ?

• G06F 30/32 - Circuit design at the digital level
• G06F 117/04 - Clock gating

Abstract

Disclosed are a clock element no-code design system including: a memory configured to store at least one instruction; a clock component storage configured to store clock component information defining an address and field values of a register of a clock instance generated based on a clock component; a hardware code logic storage configured to store a hardware code logic for generating hardware code based on a designed clock instance; and at least one processor configured to execute the at least one instruction stored in the memory, wherein the at least one instruction includes instructions to: design a new clock instance by setting field values of a register defining a function of the new clock instance based on previously generated clock instance information and the clock component information, and generate hardware code by generating a clock module and a register module corresponding to the clock module based on the field values of the register of the designed new clock instance and the hardware code logic, and combining the clock module and the register module.

IPC Classes  ?

• G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom

Goods & Services

Software design and development; Design and development of computer software for the design of semiconductor chips; Maintenance of computer software; Installation, maintenance and repair of computer software; Application service provider (ASP) featuring software for use in the design of semiconductor chips; Testing of semiconductors; Software as a service (SAAS) services featuring software for the design of semiconductor chips; Platform as a service (PAAS) featuring computer software platforms for the design of semiconductor chips

Goods & Services

Software design and development; Design and development of computer software for the design of semiconductor chips; Maintenance of computer software; Installation, maintenance and repair of computer software; Application service provider (ASP) featuring software for use in the design of semiconductor chips; Testing of semiconductors; Software as a service (SAAS) services featuring software for the design of semiconductor chips; Platform as a service (PAAS) featuring computer software platforms for the design of semiconductor chips

Goods & Services

Software design and development; Design and development of computer software for the design of semiconductor chips; Maintenance of computer software; Installation, maintenance and repair of computer software; Application service provider (ASP) featuring software for use in the design of semiconductor chips; Testing of semiconductors; Software as a service (SAAS) services featuring software for the design of semiconductor chips; Platform as a service (PAAS) featuring computer software platforms for the design of semiconductor chips

Goods & Services

Software design and development; Design and development of computer software for the design of semiconductor chips; Maintenance of computer software; Installation, maintenance and repair of computer software; Application service provider (ASP) featuring software for use in the design of semiconductor chips; Testing of semiconductors; Software as a service (SAAS) services featuring software for the design of semiconductor chips; Platform as a service (PAAS) featuring computer software platforms for the design of semiconductor chips

Goods & Services

Software design and development; Design and development of computer software for the design of semiconductor chips; Maintenance of computer software; Installation, maintenance and repair of computer software; Application service provider (ASP) featuring software for use in the design of semiconductor chips; Testing of semiconductors; Software as a service (SAAS) services featuring software for the design of semiconductor chips; Platform as a service (PAAS) featuring computer software platforms for the design of semiconductor chips

Goods & Services

Software design and development; Design and development of computer software for the design of semiconductor chips; Maintenance of computer software; Installation, maintenance and repair of computer software; Application service provider (ASP) featuring software for use in the design of semiconductor chips; Testing of semiconductors; Software as a service (SAAS) services featuring software for the design of semiconductor chips; Platform as a service (PAAS) featuring computer software platforms for the design of semiconductor chips

Abstract

Disclosed are a semiconductor system design automation apparatus and a semiconductor system design automation method for automating semiconductor system design based on no-code or low-code according to a simple selection and arrangement operation for a semiconductor component input by a user. The semiconductor system design automation apparatus includes a semiconductor component storage unit in which component information on various semiconductor components utilizable in semiconductor system design is stored, a semiconductor design operation input unit configured to receive a selection and arrangement operation of a user for at least one semiconductor component, and a semiconductor system automatic design unit configured to automate a design of a semiconductor system including the at least one semiconductor component according to the selection and arrangement operation of the user.

IPC Classes  ?

• G06F 30/31 - Design entry, e.g. editors specifically adapted for circuit design
• G06F 115/08 - Intellectual property [IP] blocks or IP cores

Abstract

The present invention relates to a system on chip by which at least two system on chips can be connected and expanded, and a multi-chip power management system. The system on chip according to the present invention, including one or more first power domains and being connected to a second system on chip, comprises: a central processing unit for generating a first power management signal for power management of the one or more first power domains and a second power management signal for power management of one or more second power domains included in the second system on chip; a power management unit for performing a power up/down sequence for each of the one or more first power domains on the basis of the first power management signal under control of the central processing unit; and a connection unit for transmitting the second power management signal to the second system on chip under control of the central processing unit.

IPC Classes  ?

• G06F 1/3234 - Power saving characterised by the action undertaken
• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit

Abstract

A clock control circuit according to the present invention comprises: a first signal line interface for interfacing with a first parent 4-channel signal line connected to a first parent clock control circuit; and a controller, which controls the first signal line interface such that handshake with the first parent clock control circuit is performed through the first parent 4-channel signal line. The first parent 4-channel signal line comprises: a crew signal line for transmitting clock necessity state information of a clock source to the first parent clock control circuit; a handshake request signal line for receiving a handshake request from the first parent clock control circuit; an acknowledgement signal line for providing an acknowledgement of the handshake request to the first parent clock control circuit; and a negative acknowledgement signal line for providing a negative acknowledgement of the handshake request to the first parent clock control circuit.

IPC Classes  ?

• G06F 1/06 - Clock generators producing several clock signals
• H03L 7/08 - Details of the phase-locked loop
• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit

Abstract

The present invention relates to a power control system that controls power of a plurality of power domains constituting a system-on-chip device by simultaneously performing power control determination at a software level and power control execution at a hardware level, and to a system-on-chip device comprising same. The power control system, according to the present invention, comprises: a central processing unit that determines power-up or power-down for at least one control target power domain among the plurality of power domains included in the system-on-chip device, and transmits at least one domain power control command of a domain power-up command and a domain power-down command on the basis of the domain power-up/down determination; and a domain power manager that receives the domain power control command and performs at least one of a power-up sequence and a power-down sequence for the control target power domain.

IPC Classes  ?

• G06F 1/3234 - Power saving characterised by the action undertaken
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit

Abstract

The present invention relates to: a programmable sequencer capable of changing a power up/down sequence for power control of a power domain; and a system-on chip device using same. The programmable sequencer according to the present invention comprises: a processing unit, which receives, from a central processing unit, a command related to power control of at least one object to be controlled, accesses a memory in which at least one instruction for performing the command is stored, and executes the at least one instruction stored in the memory; and a register bank of which at least one register field value is changed by the processing unit so that a power control signal is transmitted to the object to be controlled, wherein the memory stores the at least one instruction for performing the command by the central processing unit.

IPC Classes  ?

• G06F 1/3234 - Power saving characterised by the action undertaken
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit

Goods & Services

Downloadable computer software and recorded computer software for designing semiconductors; downloadable computer software for manufacturing semiconductors; downloadable computer software for improving efficiency in semiconductor manufacturing; downloadable computer software for use in processing semiconductor wafers; downloadable computer operating system software; downloadable and recorded computer operating software; downloadable computer software to maintain and operate computer systems; downloadable and recorded digital wireless telecommunications software for managing efficiency in semiconductor manufacturing; Downloadable and recorded computer software for digital information and data access; downloadable computer software for processing digital images; Downloadable and recorded simulation software for use in digital computers for designing and manufacturing semiconductors; Downloadable and recorded computer programs for user interface design; downloadable computer software for application and database integration; downloadable database management software applications; Semiconductors and structural parts therefore; semiconductor component, namely, electric conductors; semiconductor devices; electronic integrated circuits; computers

Goods & Services

Downloadable computer software and recorded computer software for designing semiconductors; downloadable computer software for manufacturing semiconductors; downloadable computer software for improving efficiency in semiconductor manufacturing; downloadable computer software for use in processing semiconductor wafers; downloadable computer operating system software; downloadable and recorded computer operating software; downloadable computer software to maintain and operate computer systems; downloadable and recorded digital wireless telecommunications software for managing efficiency in semiconductor manufacturing; Downloadable and recorded computer software for digital information and data access; downloadable computer software for processing digital images; Downloadable and recorded simulation software for use in digital computers for designing and manufacturing semiconductors; Downloadable and recorded computer programs for user interface design; downloadable computer software for application and database integration; downloadable database management software applications; Semiconductors and structural parts therefore; semiconductor component, namely, electric conductors; semiconductor devices; electronic integrated circuits; computers

Goods & Services

Downloadable computer software and recorded computer software for designing semiconductors; downloadable computer software for manufacturing semiconductors; downloadable computer software for improving efficiency in semiconductor manufacturing; downloadable computer software for use in processing semiconductor wafers; downloadable computer operating system software; downloadable and recorded computer operating software; downloadable computer software to maintain and operate computer systems; downloadable and recorded digital wireless telecommunications software for managing efficiency in semiconductor manufacturing; Downloadable and recorded computer software for digital information and data access; downloadable computer software for processing digital images; Downloadable and recorded simulation software for use in digital computers for designing and manufacturing semiconductors; Downloadable and recorded computer programs for user interface design; downloadable computer software for application and database integration; downloadable database management software applications; Semiconductors and structural parts therefore; semiconductor component, namely, electric conductors; semiconductor devices; electronic integrated circuits; computers

Goods & Services

Downloadable computer software and recorded computer software for designing semiconductors; downloadable computer software for manufacturing semiconductors; downloadable computer software for improving efficiency in semiconductor manufacturing; downloadable computer software for use in processing semiconductor wafers; downloadable computer operating system software; downloadable and recorded computer operating software; downloadable computer software to maintain and operate computer systems; downloadable and recorded digital wireless telecommunications software for managing efficiency in semiconductor manufacturing; downloadable and recorded computer software for digital information and data access; downloadable computer software for processing digital images; downloadable and recorded simulation software for use in digital computers for designing and manufacturing semiconductors; downloadable and recorded computer programs for user interface design; downloadable computer software for application and database integration; downloadable database management software applications; semiconductors and structural parts therefor; semiconductor component, namely, electric conductors; semiconductor devices; electronic integrated circuits; computers

Goods & Services

Downloadable computer software and recorded computer software for designing semiconductors; downloadable computer software for manufacturing semiconductors; downloadable computer software for improving efficiency in semiconductor manufacturing; downloadable computer software for use in processing semiconductor wafers; downloadable computer operating system software; downloadable and recorded computer operating software; downloadable computer software to maintain and operate computer systems; downloadable and recorded digital wireless telecommunications software for managing efficiency in semiconductor manufacturing; Downloadable and recorded computer software for digital information and data access; downloadable computer software for processing digital images; Downloadable and recorded simulation software for use in digital computers for designing and manufacturing semiconductors; Downloadable and recorded computer programs for user interface design; downloadable computer software for application and database integration; downloadable database management software applications; Semiconductors and structural parts therefore; semiconductor component, namely, electric conductors; semiconductor devices; electronic integrated circuits; computers

Abstract

A system-on-chip device is disclosed. Accordingly, the system-on-chip device comprises: one or more power domains; and one or more power management units (PMUs) corresponding to the respective one or more power domains so as to control same, wherein the PMUs each comprise a first area in charge of processing and control, and a second area for physically transferring a signal, and the first area and the second area may be independently divided so as to be present in mutually different components of the system-on-chip device.

IPC Classes  ?

• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
• G06F 30/32 - Circuit design at the digital level
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 1/3234 - Power saving characterised by the action undertaken
• G06F 115/02 - System on chip [SoC] design