Provided is a semiconductor device capable of improving reliability of a lead member and a joint part thereof in a structure that has the lead member integrated with a case. A semiconductor device (1) comprises: a substrate (40) that is disposed on a base (10) and has a conductor pattern (45) on a surface opposite from the base (10); a case (20) that encloses the substrate (40); a semiconductor element (50) that is disposed on the conductor pattern (45); and a band-shaped lead member (30) that is formed integrally with the case (20) and has one end side extending from an inner wall (20a) of the case (20) so as to be joined to the conductor pattern (45). The lead member (30) has a root part (31) positioned at the root of the case (20), an opposed part (33) facing the conductor pattern (45) on a surface parallel to the substrate (40), and a band-shaped bridge part (32) for bridging between the root part (31) and the facing part (33). The bridge part (32) extends from the case (20) so that the band surface thereof becomes perpendicular to the substrate (40). The bridge part (32) has a length of 10-60 mm.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
2.
POWER CONVERSION DEVICE, METHOD OF CONTROLLING POWER CONVERSION DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF CONTROLLING SEMICONDUCTOR DEVICE
A power conversion device configured to convert electric power using a semiconductor device includes a MOS controlled diode 1 made up of an n+ layer 11, an n− layer 12, a p− layer 13, a p+ layer 14, a cathode electrode 21, anode electrodes 22 and 220, and gate electrodes 23 and a voltage applying unit configured to apply forward voltage between the anode electrodes 22 and 220 and the cathode electrode 21 during a forward direction, to apply a reverse voltage between the anode electrodes 20 and 220 and the cathode electrode 21 during a reverse recovery, and to control a potential of the gate electrode 23 to a potential at which an inversion layer is formed in a third semiconductor layer with respect to a potential of the anode electrodes 22 and 220 before the reverse recovery. In this way, a power conversion device, a method of controlling a power conversion device, a semiconductor device, and a method of controlling a semiconductor device that are capable of further reducing power loss are provided.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H02M 7/537 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
H03K 17/16 - Modifications for eliminating interference voltages or currents
The present invention provides a semiconductor device that makes it possible to reduce stress which occurs at the time of bonding and to suppress the occurrence of current resonance. Provided is a semiconductor device comprising a semiconductor element, wiring that is formed on a substrate, and a metal component that is ultrasonically bonded to the wiring, wherein: the semiconductor element is electrically connected to the wiring; the metal component has a main part and a first portion and second portion which each branch from the main part, and the tip end parts of each of which are ultrasonically bonded to the wiring; and the metal component has a slit that is formed in the vicinity of the location where the first portion and the second portion branch from the main part and that is along a direction substantially parallel to a direction from the first portion toward the second portion.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
4.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device (100) comprises: a gate insulating film (16) disposed inside of a trench (2); a gate electrode (7) including a region at least partially disposed inside of the trench (2); a first conductivity-type JFET region (8) disposed below a channel region (5); and a second conductivity-type body region (9) disposed to the side of the JFET region (8). The gate insulating film (16) is such that an oxide film (16a) on a substrate surface in the trench short-side direction is wider than an oxide film (16b) that contacts the channel region (5) in the trench short-side direction.
Provided is a semiconductor device with which it is possible to improve surge current resistance by arranging a diode region without being restricted by the shape of a lead frame. A semiconductor device (1A) comprises: a semiconductor element (100) having a diode region (103) and a transistor region (102) that are continuous and adjacent to each other between an obverse-surface electrode and a reverse-surface electrode; a lead frame (108) that is joined to the obverse-surface electrode in a junction region on the obverse-surface-electrode side; and a joining member (106) that is provided so as to cover the diode region (103), the joining member (106) joining the obverse-surface electrode and the lead frame (108). In plan view, the region in which the diode region (103) and the joining region of the lead frame (108) overlap is smaller than the diode region (103).
A semiconductor device (11) is configured by forming an IGBT region (17) and a diode region (19) in a drift layer (101) of a first conductivity type. The diode region (19) has a structure in which a cathode electrode (21b), a cathode layer (116), a buffer layer (113), the drift layer (101), an anode layer (117), an insulating layer (111), and an anode electrode (23b) are layered from the lower side to the upper side. A columnar third through-contact part (33) having a depth reaching the anode layer (117) is formed in the anode electrode (23b) in a state of penetrating the insulating layer (111). A second high-concentration contact layer (37) of a second conductivity type is formed in the third through-contact part (33). The third through-contact part (33) and the second high-concentration contact layer (37) are provided selectively along the front-to-back direction so as to be in contact with the upper-side surface of a recessed part (117a) of the anode layer (117).
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 89/00 - Aspects of integrated devices not covered by groups
The present invention reduces on-resistance while ensuring short-circuit withstand in a trench MOSFET which has a vertical channel fin structure. Provided is a trench MOSFET which has a vertical channel fin structure comprising a plurality of trenches 2 having a longitudinal direction in a first direction and being arranged in multiple rows in a second direction. The trench MOSFET comprises: a JFET region 8 of a first conductivity type that is sandwiched between body regions 9 of a second conductivity type; and a first current spreading region 23A of the first conductivity type that is sandwiched between first pocket regions 22A of the second conductivity type arranged spaced apart from the body regions 9 with first intermediate regions 21A therebetween. A length (WJ) of the JFET region 8 in the first direction is less than a length (Wp1) of the first current spreading region 23A in the first direction. An impurity concentration of a drift region 10 is less than an impurity concentration of the first current spreading region 23A, which is less than or equal to an impurity concentration of the first intermediate region 21A, which in turn is less than an impurity concentration of the JFET region 8. The dimensions of the body regions 9 and the JFET region 8 in a depth direction from the bottom of the trench 2 are both greater than 0.5 μm.
A motor control device (11) includes: an information acquisition unit (21) that acquires information pertaining to the drive state of a motor (18), including the rotation speed (RSmtr) of the motor (18) and a DC voltage value (Vdc); an information storage unit (23) that stores correspondence relationship information between the DC voltage value (Vdc) and an optimal carrier frequency (fpwm_op) for each rotation speed (RSmtr) of the motor (18); an optimal carrier frequency setting unit that sets the optimal carrier frequency (fpwm_op) in accordance with the drive state of the motor (18) on the basis of the rotation speed (RSmtr) of the motor (18) and the DC voltage value (Vdc) acquired by the information acquisition unit (21) and the storage contents of the information storage unit (23); and a PWM control unit (27) that controls an inverter (17) on the basis of the set optimal carrier frequency (fpwm_op). As a result, it is possible to obtain a motor control device (11) having excellent versatility which makes it possible to easily cope with various target systems.
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
H02M 7/48 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
9.
ELECTRONIC COMPONENT INSPECTION METHOD AND ELECTRONIC COMPONENT INSPECTION DEVICE
In the present invention, a first optical image and a second optical image are acquired, and from such optical images it is possible to detect a plane of a solder connection part of a first electrode in an electronic component and a plane of a solder connection part of a second electrode in the electronic component. The relative position between the plane of the solder connection part of the first electrode and the plane of the solder connection part of the second electrode in the electronic component is calculated from at least one of the first optical image and the second optical image, and the flatness of the first electrode and the second electrode is calculated to determine the quality of the appearance of the electronic component.
A semiconductor device 1 comprises: a collector layer 5; a drift layer 4 stacked on the collector layer 5; a base layer 32 stacked on the drift layer 4; first gates 21 arranged side by side on the drift layer 4 in the gate length direction; and second gates 22 which are arranged side by side with some of the first gates 21 and which can be driven independently of the first gates 21. The semiconductor device is partitioned into a first region Hc and a third region Ts where the first gates 21 are disposed, and a second region Hs where the first gates 21 and the second gates 22 are disposed. The semiconductor device is disposed such that the third region Ts is disposed between the first region Hc and the second region Hs in the gate length direction. In the collector layer 5, the carrier concentration in the second region Hs and the third region Ts is lower than the carrier concentration in the first region Hc.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
Provided is a semiconductor device that achieves improved reliability when a semiconductor element is operated at a high temperature. Provided is a semiconductor device (1), in which the maximum value of the operating temperature of a semiconductor element (50) is 150°C or higher. The semiconductor device comprises: a conductor pattern (20); a semiconductor element (50) that is disposed on the conductor pattern (20) via a bonding member (40); and a sealing member (30) that contacts the conductor pattern (20), the bonding member (40), and the semiconductor element (50) and thereby seals these components, and that has added thereto an ion scavenger (32) for capturing ions of a metal (metal ions (42)), the metal being contained in the bonding member (40).
Provided is a rectifier circuit using a switching element and having a small reverse current and a low loss. A rectifier circuit 10 comprises an anode A, a cathode K, a first switching element Q1, a first diode D1, a second switching element Q2, a second diode D2, a capacitor C1, a comparator Co1, a gate driver GD1, and a control circuit 2. The control circuit 2 controls to turn off the second switching element Q2 or turn on the second switching element Q2 in a high resistance state at least during a period in which reverse recovery current due to reverse recovery of the first diode D1 flows in a direction from the cathode K of the rectifier circuit 10 to the anode A of the rectifier circuit 10.
H02M 7/21 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
A semiconductor component (20) is characterized by being provided with a semiconductor device (1), an emitter electrode (aluminum electrode (2E)) and a gate electrode (aluminum electrode (2G)) being provided on the semiconductor device (1), a plating part (Ni plating layer (3E)) being formed on the emitter electrode so as to cover the emitter electrode, the gate electrode being formed as a non-plated part composed of a sputtered film. The non-plated part has a rectangular shape in a plan view, and three corners of the rectangular shape are right-angled. The plating part facing the non-plated part has an R shape in a plan view.
The present invention enables stable performance of a determination operation in a comparator circuit. This semiconductor device is configured by including: a differential amplifier circuit having a three-stage circuit configuration between a power supply and a ground; and an output stage circuit provided at a rear stage of the differential amplifier circuit, the output stage circuit having a current-mirror type circuit configuration, and the circuit configuration between the power supply and the ground having a two-stage circuit configuration, in which a differential between a potential of a reference node of the differential amplifier circuit and a potential of a determination node is detected.
A drive circuit (100) for a semiconductor device is characterized by: during turn-off, increasing and holding the voltage of a gate drive device (120) at an intermediate voltage (Vint_com) larger than an off voltage, which is lower than a drive voltage, for a second period (Tint) after a first period (Tdraw) in which an instruction logic unit (110) issues an instruction for the off voltage; and temporarily increasing and holding a gate voltage (Vg) of an element at a voltage (Vint) larger than the off voltage and smaller than a threshold voltage (Vth). The drive circuit is characterized in that the end timing of the first period (Tdraw) is later than the start of a mirror period and earlier than the end of the mirror period, and the end timing of the second period (Tint) is later than a timing when the element reaches a surge voltage (Vsurge).
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage
H03K 17/695 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors having inductive loads
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
This semiconductor device achieves an improvement in gate withstand voltage and a reduction in on resistance. The semiconductor device comprises: first conductivity-type first semiconductor layer and second semiconductor layer; a plurality of second conductivity-type third semiconductor layers; a first conductivity-type fourth semiconductor layer that is interposed between the plurality of third semiconductor layers; a second conductivity-type fifth semiconductor layer that is interposed between the plurality of third semiconductor layers; a first conductivity-type sixth semiconductor layer; a second conductivity-type seventh semiconductor layer that has higher concentration than the third semiconductor layer; a plurality of first trenches that penetrate the fifth semiconductor layer and the sixth semiconductor layer and form a fin structure, the first trenches having bottom corners, in a longitudinal direction, in the third semiconductor layer; a second trench that connects the plurality of first trenches; a gate electrode that is in contact with a gate insulating film formed in the first trench and the second trench and is embedded in the first trench and the second trench; a drain electrode that is connected to the first semiconductor layer; and a source electrode that is connected to the sixth semiconductor layer and the seventh semiconductor layer.
In the present invention, oscillation caused by switching of a rectifying element is suppressed by reducing the influence of a time constant caused by the parasitic capacitance, etc., of the rectifying element. This semiconductor device is configured to comprise: a rectifying element; a determination circuit that determines ON/OFF of the rectifying element on the basis of the voltage between a pair of output terminals of the rectifying element; an amplification circuit that controls ON/OFF of the rectifying element on the basis of the determination result of the determination circuit; and a voltage division circuit connected between an output terminal of the amplification circuit or an input terminal of the rectifying element and one of the output terminals of the rectifying element. The determination circuit sets a divided voltage of a node of the voltage division circuit as a positive input or a negative input.
H02M 7/21 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
H03K 17/16 - Modifications for eliminating interference voltages or currents
This semiconductor device includes an IGBT region (105), a diode region (106), and an IGBT/diode boundary region (210) in a plan view. The IGBT/diode boundary region (210) is provided with a low-concentration p-type anode layer (211) which is adjacent to a low-concentration n-type drift layer (214), is formed in the vicinity of the surface opposite to a p-type collector layer (209), is electrically connected to a surface metal electrode (208), is doped at a concentration lower than that of a p-type base layer, is formed deeper than a side gate (204) and a trench (205), and covers the trench (205).
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
19.
SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE USING SAME
Provided is a semiconductor device in which a gate-anode region of a diode can be provided in a small area even if the diode region is an isolated dot type in a reverse conducting IGBT (RC-IGBT) incorporating an IGBT and a diode in the same chip, and current density per chip can be improved. This semiconductor device comprises an IGBT and a diode in the same chip, and is characterized in that the IGBT comprises a drift layer, a plurality of first trenches formed in the drift layer, and a gate electrode having a sidewall structure provided in the first trench, and the diode comprises the drift layer, a plurality of second trenches formed in the drift layer, and a structure in which a conductive member is embedded in the second trench.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/20 - Electrodes characterised by their shapes, relative sizes or dispositions
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
20.
SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE
Provided is a semiconductor device that makes it possible to suppress loss while controlling a jump-up voltage at turn-off and turn-on under all conditions for an output electric current and a temperature within a use range. The semiconductor device comprises an IGBT and a driving circuit that drives a gate of the IGBT. The driving circuit includes four MOSFETs and four resistors constituting a bridge circuit, a driver for driving each of the four MOSFETs, an electric current detection circuit for detecting an output electric current of the IGBT, a temperature detection circuit for detecting the temperature of the IGBT, and a determination circuit for controlling driving of the driver on the basis of detection values from the electric current detection circuit and the temperature detection circuit. When the output electric current detected by the electric current detection circuit is greater than a prescribed electric current threshold value, the determination circuit increases an OFF gate resistance of the IGBT. When the temperature detected by the temperature detection circuit is lower than a prescribed temperature threshold value, the determination circuit increases an ON gate resistance of the IGBT.
The present invention suppresses the operation of a parasitic bipolar transistor during recovery switching, and achieves both low loss and high recovery resistance. A gate-controlled diode 101 includes: a first semiconductor layer 1 of a first conductivity type; a second semiconductor layer 2 of the first conductivity type in which the impurity concentration is lower than in the first semiconductor layer 1; a third semiconductor layer 3 of a second conductivity type; a fourth semiconductor layer 4 of the second conductivity type in which the impurity concentration is higher than in the third semiconductor layer 3; a fifth semiconductor layer 5 of the second conductivity type in which the impurity concentration is higher than in the fourth semiconductor layer 4; a sixth semiconductor layer 6 of the first conductivity type; a first electrode 11; a second electrode 12; a gate insulating film 23; and a gate electrode 22. The second electrode 12 has a protruding part 12A in contact with the fifth semiconductor layer 5 and the sixth semiconductor layer 6. The fourth semiconductor layer 4 is in contact with the fifth semiconductor layer 5 and the gate insulating film 23. The fourth semiconductor layer 4 and the sixth semiconductor layer 6 are disposed so as not to overlap in a plan view.
A power conversion device (11) comprises: an upper arm IGBT (13) provided between a main DC power supply (Vdc) and an output terminal (Pout); a gate short-circuit MOSFET (17) provided between a first gate terminal (13G) of the upper arm IGBT (13) and an output terminal (Pout) and having a first parasitic capacitance (Cgs) formed in parallel therewith; a first Zener diode (DZ1) provided between a second gate terminal (17G) of the gate short-circuit MOSFET (17) and the output terminal (Pout); a first diode (D1) provided between the main DC power supply (Vdc) and the first Zener diode (DZ1) and having a second parasitic capacitance (Cd1) formed in parallel therewith; and a second diode (D2) provided close to the first diode (D1) and irradiating the first diode (D1) with light.
This semiconductor device (30) comprises: an active region; and a termination region that is disposed around the active region in plan view and has a corner portion. The active region and the termination region each have a first lifetime control layer (41) and a second lifetime control layer (42) in a drift layer. The corner portion of the termination region have a third lifetime control layer (43) that has a larger defect amount than the first lifetime control layer 41 of the active region and has a larger defect amount than the first lifetime control layer in the other portions of the termination region.
Provided is a semiconductor device that makes it easy to ensure broad contact between a sintered metal and a joint boundary surface. A semiconductor device according to the present invention comprises a first member that is made of metal and a second member that includes a semiconductor chip. The first member and the second member are joined by sintering. Recesses and protrusions are formed at at least one joint boundary surface of the first member and the second member such that the interval of the recesses and protrusions is no more than 10 μm.
This semiconductor device includes: a base plate on which a semiconductor chip is mounted on a first principal surface side; and a thermal interface material which is arranged on a second principal surface side opposite to the semiconductor chip mounting surface of the base plate, and the elastic modulus of which changes due to a phase change at a phase change temperature. The base plate has a convex warpage on the second principal surface side, and the thermal interface material has a phase change temperature of 40°C-100°C inclusive.
The present invention obtains a semiconductor device which properly protects a circuit to be protected from overvoltage. This semiconductor device comprises: first to third elements (M1 to M3) that are depletion-type MOSFET; and a fourth element (M4) that is a switching element. The drain terminal of the first element is connected to a power supply (92) and the source terminal thereof is connected to the drain terminal of the second element. The source terminal of the second element is connected to a first line (42). The gate terminal of the first element and the gate terminal of the second element are connected to the first line (42). The drain terminal of the third element is connected to the first line (42). The source terminal of the third element is connected to a second line (43). The gate terminal of the third element is connected to the second line (43). The internal impedance of the fourth element is controlled by the voltage of the first line (42).
A semiconductor device (200) comprises: a first package (1) that includes a control IC chip (22) for controlling a MOSFET (3) for power conversion, and a single capacitor (21) for supplying power to the control IC chip (22); the MOSFET (3) that is outside the first package (1) and turns on and off in response to a control signal received from the control IC chip (22); and a second package (2) that includes wiring (lead frame (4), wiring (5), source electrode wiring (6), and gate electrode wiring (7)) for electrically connecting the control IC chip (22) in the first package (1) and electrodes of the MOSFET (3), and is formed by sealing the first package (1), the MOSFET (3), and the wiring with a mold resin (33).
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H02M 7/04 - Conversion of AC power input into DC power output without possibility of reversal by static converters
28.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device that makes it possible to improve a recovery characteristic by more effectively suppressing hole injection into a diode part in a reverse conducting IGBT (RC-IGBT) in which an IGBT and a diode are incorporated in the same chip. This semiconductor device has an IGBT and a diode in a same chip, and is characterized in that the IGBT comprises a first conductivity-type first semiconductor layer, a plurality of first trenches formed in the first semiconductor layer; a second conductivity-type body layer sandwiched between the plurality of first trenches and formed on the first semiconductor layer, and a first conductivity-type source layer sandwiched between the plurality of first trenches and formed on the body layer, the diode comprises the first semiconductor layer, a plurality of second trenches formed in the first semiconductor layer, an n layer sandwiched between the plurality of second trenches and formed on the first semiconductor layer, and the body layer sandwiched between the plurality of second trenches and formed on the n layer, the n layer and the body layer are partially exposed on the surface in a direction parallel to the second trenches, and the n layer forms a Schottky barrier junction.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
The present invention reduces a recovery loss ocurring during recovery of a diode in an RC-IGBT. A semiconductor device 100 has an IGBT and a diode in a same chip. The IGBT has an emitter, a collector, a first trench 3A, and a gate provided inside the first trench 3A. The diode has an anode electrically connected to the emitter, a cathode electrically connected to the collector, a second trench 3B penetrating the anode and reaching the cathode, an in-trench insulating film 4B provided inside the second trench 3B, and a diode gate provided inside the second trench 3B and facing the anode and the cathode with the in-trench insulating film 4B interposed therebetween. The diode gate can apply voltage independently of the gate of the IGBT, and negative voltage is applied to the anode at least in a period T4 in which a reverse current flows during recovery of the diode.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
The present invention provides a semiconductor device comprising a lead frame and a semiconductor component secured at a prescribed position on the lead frame via a bonding material, wherein the lead frame has at least one protruding portion provided to face a lateral peripheral surface of the semiconductor component.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/52 - Mounting semiconductor bodies in containers
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
This semiconductor device is composed of: a semiconductor chip; a substrate in which the semiconductor chip is mounted on a first main surface side thereof; and a sealing resin that covers the portion of the substrate on which the semiconductor chip is mounted. On a second main surface side on the opposite side to the mounting surface of the semiconductor chip, the sealing resin has a plurality of holes that penetrate to the second main surface of the substrate.
The present invention provides a semiconductor device in which it is possible to suppress the generation of a void in solder by releasing flux that is volatilized during reflow processing through a through hole that is provided in a joint surface of a clip, and to visually determine the bonding state of the solder after the reflow processing. This semiconductor device is characterized by including semiconductor elements, a lead frame, and a clip that connects the semiconductor elements to each other and/or the semiconductor elements and the lead frame. This semiconductor device is also characterized in that the clip has a through hole, and only an outer peripheral part that surrounds the through hole is joined to the semiconductor elements or the lead frame by means of a bonding material.
The present invention provides a testing method, for an insulated gate type SiC semiconductor element, capable of highly accurate sorting of substandard products which are difficult to be distinguished by conventional testing methods. This testing method for an insulated gate-type SiC semiconductor element is characterized by comprising: (a) a step for incorporating an element under test into an H-bridge type circuit having an inductance load; and (b) a step for using a gate voltage signal of the H-bridge type circuit to repeatedly perform ON/OFF switching so as to cause a bidirectional current to flow to the element under test, wherein the element under test satisfies the relational expression dv/dt > 0.06 × t × Vav, where Vav [kV] is the interruption rated breakdown voltage, t [nm] is the thickness of a gate insulating film, and dv/dt [kV/us] is the rate of change in voltage during the ON/OFF switching.
Provided is a semiconductor device, in particular, a power semiconductor device that needs to operate stably at high temperatures, wherein moisture that has penetrated into the device interior is prevented from penetrating into an insulating material, voids or cracking are prevented from occurring in the insulating material upon heating, and partial discharge and electrical breakdown are prevented. This semiconductor device comprises a semiconductor substrate onto which a semiconductor element is mounted, and a housing in which the semiconductor substrate is hermetically sealed, wherein the housing is provided with a pressure regulation unit for changing the volume of the housing interior in accordance with the pressure in the housing interior.
Provided is a semiconductor device with which it is possible, in a reverse-conducting IGBT (RC-IGBT) in which an IGBT and a diode are internally provided in the same chip, to more effectively suppress hole injection in a diode part and improve recovery characteristics. A semiconductor device according to the present invention has an IGBT and a diode in the same chip, the semiconductor device being characterized in that: the diode has a second trench that is provided between a first-conductivity-type third body layer and fourth body layer formed on a main surface of a semiconductor substrate, a first electrode that is formed on the third-body-layer-side side wall in the second trench with an insulating film interposed therebetween, and a second electrode that is formed on the fourth-body-layer-side side wall in the second trench with an insulating film interposed therebetween and is formed so as to be set apart from the first electrode with at least a second insulating film interposed therebetween; and an n layer having a higher concentration than the impurity concentration of the semiconductor substrate is provided below the third body layer and the fourth body layer.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
H02M 3/00 - Conversion of DC power input into DC power output
H02M 7/06 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
H02M 7/48 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
37.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
The present invention improves recovery characteristics by more effectively suppressing hole injection of a diode part in a reverse conducting IGBT. Provided is a semiconductor device comprising an IGBT and a diode, characterized in that the IGBT has a first semiconductor layer of a first conductivity type, a plurality of first trenches formed in the first semiconductor layer, a body layer of a second conductivity type sandwiched between the plurality of first trenches and formed on the first semiconductor layer, and a source layer of a first conductivity type sandwiched between the plurality of first trenches and formed on the body layer, and the diode has the first semiconductor layer and a plurality of second trenches formed in the first semiconductor layer, and has a first portion sandwiched between the plurality of second trenches and having the body layer formed on the first semiconductor layer, and a second portion sandwiched between the plurality of second trenches and having a Schottky barrier junction formed by contacts in the first semiconductor layer and the first semiconductor layer.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
A semiconductor device (100) comprises: a cascode connection unit (110) configured by including a first semiconductor element (101) (HVNM1), a second semiconductor element (102) (HVNM2), a first resistor (111) (R1), a first Zener diode (VZ1) (112), and a first high-voltage diode (115); and an erroneous-ON prevention circuit (120). The cascode connection unit (110) is configured by the drain of the first semiconductor element (101) (HVNM1) and the source of the second semiconductor element (102) (HVNM2) being cascode-connected, the first resistor (111) (R1) and the first Zener diode (VZ1) (112) connecting the gate and source of the second semiconductor element (102) (HVNM2), and the first high-voltage diode (115) connecting the gate of the first semiconductor element (101) (HVNM1) and the gate of the second semiconductor element (102) (HVNM2). The erroneous ON prevention circuit (120) is a circuit for preventing malfunctions caused by walkout current in the cascode connection unit (110).
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
39.
SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD FOR SAME
Provided is a semiconductor device for improving reliability in connection to, e.g., an external circuit from a semiconductor element sealed in a semiconductor package. A semiconductor device (1) comprises: a plurality of wiring members (3); and a semiconductor package (5) that is disposed on the wiring members (3) and seals a semiconductor element (50) with a first sealing member (80). The semiconductor package (5) has a connector (30) that is positioned on the semiconductor element (50) at one end and so as to be joined to an electrode of the semiconductor element (50). The other end of the connector (30) is positioned directly above the wiring members (3).
H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
40.
SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE USING SAME
The purpose of the present invention is to provide: a semiconductor device which makes it possible to reduce size and reduce the number of components; and a power conversion device using the same. The present semiconductor device is characterized in that a first MOSFET and a second MOSFET are disposed so as to be adjacent to each other, and the present semiconductor device comprises, on a lead frame, a first control element and a first capacitor which are associated with the first MOSFET and a second control element and a second capacitor which are associated with the second MOSFET. Alternatively, the present power conversion device has disposed therein a semiconductor device in which a first MOSFET and a second MOSFET are disposed so as to be adjacent to each other and which comprises, on a lead frame, a first control element and a first capacitor which are associated with the first MOSFET and a second control element and a second capacitor which are associated with the second MOSFET.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
The present invention raises withstand voltage by reducing the concentration of an electric field at an end of a field plate 7 provided in a termination region 102. A semiconductor device 100 comprises an active region 101 having a semiconductor element, and a termination region 102 surrounding the active region 101. The termination region 102 has a first conductivity type drift layer 1, a second conductivity type field limiting layer 3 formed on a part of the surface of the drift layer 1, a field insulating film 8 covering the drift layer 1 and the field limiting layer 3, and a field plate 7 electrically connected to the field limiting layer 3. The field plate 7 is formed on the surface of the field insulating film 8 so as to extend to the outside of the field limiting layer 3. The field insulating film 8 is gradually thicker toward the end of the field plate 7 in a region overlapping the field plate 7.
The present invention reduces on-resistance while ensuring short-circuit withstand time in a trench MOSFET which has a vertical channel fin structure. Provided is a trench MOSFET which has a vertical channel fin structure and which has a longitudinal direction along a first direction and a plurality of first trenches 2 arranged in a second direction, wherein: the trench MOSFET has a first JFET region 8A of a first conductivity type that is disposed below a channel region 5 and that is sandwiched between first body regions 9A of a second conductivity type and a second JFET region 8B of a first conductivity type that is disposed so as to be in contact with the lower surface of the first JFET region 8A and that is sandwiched between second body regions 9B of a second conductivity type; the length of the second JFET region 8B in the first direction is greater than the length of the first JFET region 8A in the first direction; the impurity concentration of the first JFET region 8A is higher than the impurity concentration of the second JFET region 8B; the impurity concentration of the second JFET region 8B is higher than the impurity concentration of a drift region 10; the dimension of the first body regions 9A and the dimension of the first JFET region 8A in the depth direction from the bottom of the first trenches 2 are both more than 0.5 μm.
Provided is a semiconductor device having, in a diode region of an RC-IGBT, a small cell size, a low voltage in a conduction state when a low voltage is applied, a short recovery time after a large current is conducted, and a high pressure resistance. A semiconductor device 1 includes an IGBT region 2 and a diode region 3 in the same chip. The diode 30 includes: a second-conductivity-type first semiconductor layer 31, and a second-conductivity-type second semiconductor layer 32 having an impurity concentration lower than that of the first semiconductor layer 31, sandwiched by third trenches 13; a first-conductivity-type third semiconductor layer 33; a fourth trench 14 that penetrates through the first semiconductor layer 31 and the second semiconductor layer 32 and reaches the third semiconductor layer 33; and a first electrode 51 provided inside the fourth trench 14. The side surface of the fourth trench 14 is in contact with the first semiconductor layer 31 and the second semiconductor layer 32. The first electrode 51 forms a Schottky junction with the third semiconductor layer 33 on at least the bottom surface of the fourth trench 14.
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
44.
SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND POWER CONVERSION DEVICE
Provided are a semiconductor device, a method for manufacturing the semiconductor device, and a power conversion device for allowing the low injection of the diode unit by forming the Schottky barrier diode in the diode unit of the RC-IGBT through a process simpler than the usual process. A semiconductor device (RC-IGBT) is formed as an RC-IGBT having an IGBT unit and a diode unit formed in a single chip. The diode unit includes a plurality of first trenches connected to a gate potential or an emitter potential in the absence of a body layer of second conductive type, and a second trench which is formed between two of the first trenches, and connected to the emitter potential. A Schottky barrier diode is provided, which is constituted by the second trench and a drift layer of a first conductive type in contact with a side wall of the second trench.
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
Provided are a semiconductor device and a power conversion device for improvement in the recovery characteristic by suppressing the hole injection through reduction in the area of the p body layer in the diode unit of the RC-IGBT. A semiconductor device according to the present invention is formed as an RC-IGBT having an IGBT unit and a diode unit formed in a single chip. A collector electrode layer/cathode electrode layer, a diffusion layer, a buffer layer, a drift layer, a body layer, an insulating layer, and an emitter/anode electrode layer are stacked in the order from a back surface side to a front surface side of the chip. The diode unit includes a plurality of trenches. The plurality of trenches 6 include a region in the presence of the body layer between the trenches, and a region in the absence of the body layer between the trenches.
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H02M 7/537 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
The present invention can suppress current concentration in an end portion of an active region while suppressing an increase in the surface area of a chip, and increases cut-off resistance. In a semiconductor device (30), a diode (33) of an active region (31) includes a second electrode (12), a drift layer (5) of a first conductivity type, and a second semiconductor layer (2) of a second conductivity type that is in contact with the drift layer (5) and electrically connected to the second electrode (12). The active region (31) is in contact with the drift layer (5) between the diode (33) and a termination region (32), and includes a third semiconductor layer (3) of the second conductivity type positioned closer to the second semiconductor layer (2) than the drift layer (5), and a fourth semiconductor layer (4) positioned between the second semiconductor layer (2) and the third semiconductor layer (3). The third semiconductor layer (3) and the fourth semiconductor layer (4) are not directly connected to the second electrode (12), the third semiconductor layer (3) has a higher impurity concentration than the second semiconductor layer (2), and the fourth semiconductor layer (4) is of the second conductivity type or the first conductivity type and has a lower impurity concentration than the second semiconductor layer (2).
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
47.
SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE USING SAME
Provided is a semiconductor device in which a plurality of power semiconductor elements are connected in parallel. The semiconductor device reduces variation in the inductance generated between the power semiconductor elements to achieve both low switching loss due to high-speed switching and improvement of power cycle resistance by uniformization of the switching loss of the power semiconductor elements. A semiconductor device according to the present invention includes at least one half-bridge circuit in which a first switch and a second switch that use a power semiconductor element are connected in series. The semiconductor device is characterized by comprising an insulated substrate, a first conductor layer pattern, a second conductor layer pattern, and a third conductor layer pattern that are provided on one surface of the insulated substrate and are electrically insulated from each other, a plurality of power semiconductor elements that are provided on the first conductor layer pattern and are connected to each other in parallel, a lead frame that connects each of the plurality of power semiconductor elements and the second conductor layer pattern, individual gate wirings that connect respective gate electrodes of the plurality of power semiconductor elements and the third conductor layer pattern, and a principal terminal that connects to the second conductor layer pattern, the lead frame having first connection surface parts that respectively connect to electrode surfaces of the plurality of power semiconductor elements, a lead frame branching part that has a plurality of branches, and a second connection surface part that is provided at an end part of the lead frame branching part and connects to the second conductor layer pattern, and the gate electrodes and the individual gate wirings being sandwiched between two branches of the lead frame branching part as seen in a top view of the insulated substrate.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
A semiconductor device and power conversion device are provided in which the p-body layer area of a diode portion of an RC-IGBT is reduced, hole injection is suppressed, and the recovery characteristic is improved. The semiconductor device has first and second body layers and first trenches provided therebetween. First and second gate electrodes are formed on side walls on the first and second body layer sides, respectively, with a gate insulation film between the gate electrodes and body layer sides. The first and second gate electrodes are separated by a first insulation film. The diode has third and fourth body layers of a first conductivity type, and a second trench provided therebetween. The second trench has first and second electrodes formed on side walls on the third and fourth body layer sides, respectively, with insulation films therebetween and the first and second electrodes are separated by a second insulation film.
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A semiconductor device has an inverter circuit in which detection accuracy of a short-circuit current is improved by increasing the inductance of a main current time change rate (di/dt) detection circuit without increasing the main circuit inductance. The device includes an upper arm switching element having a gate, a first main electrode, and a second main electrode serving as a gate reference potential. A positive electrode terminal serves as an external electrode connected to the first main electrode, through which a main current flows. A first auxiliary terminal serves as an external electrode which is electrically connected to the second main electrode and through which the main current is made to be prevented from flowing. A second auxiliary terminal serves as an external electrode connected to an AC terminal and through which a main current subjected to magnetic coupling is made to be prevented from flowing.
H02M 7/00 - Conversion of AC power input into DC power outputConversion of DC power input into AC power output
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
The present invention suppresses a decrease or variation in a threshold voltage even when a trench pitch is reduced in order to increase a channel density in a trench MOSFET having a vertical channel fin structure. A semiconductor device 1 includes: a plurality of trenches 2 having a long-side direction as a first direction, and a short-side direction as a second direction when seen in plan view, and arranged in the second direction; a source region 3 of a first conductivity type including a fin structure partitioned by the plurality of trenches 2; a channel region 5 of a second conductivity type having a fin structure partitioned by the plurality of trenches 2; and a body region 9 of the second conductivity type. The channel region 5 is connected to the body region 9, and a channel current flows in the channel region 5 vertically. The channel region 5 has a first channel region 5A contacting the lower surface of the source region 3, and a second channel region 5B disposed below the first channel region 5A. The first channel region 5A has a higher impurity concentration of the second conductivity type than the second channel region 5B.
Provided is a semiconductor device capable of improving heat dissipation as a whole thereof and suppressing an increase in on-voltage of an IGBT region. This semiconductor device comprises: a chip having IGBT regions and diode regions; a lead frame electrically connected to the upper surface of the chip with solder therebetween; and an insulating substrate electrically connected to the lower surface of the chip with solder therebetween. The IGBT regions and the diode regions are alternately arranged in the chip. The cell width of an IGBT region of a part electrically connected to the lead frame with the solder therebetween is wider than the cell width of an IGBT region of another part.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
52.
SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRIC POWER CONVERTER
To provide a semiconductor device, a method for manufacturing a semiconductor device, and an electric power converter realizing prevention of rise of on-voltage in an IGBT and improvement of a reverse recovery characteristic of a diode part by a simpler process. In the semiconductor device 100 (RC-IGBT), in the RC-IGBT having an IGBT part and a diode part in a single chip, a body layer 11 of the diode part is formed shallower than a body layer 10 of the IGBT part, a lifetime control layer 8 of the IGBT part is formed in the body layer 10 of the IGBT part, and the lifetime control layer 8 of the diode part is formed in a drift layer 4 below the body layer 11 of the diode part.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
53.
RECTIFIER CIRCUIT AND CONTROL METHOD FOR RECTIFIER CIRCUIT
Provided is a rectifier circuit that can be controlled to reduce total power loss when a load current (rectified current) is relatively small. The rectifier circuit having an anode and a cathode comprises: a first switching element in which a first terminal is connected to the cathode of the rectifier circuit and a second terminal is connected to the anode of the rectifier circuit; a first diode in which a cathode is connected to the cathode of the rectifier circuit and an anode is connected to the anode of the rectifier circuit; a first capacitor in which a third terminal is connected to the anode of the rectifier circuit; a reverse current prevention diode in which a cathode is connected to a fourth terminal of the first capacitor; a second switching element in which a fifth terminal is connected to the cathode of the rectifier circuit and a sixth terminal is connected to an anode of the reverse current prevention diode; a first comparison circuit for controlling the first switching element on the basis of the voltage between the anode and the cathode of the rectifier circuit; and a second comparison circuit for controlling the second switching element so as to control the voltage between the third terminal and the fourth terminal of the first capacitor to a target voltage.
H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
54.
SEMICONDUCTOR DEVICE AND ELECTRIC POWER CONVERSION DEVICE
Thermal resistance of a sintered metal joining section is reduced to cope with an increase in the area of a chip size and layer thinning of the semiconductor chip. A sintered metal layer joins the semiconductor chip to a wiring layer and the wiring layer has a trench extending from the semiconductor chip mounting region where the semiconductor chip is mounted to the outside of the semiconductor chip mounting region. The sintered metal layer is formed in the trench and to the outside of the upper end of the trench and in the trench formed to the outside of the semiconductor chip mounting region. The depth of the trench differs between the trench in the vicinity of the center of the semiconductor chip mounting region and the trench in the vicinity of the end portion of the semiconductor chip mounting region.
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
Provided is a semiconductor device capable of improving practicality and durability as a product. This semiconductor device comprises: a substrate; semiconductor chips (103) mounted on the substrate; a lead frame (104) mounted on the substrate; a first sintered joining layer, which joins substrate conductors (102) of the substrate to the semiconductor chips (103); a second sintered joining layer (104d), which joins the semiconductor chips (103) to the lead frame (104); a plurality of first grooves (8) formed in a section where the semiconductor chips (103) on the substrate are joined; and a plurality of second grooves (104d) formed in a section where the lead frame (104) joins the semiconductor chips (103). The groove length directions of the first grooves (8) and the second grooves (104d) are different. A through hole (104e) that penetrates the lead frame (104) is formed in a portion of the lead frame (104) that is sandwiched between two or more joint surface portions.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/52 - Mounting semiconductor bodies in containers
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
The purpose of the present invention is, in an RC-IGBT, to provide a semiconductor device that can suppress a snapback phenomenon when the IGBT is on, and hole injection from the IGBT region to a diode region when the diode is conductive, using a simple structure. The semiconductor device having an IGBT region 21 and a diode region 22 within the same chip is characterized in that the gate resistance R of the IGBT near the boundary of the IGBT region 21 and the diode region 22 is greater than the gate resistance of the IGBT near the center of the IGBT region 21.
The present invention provides an overcurrent detection device that detects an overcurrent with high accuracy even when there is a site where the temperature is unknown due to an instantaneous large current. An overcurrent detection device 11 comprises: an instantaneous current estimation unit 101 that estimates an estimated instantaneous current I at a site X of unknown temperature on the basis of a measured instantaneous voltage V of a conductor 111 and an estimated resistance R at the site X of unknown temperature in the conductor 111; an overcurrent determination unit 102 that determines an overcurrent on the basis of the estimated instantaneous current I; a power consumption calculation unit 103 that calculates power consumption P on the basis of the instantaneous voltage V and the estimated instantaneous current I; a temperature estimation unit 104 that estimates and updates a temperature T at the site X of unknown temperature on the basis of known temperatures Ta, Tt at at least one site of the conductor 111, the power consumption P, and a thermal equivalent circuit Tmodel designed in consideration of at least a thermal resistance Rth and a thermal capacity Rth of the conductor 111; and a resistance estimation unit 105 that updates the estimated resistance R at the site X of unknown temperature on the basis of the updated temperature T.
Provided is a semiconductor device that has a structure in which both of front and back surfaces of a semiconductor element are connected to a rigid body via a solder alloy, wherein influence of thermal stress that occurs on both of the front and back surfaces of the semiconductor element is reduced while the semiconductor device is in use. This semiconductor device comprises a semiconductor element, a lead frame, an insulating substrate, a first joining material that joins the semiconductor element and the lead frame, a second joining material that joins the semiconductor element and the insulating substrate, and a third joining material that joins the insulating substrate and the lead frame, said semiconductor device being characterized in that the solidus temperature of the first joining material is lower than the solidus temperature of the second joining material, and the solidus temperature of the third joining material is not lower than the solidus temperature of the second joining material.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 21/52 - Mounting semiconductor bodies in containers
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
Provided is a highly reliable semiconductor device in which an insulated circuit board on which a power semiconductor chip is mounted is encapsulated by a highly heat-resistant epoxy resin, the semiconductor device being such that it is possible to suppress peeling between the highly heat-resistant epoxy resin and wiring of the insulated circuit board. This semiconductor device is characterized by comprising a power semiconductor chip, an insulated circuit board on which the power semiconductor chip is mounted, and an encapsulating resin for encapsulating at least the power semiconductor chip and the junction between the power semiconductor chip and the insulated circuit board, the insulated circuit board having a ceramic substrate and a surface wiring layer that is formed on a surface of the ceramic substrate, and the surface wiring layer having a first roughened layer on the surface on the opposite side from the surface joined to the ceramic substrate.
H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
60.
SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE USING SAME
Provided is a highly reliable semiconductor device having both a low conduction loss and a low switching loss, and, at the same time, can enhance turn-off cut-off resistance. The semiconductor device includes a switching gate and a carrier control gate that are driven independently of each other, and is characterized by comprising, as viewed in plan, a central region cell, a peripheral region cell surrounding the circumference of the central region cell, and a terminal region surrounding the circumference of the peripheral region cell, in which the central region cell includes a switching element having the switching gate and the carrier control gate, and the peripheral region cell is disposed between the central region cell and the terminal region, the switching element of the peripheral region cell having a gate only composed of the carrier control gate.
Provided is a technique capable of improving the connection reliability of solder connection of a semiconductor device under a high temperature environment and reducing the wetting and spreading defect of the solder. As a means therefor, a solder containing Cu at a content of 3 to 9 wt %, Sb at a content of 6.7 to 9.6 wt %, and Sn and added with one or a plurality of types of elements among Fe of 0.004 to 0.01 wt %, Bi of 0.002 to 0.04 wt %, Pb of 0.01 to 0.09 wt %, and As of 0.0125 to 0.02 wt % is used as a solder to bond a semiconductor element.
The present invention increases adhesive strength between copper and a hard resin and prevents increase in contact resistance during attachment of a bus bar. For that purpose, a power semiconductor device (7) comprises: an insulating substrate (1); a case 3 that houses the insulating substrate (1); copper wiring (11) formed on the insulating substrate (1); a semiconductor chip (42) connected to the copper wiring (11); and copper terminals (31) that reach the upper end of the case (3). The copper wiring (11) and the copper terminals (31) are bonded. Nuts (32) provided to a constituent member of the case (3) are in contact with the copper terminals (31). An oxide film having a thickness of 15-100 nm is formed on the surface of the copper wiring (11).
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
The present invention reduces the number of processes involving mounting and solder reflow during the manufacture of a semiconductor device 1 that has a plurality of semiconductor chips 3 joined on a substrate 2 and that also has a lead frame 4 which straddle over and are joined on the semiconductor chips 3. An on-substrate jig 10 which has a partition 10B disposed in a gap between the mutually adjacent semiconductor chips 3 (a first semiconductor chip 3A and a second semiconductor chip 3B) for the purpose of positioning the chips and the lead frame 4 which enables a corner of the semiconductor chips 3 to be visible and which has a cutout 4D in a shape that allows the partition 10B to penetrate therethrough are used. The lead frame 4 is positioned using the on-substrate jig 10 before joining the semiconductor chips 3 to the substrate 2, and then, under-chip solder and on-chip solder are caused to reflow to join the substrate 2, the semiconductor chips 3, and the lead frame 4.
H01L 21/52 - Mounting semiconductor bodies in containers
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
To provide a technique enabling stable protection of a switching element at the time of short circuit by suppressing jumping of the voltage Vge between a gate terminal and a reference potential terminal at the time of occurrence of short circuit. A power semiconductor module having at least an upper arm, includes: a Zener diode connected between a gate terminal and a reference potential terminal and provided on the outside of a semiconductor chip of a switching element and provided on an insulating substrate; a casing which houses the insulating substrate; and a plurality of external electrodes provided to the casing and connected to the gate terminal and the reference potential terminal.
Provided is a semiconductor device manufacturing method by which it is possible to reduce the width of a termination region and achieve electrical field relaxation in the termination region. The semiconductor device manufacturing method has, in the periphery of an active region, a termination region in which a plurality of second semiconductor regions with a second conductivity type functioning as RESURF regions are formed on a surface of a first semiconductor region with a first electroconductive type. When defining a distance from a reference window at the outermost periphery as x, the method uses a mask, as for forming the second semiconductor region, in which an interval S(x) between an injection window at the position of a distance x and an injection window thereof on the active region side is substantially equal to the value determined by S(x)=Smax–(Smax–Smin)·(x/XN)β 0.3 ≦β≦ 0.5, to form the second semiconductor region through injection of an impurity of the second conductivity type.
In a power module (100), a substrate on which semiconductor components including a bridge-forming component (5) are mounted is sealed with a mold resin. The bridge-forming component (5) includes a first bridge (bridge (31)) that bridges a first semiconductor component (1) and a second semiconductor component (2). On the surface of the mold resin after sealing at least a portion in the vicinity (34) of a projection surface of the first bridge, a recess is provided between a gate-side boundary (35) and an opposite-to-gate-side boundary (36) of the first bridge between the first semiconductor component (1) and the second semiconductor component (2).
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
Provided is a motor control device in which the rotor position and rotation speed of a motor can be calculated with high accuracy and in a short time. A motor control device 4 according to the present invention is provided with a speed/phase estimation unit 13 that uses the position and speed of a rotor calculated by an idling state estimation unit 14 to estimate the position and speed of the rotor of a motor 3. The idling state estimation unit 14 comprises: a first current phase calculation unit 18 that calculates a first phase θi1 that is the phase of a current Iαβ flowing through the motor 3 in an idling state; a DC component calculation unit 23 that uses the current Iαβ and the first phase θi1 when the magnitude of the first phase θi1 is maximum to calculate a DC current Iα_DC flowing through the motor 3 in the idling state; a second current phase calculation unit 25 that uses the DC current Iα_DC and the current Iαβ to calculate a second phase θi2 that is the phase of a current Ie generated by idling of the motor 3; and idling speed/phase estimation units 26, 27 that use the second phase θi2 to calculate the position and speed of the rotor of the motor 3 in the idling state.
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
H02P 21/24 - Vector control not involving the use of rotor position or rotor speed sensors
68.
POWER SEMICONDUCTOR DEVICE AND CELL DATA GENERATING SYSTEM
A performance of a power semiconductor device is improved. A power semiconductor device including unit cells UR and UL cyclically arranged in an X direction and a Y direction perpendicular to each other and a plurality of end cells is used. The unit cells UR and UL are alternately arranged in the X direction, the plurality of end cells include an X-end cell XL, Y-end cells YR and YL, an XY-end cell XY1L, and an XY-end cell XY2L for an optional region, each number of arrangement cycles of the unit cells UR and UL in the Y direction changes depending on repetition cycle coordinates in the X direction, each of the cyclically-arranged unit cells UR and UL is adjacent to any of the plurality of end cells at an endmost portion of arrangement cycle in each of the X direction and the Y direction, and regions having the plurality of end cells are different in an electric property from the unit cells UR and UL.
The present invention suppresses the occurrence of destruction in the vicinity of a wiring region passing through the inside of an active region when an IGBT is turned off. A semiconductor device (1) has a wiring region (4) that passes through the inside of an active region (2) having an IGBT. The wiring region (4) includes: a drift layer (11) of a first conductivity type; a collector layer (16) of a second conductivity type provided on the rear surface side of the drift layer (11); a well layer (17) of the second conductivity type provided on the front surface side of the drift layer (11); a gate runner (5) provided on the front surface side of the well layer (17) to supply a gate potential to the gate electrode (21); and a contact region (third contact region (30)) that electrically connects the well layer (17) and the emitter electrode (22). The gate runner (5) is composed of a single layer (first gate runner (5A)), and has an opening part (5C) larger than the contact region at a position corresponding to the contact region.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
70.
METHOD FOR ESTIMATING PARTIAL DISCHARGE FACTOR OF POWER SEMICONDUCTOR MODULE, AND DEVICE FOR ESTIMATING PARTIAL DISCHARGE FACTOR OF POWER SEMICONDUCTOR MODULE
A method for estimating a partial discharge factor of a power semiconductor module which is capable of automatically estimating a partial discharge factor is provided using time-series data of a quantity of charge discharged during a partial discharge test. The method includes: a measurement step of applying, to the power semiconductor module, a test voltage pattern in which a voltage pattern changes, and measuring a quantity of charge that is due to partial discharge of the power semiconductor module; a feature quantity extraction step of extracting a plurality of feature quantities including at least a first feature quantity that is an average value of a quantity of charge in a first time period and a second feature quantity that is an average value of a quantity of charge in a second time period; and an estimation step of estimating the partial discharge factor based on the plurality of feature quantities.
According to the present invention, a semiconductor chip (200) has a selective crystal defect region (237) provided within a drift layer (234) that includes at least a main joining region (224), with said crystal defect region (237) being provided so as to surround an active region (210). Moreover, if the depth at which the crystal defect density of the main joining region (224) is higher than the crystal defect density of the active region (210), or the depth from an interface of a surface oxide film (233) of the semiconductor device at which the crystal defect density is maximized, is defined as d_max (238), the average crystal defect density up to said depth d_max (238) in the main joining region (224) is higher than the average crystal defect density of the active region (210), and the depth d_max (238) is formed more on a back surface side than 40% of the thickness D of the drift layer of the semiconductor device.
Provided are: a semiconductor device in which planarization by means of a contact plug is easy and coverage of a barrier metal at a corner part of an insulating film is good; and a method for producing the semiconductor device. A semiconductor device 1 has: a semiconductor layer 2; a silicide layer 3 provided on the semiconductor layer 2; a first insulation film 4 provided on the semiconductor layer 2 and having an opening 4A; a second insulation film 5 provided on a side wall of the opening 4A; a barrier metal 6 provided on the first insulation film 4, a corner part 8 of the second insulation film 5, a side wall of the second insulation film 5, and a silicide layer 3; and a contact plug 7 that fills a hole formed in the barrier metal 6 due to the opening 4A, wherein the corner part 8 of the second insulation film 5 has a rounded shape.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
The present invention reduces on-resistance while ensuring a short circuit withstand time in a trench MOSFET having a vertical channel fin structure. A semiconductor device 1 comprises: a plurality of trenches 2 arranged in a second direction, each having a longitudinal direction in a first direction and having a lateral direction in the second direction when viewed from above; a first source region 3 of a first conductivity type, at least a portion of which is divided by the plurality of trenches 2; and a second conductivity-type channel region 5 which is in contact with the lower surface of the first source region 3 and is divided by the plurality of trenches 2, wherein the channel region 5 is connected to a body region 9 and a channel current flows in the vertical direction in the channel region 5, the first-direction length of a gate electrode 7 disposed inside the trench 2 is greater than the first-direction length of a JFET region 8, the impurity concentration in the JFET region 8 is higher than the impurity concentration in a drift region 10, and the dimensions of the body region 9 and the JFET region 8 in the depth direction from the bottom of the trench 2 are both greater than 0.5 μm.
Provided is a semiconductor device having a constant voltage circuit that has a relatively small circuit scale and that does not require an external power source. The semiconductor device is characterized by being provided with a first output terminal, a second output terminal, an input terminal, a voltage dividing circuit, and a depletion-type NMOSFET element, wherein: the drain of the depletion-type NMOSFET element is connected to the input terminal; the source of the depletion-type NMOSFET element is connected to the first output terminal; and the voltage dividing circuit is connected to each of the first output terminal and the second output terminal, and is connected to the gate of the depletion-type NMOSFET element.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
G05F 3/16 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
Provided is a semiconductor device (RC-IGBT) having a diode region and IGBT region, which prevents element destruction due to current concentration at the time of avalanche breakdown when high voltage is applied. There is formed, in a portion of a region in contact with an n-type (first conductivity type) drift layer (101) of a p-type (second conductivity type) anode layer (117) of a diode region (103), a p-type high concentration region (129) (second conductivity type high concentration region) having a higher concentration than the p-type (second conductivity type) anode layer (117). An n-type high concentration region (130) (first conductivity type high concentration region) having a higher concentration than the n-type (first conductivity type) drift layer (101) is formed in a portion of the n-type (first conductivity type) drift layer (101) in contact with the p-type high concentration region (129) (second conductivity type high concentration region).
Disclosed is a rectifier circuit in which the number of synchronous rectification semiconductor switching elements to be turned on can be set without using a current detection unit from among the plurality of synchronous rectification semiconductor switching elements which are to be turned on and connected in parallel. This rectifier circuit comprises: a plurality of semiconductor switching elements (Q1 to Q3) that flow currents between an anode (A) and a cathode (K) in one direction by synchronous rectification and are connected in parallel to each other between the anode and the cathode; a plurality of drive circuits (GD1 to GD3) that drive the plurality of semiconductor switching elements; and a control unit (COM) that creates a control command signal for each of the plurality of drive circuits on the basis of the inter-main-terminal voltage of each of the plurality of semiconductor switching elements. The control unit sets the number of semiconductor switching elements to be turned on from among the plurality of semiconductor switching elements on the basis of the inter-main-terminal voltage in a synchronous rectification period and generates ON control command signals for the set number of drive circuits.
H02M 7/21 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
The present invention provides a semiconductor device which has good insulation properties and heat dissipation properties. The semiconductor device 1 comprises: a semiconductor element 2; an electrically conductive lead frame 3 that is connected to the semiconductor element 2; a sealing resin 4 for sealing the semiconductor element 2 and the lead frame 3; and an insulating heat conduction part 5 that is composed of a ceramic molded body. A part of the heat conduction part 5 is sealed with the sealing resin 4, and the heat conduction part 5 is connected to the lead frame 3 inside the sealing resin 4. The other parts of the heat conduction part 5 are exposed from the sealing resin 4. Consequently, heat generated in the semiconductor element 2 can be released to the outside through the lead frame 3 and the heat conduction part 5.
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
The present invention prevents malfunction of an upper-arm switching element due to the output of a power conversion circuit having a negative potential and undershooting. This upper-arm drive circuit comprises: a first switching element SW1 connected between a gate of an upper-arm switching element Q1 and a reference potential terminal; a second switching element SW2 having a drain connected to the gate of the first switching element SW1; and a potential control circuit 4. In at least a first period T1 in which the reference potential terminal of the upper-arm switching element Q1 has a negative potential and undershoots UND, the potential control circuit 4 controls the potential of a source of the second switching element SW2 to a first potential V1 at which the first switching element SW1 can be maintained to be ON even if the second switching element SW2 is turned ON due to a malfunction. In a subsequent second period T2, the potential control circuit 4 controls the potential of the source of the second switching element SW2 to a second potential V2 which is lower than the first potential V1 and at which the first switching element SW1 can be turned OFF when the second switching element SW2 is turned ON.
The present invention realizes a semiconductor device 1 having a high degree of freedom in in terms of designing the width of a channel region 5 and the width of a JFET region 8 in a trench MOSFET having a vertical-channel fin structure. The semiconductor device 1 is a trench MOSFET having a vertical-channel fin structure, wherein: width-direction end portions of the bottom surfaces of a plurality of trenches 2 are disposed in a body region 9; the channel region 5 is connected to the body region 9, and a channel current flows in the vertical direction in the channel region 5; the JFET region 8 has a first JFET region 8A and a second JFET region 8B disposed closer to the channel region 5 than the first JFET region 8A; and the width of the second JFET region 8B is greater than the width of the first JFET region 8A.
Provided is a highly reliable motor control device capable of preventing a voltage shortage when restarting a motor using a regenerative voltage in a power failure state, and capable of controlling the motor while taking a balance between a counterflowing wind and a motor drive after the start. The motor control device is characterized by comprising: a motor control circuit for controlling a permanent magnet synchronous motor; and a power failure detection circuit for detecting the supply stop of DC power. When a power failure state is detected by the power failure detection circuit, the motor control circuit flows Id current as an initial value so as to satisfy the relationship of 0 < V1 ≦ 0.94875ωke (V1: voltage command, ω: motor rotational speed when restarting, Ke: motor power generation constant) when the permanent magnet synchronous motor generates power by a counterflowing wind and the motor control circuit restarts the permanent magnet synchronous motor using the generated energy.
Provided is an upper arm drive circuit 1 with which it is possible to prevent malfunction even when an output of an electric power conversion circuit 2 becomes a negative potential, and to suppress delay of turn-on of an upper arm switching element Q1. The upper arm drive circuit 1 for driving the upper arm switching element Q1 of the electric power conversion circuit 2 comprises: a first switching element SW1 that is connected between a gate of the upper arm switching element Q1 and a reference potential terminal; a first diode D1 that is connected between a gate and a source of the first switching element SW1; a second diode D2 that is connected between a reference potential end of the upper arm switching element Q1 and a connection node N; a second switching element SW2 that is connected between the gate of the first switching element SW1 and the connection node N; a third diode D3 that is connected to a reference potential GND; and a first resistor R1 that is connected between the third diode D3 and the connection node N.
Provided is an electronic device manufacturing method that can improve the yield of a step for dropping a sheet-shaped solder into a through hole of a jig. In this electronic device manufacturing method in which a solder 4 is used to bond an electronic component or conductive member serving as a bonding member onto a substrate 5, a jig 1 is used, said jig 1 having a through hole 2 that penetrates from an upper surface to a lower surface and is for positioning the solder 4 and the bonding member, and an air release region 3 that is connected to the through hole 2 at one end and is connected to the exterior at the other end, the sheet-shaped solder 4 is dropped into the through hole 2 from the upper surface side of the jig 1 while the lower surface of the jig 1 is in contact with the top of the substrate 5, and air inside the through hole 2 is released from the air release region 3.
The present invention provides a highly efficient semiconductor device having a power conversion function by a bridge circuit using a plurality of semiconductor elements. This semiconductor device comprises: a first semiconductor element and a second semiconductor element each having one end connected to each other; a third semiconductor element and a fourth semiconductor element connected in parallel with the first semiconductor element and the second semiconductor element and each having one end connected to each other; a first terminal connected to a connection part between the first semiconductor element and the second semiconductor element; a second terminal connected to a connection part between the third semiconductor element and the fourth semiconductor element; a third terminal connected to the other end of the first semiconductor element and the other end of the third semiconductor element; and a fourth terminal connected to the other end of the second semiconductor element and the other end of the fourth semiconductor element. The first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element are synchronous rectification type elements including a MOSFET, and convert AC power input from the first terminal and the second terminal into DC power and output the DC power from the third terminal and the fourth terminal.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H02M 7/21 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
This drive circuit of a power conversion device is characterized in that: a gate driver 25 for driving a collector gate CG of a CG-IGBT 28 that is an upper arm output element includes a charge storage circuit 33 including a capacitor 35 and a backflow prevention element 34, and includes a charge charging/discharging control circuit 32 including a switching element 36 and a resistor 37; one terminal of the capacitor 35 is connected to a main power supply 31 of the power conversion device via the backflow prevention element 34, and is connected to the collector gate CG of the CG-IGBT 28; and the other terminal of the capacitor 35 is connected to a reference potential of the power conversion device via the switching element 36, and is connected to the main power supply 31 of the power conversion device via the resistor 37.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
An upper arm drive circuit according to the present invention is characterized by comprising: a turn-off circuit 6 which is connected between a reference potential of a power conversion device and the gate of an upper arm output element 2 and turns off the gate of the upper arm output element; a turn-on circuit 5 which is connected between the main power supply 1 of the power conversion device and the gate of the upper arm output element and turns on the gate of the upper arm output element; a charge storage circuit 11 provided with a first capacitor 16 and a first backflow prevention element 17; a charge charging/discharging control circuit 12 provided with a first switching element 14 and a first resistor 15; and a second backflow prevention element 13. The upper arm drive circuit is further characterized in that: one terminal of the first capacitor is connected to the output terminal of the power conversion device via the first backflow prevention element and is connected to the gate of the upper arm output element via the second backflow prevention element; and the other terminal of the first capacitor is connected to the reference potential of the power conversion device via the first switching element and is connected to the output terminal of the power conversion device via the first resistor.
This motor control device controls the operation of a permanent magnet synchronous motor by controlling the operation of an inverter by a control signal based on a voltage command and comprises: a first control unit that generates the control signal for the inverter during normal operation of the permanent magnet synchronous motor; and a second control unit that generates the control signal for the inverter during idling of the permanent magnet synchronous motor. When the permanent magnet synchronous motor is in an idling state, the second control unit outputs a voltage command for causing DC current having a predetermined initial value to flow through the permanent magnet synchronous motor, calculates the rotor position and rotational speed of the permanent magnet synchronous motor on the basis of the voltage command and the current value of the permanent magnet synchronous motor according to the voltage command, estimates the induced voltage of the permanent magnet synchronous motor on the basis of the calculated rotational speed, and adjusts the voltage command so as to be greater than the estimated induced voltage. This makes it possible to more highly accurately calculate the position and speed of the motor rotor.
The present invention effectively reduces a recovery loss of a diode region in an RC-IGBT. A semiconductor device 1 has an IGBT region 31 and a diode region 32 in one chip. A trench 6 (first trench) of the IGBT region 31 and a trench 6 (second trench) of the diode region 32 are both wide trenches. The diode region 32 includes: a first semiconductor layer 20 of a second conductivity type provided on the upper surface side of the drift layer 2 of a first conductivity type; and a second semiconductor layer 23 of the first conductivity type and a carrier discharge layer 26 of the second conductivity type provided on the back surface side of the drift layer 2 of the first conductivity type. The second semiconductor layer 23 and the carrier discharge layer 26 are alternately disposed.
A semiconductor device has both low conduction loss and low switching loss, and uniformity of heat generation during operation. The semiconductor device has high and low conduction regions in one semiconductor chip, and includes: in the low conduction region, a first carrier control gate connected to a first gate electrode, and a switching gate connected to a second gate electrode controllable independently of the first gate electrode; and in the high conduction region, a second carrier control gate connected to a third gate electrode. In the semiconductor device, of the first carrier control gate and the switching gate, the first carrier control gate is placed at an end portion of the low conduction region on a boundary side with the high conduction region, and a concentration of carriers that can be accumulated at conduction time is lower in the low conduction region than in the high conduction region.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
H02M 7/537 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
H02P 27/06 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters
H03K 17/567 - Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
A first MOSFET, a second MOSFET, a first control circuit, and a second control circuit are provided; the second MOSFET is in a non-rectification period when the first MOSFET is in a rectification period; the first MOSFET is in a non-rectification period when the second MOSFET is in a rectification period; the first control circuit outputs a voltage generated on the basis of a first input voltage as a first output voltage between the gate and the source of the first MOSFET in at least a portion of a period in which a voltage between the drain and the source of the second MOSFET is inputted as the first input voltage and a negative voltage is applied between the drain and the source of the first MOSFET; the second control circuit outputs a voltage generated on the basis of a second input voltage as a second output voltage between the gate and the source of the second MOSFET in at least a portion of a period in which a voltage between the drain and the source of the first MOSFET is inputted as the second input voltage and a negative voltage is applied between the drain and the source of the second MOSFET.
H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
The present invention provides a semiconductor device capable of suppressing a saturation current with a high withstand voltage and a small element size using a simple structure in a lateral MOSFET. The semiconductor device 1 comprises: a drift region 2 of a first conductivity type; a body region 3 of a second conductivity type; a channel region 9 formed in the body region 3; a source region 4 of the first conductivity type; a drain region 6 of the first conductivity type provided on the same main surface side as the source region 4; a gate electrode 7; and a gate insulating film 8 provided between the gate electrode 7 and the channel region 9. There is a separation region 12 in which an insulating film 10 is provided inside a trench 11 between the drain region 6 and the body region 3, and the drift region 2 has a first extension part 16 which has a longitudinal direction in a first direction by being sandwiched by the body region 3 when viewed in the plan view, and constitutes a part of a current path between the channel region 9 and the drain region 6.
This semiconductor device comprises a substrate, a semiconductor chip (103) mounted on the substrate, a lead frame (104) mounted on the substrate, a first sintered joining layer, which joins a substrate conductor (104) of the substrate to the semiconductor chip (103), a second sintered joining layer (104d), which joins the semiconductor chip (103) to the lead frame (104), a plurality of first grooves (8) formed in the substrate, in a part thereof to which the semiconductor chip (103) thereon is joined, and a plurality of second grooves (104d) formed in the lead frame (104), in a part thereof joined to the semiconductor chip (103). The first grooves (8) and the second grooves (104d) have mutually different groove-length directions.
H01L 21/52 - Mounting semiconductor bodies in containers
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
An effective technique is applied to a rectifier circuit that performs synchronous rectification using a switching element. The rectifier circuit performs the synchronous rectification using a MOSFET, for example, as the switching element. By using the rectifier circuit, a capacitance of a capacitor for supplying power to a drive circuit can be reduced. As a result, downsizing and cost reduction of the rectifier circuit and the power supply using the rectifier circuit can be achieved.
H02M 7/217 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A semiconductor device includes a drift layer of a first conductivity type; and anode layer of a second conductivity type formed on a first main surface side of the drift layer; a field stop layer of the first conductivity type that is formed on a second main surface side of the drift layer and has a higher impurity concentration than the drift layer; and a cathode layer of the first conductivity type that has a higher impurity concentration than the field stop layer. A defect layer for carrier lifetime control is formed by light ion irradiation. In the defect layer, the region from the concentration peak of the light ions to the half-value width ΔLp of the light ion concentration profile does not overlap the depletion layer spreading in the drift layer, and does not overlap the location in the field stop layer of the first conductivity type.
H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
The present invention suppresses erroneous operation of an upper arm switching element when a reflux current flows to a lower arm. An upper arm drive circuit 2 has: a first switching element SW1 connected between the gate electrode of an upper arm switching element Q1 and the main electrode of the upper arm switching element Q1 on the reference potential side; a second switching element SW2 having a drain electrode connected to the gate electrode of the upper arm switching element Q1; and a first diode D1 and a second diode D2 which are disposed in series between the drain electrode of the second switching element SW2 and the gate electrode of the upper arm switching element Q1 with the cathodes and the anodes being on the second switching element SW2 side and on the upper arm switching element Q1 side, respectively. The withstand voltage of the second diode D2 is lower than that of the first diode D1, the recovery current of the second diode D2 is lower than that of the first diode D1, and the withstand voltage of the first diode D1 is in the range of 60V to 100V.
H03K 17/16 - Modifications for eliminating interference voltages or currents
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Disclosed is a semiconductor device which is provided with an RC-IGBT and is configured so as to comprise: a first-conductivity type semiconductor substrate; a first electrode that is in contact with the front surface of the semiconductor substrate; a second electrode that is in contact with the back surface of the semiconductor substrate; a plurality of trenches that are formed on the front surface side of the semiconductor substrate; a third electrode that is covered with an insulating film in each trench; a second-conductivity type first semiconductor layer that is in contact with the second electrode in an IGBT region; a first-conductivity type second semiconductor layer that is in contact with the second electrode in a diode region; a first-conductivity type third semiconductor layer that is in contact with the upper surface of the first semiconductor layer and with the upper surface of the second semiconductor layer; a second-conductivity type fourth semiconductor layer that is in contact with the first electrode and the insulating film in each trench; and a first-conductivity type fifth semiconductor layer that is in contact with the first electrode and the insulating film in each trench in the IGBT region, while being surrounded by the fourth semiconductor layer. In addition, this semiconductor device has a low-lifetime region within the semiconductor substrate in the vicinity of the center of the IGBT region.
Provided are a highly reliable motor drive device and the like. A motor drive device (100) comprises: an inverter circuit (40) that converts the DC voltage of a smoothing capacitor (20) into AC voltage; and a control unit (60) that controls the inverter circuit (40). The AC voltage on the output side of the inverter circuit (40) is applied to a motor (M1) connected to a fan (F1). If the detected value of the DC voltage is within a predetermined range after the power supply is stopped, the control unit (60) waits without driving the motor (M1). The upper limit value and the lower limit value of the predetermined range are set so as to increase as the induced voltage or the rotation speed of the motor (M1) associated with the idle rotation of the fan (F1) increases.
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
F24F 11/37 - Resuming operation, e.g. after power outagesEmergency starting
F24F 11/64 - Electronic processing using pre-stored data
H02M 7/48 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
F24F 140/00 - Control inputs relating to system states
The present invention provides: a semiconductor device which has higher resistance to bias at high temperatures and high humidities than ever before, while achieving good connection between a field limiting layer and a field plate; and a power conversion device which uses this semiconductor device. A semiconductor device according to the present invention is characterized by comprising a floating field limiting layer that is provided in a termination region and a field plate that is electrically connected to the field limiting layer, and is also characterized in that: the field plate is formed of a polysilicon; the field plate and the field limiting layer are connected to each other via an Al electrode; and the connection between the field limiting layer and the Al electrode and the connection between the field plate and the Al electrode are established at different contacts.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H02M 7/5387 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
The present invention suppresses a snapback phenomenon in an RC-IGBT. In a semiconductor device 100, which has an IGBT region 21 and a diode region 22 in the same chip, the IGBT of the IGBT region 21 has a drift layer 1 of a first conductivity type, a trench 3, a gate electrode 5 provided in the trench 3, a body layer 2 of a second conductivity type, an emitter layer 7 of the first conductivity type, a gate insulating film (insulating film 4), and a collector layer 11 of the second conductivity type. The diode of the diode region 22 has the drift layer 1, a first semiconductor layer 12 of the second conductivity type provided more on the front surface side than the drift layer 1, and a second semiconductor layer 13 of the first conductivity type provided more on the rear surface side than the drift layer 1. The IGBT region 21 has, at a boundary portion with the diode region 22, a boundary portion pillar layer 8A of the second conductivity type contacting the body layer 2 and the collector layer 11 through the drift layer 1.
The present invention facilitates manufacturing and reduces a recovery current while suppressing an increase in on-resistance of a MOSFET. A semiconductor device 1 comprises: a first-conductivity type drain region 11; a first-conductivity type drift region 10 which is disposed above the drain region 11 and which has an impurity concentration lower than that of the drain region 11; second-conductivity type body regions 9 which are disposed above the drift region 10; first-conductivity type source regions 3 which are disposed above the body regions 9; second-conductivity type channel regions 5 which are in contact with the body regions 9 and with the source regions 3; a gate insulating film 6 which is in contact with the channel regions 5; a gate electrode 7 which is in contact with the gate insulating film 6; a first-conductivity type JFET region 8 which is disposed between the two adjacent body regions 9; and first-conductivity type low lifetime regions 4 that do not overlap the JFET region 8, that is disposed between the body region 9 and the drift region 10, and that includes second-conductivity type impurities within a range between 6×1011cm-2and 1×1013cm-2.
Provided is a semiconductor device in which a component such as a semiconductor package or a clip is fixed on a lead frame without using a conductive bonding material, thereby avoiding an increase in manufacturing unit price due to the use of the conductive bonding material, a component displacement during a manufacturing process, and the generation of thermal stress at the time of heating of a built-in chip. The semiconductor device comprises: a semiconductor package with a built-in semiconductor chip; a first lead frame on which the semiconductor package is mounted; a second lead frame on which the semiconductor package is not mounted; and a clip connecting the semiconductor package and the second lead frame to each other. The semiconductor package and the first lead frame are fixed by mating of a protruding portion with a recessed portion. The semiconductor package and the clip are fixed by mating of a protruding portion with a recessed portion.
