Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.
A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/003 - Modifications for increasing the reliability
Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.
A method to fabricate a non-planar memory device including forming a multi-layer silicon nitride structure substantially perpendicular to a top surface of the substrate. There may be multiple non-stoichiometric silicon nitride layers, each including a different or same silicon richness value from one another.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
5.
System and method for manufacturing self-aligned STI with single poly
A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.
H01L 27/11 - Static random access memory structures
H01L 27/11568 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
At integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.
H01L 23/528 - Layout of the interconnection structure
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/003 - Modifications for increasing the reliability
Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.
An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.
H01L 23/528 - Layout of the interconnection structure
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/003 - Modifications for increasing the reliability
Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.
The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines and in a groove in the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 27/11521 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
H01L 27/11568 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 23/528 - Layout of the interconnection structure
H01L 27/11563 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Techniques for fast ramp, low supply charge-pump circuits are described herein. In an example embodiment, a non-volatile memory device comprises a flash memory array coupled to a fast charge-pump circuit. The charge-pump circuit comprises a first charge pump, an active charge pump coupled as input to the first charge pump, and a power supply coupled as input to the active charge pump. The active charge pump is configured to initialize the first charge pump to a greater absolute voltage than the power supply and to provide power to the first charge pump during an active mode of the flash memory array.
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
A method to fabricate a non-planar memory device including forming a multi-layer silicon nitride structure substantially perpendicular to a top surface of the substrate. There may be multiple non-stoichiometric silicon nitride layers, each including a different or same silicon richness value from one another.
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
15.
Rapid memory buffer write storage system and method
Data associated with a logical block address (LBA) may be received from a host system to be stored in the memory array. The LBA may be translated to a physical block address (PBA) by determining a first portion of the PBA and a second portion of the PBA. The data from the host system may be stored in the buffer space after determining the first portion of the PBA and before determining the second portion of the PBA. The data from the buffer space may be flushed to the memory array after determining the second portion of the PBA.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 29/52 - Protection of memory contents; Detection of errors in memory contents
G06F 12/1036 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
A method in accordance with one embodiment of the invention can include detecting an interrupt request during execution of an instruction by a processor of an integrated circuit. Additionally, a clock signal frequency can be changed that is received by the processor. An interrupt service routine can be executed that corresponds to the interrupt request.
Simultaneous formation of a top oxide layer in a silicon-oxide-nitride-oxide-silicon (SONOS) transistor and a gate oxide in a metal oxide semiconductor (MOS)
A semiconductor chip includes a base of a memory transistor in a first region of a substrate, and a base of a metal oxide semiconductor (MOS) transistor in a second region of the substrate. The base of the memory transistor includes a channel in a surface of substrate, a tunnel layer over the channel, and a nitride layer over the tunnel layer. The base of the MOS transistor includes a channel in the surface of substrate. The MOS transistor is coupled to the memory transistor through a shared diffusion region formed in the surface of substrate between the channel of the MOS transistor and the channel of the memory transistor. A plasma oxide overlying the nitride layer and the surface of the substrate to form a top oxide layer over the nitride layer and a gate oxide layer over the surface of substrate in the second region.
An electronic system includes a processing device and a trellis pattern of conductors coupled to the processing device. The trellis pattern of conductors forms a multiple capacitors and the processing device is configured to sense a capacitance of each of the capacitors. A host is coupled to the processing device. The host includes decision logic to determine a state of the trellis pattern of conductors responsive to a signal that indicates a capacitance of one or more capacitors sensed by the processing device.
A switching circuit includes a driver circuit DRV2 that outputs voltage for turning on and off a first transistor switch M2, positioned at a low potential side with respect to a load, among a plurality of transistor switches disposed in series between an input voltage and a ground; and a control circuit that causes the driver circuit DRV2 to output a first voltage that turns the first transistor switch M2 on upon an output voltage of the driver circuit DRV2 rising while the first transistor switch M2 is off and to cause the driver circuit DRV2 to suspend output of the first voltage upon the output voltage of the driver circuit DRV2 dropping after the driver circuit DRV2 outputs the first voltage.
H03B 1/00 - GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS - Details
H03K 3/00 - Circuits for generating electric pulses; Monostable, bistable or multistable circuits
H03K 17/04 - Modifications for accelerating switching
H03K 17/16 - Modifications for eliminating interference voltages or currents
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A capacitive sensor array may include a plurality of row sensor electrodes and a column sensor electrode capacitively coupled with each of the plurality of row sensor electrodes to form a plurality of unit cells. For each row sensor electrode, a unit cell that is associated with the column sensor electrode and the row sensor electrode comprises an area where a capacitance between the column sensor electrode and the row sensor electrode is greater than any other capacitance between the column sensor electrode and a different row sensor electrode. The capacitive sensor array further includes a first plurality of dummy electrodes, where each of the first plurality of dummy electrodes is capacitively coupled with the column sensor electrode and two adjacent row sensor electrodes of the plurality of row sensor electrodes.
In one embodiment, a method for supporting multivariable functions of an application includes receiving user input pertaining to two or more variables associated with a multivariable function of the application, and then causing code for the function to be automatically generated to update the variables based on the user input.
A method of providing visual indication of a device connection speed proceeds by determining a connection speed of the device and selecting a visual indicator representative of the connection speed. Once the appropriate indicator has been selected, the visual indicator is then displayed.
G06F 3/0481 - Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance
A capacitive sensor array includes a second sensor element intersecting a first sensor element to form an intersection associated with a unit cell. The second sensor element includes, within the unit cell: a first primary trace crossing the unit cell and a second primary trace crossing the unit cell, a first secondary trace connecting the first primary trace and the second primary trace, and a first tertiary trace branching away from the first secondary trace between the first primary trace and the second primary trace. An area of the first sensor element is greater than an area of the second sensor element within the unit cell.
The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines and an insulating layer that is provided between the first bit lines and in a groove. First faces of the first bit lines are aligned on a first line and second faces of the first bit lines are aligned on a second line. A first face of the insulating layer is disposed at a third line that is a first distance from the first line in a first direction and a second face of the insulating layer is disposed at a fourth line that is a second distance from the second line in a second direction.
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 27/11521 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
H01L 27/11568 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 23/528 - Layout of the interconnection structure
H01L 27/11563 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A method and apparatus to operate a watchdog timer having a first time out period in a processing system. The watchdog timer receives an indication of a change in a mode of operation in the processing system. In response to the change in the mode of operation of the processing system, the watchdog timer changes the time out period to a second time out period corresponding to the new mode of operation.
A crystal oscillation circuit is provided with a crystal oscillator, an inverter unit coupled in parallel with the crystal oscillator and including a plurality of inverters, a current supply unit that supplies current to at least a first inverter of the plurality of inverters, a signal converter that supplies current to at least a last inverter of the plurality of inverters and outputs a voltage to an external circuit, and a current controller that makes the current supply unit provide current corresponding to a voltage level of the output voltage of the signal converter. The crystal oscillation circuit is capable of reducing power consumption.
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.
H03K 3/00 - Circuits for generating electric pulses; Monostable, bistable or multistable circuits
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/003 - Modifications for increasing the reliability
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
A method in accordance with one embodiment of the invention may include receiving a first encryption key. A second encryption key may be generated, and a first data packet containing the second encryption key may be generated and at least part of the first data packet encrypted using the first encryption key. A second data packet may be generated and at least part of the second data packet encrypted using the second encryption key.
An apparatus may include processing logic coupled with a force sensor input and a touch sensor input. The processing logic is configured to determine a relative force magnitude based on a force signal received at the force sensor input and a baseline measurement of the force sensor. The processing logic updates the baseline measurement in response to detecting that the touch signal indicates the absence of the one or more touches from the sensing surface.
Apparatuses and methods of sense arrays with interleaving sense elements are described. One capacitive-sense array includes a repeating pattern having a first conductive element with a first polygon shape and a first width defined along a second axis that is perpendicular to the first axis; a second conductive element having a second polygon shape and a second width defined along a third axis that is perpendicular to the first axis and parallel to the second axis; a third conductive element having the first polygon shape and the first width defined along a fourth axis that is perpendicular to the first axis and parallel to the second axis; and a fourth conductive element having the second polygon shape and the second width defined along a fifth axis that is perpendicular to the first axis and parallel to the second axis.
G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
G01D 5/24 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance
H03K 17/955 - Proximity switches using a capacitive detector
An output switching circuit includes a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output s terminal at a connection node between the first and second transistors; a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and a drive pulse generating unit that generates first drive pulses for driving the first transistor and second drive pulses for driving the second transistor in accordance with the comparison signal.
G01F 1/40 - Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by using mechanical effects by measuring pressure or differential pressure the pressure or differential pressure being created by the use of flow constriction - Details of construction of the flow constriction devices
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A capacitive sensor array may include a first plurality of sensor elements and a second sensor element. The second sensor element may include a main trace intersecting each of the first plurality of sensor elements to form a plurality of intersections each associated with a unit cell, where a contiguous section of the main trace crosses at least one of the plurality of unit cells. An area within the unit cell may include at least a portion of one or more primary subtraces branching from main subtrace, a plurality of secondary subtraces branching away from the one or more primary subtraces, and at least one tertiary subtrace branching away from at least one of the secondary subtraces.
An embodiment of the present invention is directed to a semiconductor packaging frame allowing identification information to be stored in the paddle area of the individual frame. Forming identification information on the paddle allows unique tracking of the semiconductor frame package during and after manufacturing and for tracking down variances, defects, and other problems during the semiconductor packaging process. Further, the shapes formed from the identification information provide increased surface area for bonding of the molding compound and thus strengthen the bond between the die paddle and molding compound thereby improving the strength of the semiconductor package.
An adaptive algorithm running on a processing device receives a temperature value that represents a temperature at a gate terminal of a transistor. The adaptive algorithm, determines a drive strength value that represents a drive strength for a signal based on the temperature value. A signal with the determined drive strength is applied to the gate terminal of the transistor.
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
H03K 17/00 - Electronic switching or gating, i.e. not by contact-making and -breaking
An apparatus includes a selection device to select a spreading profile from a plurality of spreading profiles, and an oscillation device to generate clock signals having different frequencies over time based on the selected spreading profile. A method includes selecting a spreading profile from a plurality of spreading profiles, and generating clock signals having different frequencies over time based on the selected spreading profile.
H03B 23/00 - Generation of oscillations periodically swept over a predetermined frequency range
H04B 15/04 - Reducing interference from electric apparatus by means located at or near the interfering apparatus the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
H03K 4/501 - Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator
A method for device driver self authentication is provided. The method includes accessing a device driver having encrypted authentication parameters therein including, for instance, a vendor identification, a device identification, a serial number, an expiration date and a filename. The method includes executing an authentication portion of the device driver to generate a message digest of these parameters and comparing the message digest to a stored digest for a match thereof. The method further includes loading the device driver only if the authentication portion successfully authenticates the device driver, e.g., there is a match. The method can be applied to USB device drivers and peripherals.
G06F 21/51 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability
G06F 9/44 - Arrangements for executing specific programs
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
A self-modulated voltage reference circuit may generate a reference voltage by receiving an internal reference voltage of a programmable device at a first input of a comparator block of the programmable device, receiving a feedback voltage at a second input of the comparator block, generating a pulse density modulated (PDM) signal based on a difference between the reference voltage and the feedback voltage, outputting the PDM signal at a digital output pin of the programmable device, and filtering the PDM signal to generate the output reference voltage.
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
H03M 3/00 - Conversion of analogue values to or from differential modulation
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
A method and apparatus to operate a watchdog timer having a first time out period in a processing system. The watchdog timer receives an indication of a change in a mode of operation in the processing system. In response to the change in the mode of operation of the processing system, the watchdog timer changes the time out period to a second time out period corresponding to the new mode of operation.
An integrated circuit (IC) device can include a serial communication first interface (I/F) circuit electrically coupled to first physical connections of the IC device, and configured to respond to communication signals received at the first physical connections; at least one serial communication second interface (I/F) circuit electrically coupled to second physical connections of the IC device, and configured to enable data transactions over the second physical connections; and a repeater circuit configured to bypass the first I/F circuit and enable serial communication signals to be transmitted from the first physical connections to the second physical connections. Systems including such an IC device and related methods are also disclosed.
A circuit includes a switched modulator stage combining an information signal with a square wave carrier to produce a first modulated signal; and a second modulation stage forming additional steps in the first modulated signal to produce a second modulated signal.
Apparatuses and methods of sense arrays with interleaving sense elements are described. One capacitive-sense array includes a first electrode and a second electrode disposed adjacent to the first electrode in a first axis. The capacitive-sense array comprises a sensor pitch in the first axis. The first electrode includes a first sense element including a first shape and a first interleaving sense element that interleaves with a first portion and a second portion of the second electrode to extend a first dimension of the first electrode to be greater than the sensor pitch in the first axis. The second electrode includes a second sense element including the first shape and a second interleaving sense element that interleaves with a first portion and a second portion of the first electrode to extend a second dimension of the second electrode to be greater than the sensor pitch in the first axis.
G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
G01D 5/24 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance
42.
System and method for manufacturing self-aligned STI with single poly
A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.
A node system includes a first node, a second node, and a supervisory node which transmit frames while increasing or decreasing the cycle microtick count, and determines reduced cycle microtick counts by subtracting or adding a rate correction limit value from or to the cycle microtick count of the supervisory node when reception of the first frame transmitted by the first node stop and the cycle microtick count of the supervisory node when reception of the first and second frames stop.
A circuit with electrostatic discharge protection is described. In one case, the circuit includes trigger device configured to protect a component connected to a node of the circuit during an electrostatic discharge event, the trigger device includes an isolation structure interposed between a gate oxide layer and an extended drain region. A portion of the extended drain region proximate the isolation structure is substantially metal-free.
A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.
According to one exemplary embodiment, a host/client system includes a host module, which includes a CPU coupled to a system bridge. The host/client system further includes at least one client having an integrated interface, where the integrated interface is coupled to the system bridge through a scalable serial bus. The system bridge and the integrated interface enable high bandwidth communication between the CPU and the at least one client through the scalable serial bus, thereby allowing control of bus width between the host module and the client.
An integrated circuit device may include a plurality of external connections, any one of the connections providing both a power voltage path for the integrated circuit (IC) as well as an information signal path for the IC. At least one switch may be coupled to provide a power supply voltage to one of the external connections.
A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.
G06F 13/12 - Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/372 - Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
A method and apparatus store a command in a command register and set, with a control circuit, a first operation mode associated with a split transaction for freeing a bus in a time period between a command transfer request and a command transfer operation. The method and apparatus set, with the control circuit, a second operation mode in which a split transaction is not issued and transfer, with the control circuit, the command to a processing unit via the bus in response to the command transfer request when in the second operation mode where after the processing unit executes the command and issues a subsequent command transfer request to the control circuit, the control circuit performs the split transaction when in the first and second operation modes.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 11/36 - Preventing errors by testing or debugging of software
A method of driving an output terminal to a voltage, in which an input signal is received, an appropriate output voltage and output voltage range are determined based on the input signal, an output driver is configured to a first mode and the output driver drives the output terminal to a voltage within the voltage range, the output driver is configured to a second mode and the output driver drives the output terminal to a voltage approximately equal to the appropriate output voltage.
H03B 1/00 - GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS - Details
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
H03K 19/003 - Modifications for increasing the reliability
A method in accordance with one embodiment of the invention can include detecting an interrupt request during execution of an instruction by a processor of an integrated circuit. Additionally, a clock signal frequency can be changed that is received by the processor. An interrupt service routine can be executed that corresponds to the interrupt request.
Apparatuses and methods of integrating power supply unit (PSU) control and power line communication (PLC) to transmit data on a power line in a transmitting node. One method modulates a switching frequency of the PSU between multiple spread frequencies to transmit the data.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A charge pump, comprising a charge pump output may be operatively coupled to a filter input of a loop filter. A first amplifier input of an operational transconductance amplifier (OTA) may be operatively coupled to the filter input and the charge pump output, and the second amplifier input is operatively coupled to the amplifier output and filter output.
H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/08 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop
Systems and methods that can facilitate the utilization of a memory as a slave to a host are presented. The host and memory can provide authentication information to each other and respective rights can be granted based in part on the respective authentication information. The host can determine the available functionality of the memory. The host can activate the desired functionality in the memory and can request memory to perform the desired function(s) with regard to data stored in the memory. An optimized controller component in the memory can facilitate performing the desired function(s) associated with the data to generate a result. The result can be provided to the host, while the data and associated information utilized to generate the result can remain in the memory and are cannot be accessed by the host.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
G06F 12/14 - Protection against unauthorised use of memory
G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
56.
Method to improve charge trap flash memory core cell performance and reliability
A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.
Computer-based speech recognition can be improved by recognizing words with an accurate accent model. In order to provide a large number of possible accents, while providing real-time speech recognition, a language tree data structure of possible accents is provided in one embodiment such that a computerized speech recognition system can benefit from choosing among accent categories when searching for an appropriate accent model for speech recognition.
An integrated circuit comprises a first poly-silicon region including a first poly-silicon layer, a second poly-silicon layer disposed over the first poly-silicon layer, a first poly-silicon finger associated with the first poly-silicon layer, and a second poly-silicon finger associated with the second poly-silicon layer. The first poly-silicon finger and the second poly-silicon finger are oriented in a substantially orthogonal manner relative to each other. The integrated circuit comprises a second poly-silicon gate region including the first poly-silicon layer. The first polysilicon gate region and the second polysilicon gate region each have different poly-silicon gate structures.
A dual protocol input device for use with a host system is provided. In one embodiment, the input device comprises a chip with a number of semiconductor devices integrally formed thereon, including: an optical navigation sensor (ONS) to sense movement of the ONS relative to a surface; a wired protocol block to communicate data from the ONS to the host system by a wired communication protocol; a wireless protocol block to communicate data from the ONS to the host system by a wireless communication protocol; and a micro-controller coupled to the ONS, the wired protocol block and the wireless protocol block, to switch the input device between the wireless communication protocol and the wired communication protocol.
A semiconductor device which includes a first semiconductor chip 10, a first electrode 12 formed on the first semiconductor chip 10, a second semiconductor chip 20 to which the first semiconductor chip 10 is mounted, a second electrode 22 with a protrusion 24, which is formed on the second semiconductor chip 20, and a solder bump 14 which bonds the first electrode 12 and the second electrode 22 to cover at least a part of a side surface of the protrusion 24, and a method for manufacturing thereof are provided.
A design tool provides a conflict management graphical user interface (GUI). The conflict management GUI notifies a user that requested values of a global resource result in a conflict during development of an embedded application. The conflict management GUI further provides the user with a user interface element to adjust the requested values until the conflict is resolved.
G06F 3/048 - Interaction techniques based on graphical user interfaces [GUI]
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
A voltage adjustment circuit for adjusting a voltage to be supplied to scanning lines of a display device includes a slope adjustment circuit configured to adjust a slope of a decrease in the voltage based on data that is externally input, and a clamp voltage adjustment circuit configured to adjust a voltage value at which the voltage is clamped based on the data.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
In order to enable the optimization of a processor system without relying upon knowhow or manual labor, an apparatus includes: information obtainment unit for reading, from memory, trace information of the processor system and performance information corresponding to the trace information; information analysis unit for analyzing the trace information and the performance information so as to obtain a performance factor such as an idle time, a processing completion time of a task, or the number of interprocessor communications as a result of the analysis; and optimization method output unit for displaying and outputting a method of optimizing the system in response to a result of the analysis.
The present invention provides a semiconductor device including: a semiconductor chip; a lead frame provided with a recessed portion on at least one of an upper surface or a lower surface thereof, and electrically coupled to the semiconductor chip; and a resin section that molds the semiconductor chip and the lead frame, and is provided with an opening above the recessed portion. By inserting a conductive pin (not shown) into the recessed portion through the opening, a plurality of semiconductor devices can be mechanically and electrically coupled to each other.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups
65.
Replica node feedback circuit for regulated power supply
A power supply includes a source signal generating circuit, an output stage, and a feedback stage. The power supply further includes a replica stage configured to replicate a response of the output stage to the source signal, and an output regulator coupling the replica stage to the output stage, configured to adjust a feedback signal to the source signal generating circuit by shunting the feedback stage when a loaded output stage response does not match a response of the replica stage to the source signal.
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
An execution history tracing method includes tracing an execution history of a CPU upon executing, in a semiconductor device including the CPU, a program by using the CPU, for one or a tracing target, from outside the semiconductor device via software. The execution history tracing method includes recording, in a buffer, target information as trace information about an execution of the one or the tracing target, for each instruction cycle in which the target information is produced as the execution history; and performing data sorting by using the software to group the trace information about the execution of the one or the tracing target, the trace information being recorded for the each instruction execution cycle, for each of the one or the tracing target.
The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.
H01L 21/44 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
B29C 45/02 - Transfer moulding, i.e. transferring the required volume of moulding material by a plunger from a "shot" cavity into a mould cavity
B29C 45/16 - Making multilayered or multicoloured articles
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
B29C 45/14 - Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
H01L 23/552 - Protection against radiation, e.g. light
A voice activation system is provided. The voice activation system includes a first stage configured to output a first activation signal if at least one energy characteristic of a received audio signal satisfies at least one threshold and a second stage configured to transition from a first state to a second state in response to the first activation signal and, when in the second state, to output a second activation signal if at least a portion of a profile of the audio signal substantially matches at least one predetermined profile.
A method and apparatus for a reverse metal-insulator-metal (MIM) capacitor. The apparatus includes a lower metal layer, a bottom electrode, and an upper metal layer. The lower metal layer is disposed above a substrate layer. The bottom electrode is disposed above the lower metal layer and coupled to the lower metal layer. The upper metal layer is disposed above the bottom electrode. The upper metal layer comprises a top electrode of a metal-insulator-metal (MIM) capacitor.
A method involves regulating an output voltage of an output transistor of a voltage regulator circuit by providing a first voltage to a front gate of the output transistor, and simultaneously with providing the first voltage to the output transistor, providing a second voltage to a back gate of the output transistor, in a manner that regulates the output voltage around a target value.
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or val
H03K 3/01 - Circuits for generating electric pulses; Monostable, bistable or multistable circuits - Details
71.
Substrate bias feedback scheme to reduce chip leakage power
An oscillation circuit including a reference voltage generation circuit that adds a proportional-to-absolute-temperature (PTAT) output, which increases in proportion to an absolute temperature, to a complementary-to-absolute-temperature (CTAT) output, which decreases in proportion to an absolute temperature, to generate and output a reference voltage. The oscillation circuit generates an oscillation signal having a desired and fixed frequency.
H03L 1/04 - Constructional details for maintaining temperature constant
G05F 3/30 - Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
H03K 3/011 - Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
H03K 3/027 - Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
An electrostatic discharge (ESD) detector is coupled to the input voltage, and includes a voltage modulated input capacitance Cj configured to decrease as the input voltage increases. An output pulse generator is coupled to an output of the detector, and configured to amplify the output of the detector. An ESD protection switch is coupled to turn on upon application of an output pulse from the output pulse generator.
Error correcting systems, methods, and devices for non-volatile memory are disclosed. In one embodiment, a non-volatile memory device comprises a data area for storing data, an error correcting code generation section for generating an error correcting code in response to receipt of a code generation command, and an error correcting code area for storing the error correcting code. The non-volatile memory device further comprises a detector circuit for detecting the generating of the error correcting code, and a read section for correcting the data stored in the data area based on the error correcting code upon the detecting of the generation of the error correcting code by the detector circuit, where the code generation command is forwarded by a memory controller when the data are is filled with the data beyond a threshold level
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
A self-modulated voltage reference circuit may generate a reference voltage by receiving an internal reference voltage of a programmable device at a first input of a comparator block of the programmable device, receiving a feedback voltage at a second input of the comparator block, generating a pulse density modulated (PDM) signal based on a difference between the reference voltage and the feedback voltage, outputting the PDM signal at a digital output pin of the programmable device, and filtering the PDM signal to generate the output reference voltage.
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
H03M 3/00 - Conversion of analogue values to or from differential modulation
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or val
A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G11C 8/12 - Group selection circuits, e.g. for memory block selection, chip selection, array selection
G11C 16/12 - Programming voltage switching circuits
77.
Partial allocate paging mechanism using a controller and a buffer
A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.
A system for wear-leveling of a non-volatile memory may include a controller configured to allocate memory blocks in the non-volatile memory, a logical-to-physical table populated with pointers to memory blocks in the nonvolatile memory, and a wear-leveling table configured to store two or more pointers to unallocated memory blocks in the non-volatile memory. The unallocated memory blocks are previously allocated to store data by the controller according to the pointers in the logical-to-physical table. The controller is further configured to identify two or more pointers in the wear-leveling table and to store data to the two or more memory blocks associated with the identified pointers.
An interface device and method are provided for sensing movement of an actuator across a surface of a window in an enclosure thereof. The interface device comprises an optical navigation sensor including an illuminator within the interface to illuminate at least a portion of the actuator through the window when the actuator is positioned in contact with or proximal to the surface of the window, and a detector to receive light reflected through the window from the actuator. The interface device further includes a number of capacitive guard-sensors in the enclosure adjacent to the optical navigation sensor to disable the optical navigation sensor when a conductive body is sensed in proximity to the guard-sensors.
G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells provided in a matrix and having a charge storage layer, a plurality of word lines provided on the charge storage layer, and an application section. When reading data from a selected memory cell selected from the plurality of memory cells, the application section applies a voltage having an opposite polarity to the voltage applied to a selected word line to non-selected word lines arranged on both adjacent sides of the selected word line.
A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.
A multi-port arbitration system has a write detection circuit coupled to each of a number of ports. An address coincidence detector is coupled to each of the ports. A deactivation pulse generator circuit is coupled to the address coincidence detector.
A programmable processing device having a non-volatile memory that may comprise a first memory portion and a second memory portion, where the first section of the first memory portion is configured to store program instructions or data and the second memory portion of the memory word is configured to store either the configuration data or the error detection bits depending upon if an error detection scheme is implemented for the program instructions or data.
A design tool provides a graphical user assignable register map. The design tool graphically displays a register map that indicates locations of system variables in a memory of a processing device for an embedded application. The design tool further provides a user interface element for a user to arrange an order of the system variables in the register map.
A semiconductor device includes first and second resistors. The first resistor is formed in a first substrate region and coupled between a first node and an output node. The second resistor is formed in a second substrate region and coupled between the output node and a second node. The first substrate region is coupled to the first node which has a first voltage. The second node has a second voltage. The second substrate region is coupled to a voltage dividing node that is set in the first resistor.
An output driver circuit can include at least a first driver transistor having a source-drain path coupled between a first power supply node and an output node. A first variable current supply can generate a current having at least one component that is inversely proportional to a power supply voltage. A first driver switch element can be coupled in series with the first variable current supply between a gate of the at least first driver transistor and a second power supply node.
H03B 1/00 - GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS - Details
H03K 3/00 - Circuits for generating electric pulses; Monostable, bistable or multistable circuits
A method and apparatus to operate a watchdog timer having a first time out period in a processing system. The watchdog timer receives an indication of a change in a mode of operation in the processing system. In response to the change in the mode of operation of the processing system, the watchdog timer changes the time out period to a second time out period corresponding to the new mode of operation.
An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of a device issuing requests. The system may synchronize device resource information for requests made by a processor to access (e.g., read/write) locations of a memory device. The present invention synchronizes the device access information without restricting pulse width of a read/write signal or requiring a high speed clock.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G06F 1/12 - Synchronisation of different clock signals
G06F 1/00 - ELECTRIC DIGITAL DATA PROCESSING - Details not covered by groups and
Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.
Disclosed is a filter circuit, comprising a signal to be filtered, a difference circuit coupled to the signal to be filtered, a filter having an input coupled to the difference circuit, an integrator (or accumulator) having a first input coupled to an output of the filter circuit, and having a second input, and an accumulator coupled to an output of the integrator. A method of filtering is described also.
A system includes power saving circuitry to revive a system controller from a sleep mode for performance of operations in an active mode. The system also includes a regulator including a floating gate reference device to generate output voltage and current capable of powering the power saving circuitry during the sleep mode. A method includes generating a reference voltage and current with a float gate device, and powering wake-up circuitry with the reference voltage and current while in a power saving mode. The wake-up circuitry is configured to activate a main system controller from the power saving mode.
A voltage regulator for low power operation of digital circuits includes an output node for providing a regulated output voltage, a diode-connected P-channel transistor in series with a second diode-connected N-channel transistor coupled between the output node and ground, and a bias current having a value for biasing the first and second diode-connected transistors in a sub-threshold mode of operation. The low power voltage regulator further includes a buffer amplifier or emitter or source follower stage to provide a low impedance regulated voltage. The bias current may be generated by a bandgap circuit.
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or val
H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
93.
Method of manufacturing convex shaped thin-film transistor device
The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.
A variable reference voltage circuit for performing memory operation on non-volatile memory includes a multi-level voltage source and a selector circuit. The multi-level voltage source generates multiple voltages. The selector circuit includes a selector input and a selector output. The selector input is coupled to the multi-level voltage source to selectively couple any of the multiple voltages to the selector output. The selector output of the selector circuit is coupled to a non-volatile memory array to provide the NV memory array with a selectable program voltage for programming the NV memory array and a selectable erase voltage for erasing the NV memory array.
A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.
An embodiment of the present invention is directed to a method for reporting position information. Position information received from a plurality of capacitive sensors in an array of capacitive sensors is adjusted based on predetermined adjustment values to generate adjusted position information. Each predetermined adjustment value is associated with at least one of the plurality of capacitive sensors. A signal representative of the adjusted position information is generated. In another embodiment, the sensitivity of at least one of the capacitive sensors is adjusted based on the position of the at least one capacitive sensor within the array.
G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
97.
Clocking analog components operating in a digital system
A system and method are provided for operating first and second components in first and second domains. In one embodiment, the method includes: generating a plurality of clock signals shifted relative to one another; operating a first component in a first domain using a first one of the plurality of clock signals; operating a second component in a second domain using a second one of the plurality of clock signals selected using a selection component; and comparing a present output of the second component to a stored value, determining whether a variation between the present output and the stored value is greater than a threshold, and, if the variation is greater than the threshold, using a controller to cause the selection component to select a third clock signal from the plurality of clock signals that is shifted relative to the second clock signal to drive the second component.
Embodiments of the invention are generally directed to a high-speed differential energy difference integrator (EDI) for adaptive equalizers. In an embodiment, the EDI includes two differential full-wave rectifiers providing differential outputs that are cross-coupled to the inputs of an integration capacitor. In one embodiment, the active areas of the transistors of the differential full-wave rectifiers are substantially the same.
A programmable device includes an operational amplifier and circuitry. The operational amplifier is configured to generate an output voltage based on input voltages at input terminals thereof. The circuitry is configured to provide the input voltages to the operational amplifier. The configuration of the circuitry allows the programmable device to implement discrete-time or continuous-time functions. The circuitry includes a resistor network and a capacitor network configured to be selectively coupled to the operational amplifier.
Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.
patents