An LC display driver including a gamma reference circuit to generate N gamma-compensated reference voltages based on at least one pre-defined gamma curve divided into M regions defined by M+1 breakpoint voltages, each generated by a range-region DAC coupled to a subset of voltage taps of a range resistor string (some subsets overlapping). An output circuit generates the N gamma-compensated reference voltages, and includes a reference resistor string with N reference voltage taps, and M+1 breakpoint locations to receive respective breakpoint voltages, the N reference voltage taps divided into M subsets corresponding to the M regions of the gamma curve, each of the M subsets of reference voltage taps forming a voltage divider. N output selector circuits output a corresponding one of the N gamma-compensated reference voltages based on a respective reference voltage tap and the associated voltage divider.
H04N 9/69 - Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits for modifying the colour signals by gamma correction
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
One heuristic for tuning a wireless power transfer device includes monitoring a circuit parameter while sweeping a power source frequency; identifying two frequencies related to local maxima of the circuit parameter values; estimating self-resonant frequency of an electromagnetically coupled device based on the two frequencies; determining a value for a tuning component of the wireless power transfer device such that the device self-resonant frequency equals the estimated coupled device self-resonant frequency; and adjusting the tuning component to the determined value.
Another tuning heuristic includes monitoring a circuit parameter while sweeping the power source frequency; identifying two frequencies related to two local maximum for the values of the circuit parameter; determining a desired resonance frequency for the wireless power transfer device based on stored information; and adjusting the tuning component to a value that causes the wireless power transfer device when uncoupled to operate at or near the desired resonance frequency.
The cost and size of an atomic magnetometer are reduced by attaching together a first die which integrates together a vapor cell, top and side photo detectors, and processing electronics, a second die which integrates together an optics package and a heater for the vapor cell, and a third die which integrates together a VCSEL, a heater for the VCSEL, and control electronics.
G01J 5/20 - Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
G01J 1/42 - Photometry, e.g. photographic exposure meter using electric radiation detectors
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
4.
Automated control of semiconductor wafer manufacturing based on electrical test results
In semiconductor wafer manufacturing, processes such as analyzing test data associated with semiconductor wafers, interpreting the test data analysis, and acting on the test data interpretation and analysis are automated. Such automation can eliminate delays that were previously imposed by the action of test analysis engineers and wafer fabrication personnel, thereby reducing the amount of useless material that is produced before a process defect can be detected.
Interface circuitry and method for transmitting and receiving downstream and upstream data signals simultaneously via a common conductor pair. The composite signal containing the downstream and upstream data signal components being conveyed by the common conductor pair is isolated, e.g., via signal filtering or buffering, and combined with an appropriately scaled inverse replica of the outgoing upstream data signal to subtract out upstream data signal components and thereby provide the downstream data signal substantially free of any upstream data signal components.
H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
A method includes providing an input signal identifying a desired brightness for one or more LEDs to first and second parallel control paths. The method also includes generating a digital modulation control signal using the first control path, generating a current control signal using the second control path, and driving the one or more LEDs using the control signals. The method further includes performing compensation in at least one of the control paths to compensate for an increased efficiency of the one or more LEDs. Generating the control signals could include (i) adjusting the digital modulation control signal while maintaining the current control signal at a substantially constant value for a range of lower LED brightness values and (ii) adjusting the current control signal while maintaining the digital modulation control signal at a maximum value or within a range of maximum values for a range of higher LED brightness values.
H05B 33/08 - Circuit arrangements for operating electroluminescent light sources
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
7.
System and method for communicating with sensors/loggers in integrated radio frequency identification (RFID) tags
A system and method is disclosed for communicating with sensors/loggers in integrated radio frequency identification (RFID) tags. An RFID reader uses a Communicate With Data Logger Command to communicate with a data logger in an RFID tag. The RFID reader performs data access processes using an Index Register and a Data Register of the RFID tag. The RFID reader selects one of (1) Index Read access (2) Index Write access (3) Data Write access (4) Data Read access with parity and (5) Data Read access with cyclic redundancy check (CRC). The RFID tag performs the requested data access and then performs an error detection process.
H04Q 5/22 - Selecting arrangements wherein two or more subscriber stations are connected by the same line to the exchange with indirect connection, i.e. through subordinate switching centre the subordinate centre not permitting interconnection of subscribers connected thereto
G08B 5/22 - Visible signalling systems, e.g. personal calling systems, remote indication of seats occupied using electric transmissionVisible signalling systems, e.g. personal calling systems, remote indication of seats occupied using electromagnetic transmission
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
8.
Small highly accurate battery temperature monitoring circuit
A battery temperature monitoring circuit, which has a cold comparator and a hot comparator, achieves high accuracy in a small cell size by utilizing a cold current optimized for the cold comparator and a cold reference voltage, and a hot current optimized for the hot comparator and a hot reference voltage, along with switching circuitry that provides the cold current to the cold comparator as the battery temperature approaches the cold trip temperature, and the hot current to the hot comparator as the battery temperature approaches the hot trip temperature.
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
G01K 7/22 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements the element being a non-linear resistance, e.g. thermistor
G01R 31/36 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
A bi-directional charging device includes a rechargeable battery, a coil coupled to the rechargeable battery, a selection mechanism that selectively causes power to be delivered from the coil to the battery and selectively causes power to be delivered from the battery to the coil, and a control mechanism. Upon determining that the coil is to provide power to the battery, the control mechanism causes the selection mechanism to selectively cause power to be delivered from the coil to the battery, and upon determining that the coil is to receive power from the battery, the control mechanism causes the selection mechanism to selectively cause power to be delivered from the battery to the coil.
The bi-directional charging device includes a housing enclosing the rechargeable battery, the coil, the selection mechanism, and the control mechanism.
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02J 7/02 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from AC mains by converters
H01M 10/46 - Accumulators structurally combined with charging apparatus
H02J 5/00 - Circuit arrangements for transfer of electric power between ac networks and dc networks
H02J 17/00 - Systems for supplying or distributing electric power by electromagnetic waves
G01R 31/36 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
H02J 7/35 - Parallel operation in networks using both storage and other DC sources, e.g. providing buffering with light sensitive cells
MOD denotes a frequency of the second signal, and F( ) denotes a modulation function. This could help to modulate switching noise over a range of frequencies and spread electro-magnetic interference generated by the switching regulator.
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
11.
Background sensor diagnostic for multi-channel ADC
A digital sensing device includes a sensor diagnostic system for detecting sensor fault conditions. The sensor diagnostic system including an input multiplexer applying a first burnout current or a second burnout current to a selected input channel and a near-rail detector configured to detect when an input voltage of the digital sensing device is near a positive power supply or near a negative power supply. The burnout current injection is applied without interfering with the sensor data. In other embodiments, the sensor diagnostic system may further include an overload detector configured to detect an overflow or underflow condition at the analog-to-digital converter. The sensor diagnostic system may further include a window comparator to detect when the ADC digital output is near a zero digital value. Finally, the sensor diagnostic system may further include a sensor flag generator to generate data flags indicative of sensor fault conditions.
A system and method is disclosed for adding a low data rate data channel to a 100Base-T Ethernet link without significantly impacting an IEEE defined 100Base-T protocol for the Ethernet link. A dual data channel transmitter encodes a high data rate data stream in an MLT-3 encoder and encodes a low data rate data stream using bit representations that are not valid bit representations in the MLT-3 encoder. The dual data channel transmitter transmits both of the encoded bit streams in a dual data stream. A dual data channel receiver receives the dual data stream and separates and decodes the two bit streams. A low data rate data channel is provided in conjunction with a high data rate data channel without significantly impacting the operation of the high data rate data channel.
A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride.
H01L 31/0336 - Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups in different semiconductor regions, e.g. Cu2X/CdX hetero-junctions, X being an element of Group VI of the Periodic System
H01L 29/225 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds including two or more compounds in different semiconductor regions
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
14.
Backside stress compensation method for making gallium nitride or other nitride-based semiconductor devices
A method includes forming a stress compensation layer over a first side of a semiconductor substrate and forming a Group III-nitride layer over a second side of the substrate. Stress created on the substrate by the Group III-nitride layer is at least partially reduced by stress created on the substrate by the stress compensation layer. Forming the stress compensation layer could include forming a stress compensation layer from amorphous or microcrystalline material. Also, the method could include crystallizing the amorphous or microcrystalline material during subsequent formation of one or more layers over the second side of the substrate. Crystallizing the amorphous or microcrystalline material could occur during subsequent formation of the Group III-nitride layer and/or during an annealing process. The amorphous or microcrystalline material could create no or a smaller amount of stress on the substrate, and the crystallized material could create a larger amount of stress on the substrate.
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01L 21/36 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
15.
Line-in signal dynamic range enhancement for output of charge pump based audio amplifier
Separate control of the operation of an audio amplifier and a charge pump that synthesizes a negative voltage supply (VSS) for improving the dynamic range of the audio amplifier. The audio amplifier is typically powered by a single positive power supply (VDD) and the charge pump is arranged to synthesize a negative voltage supply rail (VSS) that enables a greater dynamic range for the amplifier's “on” and “shut down” modes of operation. Also, when the audio amplifier enters its shut down mode of operation to create at least some isolation from Line_In audio signals provided at the amplifier's output by other electronic devices, the amplifier's charge pump stays “on” and continues to provide the negative voltage supply rail (VSS). In this way, the greater dynamic range offered by the presence of both the positive and negative voltage rails is provided even if the amplifier is in a shut down mode.
An anneal recipe is provided to tighten the distribution of resistance values in the manufacture of semiconductor integrated circuits. An adjusted amount of dopant is implanted to compensate for a shift in the distribution of resistance values associated with the anneal recipe. The distribution tightening can be effectuated by including an ammonia gas flow in the anneal recipe.
A system and method is disclosed for manufacturing thin film resistors using a trench and chemical mechanical polishing. A trench is etched in a layer of dielectric material and a thin film resistor layer is deposited so that the thin film resistor layer lines the trench. A thin film resistor protection layer is then deposited to fill the trench. Then a chemical mechanical polishing process removes excess portions of the thin film resistor layer and the thin film resistor protection layer. An interconnect metal is then deposited and patterned to create an opening over the trench. A central portion of the thin film resistor protection material is removed down to the thin film resistor layer at the bottom of the trench. The resulting structure is immune to the effects of topography on the critical dimensions (CDs) of the thin film resistor.
A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.
H01L 21/86 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 21/76 - Making of isolation regions between components
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
19.
Growth of multi-layer group III-nitride buffers on large-area silicon substrates and other substrates
A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 21/76 - Making of isolation regions between components
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
20.
ESD clamp with auto biasing under high injection conditions
In a dual direction ESD protection circuit formed from multiple base-emitter fingers that include a SiGe base region, and a common sub-collector region, the I-V characteristics are adjusted by including P+ regions to define SCR structures that are operable to sink positive and negative ESD pulses, and adjusting the layout and distances between regions and the number of regions.
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
21.
Methods for manufacturing a radio frequency identification tag without aligning the chip and antenna
A method for attaching antennae to RFID tags is disclosed. Included is the use of RFID tags having asymmetrical interconnect system for one or more antennae, such that virtually any rotational orientation of the RFID tag will result in a successful antennae attachment. Two oversized and “L” shaped gold-bumped holes can be arranged on the same side of the ship in an opposing action, such that at least one axis of symmetry is formed. Accordingly, virtually all rotational orientations of the chip are then acceptable when attaching a pair of opposing pole antenna leads. Alternatively, a pair of poles can be located on opposing chips surfaces, such that antenna substrates can be attached to both the top and bottom of the chip to form a product “sandwich”, whereby the rotational orientation of the chip is irrelevant at an antenna attachment step.
A system and method are disclosed for providing an active current assist with analog bypass for a switcher circuit. An active current assist circuit is coupled to a buck regulator circuit, which includes a switcher circuit, an inductor circuit and a capacitor circuit. The active current assist circuit includes an active current analog bypass control circuit and a current source. The active current analog bypass control circuit receives and uses current limit information, voltage error information, and drop out information to determine a value of assist current that is appropriate for a current operational state of the buck regulator circuit. The active current analog bypass control circuit causes the current source to provide the appropriate value of assist current to the buck regulator circuit.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
23.
DC/DC converter power module package incorporating a stacked controller and construction methodology
Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.
A method includes forming at least one control gate over a semiconductor substrate. The method also includes depositing a layer of conductive material over the at least one control gate and the semiconductor substrate. The method further includes etching the layer of conductive material to form multiple spacers adjacent to the at least one control gate, where at least one of the spacers forms a floating gate in at least one memory cell. Two spacers could be formed adjacent to the at least one control gate, and one of the spacers could be etched so that a single memory cell includes the control gate and the remaining spacer. Also, two spacers could be formed adjacent to the at least one control gate, and the at least one control gate could be etched and separated to form multiple control gates associated with different memory cells.
A high voltage ESD protection diode wherein the p-n junction is defined by a p-well and an n-well and includes a RESURF region, the diode including a field oxide layer formed on top of the p-well and n-well, wherein the parameters of the diode are adjustable by controlling one or more of the junction width, the length of the RESURF region, or the length of the field oxide layer.
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
26.
System and method for monitoring chloride content and concentration induced by a metal etch process
A system and method for monitoring chloride content and concentration induced by a metal etch process is disclosed. A blank metal film is deposited on a semiconductor wafer. A metal etch process is then applied to partially etch the blank metal film on the wafer. The metal etch process exposes the metal film to chlorine. The wafer is then scanned using surface profiling total X-ray reflection fluorescence. A chlorine concentration map is generated that shows quantitative and spatial information about the chlorine on the wafer. Information from the chlorine concentration map is then used to select a value of chlorine concentration for a metal etch process that will not create metal chloride corrosion on a semiconductor wafer.
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
27.
Methodology for controlling a switching regulator based on hardware performance monitoring
A methodology for regulating power supplied to a powered component based on hardware performance, such as may be used in a system that includes the powered component and a switching regulator (EMU or energy management unit) configured to supply a regulated supply voltage to the powered component. Performance monitoring circuitry generates a performance monitoring signal corresponding to a detected performance level of selected digital operations of the powered component relative to a reference performance level. Switching control circuitry provides a switching control signal in response to the performance monitoring signal. In an example embodiments, the switching control circuitry for the switching regulator (switching transistor) is integrated into the powered component, and the detected performance level corresponds to a detected signal path delay associated with the digital operations of the powered component.
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
H02J 1/00 - Circuit arrangements for dc mains or dc distribution networks
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
28.
Switching regulator providing current regulation based on using switching transistor current to control on time
An apparatus includes a sense element that generates a sense signal based on an output signal generated by a regulator. The apparatus also includes a current control unit that generates a compensated reference signal using the sense signal. The compensated reference signal is associated with an average of the output signal. The apparatus further includes a comparator that compares the compensated reference signal and the sense signal. In addition, the apparatus includes a hysteretic control unit that adjusts a control signal based on an output of the comparator and that provides the control signal to the regulator in order to adjust the output signal generated by the regulator. The hysteretic control unit could dynamically adjust peak and valley currents through an inductor in the regulator to maintain the average of the output signal at a substantially constant value.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
29.
System and method for using an input data signal as a clock signal in a RFID tag state machine
A system and method is disclosed for using an input data signal as a clock signal in a state machine of a radio frequency identification (RFID) tag. An output of a demodulator in the RFID tag is directly coupled to a clock input of the command state machine in the RFID state machine. The command state machine receives an edge detect signal directly from the input data signal and then immediately generates backscatter signals to begin a backscatter process. The edge detect signal may comprise a rising edge of a data symbol of the RFID protocol. The immediate initiation of the backscatter process reduces latency of the backscatter process in the RFID state machine.
H04Q 5/22 - Selecting arrangements wherein two or more subscriber stations are connected by the same line to the exchange with indirect connection, i.e. through subordinate switching centre the subordinate centre not permitting interconnection of subscribers connected thereto
G08B 13/14 - Mechanical actuation by lifting or attempted removal of hand-portable articles
30.
Heat transfer control for a prosthetic retinal device
A method for controlling heat dissipated from a prosthetic retinal device is described. A heat transfer device employs the Peltier heat transfer effect to cool the surface of the retinal device that faces the retina by dissipating/transferring collected heat away from the retina and towards the iris or front of the eye. According to one embodiment, a heat pump is formed in a second substrate on the retinal device. The heat pump is controlled by a temperature sense device that activates the heat pump, when a first predetermined temperature limit is exceeded. The temperature sense device deactivates the heat pump, when a temperature of the retinal device drops below a second predetermined temperature. According to another embodiment, a supply current of the retinal device may pass through the heat pump and a direction of heat transfer by the heat pump can be reversed, when the first predetermined temperature is exceeded.
An insulating material interposed between two conductive materials can experience plasma process induced damage (PPID) when a plasma process is used to deposit a dielectric onto one of the conductive materials. This PPID can be reduced by reducing electric charge accumulation on the one conductive material during the plasma process dielectric deposition.
A semiconductor apparatus includes a first substrate and a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer. The semiconductor apparatus also includes an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate. The semiconductor apparatus further includes a first transistor formed at least partially in the second substrate and a second transistor formed at least partially in or over the epitaxial layer. The second substrate and the epitaxial layer have bulk properties with different electron and hole mobilities. At least one of the transistors is configured to receive one or more signals of at least about 5V. The first substrate could have a first crystalline orientation, and the second substrate could have a second crystalline orientation.
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.
A power-on reset (POR) circuit is provided. The POR circuit includes a first current source, a second current source, and a current comparator. The first current source is arranged to provide a relatively supply-independent circuit. The second current source is arranged to provide a supply-dependent current. The current comparator is arranged to compare the relatively supply-independent circuit with the relatively supply-dependent current to provide a POR signal.
A method for integrating a metal-insulator-metal (MIM) capacitor and a thin film resistor in an integrated circuit is provided that includes depositing a first metal layer outwardly of a semiconductor wafer substrate. A portion of the first metal layer forms a bottom plate for a MIM capacitor. A second metal layer is deposited outwardly of the first metal layer. A first portion of the second metal layer forms a top plate for the MIM capacitor and a second portion of the second metal layer forms contact pads for a thin film resistor.
A system and method for processing close talking differential microphone array (CTDMA) signals in which incoming microphone signals are transformed from time domain signals to frequency domain signals having separable magnitude and phase information. Processing of the frequency domain signals is performed using the magnitude information, following which phase information is reintroduced using phase information of one of the original frequency domain signals. As a result, high pass filtering effects of conventional differential signal processing of CTDMA signals are substantially avoided.
G10K 11/178 - Methods or devices for protecting against, or for damping, noise or other acoustic waves in general using interference effectsMasking sound by electro-acoustically regenerating the original acoustic waves in anti-phase
H04M 1/60 - Substation equipment, e.g. for use by subscribers including speech amplifiers
A micro-electromechanical systems (MEMS) relay includes a switch with a first contact region and a second contact region that are vertically separated from each other by a gap. The MEMS relay requires a small vertical movement to close the gap and therefore is mechanically robust. In addition, the MEMS relay has a small footprint and, therefore, can be formed on top of small integrated circuits.
A circuit is configured to receive an input signal and to produce an output signal measuring a power of the input signal. The circuit includes a multiplier cell configured to multiply first and second signals, where each of the first and second signals includes a component related to the input signal and a component related to the output signal. The circuit also includes a controlled amplifier configured to amplify an intermediate signal produced by the multiplier cell, where an amplification provided by the controlled amplifier is a function of the output signal. The circuit could further include at least one first converting amplifier configured to generate the component related to the input signal and at least one second converting amplifier configured to generate the component related to the output signal. Transconductances of the converting amplifiers could be selected to configure the circuit as a linear or logarithmic RMS power detector.
A solar-powered charger includes a solar panel configured to generate electrical energy at a first voltage level. The charger also includes a converter configured to receive the electrical energy from the solar panel, perform temperature compensation, and output the electrical energy to a load at a second voltage level. The second voltage level could be between 13.2V and 14.4V, inclusive. The converter could be configured to output the electrical energy at the second voltage level with a substantially constant current over temperatures between 0° C. and 100° C., inclusive. The converter could be configured to be coupled to and recharge a lead acid battery, a lithium ion battery, or a nickel metal hydride battery.
A device driver which includes an input driver configured to produce a sequence of uncompensated drive signals along with compensation circuitry connected to receive the uncompensated drive signals and to produce corresponding compensated drive signals. The compensation circuitry is capable of storing two or less control points that define a single compensation curve such as a Bezier curve, with the compensation circuitry converting the uncompensated drive signals to the corresponding compensated drive signals utilizing the control points. An output driver is configured to drive a device such as one or more light emitting diodes to be connected to the output driver with the compensated drive signals.
A manufacturing exception handling system is described for use with a manufacturing execution system that controls a semiconductor manufacturing process. The present invention provides real time information to the user that identifies restrictions that have been placed on the use of entities and inventories in the semiconductor manufacturing process. The present invention also provides real time information to the user that identifies the persons who are authorized to remove the restrictions. The present invention saves the time and effort that would otherwise be required to find out why a restriction existed and who could remove the restriction during the semiconductor manufacturing process.
G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)
42.
Forming a ferromagnetic alloy core for high frequency micro fabricated inductors and transformers
A plurality of sequential electro-deposition, planarization and insulator deposition steps are performed over a patterned thick photoresist film to form a laminated ferromagnetic alloy core for micro-fabricated inductors and transformers. The use of a plurality of contiguous thin laminations within deep patterns on non-removable photoresist film provides sufficient volume of magnetic film in, for example, high frequency applications, and reduces eddy current loss at high frequency.
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
H01L 29/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor bodies or of electrodes thereof
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
H01F 17/06 - Fixed inductances of the signal type with magnetic core with core substantially closed in itself, e.g. toroid
H01F 7/06 - ElectromagnetsActuators including electromagnets
A battery temperature monitoring circuit, which has a cold comparator and a hot comparator, achieves high accuracy in a small cell size by utilizing a cold current optimized for the cold comparator and a cold reference voltage, and a hot current optimized for the hot comparator and a hot reference voltage, along with switching circuitry that provides the cold current to the cold comparator as the battery temperature approaches the cold trip temperature, and the hot current to the hot comparator as the battery temperature approaches the hot trip temperature.
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.
A galvanic isolation system provides galvanic isolation in digital transfer integrated circuits by using conductivity modulation of the semiconductor substrate. Modulation of the conductivity of the substrate affects eddy current losses of a (differential) RF inductor that is isolated from the substrate by a sufficient amount of dielectric material, which provides a basis for signal transfer from the modulated substrate to the inductor across the isolation barrier.
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
A clock generator circuit for producing a clock output having a controlled duty cycle is disclosed. A bi-stable circuit provides the clock output which is switchable to a first state in response to an edge of the input clock signal and to a second state in response to a feedback signal. A duty cycle detection circuit is configured to source a current to a node and to sink a current from the node depending upon the output clock state. A capacitor is connected to receive a duty cycle current relating to the current at the node, with a comparator circuit being configured to sense a voltage on the capacitor and to produce the feedback signal when the voltage is at a selected level.
A fluxgate magnetometer is formed in a semiconductor wafer fabrication sequence, which significantly reduces the size and cost of the fluxgate magnetometer. The semiconductor wafer fabrication sequence attaches a die, which has drive and sense circuits, to the bottom surface of a cavity formed in a larger structure, and forms drive and sense coils around a magnetic core structure on the top surface of the larger structure.
A control circuit for use in a battery charger circuit that includes a switching voltage regulator, with the control circuit having a constant current charging mode and a constant voltage charging mode. A switcher controller is provided which configured to control a state of a top side switching transistor and a low side transistor of the switching voltage regulator in response to at least one error signal. A power path transistor switch is disposed intermediate an output of the switching voltage regulator and a first node for receiving a first terminal of a battery to be charged. Feedback circuitry is further provided to produce a first error signal relating to a difference between a first voltage and a first target voltage, with the first voltage being between the output of the switching voltage regulator and a second node for receiving a second terminal of the battery to be charged, with the first error signal being used by the switcher controller when the control circuit is in the constant voltage charging mode for controlling the top and low side switching transistors.
H02J 7/06 - Regulation of the charging current or voltage using discharge tubes or semiconductor devices
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A battery charger circuit having a regulator controller configured to control the switching transistors of a switching voltage regulator. A power path switch is disposed intermediate an output of the switching voltage regulator and a terminal of a battery to be charged, with the power path switch including at least two transistor segments having common respective drain electrodes, common respective source electrodes and separate respective gate electrodes. A power path switch controller operates to sequentially turn ON the at least two transistor segments of the power path switch, preferably in the order of a decreasing ON resistance.
In one aspect of the invention, an integrated circuit package is described. The integrated circuit package includes a substrate formed from a dielectric material that includes multiple electrical contacts and conductive paths. An upper lead frame is attached with and underlies the substrate. The upper lead frame is electrically connected with at least one of the contacts on the substrate. The active surface of an integrated circuit die is electrically and physically coupled to the upper lead frame through multiple electrical connectors. A lower lead frame may be attached with the back surface of the integrated circuit die. A passive device is positioned on and electrically connected with one of the contacts on the substrate and/or the upper lead frame.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
51.
Method and apparatus for achieving galvanic isolation in package having integral isolation medium
H01L 31/062 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the metal-insulator-semiconductor type
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
H01L 23/552 - Protection against radiation, e.g. light
52.
System and method for providing an improved shutter for use with a shadow tab mask
A system and method is disclosed for providing an improved shutter for use with a shadow tab mask and heater table during a conditioning process for a physical vapor deposition (PVD) chamber. A shutter for covering the heater table is provided that has a circumferential flange with a thickness that is less than a thickness of the non-circumferential flange portions of the shutter. A shadow tab mask having a portion that extends over the flange portion is placed on the heater table. When deposition material is subsequently deposited, the reduced thickness of the flange portion prevents a fused seal from being formed between deposition material deposited on the shadow tab mask and deposition material deposited on the circumferential flange of the shutter.
C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
C23C 16/04 - Coating on selected surface areas, e.g. using masks
53.
Semiconductor structure with galvanically-isolated signal and power paths
A galvanic die has signal structures and a transformer structure that provide galvanically-isolated signal and power paths for a high-voltage die and a low-voltage die, which are both physically supported by the galvanic die and electrically connected to the signal and transformer structures of the galvanic die.
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A phase detection system for providing a phase signal indicative of a phase difference between first and second input signals, with the system including a pair of amplification channels for receiving the input signals, with each channel including a plurality of amplifier stages. The outputs of the two amplification channels are connected to the inputs of a multiplier arrangement, with the arrangement producing an uncompensated phase signal. Compensation circuitry is provided to receive a magnitude signal indicative of the relative magnitudes of the two input signals, with the magnitude signal being used to produce a corrected phase signal indicative of the phase difference between the two input signals.
The spikes in current and voltage that result from the failure of a galvanic dielectric layer are safely contained by a galvanic isolation fuse that pops and forms and open circuit between a high-voltage die and a low-voltage die in response to the failure of the galvanic dielectric layer.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
56.
Sampling phase lock loop (PLL) with low power clock buffer
A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.
Galvanic isolation between a high-voltage die and a low-voltage die in a multi-die chip is provided by a galvanic isolation die that physically supports the high-voltage die and the low-voltage die, and provides capacitive structures with high breakdown voltages that allow the high-voltage die to capacitively communicate with the low-voltage die.
A master modem is configured to generate a carrier signal for transmission over a wired connection. A slave modem is configured to change an impedance of the wired connection to alter generation of the carrier signal by the master modem. The impedance of the wired connection is changed based on data to be provided by the slave modem. The master modem can demodulate its own carrier signal to obtain the data provided by the slave modem. The impedance of the wired connection could be changed by changing an impedance of a transformer winding or inductor of the slave modem, where the transformer winding or inductor is coupled to the wired connection. The impedance of the wired connection could also be changed by changing a reactance of a circuit coupled to the wired connection.
H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
A non-volatile memory cell includes NMOS programming, read, erase, and control transistors having gate electrodes connected to a storage node. The erase and control transistors have interconnected source, drain, and bulk electrodes. The cell is programmed by setting source, drain, bulk, and gate electrodes of all transistors to a positive voltage. An inhibiting voltage is applied to source, drain, and bulk electrodes of the read transistor, while setting source and drain electrodes of the programming transistor to the positive voltage and the bulk electrode of the programming transistor to the positive voltage or the inhibiting voltage. Source, drain, and bulk electrodes of the control transistor are then ramped to a negative control voltage while ramping source, drain, and bulk electrodes of the erase transistor to a negative erase voltage and then back to the positive voltage. Source, drain. bulk, and gate electrodes of the programming, erase, and control transistors are then returned to the positive voltage, while setting the source, drain, and bulk electrodes of the read transistor to the inhibiting voltage.
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
60.
Frequency domain signal processor for close talking differential microphone array
A system and method for processing close talking differential microphone array (CTDMA) signals in which incoming microphone signals are transformed from time domain signals to frequency domain signals having separable magnitude and phase information. Processing of the frequency domain signals is performed using the magnitude information, following which phase information is reintroduced using phase information of one of the original frequency domain signals. As a result, high pass filtering effects of conventional differential signal processing of CTDMA signals are substantially avoided.
A low-voltage high-speed frequency divider substantially reduces the power required to generate a half-rate in-phase clock signal and a half-rate quadrature-phase clock signal by reducing the number of pairs of transistors that respond to a full-rate clock signal and a full-rate inverse clock signal.
H03K 21/00 - Details of pulse counters or frequency dividers
H03B 19/06 - Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
62.
Circuitry and method for digital to analog current signal conversion with phase interpolation
Differential signal detection circuitry with an integrated reference voltage. The reference voltage is added as an offset to the output voltage, and its integration ensures that variations in the reference voltage closely track variations in the signal. Accordingly, the detection threshold for the signal being detected remains more consistent over variations in the circuit manufacturing process, power supply voltage and operating temperature.
H03K 5/22 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
An apparatus is provided, which includes a driving circuit. The driving circuit includes a gamma reference source and a liquid crystal display (LCD) source driver circuit. A first resistor string is provided. A plurality of digital-to-analog converters (DACs) are provided, where each DAC is coupled to the first resistor string. An output circuit having a second resistor string is provided so as to output a plurality of reference voltages. The LCD source driver circuit is coupled to the output circuit of the gamma reference source. The source driver is configured to receive the plurality of reference voltages, wherein the plurality of reference voltages are arranged in a first sequence during a positive polarity cycle and are arranged in a second sequence during a negative polarity cycle. The fifth sequence is an inverse of the fourth sequence.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
H04N 9/69 - Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits for modifying the colour signals by gamma correction
65.
Decision feedback equalizer operable with multiple data rates
Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates.
Low voltage differential signaling (LVDS) circuitry and method for dynamically controlling the common mode voltage at the input of an LVDS receiver. The common mode voltage of the incoming LVDS signal is monitored. The common mode voltage at the input of the LVDS receiver is clamped at a clamp voltage when the common mode voltage of the incoming LVDS signal is less than a predetermined voltage, and allowed to track it otherwise.
H03L 5/00 - Automatic control of voltage, current, or power
67.
Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone
An asymmetric insulated-gate field effect transistor (100U or 102U) provided along an upper surface of a semiconductor body contains first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima (316-1-316-3) at respective locations (PH-1-PH-3) spaced apart from one another. The tailoring is typically implemented so that the vertical dopant profile of the pocket portion is relatively flat near the upper semiconductor surface. As a result, the transistor has reduced leakage current.
System and method are provided for transferring electrical energy among multiple electrical energy storage devices via a differential power bus and a capacitive load switched-mode power supply. The switched-mode power supply transfers the electrical energy between the load capacitor and the differential power bus to which the electrical energy storage devices (e.g., rechargeable batteries and/or capacitors connected in parallel or series or combinations of both) are electrically connected via bus switches. As a result, electrical energy is efficiently transferred and distributed among the electrical energy storage devices.
The cost and size of an atomic magnetometer are reduced by attaching together a first die which integrates together a vapor cell, top and side photo detectors, and processing electronics, a second die which integrates together an optics package and a heater for the vapor cell, and a third die which integrates together a VCSEL, a heater for the VCSEL, and control electronics.
G01J 5/20 - Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
G01J 1/42 - Photometry, e.g. photographic exposure meter using electric radiation detectors
H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
70.
Capacitive touch screen sensing and electric field sensing for mobile devices and other devices
A system includes a touch screen having multiple electrodes. The system also includes a processing unit configured to use the electrodes to (i) detect an object contacting the touch screen or within a first distance from the touch screen in a first mode and (ii) detect the object within a second distance from the touch screen in a second mode. The second distance is larger than the first distance. The processing unit can be configured to use the multiple electrodes in the first mode to perform capacitive touch screen sensing. The processing unit can also be configured to use the multiple electrodes in the second mode to perform electric field sensing.
G06F 3/045 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using resistive elements, e.g. a single continuous surface or two parallel surfaces put in contact
71.
Schottky-clamped bipolar transistor with reduced self heating
The self heating of a high-performance bipolar transistor that is formed on a fully-isolated single-crystal silicon region of a silicon-on-insulator (SOI) structure is substantially reduced by forming a Schottky structure in the same fully-isolated single-crystal silicon region as the bipolar transistor is formed.
A dipole oscillation tank circuit includes a first capacitive structure, an inductive structure, and a second capacitive structure connected in series. The tank circuit transfers electric energy back and forth between the capacitive structures in dipole oscillation cycles. A renewal circuit injects energy into the tank circuit to replenish energy lost during the oscillation cycles. A switch is connected in parallel across the first capacitive structure and in parallel across the inductive structure and the second capacitive structure. During one phase of the oscillation cycles, the switch is opened for current to flow through the first capacitive structure and the inductive structure, and then closed to bypass the first capacitive structure. During another phase of the oscillation cycles, the switch is closed to bypass the first capacitive structure and then opened for current to flow through the first capacitive structure and the inductive structure.
H03B 5/18 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance
73.
Thermally conductive substrate for galvanic isolation
A galvanic isolation integrated circuit system includes a semiconductor substrate; a layer of thermally conductive material, e.g., CVD nano- or poly-diamond thin film or boron nitride CVD thin film, formed over the semiconductor substrate; a first integrated circuit structure formed over the layer of thermally conductive material; a second integrated circuit structure formed over the layer of thermally conductive material, the second integrated circuit structure being spaced apart from the first integrated circuit structure; and a galvanic isolation structure formed over the layer of thermally conductive material between the first and second integrated circuit structures and connected to the first integrated circuit structure and the second integrated circuit structure.
A circuit includes multiple doped regions in a substrate. A first of the doped regions has a tip proximate to a second of the doped regions and is separated from the second doped region by an intrinsic region to form a P-I-N structure. The circuit also includes first and second electrodes electrically coupled to the first and second doped regions, respectively. The electrodes are configured to supply voltages to the first and second doped regions to reverse bias the P-I-N structure and generate light. The first doped region could include multiple tips, the second doped region could include multiple tips, and each tip of the first doped region could be proximate to one of the tips of the second doped region to form multiple P-I-N structures. The P-I-N structure could also be configured to operate in double avalanche injection conductivity mode with internal positive feedback.
A system includes a load and a single-ended primary-inductance converter (SEPIC) power converter configured to provide power to the load. The SEPIC power converter includes a primary side and a secondary side that are electrically isolated by a transformer. The transformer includes a primary coil and a secondary coil. The primary side includes (i) a capacitor coupled to a first end of the primary coil and (ii) an inductor and a switch coupled to a second end of the primary coil. The primary side of the SEPIC power converter could also include a diode coupled between the inductor and the switch, where the diode is coupled to the second end of the primary coil. The capacitor could be configured to transfer energy to the secondary side of the SEPIC power converter through the transformer during valleys associated with a rectified input voltage.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
76.
Method and apparatus for dicing die attach film on a semiconductor wafer
In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing apparatus that includes a sawing blade and a movable support structure that physically supports the semiconductor wafer. The semiconductor wafer is coupled with the support structure with various layers, including a die attach film, an adhesive and a base film. The die attach film is cut with the sawing blade. During the cutting operation, a contact portion of the sawing blade engages one of the layers and moves at least partly in one direction. While the contact portion of the sawing blade engages the layer, the support structure moves in the opposite direction. Various aspects of the present invention relate to arrangements and a wafer sawing apparatus that involve the aforementioned sawing method.
H01L 21/461 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
A rail-to-rail buffer receiving a differential input signal and generating a differential output signal includes first and second amplifier circuits configured in a pseudo differential buffer structure and first and second comparators coupled to compare the respective part of the differential input signal and a first voltage and to generate select signals. Each of the first and second amplifier circuits includes first and second complementary differential input stages and the first and second comparators generate respective select signals to turn on only one of the first or the second differential input stage in each amplifier circuit depending on a value of the respective part of the differential input signal. In operation, the first and second complementary differential input stages of each amplifier circuit not being turned on at the same time.
An apparatus includes a sawtooth generator configured to generate a sawtooth voltage, where the sawtooth generator is configured to repeatedly reset the sawtooth voltage using a clock signal. The apparatus also includes a pulse width modulation (PWM) generator configured to generate a PWM signal using the sawtooth voltage, the PWM signal comprising multiple PWM pulses, where an output voltage is based on the PWM signal. The apparatus further includes a transient detector configured to detect a transient associated with the output voltage and to cause the sawtooth generator to asynchronously reset the sawtooth voltage in response to the detected transient. The resetting of the sawtooth voltage may cause the sawtooth generator to lengthen one or more of the PWM pulses in the PWM signal and/or generate one or more additional PWM pulses in the PWM signal. This can help to increase a duty cycle of the PWM signal.
G05F 1/59 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
79.
Technique for reducing crosstalk interference between integrated switching regulators
An apparatus includes multiple switching regulators configured to generate at least one regulated output signal. The apparatus also includes a combination unit configured to blank the switching regulators in response to a switching event associated with one or more of the switching regulators. Each switching regulator could include a one shot timer configured to generate a first signal having pulses that identify switching events associated with that switching regulator. The combination unit may be configured to combine the first signals to generate at least one second signal, which can be provided to blanking inputs of the switching regulators. The combination unit could include one or more logical OR gates configured to combine the pulses in the first signals. The one shot timer in each switching regulator could generate a pulse in the first signal in response to each rising and falling edge of a control signal in that switching regulator.
G05F 1/44 - Regulating voltage or current wherein the variable is actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices semiconductor devices only
80.
Method of forming a capacitive micromachined ultrasonic transducer (CMUT)
A method includes forming first isolation trenches in a first side of a first semiconductor-on-insulator (SOI) structure to electrically isolate multiple portions of the first SOI structure from each other. The method also includes bonding a second SOI structure to the first SOI structure to form multiple cavities between the SOI structures. The method further includes forming conductive plugs through a second side of the first SOI structure and forming second isolation trenches in the second side of the first SOI structure around the conductive plugs. In addition, the method includes removing portions of the second SOI structure to leave a membrane bonded to the first SOI structure. The isolated portions of the first SOI structure, the cavities, and the membrane form multiple capacitive micromachined ultrasonic transducer (CMUT) elements. Each CMUT element is formed in one of the isolated portions of the first SOI structure and includes multiple CMUT cells.
H01H 9/00 - Details of switching devices, not covered by groups
H01L 21/449 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups involving the application of mechanical vibrations, e.g. ultrasonic vibrations
81.
System and method for providing adaptively equalized data signal with alternately adjusted data signal boost and sliced data signal amplitude
Method and system for adaptive signal equalizing with alternating boost and amplitude controls. In accordance with one exemplary embodiment, data signal boost control is based on measured equalized and sliced data signal energies within a bandwidth disposed about a higher frequency, while sliced data signal amplitude control is based on measured equalized and sliced data signal energies within a bandwidth disposed about a lower frequency.
An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
A method of fabricating chip carriers suitable for use in packaging integrated circuits and other electronic, electro-mechanical and opto-electronic devices is described. In general, a number of wires (or wires and rods) are arranged in parallel in a wiring fixture. After the wires are positioned, they are encapsulated to form an encapsulated wiring block. The wiring block is then sliced to form a number of discrete panels. Preferably, the various wires are geometrically positioned such that each resulting panel has a large number of device areas defined therein. The encapsulant in each panel effectively forms a substrate and the wire segments in each panel form conductive vias that extend through the substrate. The resulting panels/chip carriers can then be used in a wide variety of packaging applications.
A semiconductor structure is provided with (i) an empty well having relatively little well dopant near the top of the well and (ii) a filled well having considerably more well dopant near the top of the well. Each well is defined by a corresponding body-material region (108 or 308) of a selected conductivity type. The regions respectively meet overlying zones (104 and 304) of the opposite conductivity type. The concentration of the well dopant reaches a maximum in each body-material region no more than 10 times deeper below the upper semiconductor surface than the overlying zone's depth, decreases by at least a factor of 10 in moving from the empty-well maximum-concentration location through the overlying zone to the upper semiconductor surface, and increases, or decreases by less than a factor of 10, in moving from the filled-well maximum-concentration location through the other zone to the upper semiconductor surface.
A controlled seam magnetic core lamination utilizable in an inductor structure includes a magnetic base and first and second spaced-apart magnetic sidewalls extending substantially orthogonally from the base to define a seam therebetween. The controlled seam magnetic core lamination is utilizable in an inductor structure that includes: a non-conductive lower mold; a plurality of spaced-apart controlled seam lower laminations formed in the lower mold, each magnetic lower lamination having a horizontal base and first and second spaced-apart sidewalls extending substantially vertically upward from the base to define a seam therebetween; a non-conductive isolation layer formed on the lower mold and the magnetic lower laminations; a conductive trace formed on the isolation layer; a non-conductive upper mold formed over the isolation layer and the conductive trace; and a plurality of spaced-apart controlled seam magnetic upper laminations formed in the upper mold, each magnetic upper lamination having a horizontal base and first and second spaced-apart sidewalls that extend substantially vertically upward from the base to define a seam therebetween.
H01F 7/06 - ElectromagnetsActuators including electromagnets
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
86.
Dynamic control of frequency compensation for improved over-voltage protection in a switching regulator
An error amplifier includes a difference amplifier providing an error signal representing a difference in voltage between a feedback signal and a reference signal. The error amplifier further includes a compensation circuit limiting the rate of change of the error signal. The compensation circuit includes a switch that when activated effectively removes a circuit portion from the compensation circuit. A switch signal indicates for the switch to be activated when the feedback signal exceeds the reference signal by a predefined amount.
The compensation circuit may further include a second switch that when activated effectively removes a second circuit portion from the compensation circuit. A second switch signal indicates for the second switch to be activated when the feedback signal exceeds the reference signal by a second predefined amount.
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
A phase frequency detector detects the difference between the edges of a fractional-rate recovered clock signal and the edges within a serial data bit stream, where the edges within the serial data bit stream correspond with the edges of a full-rate clock signal that was used to clock the serial data bit stream.
A clock conditioning circuit including a phase detector circuit configured to provide an analog tuning signal indicative of a phase relationship between a reference clock to be conditioned and a generated clock. The controlled oscillator is configured to produce the generated clock, with the generated clock having an output frequency adjustable in response to an analog tuning signal applied to a control signal input of the controlled oscillator. Converter circuitry is provided to produce a digital representation of the analog tuning signal when the mode control circuitry is in a tracking mode. In the event the reference clock is lost, the mode control circuitry switches to a holdover mode so as to provide an analog holdover signal to the control signal input based upon the digital representations produced just prior to the loss of the reference clock.
A buck/boost regulator controller is provided. The buck-boost regulator controller controls four switches in an H-bridge configuration to control voltage regulation. The buck/boost regulator controller includes a digital error amplifier and buck-boost control logic. The digital error amplifier provides a multi-bit digital error voltage signal that is based on the difference between the output voltage and the desired output voltage. The buck-boost control logic controls the opening and closing of the four switches in the H-bridge based, in part, on the multi-bit digital error voltage signal.
G05F 1/24 - Regulating voltage or current wherein the variable is actually regulated by the final control device is AC using bucking or boosting transformers as final control devices
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
90.
DMOS Transistor with a cavity that lies below the drift region
A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
An improved method for manufacturing bipolar transistors is disclosed. The method for forming a PNP transistor comprises the steps of forming a P type collector on a substrate, forming a PNP epitaxial base on the P type collector, forming a PNP extrinsic base in the PNP epitaxial base, and forming a PNP emitter in contact with the PNP extrinsic base. The method for forming an NPN transistor comprises the steps of forming an N type collector on a substrate, forming a NPN epitaxial base on the N type collector, forming an NPN extrinsic base in the NPN epitaxial base, and forming an NPN emitter in contact with the NPN extrinsic base. The PNP and NPN transistors may be manufactured in the same control flow process.
In a snapback NMOS ESD protection structure, the output voltage presented to an internal circuit for ESD protection is limited by providing for a separate output terminal at a lower voltage than the input terminal. The voltage drop between the two terminals is achieved by connecting the input and output terminals to different parts of a ballast region of the structure and using the saturation resistance of the portion of the ballast region between the terminals to achieve the voltage drop.
Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses
A group of high-performance like-polarity insulated-gate field-effect transistors (100, 108, 112, 116, 120, and 124 or 102, 110, 114, 118, 122, and 126) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.
A system and method is described for providing a continuous bath wetdeck process for use in the manufacture of semiconductor wafers. The invention provides a method for extending an effective working life of a chemical bath of the type that comprises a chemical bath liquid within a chemical bath container. An amount of fresh chemical is continuously added to the chemical bath liquid and an amount of chemical bath liquid is simultaneously purged from the chemical bath container. A balance is maintained between the amount of fresh chemical that is added to the chemical bath liquid and the amount of chemical bath liquid that is purged in order to maintain the effectiveness of the chemical bath liquid to clean semiconductor wafers within the chemical bath.
An error amplifier includes a first amplification circuit with a reference signal input and a feedback signal input representing the amplitude of a load voltage of a switched mode power supply. The error amplifier includes a difference amplifier providing a difference signal representing a difference between the reference signal and the feedback signal, provided for determining the duty cycle of a switching signal in the switched mode power supply. The first amplification circuit further includes a control circuit providing a control signal generated as a function of the difference between the reference signal and the feedback signal.
The error amplifier also includes a second amplification circuit, included in a compensation circuit. The second amplification circuit receives the control signal, and the operating current of the second amplification circuit is adjusted by an amount indicated by the control signal.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
97.
Lead frame interconnect scheme with high power density
An integrated circuit package configured to incorporate a lead frame and methods for its making are is described. The package comprising an IC with aluminum bond pads in communication with circuitry of the die with lead frame with silver bond pads. The package having gold bumps bonded between the aluminum bond pad of the die and the silver bond pad of the lead frame. The package including an encapsulant envelope and including various materials and bond pad structures and constructed in a manner formed by thermosonically or thermocompressionally bonding the gold balls to the bond pads. Also, disclosed are methods of making the package.
A non-volatile memory (NVM) cell comprises an NMOS control transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to a storage node; a PMOS erase transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the storage node; an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the storage node, the bulk region electrode being connected to a common bulk node; the first NMOS pass gate transistor having a source electrode connected to the drain electrode of the NMOS data transistor, a drain electrode, a bulk region electrode connected to the common bulk node, and a gate electrode; and a second NMOS pass gate transistor having a drain electrode connected to the source electrode of the NMOS data transistor, a source electrode, a bulk region electrode connected to the common bulk node, and a gate electrode.
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
99.
High voltage tolerant SCR clamp with avalanche diode triggering circuit
A D/A converter having reference node for receiving a reference voltage and together network having a network reference bus connected to the reference node by way of a first electrical connection. The converter network produces a series of reference outputs derived from the reference voltage in response to a digital input applied to the converter, with the converter network sinking a network reference current at the network reference bus which varies with the converter digital input. A reference current compensator circuit is included which provides a compensation current at the network reference bus having a magnitude which varies in response to at least a portion of the digital input, with the compensation current operating to reduce variations in current through the first electrical connection caused by changes in the digital input.
