A radio communication apparatus is provided which comprises first and second radio circuit portions arranged to receive radio signals in a common frequency band from an antenna, the first and second radio circuit portions comprising respective first and second amplifiers. An amplifier sharing portion is operable to direct radio signals amplified by the first amplifier to one or more further components of the second radio circuit portion. The radio communication apparatus is operable in a first mode in which only the first radio circuit portion is configured to receive radio signals, said radio signals being amplified using the first amplifier, a second mode in which only the second radio circuit portion is configured to receive radio signals, said radio signals being amplified using the second amplifier, and a third mode in which the first and second radio circuit portions are configured to receive radio signals, said radio signals being amplified by the first amplifier and directed to one or more further components of the second radio circuit portion using the amplifier sharing portion.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
H04B 1/401 - Circuits for selecting or indicating operating mode
A first radio transceiver device is configured for communication with a second radio transceiver device. It sends the second device, over a first radio connection, a connection establishment data packet comprising connection timing information for establishing a second radio connection and establishes the second connection. Each connection is associated with a respective time series of periodic connection events for radio transmissions. After the second connection has been established, the first device suspends the first connection by ceasing transmitting any data packets to the second device over the first connection. While the first connection is suspended, the first device can transmit to the second device, or receive from the second device, over the second connection, a data packet comprising an activation request, and, thereafter, activate the first connection by transmitting a data packet to the second device over the first connection in a connection event associated with the first connection.
A system (102) for characterising an integrated circuit (104) comprises an integrated circuit (104), a processor (118) and a memory (116) storing instructions that cause the processor (118) to run a characterisation model. The integrated circuit (104) comprises an all-digital phase-locked loop (106) that generates an output clock signal with the same phase as a reference clock signal. The all-digital phase-locked loop (106) comprises a digital-to-time converter (120) that delays the reference clock signal. The integrated circuit (104) also includes circuitry (130) for generating an indication of the step size of the digital-to-time converter (120), and memory (108) for storing this indication. The processor (118) receives the indication from the memory (108), and runs the characterisation model to generate a characterisation of the integrated circuit (104) based on the step-size of the digital- to-time converter (120).
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G04F 10/00 - Apparatus for measuring unknown time intervals by electric means
A system comprises a first circuit portion operating with a first clock having a first frequency, a second circuit portion operating with a second clock having a second, higher frequency, and an interface circuit portion for transferring data from the first and the second circuit portions. The first circuit portion is arranged to assert a data valid signal when asserting data at a data input. The data storage portion is configured to detect the data valid signal and to change an input data storage location of a shared memory in response thereto. The signalling portion is configured to change a state of an interface signal in response to the data valid signal. The data access portion is configured to change an output data storage location in response to the change of state of an interface signal and to output a data ready signal to the second circuit portion.
A radio apparatus is configured to implement a method for computing a polar transformation of an input bit sequence of 2n bits for transmission by radio. The method comprises storing the input bit sequence in electronic memory as a working bit sequence, and then computing a bitwise XOR of a contiguous first half of the working bit sequence with a contiguous second half of the working bit sequence, the second half being disjoint from the first half. The result of the bitwise XOR is stored in electronic memory. A bit-interleave sequence is generated by interleaving the result of the bitwise XOR with the second half of the working bit sequence. Next, the bit interleave sequence is stored as the updated working bit sequence. After n iterations of the previous steps are performed, the working bit sequence, or a contiguous subsequence thereof, is the polar transformation of the input sequence.
A first radio device is configured, for each of a plurality of further radio devices, to determine a respective connection interval and a respective periodic series of connection events, having a period equal to the connection interval, each connection event comprising time for transmitting data packets to the further radio device. The first radio device communicates the respective connection interval to each of the further radio devices. Before transmitting a first data packet of a connection event, over a radio channel, to a further radio device, the first radio device performs a clear channel assessment to determine whether the radio channel is clear, and, in response, before a start of the connection event, transmits a channel reservation signal over the radio channel until the start of the connection event. It then transmits the first data packet over the radio channel to the further radio device.
There is disclosed a radio system, and a method for operating a radio system. An orthogonal frequency-division multiple-access (OFDMA) radio signal is transmitted, which has information digitally modulated onto it as OFDMA symbols on subcarriers in a first set of symbol periods. The radio signal has a second set of symbol periods interleaved, with the first set of symbol periods in time, in which these subcarriers are unmodulated, so as to create a predetermined temporal pattern. The radio signal is received on a first radio apparatus, which demodulates and uses information from the modulated symbol periods of the predetermined temporal pattern. A second radio apparatus receives the same radio signal, detects the predetermined temporal pattern of modulated and unmodulated symbol periods in the received radio signal, and, in response, activates its radio module by generating an electrical wake-up signal.
A radio-frequency transceiver is operable to transmit one or more radio-frequency signals via an antenna in a transmitter mode and to receive one or more radio-frequency signals via the antenna in a receiver mode. The transceiver comprises a power amplifier for use in the transmitter mode comprising a switched-capacitor array comprising a plurality of capacitance elements, and a low-noise amplifier for use in the receiver mode. The transceiver is configured, when operating in the receiver mode, to pull one or more of the capacitance elements in the switched-capacitor array to a ground potential.
A radio communication system, comprising a transmitter and a receiver wherein the transmitter is configured to transmit a multi-block request including control and timing information relating to a subsequent multi-block transmission, the receiver is configured to receive and decode said multi-block request, the transmitter is configured to subsequently transmit the multi-block transmission, wherein the multi-block transmission comprises a series of discrete blocks. Each block comprises a respective data payload and a synchronisation portion, and each synchronisation portion enables synchronisation between the transmitter and receiver when used in combination with the control and timing information, independently of receipt of other blocks in the multi-block transmission.
An integrated-circuit device comprising a non-volatile memory (NVM), a debug port, and debug-port control circuitry for controlling access to the integrated-circuit device through the debug port. The debug-port control circuitry is configured to read a first bit array and a second bit array from respective predetermined locations in the NVM in a single read cycle. The second bit array is distinct from the first bit array, and at least the second bit array contains a plurality of bits. The debug-port control circuitry is further configured to determine whether the first bit array has a first predetermined bit pattern and whether the second bit array has a pattern other than a second predetermined bit pattern, and to control access through the debug port at least partly in dependence on said determination.
G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
A circuit portion comprises a DCDC converter arranged to provide current from an output of the converter to one of a plurality of loads at a time. The plurality of loads includes a low priority load and a primary load. In response to the controller detecting, while the DCDC converter is providing current to the low priority load, that the voltage across the primary load is below a first threshold, channel logic circuitry is configured to stop providing current from the output of the converter to the low priority load and to provide current from the output of the converter to the primary load. A voltage regulator provides current to the low priority load when the voltage across the low priority load is below a second threshold.
H02J 1/08 - Three-wire systemsSystems having more than three wires
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A switched capacitor power amplifier comprising a first, positive signal path and a second, negative signal path. The switched capacitor power amplifier is arranged to receive a digital control signal and, based on the digital control signal, to selectively activate both the first signal path and the second signal path, in a differential mode, to provide a first peak output power level, or either the first signal path or the second signal path, to produce a second peak output power level, wherein the second peak output power level is lower than the first output power level.
H03F 3/00 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A circuit system is disclosed that comprises a first circuit portion comprising a clock output portion, a data input portion and a delay portion, and a second circuit portion comprising a clock input connected to the clock output portion and a data output connected to the data input portion. The delay portion comprises a replica of at least part of the clock output portion or the data input portion. The first circuit portion is arranged to transmit a first clock signal via the clock output portion, and to input the first clock signal to the delay circuit portion to generate a second clock signal comprising a delayed version of the first clock signal. The second circuit portion is arranged to receive the first clock signal and to send data to the first circuit portion by transmitting a data signal to the data input portion via the data output according to the first clock signal. The first circuit portion is arranged to receive the data from the second circuit portion by sampling the data signal according to the second clock signal.
Radio transceiver device and method are provided. The method includes sequentially transmitting radio frequency signals on radio channels, each channel being nonuniformly spaced and representing a distinct continuous tone, sequentially transmitting radio frequency signals with distinct continuous tones on same channels as those received from the first radio transceiver device, as well as measured phase difference of the radio frequency signals on each radio channel received from the first radio transceiver device, creating a first set of estimate candidates, repeatedly for the radio channels, determining an optimal phase unwrapping vector candidate based on the first set of estimate candidates and the measured phase differences of signals received on the first and second transceiver devices to determine a second set of candidates, and calculating the distance between the first and second radio transceiver devices using the optimal phase unwrapping vector candidate and the second set.
A method for controlled phase adjustment and coherent modulation in a radio frequency transceiver is provided. The radio frequency transceiver comprises an analogue circuitry for transmitting and receiving radio frequency signals and an all-digital phase locked loop controlled by a Phase Locked Loop, PLL, Control unit (200). The method comprises: receiving a phase shift, and based thereon, deriving a corresponding digital control signal; inputting the digital control signal to the PLL Control unit (200), the control signal defining a temporary iteration pattern of delays to be used by a configurable delay block, DTC (240); locking a radio frequency oscillator signal of a Digital Controlled Oscillator (220) in the phase locked loop to the temporary iteration pattern of delays; adjusting the phase of the frequency signal in digital circuitry, until the signal phase matches the phase shift defined by the digital control signal.
H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H04B 1/403 - Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency
16.
METHOD AND DEVICE FOR PERFORMING RANGING BETWEEN RADIO SIGNAL DEVICES
A method and device for phase-based ranging measurement between a first radio frequency transceiver and a second radio frequency transceiver. The method comprises the steps of: transmitting a radio frequency signal from the first radio frequency transceiver to the second radio frequency transceiver; receiving, on the first radio frequency transceiver, a radio frequency signal transmitted from the second radio frequency transceiver, the frequency being the same as the frequency transmitted from the first radio frequency transceiver; shifting the frequencies of the transmitted and the received radio signals of a transceiver to a same frequency, different from the transmitted and received frequencies, prior to being input to processing modules in the transmitter and receiver signal paths of the transceiver, where the modules in these signal paths are synchronized by sharing same clock domain; after an analogue to digital conversion module, converting the analogue transmitted and received radio frequency signals to digital signals, shifting the frequencies of the digital signals to the same frequency as the frequency of the transducer's transmitted and the received radio frequency signals, and measuring the frequency response between the transmitted and reflected radio frequency signals from the resulting digital signals. The device comprises means for performing said method.
G01S 13/84 - Systems using reradiation of radio waves, e.g. secondary radar systemsAnalogous systems wherein continuous-type signals are transmitted for distance determination by phase measurement
H04B 1/408 - Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency the transmitter oscillator frequency being identical to the receiver local oscillator frequency
An electronic wireless communication device, comprising a memory region, storing a priority ordering of network identifiers, comprising at least a first wireless network identifier and a second wireless network identifier; and a network status indicator, having at least a first value and a second value. The electronic wireless communication device is arranged to carry out a network searching process, in which the electronic wireless communication device searches for available networks in an order defined by the priority ordering of network identifiers until an available network is identified and the electronic wireless communication device successfully connects to the available network. The electronic wireless communication device is arranged to omit at least the first network identifier from the priority ordering of network identifiers used during the network searching process whenever the network status indicator has the first value.
An oscillator circuit portion 200 including a resonator 216 arranged to oscillate with a resonant frequency, a capacitor 208 arranged to provide charge to the resonator, a first switch 206 arranged to connect the capacitor to an input voltage to charge the capacitor, a second switch 210 arranged to connect the resonator to the capacitor, and a timing circuit 202 configured to generate periodically a first pulse PULSE_L and a second pulse PULSE_H. The first pulse is configured to close the first switch, the second pulse is configured to close the second switch, and the first and second switches are arranged to be open when the timing circuit is not generating the first or second pulses, to maintain oscillation of the resonator.
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
H03B 5/04 - Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
An electronic comparator circuit, including an input portion, an output portion, a first portion, a second portion and a gain portion. The input portion includes a first input transistor and a second input transistor. In the first portion a first terminal of a first input transistor is connected between a first terminal of a third transistor and a second terminal of a fourth transistor, wherein the fourth transistor is connected in a diode configuration. The second portion includes a first terminal of a second input transistor connected between a first terminal of a fifth transistor and a second terminal of a sixth transistor, wherein the sixth transistor is connected in a diode configuration. The gain portion includes a gate of a seventh gain transistor cross-coupled to a gate of the fifth transistor. A gate of an eighth gain transistor is cross-coupled to a gate of the third transistor.
An integrated-circuit chip comprises a plurality of scan flip-flops and a retention cell. The chip is configured to have a scan-capture mode, in which the plurality of scan flip-flops and the retention cell are connected to respective functional circuitry of the integrated-circuit chip, and to have a scan-shift mode, in which the plurality of scan flip-flops and the retention cell are connected so as to form a scan chain for use during scan-chain testing of the integrated-circuit chip. The chip further comprises on-chip test circuitry arranged to generate and output a save signal, a clock signal, and a restore signal to the retention cell, for testing the retention cell during scan-chain testing of the integrated-circuit chip.
A radio frequency communication system is provided. The system comprises a first radio frequency device and a second radio frequency device arranged to establish a communication link by exchanging radio frequency signals in which data are encoded. The first radio frequency device is arranged to broadcast a radio frequency signal in which an advertising packet is encoded, the advertising packet comprising authentication information encrypted using an advertising key. The second radio frequency device is arranged to retrieve the authentication information and use the authentication information to authenticate the communication link.
An integrated circuit comprises an oscillator which outputs a clock signal, a logic circuit portion, a detection circuit portion for detecting signal propagation delay relative to clock frequency, and a power supply which provides a configurable supply voltage. The detection circuit comprises a latch circuit portion, a delay circuit portion and a comparison circuit portion. The latch circuit portion outputs an alternating signal which changes state in dependence on the clock signal. This is received by the delay circuit portion which outputs first and second delayed signals respectively subject to first and second propagation delays each dependent on the supply voltage. The comparison circuit portion compares the alternating signal with the delayed signals, and outputs respective comparison signals if said signals indicate that the respective propagation delay is smaller than the clock signal period. A control circuit portion controls the supply voltage in dependence on the comparison signals.
According to an aspect, there is provided a single-ended-to-differential complementary metal-oxide-semiconductor, SE2D CMOS, transconductance amplifier for a radio receiver. The SE2D CMOS transconductance amplifier comprises an input for receiving a radio frequency signal, first common-source n-type metal-oxide-semiconductor. CS NMOS (M1), and common-source p-type metal-oxide-semiconductor, CS PMOS, transistors (M5), second CS NMOS (M2) and CS PMOS (M6) transistors, a cross-coupled cascode stage for adjusting balance of the radio frequency currents outputted by the first (M1) and second (M2) CS NMOS transistors and a differential output. The first (M1) and second (M2) CS NMOS transistors have substantially equal transconductances and the first (M5) and second (M6) CS PMOS transistors have substantially equal transconductances. The first and second cross-coupled cascode NMOS transistors have substantially equal transconductances.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements
A method of synchronizing a plurality of client devices with an access point device comprises broadcasting by radio, from the access point, an encrypted broadcast message comprising synchronization information. The method further comprises receiving the encrypted broadcast message at each of the plurality of client devices, decrypting the encrypted broadcast message at each client device of the plurality of client devices, and using the synchronization information at each client device to synchronize the respective client device with the access point device.
An electronic apparatus comprises a resistive random access memory (ReRAM) and hardware or software logic for reading from and writing to the ReRAM. The logic is configured, for a predetermined integer K>0 and for each word of a plurality of multi-bit words of length W bits stored at respective addresses in the ReRAM, to replace the respective word with a respective replacement value. The logic reads the word from the respective address in the ReRAM and uses a selection process to select K bits of the word. It stores the respective replacement value of length W bits at the respective address by writing to the address to flip the selected K of the bits of the word.
An integrated circuit comprising a detection circuit portion for detecting an electromagnetic pulse attack on the integrated circuit is provided. The detection circuit portion comprises a shadow flip-flop comprising a clock input and a clock net connected to said clock input. The detection circuit portion also comprises a clock gate connected to the clock net that is controlled by an enable signal to selectively be in an open state in which the clock gate passes a clock signal to the clock net or in a closed state in which the clock gate does not pass the clock signal to the clock net. The detection circuit portion further comprises an error circuit portion, wherein the error circuit portion is arranged to selectively output an error signal if: the shadow flip-flop is clocked by a signal from the clock net and the clock gate is in the closed state.
G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
A circuit portion has an analog voltage supply module, a clock and a digital control module clocked by the clock. A bias voltage is applied to an analog voltage supply module so that it supplies a voltage to a node. The voltage is sampled at the node, at a signal edge of the clock, to obtain a sampled voltage. The sampled voltage is stored, the bias voltage to the analog voltage supply module is disabled and the sampled voltage is supplied to the node. A refresh signal is subsequently generated in response to at least one refresh criterion being met; and in response to the digital control module receiving the refresh signal, a refresh sequence is initiated. The refresh sequence includes re-applying the bias voltage to the analog voltage supply module; re-sampling the voltage at the node at a signal edge of the clock; and storing the re-sampled voltage.
A circuit portion for filtering digital signals comprises a first delay circuit portion, a second delay circuit portion, and a logic circuit portion. The first delay circuit portion introduces a time delay to rising edges of an input signal and outputs a first delayed digital signal. The second delay circuit portion introduces a time delay to falling edges of the input signal and outputs a second delayed digital signal. The logic circuit portion outputs a signal which retains a current state when the first and second delayed signals have different states, and a state that is dependent on a state of the first and second delayed signals when the first and second delayed 10 signals have the same state. The circuit portion effectively removes glitches—i.e. pulses of short duration—from the input signal.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A radio frequency receiver arranged to monitor for wake-up frames in a plurality of sample windows is provided. The wake-up frames are transmitted by a radio frequency transmitter in a sequence according to one or more sequence parameters including a wake-up interval between each wake-up frame of the sequence, and each sample window has a sample duration that is less than the wake-up interval. The sample windows occur in a pattern based on at least one of the one or more sequence parameters, such that the radio frequency receiver is arranged to detect at least one of the sequence of wake-up frames.
An integrated-circuit device comprises a plurality of processor cores and a system timer. The system timer includes a first oscillator that outputs a first clock signal at a first frequency, a first counter register incremented by the first clock signal and a plurality of event registers. Each event register triggers an event when a value held therein is determined to be equal to a value held in the first counter register. The first counter register is readable by each of the plurality of processor cores, and each of the processor cores are capable of writing to at least one of the event registers.
A circuit portion is disclosed comprising an operational input and a scan input; a logic portion comprising at least one input and at least one output; and a first scan latch comprising at least one input and at least one output. The circuit portion is arranged to operate in an operational mode in which the operational input is connected to an input of the logic portion and the logic portion operates as an asynchronous latch to generate an operational output signal at an output of the logic portion; and a scan mode in which the logic portion operates as part of a second scan latch, and the first scan latch and the second scan latch form a synchronous flip-flop comprising an input connected to the scan input and arranged to generate a scan output signal.
There is disclosed an integrated circuit which has a hardware semaphore that stores a value, and asynchronous hardware logic circuitry for operating the hardware semaphore. The asynchronous hardware logic circuitry has a hardware synchronization mutex which can be switched between any of one or more acquired states and an unacquired state, and has a first input for receiving requests to change the value of the hardware semaphore. In response to receiving one of said requests at the first input, if the synchronization mutex is unacquired, the asynchronous hardware logic circuitry switches the synchronization mutex to an acquired state, changes the value of the hardware semaphore in response to the request, then switches the synchronization mutex to being unacquired. If the synchronization mutex is acquired, the asynchronous hardware logic circuitry does not change the value of the hardware semaphore, at least while the synchronization mutex remains acquired.
An electronic apparatus comprises a processor, memory, a direct memory access (DMA) controller, and a bus system. The processor and memory are coupled to the bus system. The DMA controller is coupled to the bus system at a bus connection point. The DMA controller comprises a plurality of inputs and circuitry configured, for each input of the inputs, in response to receiving a signal at the respective input, to: determine a respective memory address in dependence on which of the plurality of inputs received the signal; read from the memory a respective job list of one or more jobs located at the respective memory address, each job specifying a respective transfer operation for the DMA controller to perform; and perform each job in the job list by transferring data through the bus connection point in accordance with the respective transfer operation.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
An asynchronous circuit portion for sampling an input signal is provided. The asynchronous circuit portion comprises a sampling circuit portion arranged to receive the input signal and to generate first and second sample signals; a first storage element arranged to generate a first storage signal on a first storage output on reception of the first sample signal; and a second storage element arranged to generate a second storage signal on a second storage output on reception of the second sample signal. A control circuit portion is arranged to detect if either of said first and second storage signals has been generated, to fix the first and second storage outputs and to generate a sample ready signal. The circuit portion generates an output signal corresponding to the input signal using the first storage output when the sample ready signal is generated.
The cut-off frequency of an electronic filter having a nominal transfer function and a nominal cut-off frequency is estimated by: applying a first signal at a first frequency to an input of the filter while sampling an output of the filter in order to obtain a first magnitude measurement, the first frequency being less than the nominal cut-off frequency; applying a second signal at a second frequency to the input of the filter while sampling the output of the filter in order to obtain a second magnitude measurement, the second frequency being greater than the nominal cut-off frequency; and estimating the cut-off frequency of the filter based on the nominal transfer function, the first magnitude measurement, and the second magnitude measurement.
H04B 17/11 - MonitoringTesting of transmitters for calibration
G01R 27/28 - Measuring attenuation, gain, phase shift, or derived characteristics of electric four-pole networks, i.e. two-port networksMeasuring transient response
H03H 11/12 - Frequency selective two-port networks using amplifiers with feedback
A circuit portion comprises a mapping module, a source component, a destination component and a memory. The mapping module comprises a plurality of channels that each provides a connection for connecting two components of the circuit portion in a one-to-one relationship. The source component is arranged in a first clock or power domain, and the destination component is arranged in a second clock or power domain. In response to an assertion of an event signal or an interrupt by the source component, the mapping module is configured to forward the event signal or interrupt to the destination component via only one channel of the plurality of channels so as to cause the destination component to perform a corresponding task according to a mapping stored in the memory.
An amplifier apparatus is arranged to amplify an input signal with a gain based on a digital gain control signal. The amplifier apparatus comprises a digital-to-analogue converter arranged to convert the digital gain control signal into an analogue gain control signal according to a first non-linear relationship between digital gain control signal and analogue gain control signal; and an amplifier circuit portion arranged to amplify the input signal with a gain based on the analogue gain control signal according to a second non-linear relationship between analogue gain control signal and gain. The first non-linear relationship is based on the second non-linear relationship.
An amplifier circuit portion is proved. The amplifier circuit is arranged to amplify an input signal with a gain based on a gain control signal. The amplifier circuit portion comprises a plurality of amplifier cells having a common input for receiving the input signal and a common output for providing an amplified version of the input signal. At least one of the amplifier cells is operable in: a controllable gain mode in which the amplifier cell provides an amplification gain to the input signal based on the gain control signal; and a fixed gain mode in which the amplifier cell provides a fixed, non-zero amplification gain to the input signal.
According to an aspect, there is provided a tunable radio frequency filter (209) for preselection in a multiband radio receiver or transceiver with a low-noise amplifier with a single-ended input. The tunable radio frequency filter comprises a first capacitor (C1, 1001) having a first terminal for connecting to at least one antenna of the multiband radio receiver or transceiver and a second terminal; and a series resonant circuit, connected between the second terminal of the first capacitor and the ground. The series resonant circuit comprises a first inductor (L1 1003) and a tunable capacitor (Ct, 1004) connected in series with first inductor and having a plurality of tuning values corresponding to operating frequency bands of the multiband radio receiver or transceiver. The tunable capacitor is implemented in an integrated circuit. The series resonant circuit is configured to be resonant at a plurality of first subharmonics of frequencies of the operating frequency bands. Optionally the filter comprises a second capacitor (C2, 1002) and a second inductor (L2, 1010) in series between the resonant circuit to ground and the input of the LNA. The second inductor adds to impedance matching and low pass filtering above the operating frequency bands.
H04B 1/525 - Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
H04B 1/18 - Input circuits, e.g. for coupling to an antenna or a transmission line
A circuit portion for generating a current that is proportional to absolute temperature comprises first and second bipolar-junction transistors (BJTs) arranged to present a voltage difference between the emitter of the first BJT and the emitter of the second BJT that is proportional to absolute temperature. Circuitry is arranged to generate an output current in dependence on this voltage difference, wherein the output current is proportional to absolute temperature. Adjustment circuitry is electrically coupled to the base of the second BJT to sink current away from this base such that a temperature coefficient of the output current is at least partly determined by the adjustment circuitry.
G05F 1/567 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
41.
SYSTEM TIMER WITH HIGH RESOLUTION AND ULTRA-LOW POWER OPERATION
An integrated-circuit device comprises a low-resolution timer and a high-resolution timer. The low-resolution timer comprises a first oscillator that outputs a first clock signal at a first frequency, and a first counter register incremented by the first clock signal. The high-resolution timer comprises a second oscillator that outputs a second clock signal at a second frequency, greater than the first frequency, and a second counter register incremented by the second clock signal. The device operates in one of a plurality of states, including an active state in which both the high-resolution timer and the low-resolution timer are enabled, and a sleep state in which the high-resolution timer is disabled and the low-resolution timer is enabled. The device transitions from the sleep state to the active state by writing a value to the second counter register based on a value held in the first counter register.
A radio communication method, performed by a first radio device, comprises receiving an incoming radio packet from a second radio device, measuring a local radio condition while receiving the incoming radio packet, and transmitting an outgoing radio packet to the second radio device. The outgoing radio packet comprises a header which includes a field containing a value that is indicative of the local radio condition and that is suitable for the second radio device to use when determining a data rate at which to transmit a body of a further radio packet to the first radio device.
A radio device communicates with a 4G or 5G cellular network that comprises one or more cells and supports a 4G LTM PSM or 5G MICO power saving mode for devices registered to the cellular network. When the radio device is registered to the cellular network and has the power saving mode activated, in response to determining that the radio device has data to send to the cellular network, the radio device deactivates the power saving mode and searches for a suitable cell of the cellular network for sending the data. If the radio device is unable to find to any suitable cell of the cellular network for sending the data to the cellular network, it reactivates the power saving mode.
A radio transmitter device for transmitting radio signals according to an orthogonal frequency division multiplexing protocol using a plurality of frequency resources is provided. The radio transmitter device is configured to transmit a plurality of reference signals within a first subset of said plurality of frequency resources at a first monitoring occasion and a second monitoring occasion and transmit paging information within a second subset of said plurality of frequency resources at one or more of the first and second monitoring occasions, wherein the first subset has a larger frequency span than the second subset.
According to an aspect, there is provided a method for transmitting a low-power radio signal, comprising: transmitting, by a radio device, a data radio signal by using binary frequency-shift-keying modulation introducing a phase change between consecutive bit intervals in the data radio signal; and transmitting, by the radio device, a wake-up radio signal using the binary frequency-shift-keying modulation where repetition coding is applied before the frequency-shift-keying to eliminate the phase change between consecutive bit intervals in the wake-up radio signal.
A signal processing device is configured to compensate for process and temperature variations deviating from a nominal process and temperature condition. A transconductance amplifier circuit produces a current output dependent on a voltage input and a transconductance gain. A transimpedance amplifier circuit produces a voltage output dependent on the current. A bias circuit comprises transistors (M1, M2) configured such that the gate and drain of the first transistor (M1) are connected to the gate of the second transistor (M2) and to a PTAT current source. The source of the first transistor (M1) is connected to a node via a first resistor (R1), and the source of the second transistor (M2) is connected to that node via a second, trimmable resistor (R2). A feedback circuit for the transimpedance amplifier comprises a third, trimmable resistor (R3). The ratio between a resistance of the second and third resistors (R2, R3) is constant.
H03F 3/08 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage
According to an aspect, there is provided an all-digital phase-locked loop, ADPLL, for a radio receiver, transmitter or transceiver. The ADPLL comprises a time-to-digital converter for generating a digital time signal based on an external reference clock signal and a feedback signal, a switched capacitor digitally controlled oscillator, SC-DCO, for generating a radio frequency signal used as the feed-back signal, a phase-locked loop for controlling the SC-DCO based on the digital time signal for achieving a phase and frequency lock and digital processing means. The digital processing means are configured to maintain, in at least one memory, a lookup table defining a plurality of switching configurations of the SC-DCO corresponding to a plurality of frequencies of the radio frequency signal and to cause the phase-locked loop controller to adjust the switching configuration of the SC-DCO according to the lookup table.
H03L 7/10 - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
A method of operating a radio communication system comprising a group of radio devices is provided. The method comprises a first radio device of the group broadcasting a radio signal in which data are encoded; radio devices of the group receiving the radio signal from the first radio device and decoding the data encoded therein; and a second radio device of the group broadcasting a radio signal in which data are encoded; coordinating at least one radio device of the group to transition from receiving the radio signal broadcast by the first radio device and decoding the data encoded therein to receiving the radio signal broadcast by the second radio device of the group and decoding the data encoded therein; and radio devices of the group receiving the radio signal from the second radio device and decoding the data encoded therein.
A method of operating a radio communication system is provided comprising a central radio device and a plurality of peripheral radio devices. The method comprises the central radio device receiving data from a first peripheral radio device over a first unicast radio connection; the central radio device broadcasting a radio signal in which data received from the first peripheral radio device are encoded; at least one peripheral radio device receiving the radio signal broadcast by the central radio device and decoding the data encoded therein; the central radio device receiving data from a second peripheral radio device over a second unicast radio connection; the central radio device broadcasting a radio signal in which data received from the second peripheral radio device are encoded; and at least one peripheral radio device receiving the radio signal broadcast by the central radio device and decoding the data encoded therein.
A radio communication system comprises an electronic device (102) and a base station (107) of a cellular telecommunications network (106). The base station (107) determines a delay duration (324) and sends it to the electronic device (102). The electronic device (102) initiates a first timer having a length equal to the delay duration (324) whilst obtaining a GNSS location fix. The base station (107) initiates a second timer having a length corresponding to the delay duration (324) and, upon its expiry, sends information to the electronic device (102). The electronic device (102), after obtaining the location fix and after expiry of the first timer, monitors for information (320) from the base station (107).
An integrated circuit has multiple clock domains. At least one of the clock domains is a secure domain including a protection clock portion. The protection clock portion is arranged to produce a clock signal having a clock period which varies randomly over at least some cycles of operation. The clock signal is arranged to clock one or more components in the secure domain.
An integrated-circuit device comprises a processor, a program memory, a hardware-based key generation system that outputs a selectable device identity key of a plurality of predetermined device identity keys, and a one-time programmable (OTP) memory for storing one or more public cryptographic keys. When a public cryptographic key is stored in the OTP memory, and when software is stored in the program memory, the device uses the public cryptographic key to determine whether the software stored in the program memory is validly signed by a private cryptographic key associated with the public cryptographic key, before the software is executed by the processor. The device controls which device identity key of the plurality of predetermined device identity keys is output by the hardware-based key generation system at least partly in dependence on the outcome of this determination.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
H04L 9/14 - Arrangements for secret or secure communicationsNetwork security protocols using a plurality of keys or algorithms
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
PIERCE, of an oscillator. The method includes acquiring or determining a digital representation encoding a bias current. The method also includes carrying out an algorithm to update the digital representation if the oscillation amplitude is measured, by one or more peak detectors, to be outside of upper and lower thresholds. Also provided is an apparatus arranged to control the bias current of an oscillator using this method, the apparatus including one or more peak detectors and a current digital to analogue converter.
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
H03L 5/00 - Automatic control of voltage, current, or power
A circuit portion comprises a signal generator, clocked by a clock signal, for generating an alternating logic signal comprising a repeated sequence of alternating logic transitions. A circuit sub-portion introduces a delay to the alternating logic signal. An edge-travel detector samples the delayed alternating logic signal and outputs an edge-travel signal representative of a timing of a logic transition in the alternating logic signal with respect to the clock signal. A mask block compares the edge-travel signal with a mask signal to determine whether the timing of the logic transition matches one or more candidate timings, and outputs a comparison signal in dependence on this determination.
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
A circuit portion receives, at a synchroniser, a signal clocked at a first frequency and outputs a synchronised signal clocked at a second frequency to a bounce-rejection circuit portion. The bounce-rejection circuit portion operates on a plurality of successive samples of the synchronised signal and outputs an output signal. The bounce-rejection circuit portion: changes the output signal from a first value to a second value if a proportion of said plurality of successive samples having said second value is determined to meet a threshold, the threshold being greater than 50% of the plurality of successive samples; otherwise, it maintains the output signal at the first value.
A method of generating a puncturing pattern for use with a 1/n convolutional code having a predetermined code rate is disclosed. The 1/n convolutional code uses a predetermined set of binary generator polynomials comprising a first generator polynomial and a second generator polynomial, wherein the second generator polynomial has more non-zero coefficients than the first generator polynomial. For each of a plurality of candidate puncturing patterns, transmission of data over a noisy channel is simulated, the data being encoded using the 1/n convolutional code punctured in accordance with the respective puncturing pattern. A transmission error rate is determined for each candidate, and the error rates are compared to identify a candidate that has a lowest error rate. The plurality of candidate puncturing patterns includes only patterns that puncture no more coded bits generated by the second generator polynomial than they puncture coded bits generated by the first generator polynomial.
An electronic wireless communication device arranged to connect to a first wireless network of a plurality of wireless networks. The device includes a status indicator having at least two values, comprising a first value indicating that the electronic wireless communication device is assigned a status as a moving device and a second value indicating that the electronic wireless communication device is assigned a status as a stationary device. The device is arranged to periodically search, at intervals defined by a search period, for available networks of the plurality of wireless networks, other than the first wireless network to which the electronic wireless communication device is connected. The search period has a first period value when the status indicator has the first value and a second period value when the status indicator has the second value. The first period value is lower than the second period value.
An electronic device for processing near-field communication signals includes first and second antenna connection terminals for connection to a near-field antenna, a linear load and a voltage clamp, each connected between said connection terminals. A current flowing through the linear load has a substantially linear, positive relationship with a voltage across the linear load, defining a conductance of the linear load. The conductance of the linear load is adjustable. The voltage clamp has an adjustable clamping voltage. The electronic device also includes a peak detector arranged to detect an amplitude of an incoming near-field communication signal across said antenna connection terminals, and a control circuit arranged to adjust the conductance of the linear load and the clamping voltage of the voltage clamp based on the amplitude detected by the peak detector, so as to regulate the voltage swing across the antenna connection terminals.
A method of operating a client device is provided. The method comprises receiving a radio signal comprising an encrypted data packet, said data packet comprising one or more data structures addressed to one or more client devices; decrypting said data packet to obtain said one or more data structures; and establishing whether any of the one or more data structures is addressed to the client device. If a data structure of the data packet is addressed to the client device, the data packet is authenticated. If no data structure of the data packet is addressed to the client device, the data packet is discarded.
A method of determining device locations includes receiving a set of candidate locations in an environment and generating training data representing synthetic distance measurements between pairs of the candidate locations. The synthetic distance measurements are generated by applying random variations to the geometric distances between the candidate locations. The training data and candidate locations are used to train a machine learning model. A set of measured distances between devices are input to the trained learning model, which is used to determine a respective location in the environment of each of the devices.
A method and apparatus for transmission are disclosed. The solution comprises forming a frame for transmission, where the frame comprises a header section, a training sequence section, an address and rate section, and a payload section. The training sequence section (202) comprises a given number of first fields (300A, 300B, 300C, 300D) of equal length and a second field (302). The total length of the given number of the first fields is shorter or equal than the length of the second field, the second field (302) comprises a given symbol sequence, and the first field (300A, 300B, 300C, 300D) comprises a part of the same given symbol sequence.
A circuit portion for generating an output reference voltage (VZERO, VUPPER, VLOWER) comprises a self-cascode circuit portion, a follower circuit portion, and a reference resistor (R1). The self-cascode circuit portion generates a first intermediate reference voltage (VREF1) at a first node based on an input current (Ibias) provided thereto. The follower circuit portion mirrors the input current (Ibias) and generates a second intermediate reference voltage (VREF2) at a second node based on the first intermediate reference voltage (VREF1). The reference resistor (R1) is coupled to the second node. The follower circuit portion comprises a feedback loop that counteracts variations in the second intermediate reference voltage (VREF2), and the circuit portion generates the output reference voltage (VZERO, VUPPER, VLOWER) based on a current through the reference resistor (R1).
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A radio device is configured for radio communication as a master device over each of a plurality of connections between the master device and a respective plurality of slave devices. The radio device is configured to schedule radio transmissions over the connections. For each time period of a succession of time periods, it assigns to each of the connections a respective first time slot for radio transmissions between the radio device and the respective slave device, wherein the first time slots within the time period are non-overlapping and are all located within a first portion of the time period. In response to a request to provide additional time to a first connection, it assigns to the first connection an additional time allocation within a second portion of a time period of the succession of time periods, the second portion occurring after the first portion of the time period.
An arbitration circuit portion is provided for coordinating first and second radio circuit portions arranged to transmit and/or receive radio signals. The arbitration circuit is arranged to receive a communication request signal from the first radio circuit portion and/or the second radio circuit portion; determine an arbitration outcome based at least partially on said communication request signal; and apply said arbitration outcome to the first and/or second radio circuit portions. The arbitration circuit portion is operable in a normal arbitration mode, in which determining the arbitration outcome comprises determining an input state based at least partially on said communication request signal and determining an arbitration outcome that corresponds to said input state according to a set of arbitration rules; and a first radio priority mode in which the arbitration outcome prioritizes all requests from the first radio circuit portion over requests from the second radio circuit portion.
According to an aspect, there is provided an apparatus for power management of a system on a chip, SoC. The apparatus comprises means for performing the following. The apparatus maintains, in a memory, a knowledge-based system comprising a plurality of rules. Each rule maps a shift from a first to a second SoC state to a set of one or more sequential actions for activating a power tree configuration corresponding to said second SoC state. The apparatus receives a request for adjusting a current power tree configuration so as to match a target SoC state. The apparatus determines a set of one or more sequential actions for activating an optimal power tree configuration for the SoC based on the knowledge-based system using current and target SoC states as an input. Finally, the apparatus adjusts the current power tree configuration according to the set of one or more sequential actions.
A computer-implemented method for designing an integrated circuit includes placing a predefined cell within a twin-well CMOS silicon-on-insulator integrated circuit design. The predefined cell comprises a logic region comprising one or more transistors of a first type, the first type being either conventional-well CMOS transistors or flipped-well CMOS transistors. The predefined cell also comprises an inner set of boundary cells that are arranged along one or more edges of the logic region, and an outer set of boundary cells that are arranged along one or more edges of the predefined cell and that are configured for placement adjacent transistors of a second type, the second type being either flipped-well CMOS transistors or conventional-well CMOS transistors and the second type being different from the first type.
A method of operating a radio receiver device is provided. The method comprises receiving a radio signal comprising an encrypted advertising packet, said advertising packet comprising a header portion and a payload portion comprising one or more encrypted payload structures. A decryption operation is performed using a decryption key on a first section of the payload portion and a length of a first payload structure of the payload portion indicated by the decryption result is determined. The indicated length of the first payload structure is compared to a set of feasible lengths based at least partially on the length of the payload portion. If the length of the first payload structure is not in the set of feasible lengths for the first payload structure, it is determined that the decryption key does not correspond to the advertising packet.
A circuit portion is provided which is arranged to be operable in a test mode. The circuit portion includes a Successive Approximation Register Analog to Digital Converter, SAR ADC, and an input for a reference signal. The SAR ADC is arranged to generate a feedback signal having a duty cycle representing a time taken for the SAR ADC to complete an analogue to digital conversion. The SAR ADC can carry out a comparison of a duty cycle of the reference signal with the duty cycle of the feedback signal, and can generate an output signal comprising a digital representation of the comparison of the reference duty cycle and the feedback duty cycle.
According to an aspect, there is provided a comparator comprising input terminals, first, second and third biasing current sources configured to output first, second and third biasing currents, an input circuit driven by the first biasing current source and comprising an amplification circuit and a load circuit configured to provide positive feedback for the amplification circuit, first and second current mirroring circuits for forming, with the input circuit, first and second current mirrors producing first and second current mode signals, first and second current-controlled driver circuits configured to be controlled by the second and third biasing currents, respectively, and the first and second current mode signals, respectively, a latch circuit comprising first and second cross-coupled complementary metal-oxide semiconductor transistors acting as a latch having substantially rail-to-rail output voltage swing and being driven, respectively, by the first and second current-controlled driver circuits and an output circuit implementing a current starved inverter.
A radio receiver is arranged to detect a symbol boundary in a received encoded signal, by receiving the signal, and correlating a portion of the received signal against a predetermined training field sequence to generate a correlation signal. The portion of the received signal has a length which is shorter than the length of the predetermined training field sequence. The radio receiver is also arranged to compare the correlation signal to a threshold derived from the received signal, and identify at least one peak in the correlation signal if any portion of the correlation signal exceeds the threshold. The symbol boundary is derived from the at least one peak.
A method for a RACH procedure comprises: generating system broadcast information indicating random access channel, RACH, occasions for a RACH procedure of a legacy user apparatus capable of employing a downlink and an uplink initial bandwidth part of a base station of the cellular radio network; and causing a transmission of the system broadcast information in a first downlink portion of the one or more non-overlapping portions of the downlink initial bandwidth part. The system broadcast information also indicates i) a set of the RACH occasions for the reduced capability user apparatus that are confined to one or more non-overlapping portions of the uplink initial bandwidth part, and ii) at least one of the one or more non-overlapping portions of the downlink initial bandwidth part containing a control resource set for a random access response and/or a contention resolution of the RACH procedure of the reduced capability user apparatus.
A radio receiver device is provided. The radio receiver device is arranged to receive a radio signal comprising a symbol sequence corresponding to a training sequence; to determine a first autocorrelation of said symbol sequence using a first autocorrelation latency; to determine a second autocorrelation of said symbol sequence using a second autocorrelation latency that is longer than the first autocorrelation latency; and to combine said first and second autocorrelations to determine an estimate of carrier frequency offset between the radio signal and the radio receiver device.
A digital radio receiver comprises a configurable filter, a configurable re-sampler and a configurable mixer, and operates in accordance with a predetermined radio communication protocol which defines a first type of data packet that, when transmitted, occupies a first range of frequencies, and a second type of data packet that, when transmitted, occupies a second range of frequencies, the first range being wider than the second range. The filter, re-sampler and mixer process data packets of both the first and second type. By default, the filter attenuates frequencies that fall outside of the first range. When the receiver receives a data packet transmitted by a remote device it determines whether the data packet is of the second type and, if so, it configures the filter to attenuate frequencies that fall outside of the second range, and configures the re-sampler and mixer in dependence on the determination.
An integrated circuit includes a closed loop oscillator circuit portion. The closed loop oscillator circuit portion has an input for a reference clock signal and an output providing an output clock signal to one or more further components of the integrated circuit. The output clock signal has an average output frequency derived from the reference clock signal. The closed loop oscillator circuit portion is operable in a spread spectrum mode in which the closed loop oscillator circuit portion varies a frequency of said output clock signal, by temporarily increasing the frequency by a predetermined amount and temporarily decreasing the frequency by said predetermined amount, at different times, within a predetermined multiple of a clock cycle of the reference clock signal.
G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
An integrated circuit comprises an oscillator arranged to output a periodic clock signal, a logic circuit portion, and a detection circuit portion for detecting a low logic speed relative to a clock signal frequency. The detection circuit portion comprises a latch circuit portion that outputs a first signal that changes state once per clock cycle, a delay circuit portion arranged to receive said first signal and output a second signal subject to a propagation delay, and a comparison circuit portion arranged to compare the first signal and the second signal and output an error signal if the signals are indicative of low logic speed relative to the clock signal frequency. The delay circuit portion comprises a replica delay path that includes a plurality of logic elements, each of said logic elements being type-matched to a respective logic element included in a critical path of the logic circuit portion.
G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
An arbitration circuit portion for coordinating first and second radio circuit portions arranged to transmit and/or receive radio signals in a common frequency band is provided. The arbitration circuit portion comprises a memory storing a look-up table comprising a plurality of arbitration outcomes for a corresponding plurality of input states. The arbitration circuit portion is arranged to receive a communication request signal from the first radio circuit portion or the second radio circuit portion; determine an input state based at least partially on said communication request signal; use the look-up table to determine an arbitration outcome for said input state; and apply said arbitration outcome to the first and/or second radio circuit portions.
A radio receiver device is provided. The radio receiver device is configured to receive a radio signal comprising a data packet with a packet duration, said data packet comprising a first portion and a second portion; to determine an initial estimate of the packet duration using data included in the first portion; to determine a correction factor for said initial estimate of the packet duration using data included in the second portion; and to combine the initial estimate and the correction factor to determine a refined estimate of the packet duration.
The invention provides a direct memory access (DMA) controller. The DMA controller has an address register, a data register and transfer circuitry for transferring data over a bus of a computing system. The DMA controller is configured to use the transfer circuitry to read data over the bus from a memory location having a first memory address, wherein the data comprises a second memory address, and store the second memory address in the address register, and use the transfer circuitry to transfer data over the bus between a memory location having the second memory address, or having a memory address derived from the second memory address, and the data register.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 12/14 - Protection against unauthorised use of memory
A configurable radio frequency receiver is provided. The receiver has at least one low noise amplifier; an oscillator arrangement for producing a plurality of signals having a first number or a second number of separate phases; and multiple mixer modules having inputs connected to an output of the low noise amplifier. The receiver has a configurable resistor network. The receiver is configured such that it can operate in a first mode with said plurality of signals having said first number of phases or a second mode with said plurality of signals having said second number of phases. The configurable resistor network enables the receiver to operate in the first mode in a first configuration, and the second mode in a second configuration. The mixer modules are employed during the operation of the first mode and the second mode.
A radio receiver device is disclosed. The radio receiver device is configured to receive a radio signal comprising a data packet, said data packet comprising a first portion comprising an encoded bit sequence and including information specific to the data packet and a second portion comprising an encoded bit sequence and comprising corresponding information specific to the data packet. The radio receiver device is configured to calculate a correlation metric using the first portion and the second portion; and to estimate a carrier frequency offset between the radio signal and the radio receiver device using the correlation metric.
A receiver apparatus for receiving an OFDM radio signal comprising a first plurality of subcarrier-symbols, modulated on a corresponding plurality of subcarriers, and a second plurality of subcarrier-symbols, modulated on the corresponding plurality of subcarriers, to generate first and second bit sequences, the first bit sequence being an interleaved version of the second bit sequence according to a predetermined interleave function. Soft-output decoder logic generates a first soft-bit sequence for the first plurality of subcarrier-symbols, and a second soft-bit sequence for the second plurality of subcarrier-symbols. Combiner logic combines the soft-bit sequences, with the soft-bit sequences either both in an interleaved state or both in a non-interleaved state, by combining a respective soft-bit having a bit position in the first soft-bit sequence with a respective soft-bit having a same bit position in the second soft-bit sequence. Hard-output decoder logic outputs a hard-bit sequence representing the transmitted bit sequence.
According to an aspect, there is provided a swing-boosted differential oscillator and a method for trimming the oscillator. The oscillator comprises a switch (110) for connecting a set of capacitors (C1, C2) alternately to power supply and ground (102, 112) based on a switching control (116A, 116B), a comparator (114) configured to produce the switching control (116A, 116B) by comparing a voltage of the capacitors (C1, C2) at the inputs (VC1, VC2) of the comparator to a preset threshold voltage, and a trimmable resistor (RCAL) connecting the inputs (VC1, VC2) of the comparator, the resistor controlling the frequency of the output (118) of the oscillator.
H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
H03K 3/013 - Modifications of generator to prevent operation by noise or interference
H03K 4/502 - Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator the capacitor being charged from a constant-current source
An integrated-circuit device comprises a resettable source register in a first reset domain. A destination circuit, outside the first reset domain, is arranged to sample an output of the resettable source register. A digital logic module causes a central reset controller to output a reset-warning signal in response to receiving a request to reset first reset domain, and to reset the first domain after a predetermined delay period from outputting the reset-warning signal.
A receiver apparatus is configured to receive a radio-frequency signal comprising a first subcarrier comprising first subcarrier symbols and a second subcarrier comprising second subcarrier symbols, wherein the first subcarrier symbols and the second subcarrier symbols both encode a same bit sequence in a respective first subcarrier symbol and a second subcarrier symbol. Soft-output decoder logic calculates respective log-likelihood ratios for each of the first subcarrier symbols and generates a first output sequence comprising the respective log-likelihood ratios calculated for the first subcarrier symbols and similarly generates a second output sequence. Combiner logic combines the output sequences by adding or subtracting a respective log-likelihood ratio with a respective log-likelihood ratio calculated for the respective second subcarrier symbol to obtain a combined log-likelihood ratio for a respective bit of the bit sequence, and outputs a combined output sequence comprising a respective combined log-likelihood ratio for each bit of the bit sequence.
According to an aspect, there is provided a swing-boosted differential oscillator (500) and a method for trimming the oscillator. The oscillator comprises a switch (110') for connecting a set of capacitors (C1, C2) alternately to power supply and ground (102', 112') based on a switching control (116A', 116B'), two comparators (502, 504) configured to produce an output signal of the oscillator (ck) and the switching control (116A', 116B') via a multiplexer (508) by comparing a voltage of the capacitors (C1, C2) at the inputs (VC1, VC2) of the comparators to a threshold voltage (VBB), where the comparators comprising back gate bias input (fig. 5: 804, fig. 8: Vbb, 804) for controlling the threshold voltage of the comparators, the threshold voltage trimming the frequency of the output signal of the oscillator.
H03K 4/502 - Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator the capacitor being charged from a constant-current source
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
There is provided a method of testing an RF transceiver circuit and an RF transceiver circuit arranged to be operable in a test mode including a transmitter circuit portion and a receiver circuit portion, the receiver circuit portion including a mixer. The method involves the transmitter circuit portion generating a modulated signal and the receiver circuit portion receiving a continuous radio frequency wave. The mixer mixes the modulated signal with a signal derived from the continuous radio frequency wave to produce an output. A remainder of the receiver circuit portion processes the output of the mixer.
A radio frequency device arranged to communicate with a radio network cell of a radio network is provided. The radio frequency device is arranged to operate in a first mode in which the radio frequency device communicates with a radio network cell using a standard communication protocol; to operate in a second mode in which the radio frequency device communicates with a radio network cell using a coverage enhancement communication protocol; to operate in a third mode in which the radio frequency device is restricted from communicating with a radio network cell using the coverage enhancement communication protocol; and to transition from operating in the third mode to operating in the second mode without operating in the first mode.
According to an aspect, there is provided a relaxation oscillator (100) comprising first (101, 11) and second (102, 12) current sources and a comparator (103) having a first input (103-) connected to the first current source, a second input (103+) connected to the second current source and an output. One of the first and second inputs is an inverting input and other one of the first and second inputs is a non- inverting input. The relaxation oscillator further comprises a resistive circuit (110) connected between the first input of the comparator and the ground. The resistive circuit comprises at least a first resistor (R) and a capacitor charging circuit (111) connected between the second input of the comparator and the ground. The capacitor charging circuit comprises a capacitor (105, C), a second resistor (107, R0) connected in series with the capacitor and a switch (106) connected in parallel with the capacitor. The switch is configured to be controlled based on the output of the comparator.
H03K 4/502 - Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator the capacitor being charged from a constant-current source
A control portion for controlling an amplifier portion of a transmitter device is provided. The amplifier portion is arranged to amplify a radio signal with a transmission gain based at least partially on a gain control signal and having a nominal gain relationship between the gain control signal and the transmission gain. The control portion is arranged to determine a desired transmission gain, to determine one or more operating conditions, to calculate a gain control signal for causing the amplifier portion to apply the desired transmission gain, taking into account the nominal gain relationship and the one or more operating conditions, and to output said gain control signal. The gain control signal is different to a gain control signal calculated based only on the nominal gain relationship.
A battery characterisation system for determining one or more characteristics of a battery is provided. The system comprises a controllable load arranged to be connected to a battery and a voltage sensor arranged to measure a voltage output from said battery. The battery characterisation system is arranged to receive information identifying one or more nominal properties of said battery; to select a discharge profile based on said one or more nominal properties; to control the controllable load to discharge said battery according to said discharge profile; to record the voltage output measured by the voltage sensor and a current output from the battery as the battery is being discharged; and to determine one or more characteristics of the battery using said recorded voltage output and current output.
G01R 31/36 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
G01R 31/3842 - Arrangements for monitoring battery or accumulator variables, e.g. SoC combining voltage and current measurements
A battery-powered device is disclosed comprising a battery and a voltage sensor arranged to measure a terminal voltage of the battery. The battery-powered device is arranged to: a) determine a current flowing into or out of the battery, b) predict a terminal voltage of the battery using the current and an estimated state of charge of the battery, c) measure an actual terminal voltage of the battery using the voltage sensor, d) compare the predicted terminal voltage with the actual terminal voltage and e) update the estimated state of charge of the battery based on said comparison. The battery-powered device is arranged to repeat steps (a)-(e) at one or more subsequent times, said one or more subsequent times being determined based on an operating state of the battery-powered device.
A boost converter circuit is disclosed comprising an input arranged to receive an input voltage from a battery; an output arranged to generate a higher, output voltage for powering a further circuit portion; and a switching arrangement arranged to control generation of the output voltage. The boost converter circuit compares the input voltage with a first reference input voltage and controls the switching arrangement to limit the output current of the boost converter circuit based on the comparison of the input voltage and the first reference input voltage. The boost converter circuit monitors a parameter indicative of a condition of the battery, determines a second, lower reference input voltage in response to the monitored parameter, compares the input voltage with the second reference input voltage and controls the switching arrangement to limit the output current of the boost converter circuit based on the comparison of the input voltage and the second reference input voltage.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
A radio transmitter is configured to operate in accordance with a first predetermined OFDM radio protocol. The transmitter reserves, within a timeslot with a predetermined timeslot duration, a reserved set of time-frequency resource units not available for an OFDM data channel defined by the first protocol. The transmitter allocates, within the timeslot, an allocated set of R time-frequency resource units for the OFDM data channel defined by the first protocol, wherein a number M of time-frequency resource units are included in both the allocated set and the reserved set, wherein the value R is such that R>N and R−M≤N, where N is a predetermined maximum number of time-frequency resource units that can be used to carry the data channel. The transmitter then transmits data indicative of the allocated set of R time-frequency resource units and data indicative of the reserved set of time-frequency resource units.
A digital radio transmitter device operates in accordance with a predetermined communication protocol that defines a default inter-frame spacing. The device has a minimum inter-frame spacing that is shorter than said default inter-frame spacing. The device is configured to: transmit a first data packet indicating that the device is able to support an inter-frame spacing shorter than said default inter-frame spacing; receive a second data packet from a peer device after said default inter-frame spacing; if said second data packet indicates that said peer device is able to support an inter-frame spacing shorter than said default inter-frame spacing, transmit a third data packet using an inter-frame spacing shorter than said default inter-frame spacing; and if said second data packet does not indicate that said peer device is able to support an inter-frame spacing shorter than said default inter-frame spacing, transmit said third packet using said default inter-frame spacing.
A receiver device is provided which is arranged to receive a data packet from a transmitter device comprising a control portion and a payload portion, said control portion comprising a feedback request indicator. The receiver device is arranged to detect the feedback request indicator, to attempt to decode the payload portion of the data packet, to transmit an acknowledgement to the transmitter device if said feedback request indicator indicates that an acknowledgement is requested for said data packet, and to process said data packet without transmitting an acknowledgement if said feedback request indicator indicates that an acknowledgement is not requested for said data packet.
An integrated-circuit chip and method of operating said chip is provided. The integrated-circuit chip includes multiple processors, a system memory and a main system bus for carrying data between each of the processors and the system memory. The chip also has debug logic, a debug port for communicating with the debug logic from outside the chip and a debug connection that connects the debug logic to the main system bus. A power management system is also included for controlling the power supplied to each of a number of power domains on the chip. The debug logic and each of the processors are in different respective power domains. The debug logic is configured to send a debug instruction to any of the processors. The debug instruction is communicated over the debug connection and over the main system bus.
A receiver device comprises receiving circuitry configured to receive a radio signal modulated using frequency shift keying or phase shift keying, the radio signal comprising a plurality of successive symbol intervals, differential detector circuitry configured to multiply a signal for a current symbol interval with a first reference signal and output a first output signal for the current symbol interval, wherein the first reference signal corresponds to a conjugate of a signal for a first symbol interval preceding the current symbol interval and multiply the signal for the current symbol interval with a second reference signal and output a second output signal for the current symbol interval, wherein the second reference signal corresponds to a conjugate of a signal for a second symbol interval preceding the first symbol interval, in which the conjugate of the signal for the second symbol interval has been phase adjusted in dependence on a previous phase decision for the first symbol interval preceding the current symbol interval, combining circuitry configured to combine the first output signal for the current symbol interval and the second output signal for the current symbol interval to obtain a combined signal for the current symbol interval, and decision circuitry configured to output a phase decision for the current symbol interval in dependence upon the combined signal.
An amplitude regulator circuit portion is arranged to supply a current to an inverter in an oscillator circuit. The regulator monitors a voltage at the input terminal of the inverter and varies the current supplied to the inverter in response to the monitored voltage. The amplitude regulator comprises first, second, and third PMOS transistors, and first and second NMOS transistors and is arranged such that an input node is connected to the input terminal of the inverter, a respective gate terminal of each of the first and second NMOS transistors, and a respective drain terminal of the first NMOS and first PMOS transistors. The amplitude regulator also comprises a back-bias circuit portions arranged to vary a back-bias voltage at a back-gate terminal of the second NMOS transistor, to vary a threshold voltage, where the threshold voltage of the second NMOS transistor is lower than that of the first NMOS transistor.
H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
G05F 3/24 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations wherein the transistors are of the field-effect type only
According to an aspect, there is provided a first radio device for performing the following. The first radio device causes wireless transmission of one or more first advertising messages at one or more advertising radio frequencies using a connectionless mode of the first radio device. The radio device receives, for at least one first advertising message, a first scan request from a second radio device and transmits, for each first scan request, a first scan response to the second radio device. Based on one or more received first scan requests, the first radio device performs bi-directional channel sounding with the second radio device at one or more sounding radio frequencies. The first radio device receives, from the second radio device, at least one first message comprising information on second channel sounding measurements and transmits. to the second radio device, at least one second message comprising information on first channel sounding measurements performed by the first radio device.
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
An integrated circuit device includes an n-bit register comprising: a plurality of latches and at least one flip-flop, and clock gating circuitry, which includes a clock signal coupled to the latches and the flip-flop. Each latch comprises a latch gating terminal configured to receive a gating signal, wherein a respective latch is configured to receive the gating signal that either corresponds to the clock signal or is determined according to a logical operation including the clock signal such that a transparency for each respective latch is controlled in dependence upon a level of the gating signal. The integrated circuit device is configured to operate in a scan test mode, wherein during a scan shift operation, an input signal terminal of the flip-flop is configured to receive a test input signal and the flip-flop is configured to load the test input signal to an output signal terminal of the flip-flop.
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
