Mediatek Inc.

Taiwan, Province of China

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H04L 5/00 - Arrangements affording multiple use of the transmission path 320
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1.

CANDIDATE REORDERING AND MOTION VECTOR REFINEMENT FOR GEOMETRIC PARTITIONING MODE

      
Application Number 18684236
Status Pending
Filing Date 2022-08-15
First Publication Date 2025-05-08
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chiu, Chih-Yao
  • Lo, Chih-Hsuan
  • Chen, Chun-Chia
  • Hsu, Chih-Wei
  • Chen, Ching-Yeh
  • Chuang, Tzu-Der

Abstract

A method that reorders partitioning candidates or motion vectors based on template matching costs for geometric prediction mode (GPM) is provided. A video coder receives data to be encoded or decoded as a current block of a current picture of a video. The current block is partitioned into first and second partitions by a bisecting line defined by an angle-distance pair. The video coder identifies a list of candidate prediction modes for coding the first and second partitions. The video coder computes a template matching (TM) cost for each candidate prediction mode in the list. The video coder receives or signals a selection of a candidate prediction mode based on an index that is assigned to the selected candidate prediction mode based on the computed TM costs. The video coder reconstructs the current block by using the selected candidate prediction mode to predict the first and second partitions.

IPC Classes  ?

  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries
  • H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
  • H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability
  • H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
  • H04N 19/513 - Processing of motion vectors

2.

Adaptive Minimum Voltage Aging Margin Prediction Method and Adaptive Minimum Voltage Aging Margin Prediction System Capable of Providing Satisfactory Prediction Accuracy

      
Application Number 18915358
Status Pending
Filing Date 2024-10-15
First Publication Date 2025-05-08
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Yang, Yu-Lin
  • Tsao, Po-Chao
  • Chen, Hsiang-An
  • Lin, Chin-Wei
  • Lee, Ming-Cheng
  • Lee, Tung-Hsing

Abstract

An adaptive minimum voltage aging margin prediction method includes acquiring characteristic data of a plurality of dies in a testing line, predicting a wear-out failure rate of each module of the plurality of dies according to the characteristic data by using a neural network, and predicting a minimum voltage aging margin of the each module according to the wear-out failure rate of the each module by using the neural network.

IPC Classes  ?

3.

BATTERY RESISTANCE MEASURING METHOD, BATTERY POWER MANAGING METHOD AND ELECTRONIC DEVICE USING THE METHOD

      
Application Number 18504120
Status Pending
Filing Date 2023-11-07
First Publication Date 2025-05-08
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chuang, Jia-You
  • Wu, Jui-Chi
  • Chen, Kuan-Yu

Abstract

A battery resistance measuring method, applied to a battery with a battery resistance, comprising: (a) acquiring charge variation of the battery for a measuring time interval; (b) acquiring a voltage difference between a first battery voltage and a second battery voltage for the measuring time interval, wherein the first battery voltage is a battery voltage with loading and the second battery voltage is a battery voltage without loading; and (c) computing a battery resistance according to the charge variation and the voltage difference, and updating the battery resistance to a battery resistance table of the battery. The above-mentioned steps (a), (b) and (c) may be performed by the electronic device, which can be a mobile electronic device such as a mobile phone or a plate computer.

IPC Classes  ?

  • G01R 31/3842 - Arrangements for monitoring battery or accumulator variables, e.g. SoC combining voltage and current measurements
  • G01R 31/367 - Software therefor, e.g. for battery testing using modelling or look-up tables
  • G01R 31/388 - Determining ampere-hour charge capacity or SoC involving voltage measurements
  • G01R 31/396 - Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery

4.

MOTION DETECTION METHOD AND ELECTRONIC DEVICE APPLYING THE SAME

      
Application Number 18941225
Status Pending
Filing Date 2024-11-08
First Publication Date 2025-05-08
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Tsai, Tsung-Han
  • Liu, Hsuan-Yu
  • Chen, Jun-Shen
  • Wang, Ting-Hsiang
  • Liu, I-Ying

Abstract

The application discloses a motion detection method and an electronic device applying the same. A plurality of transmission packets are transmitted and a plurality of received packets are received. A received packet among the plurality of received packets is compensated into a compensated received packet. Cross packet cancellation is performed on the compensated received packet. A packet difference between the compensated received packet and another received packet among the plurality of received packets is determined. Whether an object is detected based on the packet difference is determined.

IPC Classes  ?

  • G01S 13/62 - Sense-of-movement determination
  • G01S 13/04 - Systems determining presence of a target

5.

LOGIC CELL WITH SMALL CELL DELAY

      
Application Number 19009302
Status Pending
Filing Date 2025-01-03
First Publication Date 2025-05-08
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Dia, Kin-Hooi
  • Hsieh, Ho-Chieh

Abstract

A semiconductor structure is provided. A logic cell with a logic function includes P-type and N-type transistors in first and second active regions over a semiconductor substrate, first and a second isolation structures on opposite edges of the first and second active regions, first and third transistors in the first and second active regions and between the first isolation structure and the P-type transistors, second and fourth transistors in the first and second active region and between the second isolation structure and the P-type transistors. Each of the N-type transistors and a respective P-type transistor shares a first gate electrode along the first direction. The first and third transistors share a second gate electrode extending along the first direction. The second and fourth transistors share a third gate electrode extending along the first direction. The P-type transistors and the N-type transistors are configured to perform the logic function.

IPC Classes  ?

6.

CANDIDATE REORDERING FOR MERGE MODE WITH MOTION VECTOR DIFFERENCE

      
Application Number 18684245
Status Pending
Filing Date 2022-08-15
First Publication Date 2025-05-08
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chiu, Chih-Yao
  • Chen, Chun-Chia
  • Hsu, Chih-Wei
  • Chen, Ching-Yeh
  • Chuang, Tzu-Der
  • Huang, Yu-Wen

Abstract

A video coding system that reorders prediction candidates is provided. A video coder receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video coder identifies possible candidate prediction positions. The video coder computes a cost for each of the identified possible candidate prediction positions. The video coder assigns, based on the computed costs, a reordered index to each of N lowest cost candidate prediction positions from the identified possible candidate prediction positions. The video coder selects a candidate prediction position using the assigned reordered indices, wherein the selection is signaled in or parsed from the bitstream. The video coder encodes or decodes the current block by using the selected candidate prediction position.

IPC Classes  ?

  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries
  • H04N 19/513 - Processing of motion vectors

7.

Method for Link Transition in Universal Serial Bus and System Thereof

      
Application Number 18501050
Status Pending
Filing Date 2023-11-03
First Publication Date 2025-05-08
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chen, Yu-Cheng
  • Wang, Chih-Chieh

Abstract

A method for link transitions in a Universal Serial Bus system includes transmitting a plurality of first RS-FEC blocks by a first transmitter of the USB system, transmitting a training sequence by a second transmitter of the USB system, determining number of sets in a first RS-FEC block which have been transmitted by the first transmitter when the second transmitter completes transmitting the training sequence, generating a specific pattern sequence according to the number of sets in the first RS-FEC block which have been transmitted by the first transmitter and a total number of sets in the first RS-FEC block, and transmitting the specific pattern sequence by the second transmitter.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received

8.

Method for Link Transition in Universal Serial Bus and System Thereof

      
Application Number 18501053
Status Pending
Filing Date 2023-11-03
First Publication Date 2025-05-08
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chen, Yu-Cheng
  • Wang, Chih-Chieh

Abstract

A method for link transition in a USB device includes transmitting a plurality of first RS-FEC blocks by a first transmitter, receiving an UNBOND set by a receiver, waking up a second transmitter by a LASM when the receiver receives the UNBOND set, transmitting a training sequence by the second transmitter, transmitting a specific pattern sequence by the second transmitter after finishing transmitting the training sequence, determining whether a current RS-FEC block to be transmitted by the first transmitter is a DESKEW block, stopping transmitting the specific pattern sequence if the current RS-FEC block is determined to be the DESKEW block, and transmitting a plurality of second RS-FEC blocks by the first transmitter and the second transmitter.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received

9.

METHOD AND DEVICE FOR ENHANCING ROAMING PERFORMANCE

      
Application Number 18938547
Status Pending
Filing Date 2024-11-06
First Publication Date 2025-05-08
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Wu, Chun-Ting
  • Chang, Yu-Shu
  • Lin, Ray-Kuo

Abstract

A method for enhancing roaming performance is provided. The method is implemented by a station MLD and comprises: communicating with a current AP through at least two links, wherein the at least two links comprise a first link and a second link; disabling the second link connected to the current AP; establishing an association with a target AP through a new second link; transmitting a message to the target AP through the new second link to notify a network node that the STA is camping on a cell served by the target AP and to disable the new second link connected to the target AP; retrieving buffered packets from the current AP through the first link for a time duration; disconnecting from the current AP after the time duration; and enabling the new first link and the new second link to retrieve packets from the target AP.

IPC Classes  ?

  • H04W 36/18 - Performing reselection for specific purposes for allowing seamless reselection, e.g. soft reselection
  • H04W 36/02 - Buffering or recovering information during reselection
  • H04W 36/36 - Reselection control by user or terminal equipment
  • H04W 52/02 - Power saving arrangements
  • H04W 84/12 - WLAN [Wireless Local Area Networks]

10.

METHOD OF PERFORMING CODE REVIEW AND RELATED SYSTEM

      
Application Number 18935662
Status Pending
Filing Date 2024-11-04
First Publication Date 2025-05-08
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Huang, Min-Shan
  • Kuo, Hui-Chi
  • Fan, Wei-Geng
  • Lai, Chin-Tang
  • Lu, Chiang-Lin
  • Yeh, Chia-Shun

Abstract

A method of performing code review and a code review system are provided. The code review system includes a code repository, a static scanning tool, an analytical neural network and a generative neural network. The code repository is configured to store an original source code and a new code created by a developer in response to a code change request to merge the new code with the original source code. The static scanning tool is configured to collect data associated with each commit in the new code. The analytical neural network is implemented with an analytical AI and configured to assess a risk level of each commit in the new code. The generative neural network is implemented with a generative AI and configured to provide a code summarization and an initial code review comment of each commit in the new code.

IPC Classes  ?

11.

WIRELESS LOCAL AREA NETWORK SYSTEM USING FREQUENCY HOPPING FOR CO-CHANNEL INTERFERENCE AVOIDANCE

      
Application Number 18936992
Status Pending
Filing Date 2024-11-04
First Publication Date 2025-05-08
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chen, Kuo-Wei
  • Fang, Pochun
  • Lu, Kai Ying

Abstract

A wireless local area network (WLAN) system includes a first Wi-Fi device and at least one second Wi-Fi device. When the first Wi-Fi device and the at least one second Wi-Fi device receive an interference signal that occupies a current operation channel of the first Wi-Fi device and a current operation channel of the at least one second Wi-Fi device, the first Wi-Fi device performs channel switching upon the current operation channel of the first Wi-Fi device, and the at least one second Wi-Fi device performs channel switching upon the current operation channel of the at least one second Wi-Fi device.

IPC Classes  ?

  • H04W 72/541 - Allocation or scheduling criteria for wireless resources based on quality criteria using the level of interference
  • H04W 84/12 - WLAN [Wireless Local Area Networks]

12.

SIGNAL AND PROCEDURE DESIGNS OF BACKSCATTERING DEVICES FOR A-IOT

      
Application Number 18929876
Status Pending
Filing Date 2024-10-29
First Publication Date 2025-05-08
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Cheng, Chien-Chun
  • Chuang, Chiao-Yao
  • Wu, Wei-De
  • Tsai, Chiou-Wei
  • Tsai, Tai-Cheng

Abstract

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a reader. The reader broadcasts a radio signal indicating an available slot set. The reader transmits an acknowledge (ACK) signal including a decoded sequence to an ambient internet of things (A-IoT) device. The reader receives an identifier from the A-IoT device. The identifier is a reply of the A-IoT device when there is a match between the decoded sequence and a chosen sequence, and the chosen sequence is a random sequence that responds to the radio signal in a random slot chosen from the available slot set.

IPC Classes  ?

  • H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/0446 - Resources in time domain, e.g. slots or frames

13.

Method for Handling Calls with Sessions Initiation Protocol

      
Application Number 18503195
Status Pending
Filing Date 2023-11-07
First Publication Date 2025-05-08
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Lai, Ying-Cen
  • Wang, Chien-Yi
  • Yang, Nuan-Yu

Abstract

A method for handling a call using Sessions Initiation Protocol (SIP) includes sending an INVITE or a first media type by a network side to user equipment, sending an UPDATE of a second media type by the user equipment to the network side, receiving an SIP global failure response for the UPDATE by the user equipment from the network side, sending an SIP success response for the INVITE of the first media type by the user equipment to the network side, receiving an ACK of the first media type by the user equipment from the network side, and establishing a call session of the first media type between the user equipment and the network side.

IPC Classes  ?

14.

SYSTEM AND METHOD FOR UTILIZING TRANSFORMER DEEP LEARNING BASED OUTLIER IC DETECTION

      
Application Number 18926397
Status Pending
Filing Date 2024-10-25
First Publication Date 2025-05-08
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Koh, Khim Jun
  • Lee, Chi-Ming
  • Ting, Yi-Ju
  • Chang, Chung-Kai
  • Tsao, Po-Chao
  • Lin, Chin-Wei
  • Yang, Yu-Lin
  • Lee, Tung-Hsing
  • Lai, Chin-Tang

Abstract

In an aspect of the disclosure, a method for detecting outlier integrated circuits on a wafer is provided. The method comprises: operating multiple test items for each IC on the wafer to generate measured values of the multiple test items for each IC; selecting a target IC and neighboring ICs on the wafer repeatedly. each time after selecting the target IC executes the following steps: selecting a measured value of the target IC as a target measured value and selecting measured values of the target IC and the neighboring ICs as feature values of the target IC and the neighboring ICs; executing a transformer deep learning model to generate a predicted value of the target measured value; and identifying outlier ICs according to the predicted values of all the target ICs and the corresponding target measured values of all the target ICs.

IPC Classes  ?

15.

BUFFER CIRCUITS AND SEMICONDUCTOR STRUCTURES THEREOF

      
Application Number 19009332
Status Pending
Filing Date 2025-01-03
First Publication Date 2025-05-01
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Yu, Hao-Hsiang
  • Yang, Jen-Hang

Abstract

A buffer circuit is provided to output an output signal at an output node. The buffer circuit includes first and second inverters and first and second switches. The first inverter inverts an input signal. The second inverter is coupled between the first inverter and the output node. The first switch is coupled between a first voltage source terminal and the output node. The second switch is coupled between the output node and a second voltage source terminal. First and second voltages are respectively provided to the first and second voltage source terminals. In response to the input signal switching to a first level from a second level, the first switch is turned on to pre-charge the output node. In response to the input signal transiting to the second level from the first level, the second switch is turned on to pre-discharge the output node.

IPC Classes  ?

  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H03K 19/01 - Modifications for accelerating switching
  • H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
  • H10D 84/85 - Complementary IGFETs, e.g. CMOS

16.

METHOD AND APPARATUS FOR INCREASING SYSTEM CAPACITY OF DEMODULATION REFERENCE SIGNALS

      
Application Number 18835817
Status Pending
Filing Date 2023-04-12
First Publication Date 2025-05-01
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Shabara, Yahia Ahmed Mahmoud Mahmoud
  • Cheraghi, Parisa

Abstract

This disclosure provides an apparatus and a method for wireless communication. Processing circuitry of the apparatus determines one or more antenna ports of the apparatus for data transmission. The processing circuitry generates, for each of the one or more antenna ports, a respective demodulation reference signal (DMRS) based on one of a first DMRS pattern, a second DMRS pattern, a third DMRS pattern, and a fourth DMRS pattern. The one or more antenna ports transmit the one or more DMRSs. The first DMRS pattern includes four code division multiplexing (CDM) groups each comprising a length-2 orthogonal cover code (OCC), the second DMRS pattern includes six CDM groups each comprising a length-2 OCC, the third DMRS pattern includes three CDM groups each comprising a length-4 OCC, and the fourth DMRS pattern includes two CDM groups each comprising a length-6 OCC.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path

17.

METHOD AND APPARATUS FOR MEASUREMENT GAP CONFIGURATION WITH ADAPTIVE CONFIGURATION

      
Application Number 18836045
Status Pending
Filing Date 2023-04-11
First Publication Date 2025-05-01
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Hsieh, Chi-Hsuan
  • Li, Cheng-Hsun
  • Lo, Yi-Chia
  • Hsu, Chia-Chun

Abstract

Various solutions for measurement gap configuration with adaptive configuration with respect to user equipment and network node in mobile communications are described. A network node may determine a traffic type. The network node may determine a measurement gap repetition period or a measurement gap length for the traffic type according to at least one condition. The network node may transmit a measurement gap configuration with the measurement gap repetition period or with the measurement gap length to a user equipment (UE).

IPC Classes  ?

  • H04W 24/10 - Scheduling measurement reports
  • H04W 76/28 - Discontinuous transmission [DTX]Discontinuous reception [DRX]

18.

BACKSCATTERING AND UE FINDER-BASED POSITIONING FOR A-IOT

      
Application Number 18919716
Status Pending
Filing Date 2024-10-18
First Publication Date 2025-05-01
Owner Mediatek Inc. (Taiwan, Province of China)
Inventor
  • Cheng, Chien-Chun
  • Chuang, Chiao-Yao
  • Wu, Wei-De
  • Tsai, Chiou-Wei
  • Tsai, Tai-Cheng

Abstract

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a reader. The reader receives a response signal set that responds to a radio signal, from an ambient internet of things (A-IoT) device set, a response signal in the response signal set being modulated by a corresponding A-IoT device in the A-IoT device set to include an identification of the corresponding A-IoT device. The reader identifies the corresponding A-IoT device based on the identification of the corresponding A-IoT device, and performs measurement for a positioning parameter. The reader executes a positioning related operation based on the identified A-IoT device and the measurement for the positioning parameter.

IPC Classes  ?

  • H04W 64/00 - Locating users or terminals for network management purposes, e.g. mobility management
  • H04B 17/318 - Received signal strength
  • H04L 43/0864 - Round trip delays
  • H04W 24/10 - Scheduling measurement reports

19.

IMAGE PROCESSING FREQUENCY MANAGING METHOD AND IMAGE PROCESSING SYSTEM

      
Application Number 18925002
Status Pending
Filing Date 2024-10-23
First Publication Date 2025-05-01
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Tsai, Min-Han
  • Chou, Kuan-Hung
  • Chen, Chieh-Ling

Abstract

An electronic device comprising an image processing device, comprising: (a) monitoring a reception speed of image data, which is received by the electronic device; and (b) adjusting an image processing frequency of the image processing device according to the reception speed. The step (a) may monitor a queuing speed of an input buffer receiving an image data stream to acquire the reception speed.

IPC Classes  ?

  • H04N 19/152 - Data rate or code amount at the encoder output by measuring the fullness of the transmission buffer

20.

ELECTRONIC DEVICE AND METHOD FOR MANAGING TOUCH LATENCY

      
Application Number 18926645
Status Pending
Filing Date 2024-10-25
First Publication Date 2025-05-01
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Shen, Yi-Hsin
  • Lin, Nien-Hsien
  • Chien, Yen-Po
  • Shih, Yen-An
  • Lin, Chiu-Jen
  • Chen, Cheng-Che

Abstract

An electronic device including a display panel and a CPU is provided. The display panel updates displayed images at a refresh rate. The CPU implements a latency monitor, a system resource controller, a display controller, and an application. The latency monitor collects time information related to touch latency. The touch latency is the duration between the time point at which the display panel detects a touch event and the time point at which the display panel displays an image generated by the application in response to said touch event. The display controller informs the system resource controller of the refresh rate. The system resource controller adjusts the resource allocation of the electronic device to cause the touch latency to be lower than a threshold, according to the time information and the refresh rate.

IPC Classes  ?

  • G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
  • G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix

21.

Distributed-Tone Resource Unit Optimization To Improve Sepctrum Mask In Wireless Communications

      
Application Number 18928148
Status Pending
Filing Date 2024-10-27
First Publication Date 2025-05-01
Owner MediaTek Inc. (Taiwan, Province of China)
Inventor
  • Hu, Shengquan
  • Liu, Jianhan
  • Pare, Jr., Thomas Edward

Abstract

Techniques pertaining to distributed-tone resource unit (DRU) optimization to improve spectrum mask in wireless communications are described. An apparatus (e.g., a station (STA)) generates a DRU according to a tone plan. The apparatus also applies a first shift and a second shift to tones of the DRU in a first half of the tone plan and tones of the DRU in a second half of the tone plan, respectively. The apparatus then performs a wireless communication with the DRU.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path

22.

COMPUTING SYSTEM AND DATA TRANSPORT SYSTEM

      
Application Number 18383481
Status Pending
Filing Date 2023-10-25
First Publication Date 2025-05-01
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor Hsieh, Tsai-Chun

Abstract

A computing system comprising: routers, configured to transport data to nodes; transport stations, configured to transport the data to the nodes through the routers; first paths, provided between adjacent ones of the routers; second paths, provided between adjacent ones of the transport stations. The computing system operates in a first mode, which transmits the data from a first target device to a second target device via the first paths and the second paths.

IPC Classes  ?

  • H04L 49/109 - Integrated on microchip, e.g. switch-on-chip
  • H04L 49/101 - Packet switching elements characterised by the switching fabric construction using crossbar or matrix
  • H04L 49/112 - Switch control, e.g. arbitration

23.

Method of Synchronization for Universal Serial Bus and System Thereof

      
Application Number 18381175
Status Pending
Filing Date 2023-10-18
First Publication Date 2025-04-24
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Wang, Chih-Chieh
  • Wang, Tse-Wei
  • Chen, Yu-Cheng

Abstract

A method of synchronization in a training state of Universal Serial Bus (USB) includes sending SLOS1 ordered sets by a transmitter in a LOCK1 state, receiving the SLOS1 ordered sets by a receiver in the LOCK1 state, stopping the transmitter from sending training ordered sets according to a lane adapter state machine (LASM) if the transmitter sends the training ordered sets in the LOCK1 state continuously in an infinite loop. The training ordered sets include the SLOS1 ordered sets. The method further includes sending new SLOS1 ordered sets by the transmitter, receiving the new SLOS1 ordered sets by a receiver, and the transmitter and the receiver entering a LOCK2 state. The length of the new SLOS1 ordered sets is different from the length of the SLOS1 ordered sets.

IPC Classes  ?

24.

ACCESS POINT (AP) AND METHOD TO ACHIEVE SECURITY OF COORDINATED BEAMFORMING

      
Application Number 18917396
Status Pending
Filing Date 2024-10-16
First Publication Date 2025-04-24
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Hsu, Chien-Fang
  • Kang, Hao-Hua
  • Kuo, Chih-Chun

Abstract

A first access point (AP) in a multiple access points (MAP) system of a wireless network is provided. The MAP system further includes a second AP. The first AP includes a transceiver and a control circuit. The transceiver transmits and receives frames over the wireless network. The control circuit transmits a protected frame to a non-AP station associated to the second AP, and receives a response frame in response to the protected frame from the non-AP station.

IPC Classes  ?

  • H04W 12/04 - Key management, e.g. using generic bootstrapping architecture [GBA]

25.

WIRELESS COMMUNICATION DEVICE AND METHOD

      
Application Number 18918296
Status Pending
Filing Date 2024-10-17
First Publication Date 2025-04-24
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor Peng, Yang-Hung

Abstract

A multi-link operation wireless communication method and device are disclosed. A first synchronization information from the first wireless communication control circuit is received by the second wireless communication control circuit. The first synchronization information includes a first updated status of a first packet queue and an end time of a first transmission packet transmitted by the first wireless communication control circuit over a first link. The second wireless communication control circuit generates a synchronization collision period based on the end time of the first transmission packet. The second wireless communication control circuit aggregates data packets into a second transmission packet transmitted over a second link. The second wireless communication control circuit adjusts an end time of the second transmission packet as either before a start of the synchronization collision period or after an end of the synchronization collision period.

IPC Classes  ?

  • H04W 74/0816 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA] with collision avoidance
  • H04W 8/22 - Processing or transfer of terminal data, e.g. status or physical capabilities
  • H04W 74/08 - Non-scheduled access, e.g. ALOHA

26.

DATA PROCESSING METHOD AND DATA PROCESSING DEVICE

      
Application Number 18922944
Status Pending
Filing Date 2024-10-22
First Publication Date 2025-04-24
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chang, Chi-Peng
  • Ho, Cheng-Jung

Abstract

An embodiment of the disclosure provides a data processing method, which includes the following steps. A sync event is received by a first processor from a first driver. The first processor is woken up from a power saving mode after receiving the sync event. First data for a first function is decoded by the first processor. The decoded first data is transferred by the first processor to a first buffer. The power saving mode is entered by the first processor after transferring the decoded first data to the first buffer. The sync event is used to indicate that a second processor needs to wake up to process second data for a second function.

IPC Classes  ?

27.

APPARATUS FOR TESTING INTEGRATED CIRCUITS

      
Application Number 18906148
Status Pending
Filing Date 2024-10-03
First Publication Date 2025-04-24
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Zhuang, Jing-Hui
  • Shih, Ying-Chou
  • Wei, Chang-Lin
  • Lei, Sheng-Wei
  • Liu, Chih-Yang
  • Chiu, Jhih-Huei
  • Li, Yen-Hui
  • Lin, Che-Sheng

Abstract

A probe head includes an upper pin holder and a lower pin holder coupled to the upper pin holder. A pin arrangement space is defined between the upper pin holder and the lower pin holder. A conductive film is disposed between the upper pin holder and the lower pin holder. A plurality of probe pins penetrates through the upper pin holder, the conductor film and the lower pin holder, and extends outwardly from a bottom surface of the lower pin holder.

IPC Classes  ?

28.

METHOD AND APPARATUS FOR IMPROVING SERVICE CONTINUITY

      
Application Number 18909020
Status Pending
Filing Date 2024-10-08
First Publication Date 2025-04-24
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Pan, Shang-Heh
  • Lee, Tsung-Ming
  • Lu, Tsung-Liang

Abstract

A method for improving service continuity is provided. The method is implemented by a reduced capability (RedCap) user equipment (UE) and includes generating a not-allowed cell list of new radio (NR) standalone (SA) cells. The method includes avoiding performing a mobility decision on the NR SA cells recorded in the not-allowed cell list during a mobility procedure or a measurement reporting procedure.

IPC Classes  ?

  • H04W 36/00 - Handoff or reselecting arrangements
  • H04L 27/26 - Systems using multi-frequency codes
  • H04W 36/36 - Reselection control by user or terminal equipment

29.

COMPUTING SYSTEM AND METHOD FOR POWER-SAVING COMPUTE-IN-MEMORY DESIGN

      
Application Number 18917369
Status Pending
Filing Date 2024-10-16
First Publication Date 2025-04-24
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor Wang, Tso

Abstract

A computing system with power-saving compute-in-memory (CIM) design that minimizes the computation energy of the matrix-matrix multiplication is shown. A processor control unit loads A blocks divided from a matrix AM×K from a second-level (L2) memory to a first-level (L1) memory, and loads B blocks divided from a matrix BK×N from the L2 memory to a CIM memory. The A blocks buffered in the L1 memory are programmed to a register file to be entered into the CIM memory. The CIM memory performs multiply-and-accumulate (MAC) calculations on the A blocks and the B blocks to generate C blocks which form a matrix CM×N(=AM×K×BK×N). Based on the size of AM×K and BK×N, an A block buffering capability of the L1 memory, and a B block buffering capability of the CIM memory, the reuse scheme is properly selected to reuse the buffered A blocks and B blocks.

IPC Classes  ?

  • G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels

30.

VOICE CALL MANAGEMENT METHOD AND APPARATUS THEREOF

      
Application Number 18910553
Status Pending
Filing Date 2024-10-09
First Publication Date 2025-04-17
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Wang, Hao-Cheng
  • Lin, Kuan-Ming
  • Yang, Nuan-Yu
  • Wang, Chien-Yi

Abstract

A voice call management method is provided. The voice call management method may be applied to an apparatus. The voice call management method may include the following steps. The apparatus may determine the current scenario associated with the operation environment of the apparatus. Then, the apparatus may determine to perform a voice call through a modem (MD) voice engine or through an application processor (AP) voice engine according to the current scenario.

IPC Classes  ?

  • H04M 7/00 - Arrangements for interconnection between switching centres

31.

METHOD AND ELECTRONIC DEVICE FOR HANDLING DISPLAY CONTROL

      
Application Number 18814575
Status Pending
Filing Date 2024-08-25
First Publication Date 2025-04-17
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chen, Tsung-Hsin
  • Liang, Chin-Wen
  • Lin, Wei-Chen
  • Lin, Tung-Hung
  • Huang, Shih-Yu
  • Yu, Chen-Wei

Abstract

A method for handling a display control of a microprocessor in an electronic device includes: receiving a display trigger signal; and controlling a panel device in the electronic device to display a content, in response to the display trigger signal; wherein a central processing unit (CPU) in the electronic device is in a power off state, when controlling the panel device to display the content.

IPC Classes  ?

  • G06F 3/147 - Digital output to display device using display panels
  • G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source

32.

PROCEDURES AND SIGNAL DESIGN FOR NTN NB-IOT WUR

      
Application Number 18903156
Status Pending
Filing Date 2024-10-01
First Publication Date 2025-04-17
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Cheng, Chien-Chun
  • Wu, Wei-De
  • Liao, Yi-Ju
  • Chen, Chun-Chia

Abstract

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE receiving a unified waveform signal from a base station, wherein the unified waveform signal comprises an On-Off Keying (OOK) signal and an Orthogonal Frequency Division Multiplexing (OFDM) signal; determining whether an indicator in the OFDM signal indicates that the unified waveform signal is a low-power wake-up signal (LP-WUS); decoding the LP-WUS when the indicator indicates that the unified waveform signal is the LP-WUS; and terminating a decoding operation when the indicator indicates that the unified waveform signal is not the LP-WUS.

IPC Classes  ?

  • H04L 27/26 - Systems using multi-frequency codes
  • H04L 27/32 - Carrier systems characterised by combinations of two or more of the types covered by groups , , , or
  • H04W 52/02 - Power saving arrangements

33.

IN-LOOP NEURAL NETWORKS FOR VIDEO CODING

      
Application Number 18727505
Status Pending
Filing Date 2023-01-12
First Publication Date 2025-04-17
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Klopp, Jan
  • Chen, Ching-Yeh
  • Chuang, Tzu-Der
  • Huang, Yu-Wen

Abstract

A method for video decoding includes receiving a video frame reconstructed based on data received from a bitstream. The method further includes extracting, from the bitstream, a first syntax element indicating whether a spatial partition for partitioning the video frame is active. The method also includes, responsive to the first syntax element indicating that the spatial partition for partitioning the video frame is active, determining a configuration of the spatial partition for partitioning the video frame, determining a plurality of parameter sets of a neural network, and applying the neural network to the video frame. The video frame is spatially divided based on the determined configuration of the spatial partition for partitioning the video frame into a plurality of portions, and the neural network is applied to the plurality of portions in accordance with the determined plurality of parameter sets.

IPC Classes  ?

  • G06T 9/00 - Image coding
  • H04N 19/117 - Filters, e.g. for pre-processing or post-processing
  • H04N 19/184 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being bits, e.g. of the compressed video stream

34.

TRANSMISSION CHANNEL SWITCHING METHOD AND APPARATUS THEREOF

      
Application Number 18893200
Status Pending
Filing Date 2024-09-23
First Publication Date 2025-04-10
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chen, Wei-Shuo
  • Wu, Kun-Lin
  • Shih, Pang-Hsin
  • Wen, Yuan-Chin
  • Lin, Te-Hsin
  • Chen, Cheng-Che

Abstract

A transmission channel switching method is provided. The transmission channel switching method may include the following steps. An apparatus may establish a plurality of transmission channels. The apparatus may transmit data through a default transmission channel of the transmission channels, wherein the default transmission channel corresponds to the lowest power consumption. The apparatus may determine whether to switch to another transmission channel of the transmission channels according to channel quality of each transmission channel and power consumption corresponds to each transmission channel.

IPC Classes  ?

  • H04W 40/12 - Communication route or path selection, e.g. power-based or shortest path routing based on transmission quality or channel quality
  • H04W 40/10 - Communication route or path selection, e.g. power-based or shortest path routing based on wireless node resources based on available power or energy
  • H04W 84/12 - WLAN [Wireless Local Area Networks]

35.

METHOD FOR DYNAMICALLY ALLOCATING RADIO FREQUENCY EXPOSURE AMONG MULTIPLE RADIO FREQUENCY GROUPS AND ASSOCIATED CONTROL CIRCUIT

      
Application Number 18882706
Status Pending
Filing Date 2024-09-11
First Publication Date 2025-04-10
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Kao, Fu-Tse
  • Lin, Yi-Hsuan
  • Yu, Tsung-Po

Abstract

A method for dynamically allocating radio frequency (RF) exposure across multiple RF groups including a first RF group and a second RF group includes: estimating RF exposure of the first RF group according to at least one message of the first RF group, in order to generate estimated RF exposure; calculating RF exposure of the second RF group according to at least one message of the second RF group, the estimated RF exposure, and one or more equations, in order to generate calculated RF exposure, wherein the one or more equations are associated with a predetermined regulation; and determining a TX power limit corresponding to the first RF group and a TX power limit corresponding to the second RF group according to the estimated RF exposure and the calculated RF exposure, respectively.

IPC Classes  ?

  • H04B 1/3827 - Portable transceivers
  • H04W 52/24 - TPC being performed according to specific parameters using SIR [Signal to Interference Ratio] or other wireless path parameters
  • H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets

36.

METHOD FOR PERFORMING MAPPING BETWEEN ONE OR MORE RADIO MODULES AND ONE OR MORE RADIOFREQUENCY GROUPS AND ASSOCIATED ELECTRONIC DEVICE

      
Application Number 18902964
Status Pending
Filing Date 2024-10-01
First Publication Date 2025-04-10
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Yu, Tsung-Po
  • Lin, Yi-Hsuan
  • Kao, Fu-Tse

Abstract

A method for performing mapping between one or more radio modules and one or more radiofrequency (RF) groups includes: separating the one or more radio modules into the one or more RF groups according to one or more messages, wherein the one or more messages comprise a previous TX power ratio, a TX power ratio margin, one or more weighting information, one or more TX performance indices, one or more receiving (RX) performance indices, one or more configurations, or one or more usage scenarios; accumulating RF exposure of the one or more radio modules to at least one RF group among the one or more RF groups; and determining at least one transmitting (TX) power limit corresponding to the at least one RF group according to accumulated RF exposure of the at least one RF group.

IPC Classes  ?

  • H04W 52/22 - TPC being performed according to specific parameters taking into account previous information or commands
  • H04B 17/10 - MonitoringTesting of transmitters
  • H04B 17/20 - MonitoringTesting of receivers
  • H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets

37.

ELECTRONIC DEVICE AND METHOD OF HANDLING A SELF-ADAPTIVE MECHANISM

      
Application Number 18906139
Status Pending
Filing Date 2024-10-03
First Publication Date 2025-04-10
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Ho, Yi-Wei
  • Hsieh, Hsien-Hsi
  • Chang, Kan-Yao
  • Chen, Wei-Shuo
  • Chen, Chung-Yang
  • Chen, Cheng-Che

Abstract

An electronic device includes a processor arranged to execute an application, a platform and a middleware. The application is configured to execute operations of: providing at least one acceptable quality and at least one priority of the at least one profile parameter. The platform is configured to execute an operation of: providing platform information in response to a demand request. The middleware is configured to execute operations of: receiving the at least one acceptable quality and the at least one priority from the application; receiving the platform information from the platform; performing a self-adaptive algorithm according to the platform information to generate a result; adjusting the at least one profile parameter according to the result, the at least one acceptable quality and the at least one priority; and transmitting an adjustment notification to the platform, after adjusting the at least one profile parameter.

IPC Classes  ?

  • G06F 9/445 - Program loading or initiating
  • A63F 13/77 - Game security or game management aspects involving data related to game devices or game servers, e.g. configuration data, software version or amount of memory

38.

MULTI-PASS DECODER-SIDE MOTION VECTOR REFINEMENT

      
Application Number 18730921
Status Pending
Filing Date 2023-01-16
First Publication Date 2025-04-10
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Lai, Chen-Yen
  • Chuang, Tzu-Der
  • Chen, Ching-Yeh

Abstract

A method for constraining multi-pass decoder-side motion vector refinement (MP-DMVR) is provided. A video coder receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. A video coder receives a motion vector that references a block of pixels in a reference picture based on the received data. A video coder refines the motion vector in a plurality of refinement passes by examining pixels in the reference picture that are identified based on the refined motion vector. The refinement of the motion vector is constrained by a refinement range. The video coder encodes or decodes the current block by using the refined motion vector to produce prediction residuals or to reconstruct the current block.

IPC Classes  ?

  • H04N 19/513 - Processing of motion vectors
  • H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
  • H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock

39.

METHOD FOR ADJUSTING APPLICATION SETTINGS AND ELECTRONIC DEVICE

      
Application Number 18645738
Status Pending
Filing Date 2024-04-25
First Publication Date 2025-04-10
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chen, Ching-Yeh
  • Ho, Yi-Wei
  • Lin, Te-Hsin
  • Huang, Shih-Ting
  • Ho, Chung Hao
  • Lin, Yu-Hsien
  • Lin, Chiu-Jen
  • Chen, Cheng-Che

Abstract

A method for adjusting application settings is provided. The method includes using an application setting module to receive at least one performance target from an application running on an electronic device. The method further includes using the application setting module to record at least one performance indicator of the application while the application is running, wherein the performance indicator corresponds to the performance target. The method further includes using the application setting module to estimate the estimated time that the temperature of the electronic device sustains less than the defense temperature. The method further includes using the application setting module to determine the score according to the performance indicator and the estimated time, wherein the score indicates to the application that it should raise, lower, or keep a current setting.

IPC Classes  ?

  • G06F 9/445 - Program loading or initiating
  • G06F 11/30 - Monitoring
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation

40.

ELECTRONIC DEVICE AND METHOD FOR ESTIMATING SCATTERING PARAMETERS OF TWO-PORT NETWORK

      
Application Number 18375997
Status Pending
Filing Date 2023-10-03
First Publication Date 2025-04-03
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chen, Kuo-Hao
  • Matsuura, Toru

Abstract

An electronic device and a method for estimating scattering parameters of a two-port network are provided. The electronic device includes a two-port network, a directional coupler, an input calibration kit placed in front of the two-port network, an output calibration kit placed behind the two-port network, and a control switch connected between the directional coupler and the two-port network. The directional coupler transmits a desired signal and receives a forward signal and a reverse signal from the two-port network. When the control switch is turned off, input calculation results are calculated according to the forward signal and the reverse signal by controlling the input calibration kit. When the control switch is turned on, output calculation results are calculated according to the forward signal and the reverse signal by controlling the output calibration kit. The scattering parameters are estimated according to the input calculation results and the output calculation results.

IPC Classes  ?

  • H04B 1/44 - Transmit/receive switching
  • H04B 17/14 - MonitoringTesting of transmitters for calibration of the whole transmission and reception path, e.g. self-test loop-back

41.

DIGITAL SIGNAL PROCESSING SYSTEM AND METHOD THEREOF

      
Application Number 18476493
Status Pending
Filing Date 2023-09-28
First Publication Date 2025-04-03
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Yeh, Yang-Ting
  • Tsai, Ping-Tsai

Abstract

A digital signal processing system is provided. The system includes a signal-receiver unit, a signal-generation unit, a tracking unit, and a period-adjustment unit. The signal-receiver unit is configured to receive a transmission signal sequence that includes the first transmission signal and the second transmission signal. The signal-generation unit is configured to generate a processing signal sequence that includes the first processing signal and the second processing signal next to the first processing signal. The tracking unit is configured to keep track of the first arrival time of the first transmission signal. The period-adjustment unit is configured to adjust the duration of the second period based on the first arrival time and the first ideal interval with a specified duration in the first period of the first processing signal, and cause the signal-generation unit to generate the second processing signal with the second period.

IPC Classes  ?

  • H04B 17/309 - Measuring or estimating channel quality parameters
  • H04B 17/20 - MonitoringTesting of receivers

42.

CONFIGURABLE COMPUTING-IN-MEMORY (CIM) FOR POWER CONTROL

      
Application Number 18476882
Status Pending
Filing Date 2023-09-28
First Publication Date 2025-04-03
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Teng, Chieh-Fang
  • Chang, En-Jui
  • Cheng, Chih Chung

Abstract

A method can include determining which computing units in a computing-in-memory (CIM) macro are to be turned off, the CIM macro including an array of the computing units with X rows and Y columns, the X rows of computing units being organized into N row-groups, each row-group including multiple rows of computing units, the Y columns of computing units being organized into M column-groups, each column-group including multiple columns of computing units, based on the determination of which computing units in the CIM macro are to be turned off, turning off at least one row-group or column-group of computing units, each row-group and column-group of computing units being separately controllable to be turned off, and performing a computation based on kernel weights and activations of a neural network stored in the active computing units in the CIM macro that are not turned off.

IPC Classes  ?

  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

43.

METHOD AND APPARATUS FOR WAKE-UP SIGNAL TRANSMISSION BASED ON TIMING INFORMATION

      
Application Number 18726313
Status Pending
Filing Date 2023-03-20
First Publication Date 2025-04-03
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Cheng, Chien-Chun
  • Wu, Wei-De
  • Liao, Yi-Ju
  • Li, Cheng-Hsun

Abstract

Various solutions for wake-up signal (WUS) transmission based on timing information with respect to user equipment and network apparatus in mobile communications are described. An apparatus may receive a system information and a timing information for waking up a non-anchor cell from an anchor cell. The apparatus may transmit a WUS based on the system information and the timing information to wake up the non-anchor cell. The anchor cell comprises a cell where the apparatus is capable of receiving the system information and the timing information and performing a timing and frequency synchronization. The non-anchor cell comprises a cell where the apparatus cannot receive the system information and the timing information.

IPC Classes  ?

44.

SEMICONDUCTOR PACKAGE STRUCTURE

      
Application Number 18762183
Status Pending
Filing Date 2024-07-02
First Publication Date 2025-04-03
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Peng, Tai-Hao
  • Huang, Yao-Tsung

Abstract

A semiconductor package structure includes a package substrate and a semiconductor die. The package substrate includes a core structure, a heat sink, and a redistribution layer. The heat sink is embedded in the core structure. The redistribution layer includes a thermal via disposed over the heat sink. The semiconductor die is disposed over the package substrate and is thermally coupled to the heat sink through the thermal via.

IPC Classes  ?

  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/498 - Leads on insulating substrates

45.

REFERENCE VOLTAGE AUTO-SWITCHING MECHANISM USED IN REGULATOR FOR SAVING MORE POWER IN LOW-POWER MODE

      
Application Number 18977977
Status Pending
Filing Date 2024-12-12
First Publication Date 2025-04-03
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Huang, Chih-Chien
  • Lee, Chuan-Chang

Abstract

The present invention provides a circuitry including a regulator and a control circuit is disclosed. The regulator is configured to receive an input signal to generate an output voltage. The control circuit is configured to select one of a first reference voltage and a second reference voltage to serve as an output reference voltage according to an output signal of the regulator, and generate a control signal according to the output reference voltage to control a voltage level of the output voltage of the regulator.

IPC Classes  ?

  • G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage

46.

IMAGE ADJUSTMENT METHOD AND IMAGE SENSING SYSTEM

      
Application Number 18373987
Status Pending
Filing Date 2023-09-28
First Publication Date 2025-04-03
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Wang, Jan-Wei
  • Jhuang, Huei-Han
  • Huang, Po-Yu
  • Chen, Ying-Jui
  • Ju, Chi-Cheng

Abstract

An image adjustment method, applied to an image sensing system comprising an image sensor, comprising: (a) sensing a target image by the image sensor; (b) dividing the target image to a plurality of image regions; (c) acquiring location information of at least one first target feature in the image regions; (d) computing brightness information of each of the image regions; (e) generating adjustment curves according to the brightness information and according to required brightness values of each of the image regions; and (f) adjusting brightness values of the image regions according to the adjustment curves. The step (d) adjusts the brightness information according to the location information or the step (e) adjusts the adjustment curves according to the location information.

IPC Classes  ?

  • H04N 23/76 - Circuitry for compensating brightness variation in the scene by influencing the image signals
  • G06T 5/00 - Image enhancement or restoration
  • G06T 7/11 - Region-based segmentation
  • G06T 7/246 - Analysis of motion using feature-based methods, e.g. the tracking of corners or segments
  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
  • H04N 23/68 - Control of cameras or camera modules for stable pick-up of the scene, e.g. compensating for camera body vibrations
  • H04N 23/745 - Detection of flicker frequency or suppression of flicker wherein the flicker is caused by illumination, e.g. due to fluorescent tube illumination or pulsed LED illumination

47.

Methods And Apparatus For Beam Indication In Mobile Communications

      
Application Number 18811622
Status Pending
Filing Date 2024-08-21
First Publication Date 2025-04-03
Owner MediaTek Inc. (Taiwan, Province of China)
Inventor
  • Chen, Yi-Ru
  • Tsai, Cheng-Rung

Abstract

Various solutions for beam management with respect to user equipment and network node in mobile communications are described. An apparatus may measure at least one reference signal from a network node. The apparatus may transmit a beam report to the network node. The beam report may indicate at least one beam which has been synchronized by the apparatus. The beam report may comprise a reporting order to determine at least one codepoint of a transmission configuration indicator (TCI) field.

IPC Classes  ?

  • H04W 16/28 - Cell structures using beam steering
  • H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
  • H04W 72/231 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the layers above the physical layer, e.g. RRC or MAC-CE signalling
  • H04W 76/20 - Manipulation of established connections

48.

Methods And Apparatus For Response Of Beam Reporting In Mobile Communications

      
Application Number 18818929
Status Pending
Filing Date 2024-08-29
First Publication Date 2025-04-03
Owner MediaTek Inc. (Taiwan, Province of China)
Inventor
  • Chen, Yi-Ru
  • Tsai, Cheng-Rung

Abstract

Various solutions for response of beam reporting with respect to user equipment and network node in mobile communications are described. An apparatus may transmit a report indicating at least one beam to a network node. The apparatus may receive a downlink control information (DCI) indicating an indicator from the network node within an effective duration corresponding to the report. The apparatus may determine whether the report is received or confirmed by the network node according to the indicator. The apparatus may perform a beam switching or a beam synchronization based on the at least one beam indicated in the report if the report is received or confirmed by the network node.

IPC Classes  ?

  • H04W 16/28 - Cell structures using beam steering
  • H04W 24/10 - Scheduling measurement reports
  • H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling

49.

FRAME NUMBER OFFSET FOR POSITIONING OF A REMOTE UE

      
Application Number 18834214
Status Pending
Filing Date 2023-05-09
First Publication Date 2025-04-03
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Tenny, Nathan Edward
  • Wang, Xuelong
  • Chen, Tao
  • Chuang, Chiao-Yao

Abstract

A method can include receiving a system frame number (SFN) from a base station by a first relay UE, determining a timeline of the SFN based on one or more synchronization signals by the first relay UE, determining a timeline of a direct frame number (DFN) based on a reference time source by the first relay UE, computing an SFN-DFN offset based on the difference between the timeline of the SFN and the timeline of the DFN by the first relay UE, and transmitting the SFN-DFN offset and the DFN to a receiving UE on a sidelink interface.

IPC Classes  ?

  • H04L 1/1607 - Details of the supervisory signal
  • H04W 56/00 - Synchronisation arrangements
  • H04W 72/25 - Control channels or signalling for resource management between terminals via a wireless link, e.g. sidelink
  • H04W 76/20 - Manipulation of established connections
  • H04W 92/18 - Interfaces between hierarchically similar devices between terminal devices

50.

COMPUTER VISION PROCESSING SYSTEM AND METHOD THEREOF

      
Application Number 18891467
Status Pending
Filing Date 2024-09-20
First Publication Date 2025-04-03
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Jeng, Po-Yuan
  • Liu, Hung-Chun
  • Lin, Yu-Chieh
  • Su, Chien-Han
  • Chiu, Yung-Chih
  • Chen, Lei

Abstract

A computer vision processing system is provided. The system includes one or more target devices and a processing unit. The target devices are configured to run the executable code of an image processing pipeline. The processing unit is configured to receive a series of application programming interface (API) calls and create a raw graph accordingly, redraw the raw graph into a compilable graph by sequentially processing each node, and compile the compilable graph into the executable code of the image processing pipeline. The series of API calls includes at least one tiling API call to set at least one of the nodes and at least one of the data objects as tileable. Each tileable node corresponds to multiple parallel processing nodes in multiple branches in the compilable graph, and each tileable data object corresponds to multiple tile data objects in the branches in the compilable graph.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

51.

FLIP CHIP PACKAGE AND FABRICATION METHOD THEREOF

      
Application Number 18892518
Status Pending
Filing Date 2024-09-22
First Publication Date 2025-04-03
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Tsao, Pei-Haw
  • Wong, Te-Chi

Abstract

A flip-chip package includes a substrate having a bond pad in a die-mounting area of the substrate. A DRAM die is mounted on the die-mounting area of the substrate in a flip chip fashion. The DRAM die includes an input/output (I/O) pad on its active surface and the I/O pad is electrically coupled to the t bond pad through a connecting element. The bond pad has a diameter that is smaller than a diameter of the I/O pad. A SoC die is mounted on the substrate in a flip chip fashion. The DRAM die and the SoC die are mounted on the substrate in a side-by-side manner.

IPC Classes  ?

  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

52.

WIREBOND MULTICHIP PACKAGE

      
Application Number 18892576
Status Pending
Filing Date 2024-09-23
First Publication Date 2025-04-03
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Hsiao, Yu-Liang
  • Chou, Ming-Hsien

Abstract

A semiconductor package includes a carrier substrate comprising a first surface and a second surface opposite to the first surface. A first electronic component and a second electronic component are mounted on the first surface of the carrier substrate in a side-by-side manner. The first electronic component is provided with first data (DQ) pads along a first side directly facing the second electronic component. The second electronic component is provided with second data (DQ) pads along a second side in proximity to the first electronic component. The first DQ pads are directly connects to the second DQ pads through first bond wires.

IPC Classes  ?

  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

53.

METHOD AND APPARATUS FOR USING ON-DEMAND REFERENCE SIGNAL OR SYSTEM INFORMATION BLOCK FOR NETWORK ENERGY SAVING

      
Application Number 18832724
Status Pending
Filing Date 2023-01-18
First Publication Date 2025-04-03
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor Cheng, Chien-Chun

Abstract

Various solutions for using on-demand reference signal (RS) or system information block (SIB) for network energy saving with respect to user equipment and network apparatus in mobile communications are described. An apparatus may determine whether to trigger an on-demand RS/SIB or SIB request according to a trigger condition. The apparatus may transmit the on-demand RS/SIB or SIB request to a network node in an event that the trigger condition is satisfied. The apparatus may receive a response of the on-demand RS/SIB or SIB request from the network node. The apparatus may perform an on-demand RS/SIB or SIB measurement according to the response.

IPC Classes  ?

  • H04B 17/327 - Received signal code power [RSCP]
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 74/0833 - Random access procedures, e.g. with 4-step access

54.

Method and Apparatus for Geometry Partition Mode MV Assignment in Video Coding System

      
Application Number 18730932
Status Pending
Filing Date 2023-01-13
First Publication Date 2025-04-03
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chuang, Tzu-Der
  • Chen, Ching-Yeh
  • Hsu, Chih-Wei

Abstract

A method and apparatus for video coding are disclosed for the encoder side and the decoder side. According to the method for the decoder side, encoded data associated with a current block is received. A pseudo GPM in a target GPM group for the current block is determined. The current block is divided into one or more subblocks. Assigned MVs (Motion Vectors) of each subblock are determined according to the pseudo GPM. A cost for each GPM in the target GPM group is determined according to decoded data. A selected GPM is determined based on a mode syntax and a reordered target GPM group corresponding to the target GPM group reordered according to the costs, wherein the pseudo GPM is allowed to be different from the selected GPM. The encoded data is decoded using information comprising the selected GPM.

IPC Classes  ?

  • H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
  • H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
  • H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards

55.

Fast Synchronization Mechanism for Heterogeneous Computing

      
Application Number 18473514
Status Pending
Filing Date 2023-09-25
First Publication Date 2025-03-27
Owner MediaTek Inc. (Taiwan, Province of China)
Inventor
  • Liu, Hsing-Chuang
  • Chen, Yu-Shu
  • Chen, Hong-Yi

Abstract

A heterogeneous computing system performs data synchronization. The heterogeneous computing system includes a system memory, a cluster, and a processing unit outside the cluster. The cluster includes a sync circuit, inner processors, and a snoop filter. The sync circuit is operative to receive a sync command indicating a sync address range. The sync command is issued by one of the processing unit and the inner processors. The sync circuit further determines whether addresses recorded in the snoop filter fall within the sync address range. In response to a determination that a recorded address falls within the sync address range, the sync circuit notifies a target one of the inner processors that owns a cache line having the recorded address to take a sync action on the cache line.

IPC Classes  ?

  • G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
  • G06F 12/02 - Addressing or allocationRelocation

56.

DYNAMIC BEAM INDICATION FOR NETWORK-CONTROLLED FORWARDING IN MOBILE COMMUNICATIONS

      
Application Number 18728609
Status Pending
Filing Date 2023-06-05
First Publication Date 2025-03-27
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Tsai, Cheng-Rung
  • Tsai, Lung-Sheng

Abstract

Examples pertaining to dynamic beam indication for network-controlled forwarding in mobile communications are described. An apparatus (e.g., a network-controlled repeater (NCR)) may receive downlink control information (DCI) from a network node. The DCI may include first beam indication information indicating one or more first pairs of a spatial setting and a time-domain resource. The apparatus may also forward a radio signal based on the first beam indication information.

IPC Classes  ?

  • H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling
  • H04W 72/044 - Wireless resource allocation based on the type of the allocated resource

57.

Methods And Apparatus For Enhancing Quality Of Service Based On Environmental Conservation In Mobile Communications

      
Application Number 18792262
Status Pending
Filing Date 2024-08-01
First Publication Date 2025-03-27
Owner MediaTek Inc. (Taiwan, Province of China)
Inventor
  • Yang, Chien-Sheng
  • Lai, Chia-Lin
  • Lin, Yuan-Chieh
  • Lin, Yu-Hsin
  • Fu, I-Kang

Abstract

Various solutions for enhancing quality of service (QoS) based on environmental conservation in mobile communications are described. An apparatus may determine whether an eco-friendly condition associated with a data session is met. Also, the apparatus may determine to modify a QoS associated with the data session in an event that the eco-friendly condition associated with the data session is met.

IPC Classes  ?

  • H04W 28/24 - Negotiating SLA [Service Level Agreement]Negotiating QoS [Quality of Service]
  • H04W 60/06 - De-registration or detaching
  • H04W 76/30 - Connection release

58.

SEMICONDUCTOR DEVICE

      
Application Number 18892608
Status Pending
Filing Date 2024-09-23
First Publication Date 2025-03-27
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor Chen, Nan-Jang

Abstract

A semiconductor device is provided. The semiconductor device includes a first conductive layer and second conductive layer. The second conductive layer is disposed opposite to the first conductive layer. One of the first conductive layer and the second conductive layer includes a first grounding net and a first signal ball-pad. The first grounding net has a first ground void, and the first signal ball-pad is disposed in the first ground void. The first signal ball-pad has a first ball-pad diameter, the first ground void has a first ground void diameter, and a ratio of the first ground void diameter to the first ball-pad diameter is equal to or greater than 1.2.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01F 17/00 - Fixed inductances of the signal type
  • H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
  • H05K 1/02 - Printed circuits Details

59.

Out-of-Service Recovery Search Method and Out-of-Service Recovery Search System Capable of Performing High Search Efficiency and Link Tracking for Cell Detection

      
Application Number 18894027
Status Pending
Filing Date 2024-09-24
First Publication Date 2025-03-27
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Wu, Jia-Hao
  • Shiu, Tzyuan
  • Wang, Da-Wei
  • Lin, Lu-Chi
  • Fang, Mu-Chi
  • Chou, Wen-Yang
  • Tang, Tsung-Sheng
  • Lee, Chung-Pi

Abstract

An out-of-service recovery search method includes establishing a frequency list including at least one searchable frequency, searching a suitable cell of a network according to the frequency list when the user terminal is in an out-of-service state, determining at least one first skip condition of the user terminal, performing a full-band power scan mechanism for scanning received signal strength indication (RSSIs) of user terminal supported frequency bands when the at least one first skip condition of the user terminal is absent and no suitable cell of the network is searched within the searchable frequency of the frequency list, skipping the full-band power scan mechanism when the at least one first skip condition of the user terminal is present and no suitable cell of the network is searched within the searchable frequency, and performing an RSSI sniffer for scanning a signal power of each frequency of the searchable frequency.

IPC Classes  ?

  • H04W 48/16 - DiscoveringProcessing access restriction or access information
  • H04W 56/00 - Synchronisation arrangements
  • H04W 84/04 - Large scale networksDeep hierarchical networks

60.

ELECTRONIC DEVICE AND METHOD TO REDUCE POWER CONSUMPTION DURING ACCESS

      
Application Number 18883815
Status Pending
Filing Date 2024-09-12
First Publication Date 2025-03-27
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Hsieh, Ming-Hung
  • Wu, Pei-Lun
  • Chang, Hsin-Yu
  • Wu, Yu-Cheng

Abstract

An electronic device includes a first buffer, a second buffer, and a multiplexer. The first buffer receives and stores first data when the first buffer is not full, and performs a First-In-First-Out (FIFO) operation on the first data. The second buffer receives and stores second data when the first buffer is full, and performs the FIFO operation on the second data. The multiplexer is electrically connected between the first buffer and the second buffer. The multiplexer receives the first data from outside of the electronic device, or it receives the second data from the second buffer. A depth of the first buffer is less than that of the second buffer.

IPC Classes  ?

  • G06F 5/16 - Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
  • G06F 1/3234 - Power saving characterised by the action undertaken
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

61.

ELECTRONIC DEVICE

      
Application Number 18883834
Status Pending
Filing Date 2024-09-12
First Publication Date 2025-03-27
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Kuo, Kai-Lun
  • Tsai, Kun-Ting
  • Kuo, Che-Hung

Abstract

An electronic device is provided. The electronic device includes a semiconductor die. The semiconductor die has a first region of a first functional cell close to the peripheral edge of the semiconductor die. The semiconductor die includes a semiconductor substrate, a first signal bump, and a first power bump. The first signal bump and the first power bump are disposed on opposite surfaces of the semiconductor substrate and electrically connected to the first functional cell. The first signal bump and the first power bump both overlap the first region.

IPC Classes  ?

  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/528 - Layout of the interconnection structure

62.

SEMICONDUCTOR PACKAGE ASSEMBLY

      
Application Number 18893113
Status Pending
Filing Date 2024-09-23
First Publication Date 2025-03-27
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Yang, Chung-Min
  • Kuo, Che-Hung

Abstract

A semiconductor package assembly is provided. The semiconductor package assembly includes first and a second semiconductor dies. The first semiconductor die has a first surface and a second surface opposite the first surface. The first semiconductor die includes a first interface and a second interface. The second interface is arranged beside the first interface. The second interface is farther from the corresponding first edge of the first semiconductor die than the first interface. The second semiconductor die is stacked on the first semiconductor die. The semiconductor package assembly further includes a first conductive bump and a second conductive bump. The first conductive bump is disposed on the first surface of the first semiconductor die. The second conductive bump is disposed on the second surface of the first semiconductor die. The second semiconductor die is electrically coupled to the first semiconductor die by the second interface.

IPC Classes  ?

  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

63.

SEMICONDUCTOR STRUCTURE

      
Application Number 18971358
Status Pending
Filing Date 2024-12-06
First Publication Date 2025-03-20
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor Tsao, Po-Chao

Abstract

A semiconductor structure includes a substrate, a first well region on the substrate, a shallow trench isolation (STI) region over the first well region, and a first transistor. The first transistor includes a first fin formed on the first well region, a first gate electrode formed on the first fin, and a first doping region formed on the first fin. The semiconductor structure further includes a first power rail on the first well region and in the STI region and a first source/drain contact over the first doping region and the first power rail to electrically connect the first doping region to the first power rail. A bottom surface of first source/drain contact is in direct contact with the STI region.

IPC Classes  ?

  • H01L 21/8234 - MIS technology
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

64.

Adaptive radio frequency front-end circuit with low insertion loss for WLAN

      
Application Number 18814570
Status Pending
Filing Date 2024-08-25
First Publication Date 2025-03-20
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chang, Yu-Hsien
  • Shanaa, Osama Khalil
  • Shi, Yan

Abstract

A radio frequency (RF) front-end circuit has a multi-way switch, an output terminal, and a shunt circuit. The multi-way switch has an input end, a plurality of output ends, and a control end. The input end is coupled to an antenna for receiving a radio frequency signal from the antenna. The control end is used to couple the input end to one of the output ends according to a switch control signal. The shunt circuit is coupled between the multi-way switch and the output terminal to provide one of shunt paths according to the switch control signal. The shunt paths correspond to different amounts of rejection to the radio frequency signal.

IPC Classes  ?

  • H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
  • H04B 1/04 - Circuits

65.

PRECODER SELECTION FOR MINIMIZING IMPACT OF CYCLIC SHIFT PORT VIRTUALIZATION ON COMMUNICATION PERFORMANCE IN JOINT COMMUNICATION AND SENSING

      
Application Number 18828028
Status Pending
Filing Date 2024-09-09
First Publication Date 2025-03-20
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Ren, Jiaying
  • Tsai, Shiauhe

Abstract

A method of joint communication and sensing of a target obstacle includes deploying an integrated sensing and communication (ISAC) node having an ISAC transmitter having M transmitting antenna(s) and a radar receiver having L receiving antenna(s), wherein the M and L are integers; transmitting radio frequency (RF) signals carrying data to a communication receiver by the M transmitting antenna(s) of the ISAC transmitter; receiving radio frequency (RF) signals reflected by the target obstacle by the L receiving antenna(s); and obtaining a sounding result based on the reflected radio frequency (RF) signals; wherein the RF signals are applied with cyclic shift diversity; and wherein the RF signals contain precoders which are selected by aligning a range of communication direction linked to a communication channel between the ISAC node and the communication receiver with minimal capacity loss based on the sounding result.

IPC Classes  ?

  • H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
  • H04L 5/00 - Arrangements affording multiple use of the transmission path

66.

High-Speed Hardware-Based DVFS System Using Frequency Lock Loop and On-Die Voltage Controller

      
Application Number 18885866
Status Pending
Filing Date 2024-09-16
First Publication Date 2025-03-20
Owner MediaTek Inc. (Taiwan, Province of China)
Inventor
  • Varma, Anshul
  • Chen, Hsin-Chen

Abstract

A voltage controller circuit is provided for dynamic frequency and voltage scaling. The voltage controller circuit receives an error signal indicating a frequency error and a code error. The frequency error indicates a first difference between a target frequency and an actual frequency generated by an oscillator, and the code error indicates a second difference between a minimum code and an actual code with which the oscillator is configured to generate the actual frequency. The minimum code corresponds to a maximum frequency that the oscillator generates for a processor to safely operate under a given voltage. The voltage controller circuit calculates a voltage correction value based on the error signal, a first gain parameter for the frequency error, and a second gain parameter for the code error, and sends a request to a power management circuit to cause an updated voltage to be supplied to the processor.

IPC Classes  ?

  • G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
  • H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
  • H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop

67.

METHOD AND APPARATUS FOR PERFORMING SINGULARITY DETECTION AIDED CALIBRATION ON TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER

      
Application Number 18890768
Status Pending
Filing Date 2024-09-20
First Publication Date 2025-03-20
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Pan, Yun-Han
  • Chiang, Chien-Hung
  • Manganaro, Gabriele

Abstract

A calibration apparatus includes a calibration circuit and a singularity detection (SD) circuit. The calibration circuit performs a calibration process upon a time-interleaved analog-to-digital converter (TI-ADC) with a plurality of TI channels, wherein the calibration process includes detecting and correcting mismatch between different TI channels of the TI-ADC. The SD circuit sets an SD flag by evaluating variation of statistical characteristics of an ADC input signal between different TI channels of the TI-ADC, and outputs the SD flag to the calibration circuit, wherein the calibration circuit controls the calibration process according to the SD flag.

IPC Classes  ?

  • H04B 17/11 - MonitoringTesting of transmitters for calibration

68.

DIGITAL SERIALIZER/DESERIALIZER CIRCUIT AND DATA EYE MONITORING METHOD THEREOF

      
Application Number 18890839
Status Pending
Filing Date 2024-09-20
First Publication Date 2025-03-20
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Yang, Ting-Ming
  • Juang, Bi-Jing
  • Yen, Wei-Ping
  • Peng, Chia-Sheng
  • Yeh, Tse-Hsien

Abstract

The application disclose a digital serializer/deserializer circuit and a data eye monitoring method thereof. A received analog signal is converted to first digital samples at a first sample rate. The first digital samples are equalized to generate a first equalized signal. A symbol decision signal is generated from the first equalized signal. The received analog signal is converted to second digital samples at a second sample rate. Difference between the first digital samples and the second digital samples is determined, and the first equalized signal and the determined difference are combined to generate a signal processing output. A data eye error rate is determined according to the symbol decision signal and the signal processing output.

IPC Classes  ?

  • H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
  • H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels

69.

POWER CONTROL FOR REPEATERS AND MULTI-PATH COMMUNICATION

      
Application Number 18724371
Status Pending
Filing Date 2023-05-09
First Publication Date 2025-03-20
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Tsai, Lung-Sheng
  • Yu, Chia-Hao
  • Fang, Chun-Hao
  • Chen, Kuan-Yuan

Abstract

A method of power control can include receiving at a UE a first downlink reference signal from a repeater and a second downlink reference signal from a base station, the first downlink reference signal corresponding to a first path that is between the UE and the base station and passes the repeater, the second downlink reference signal corresponding to a second path that is between the UE and the base station. The UE estimates a first uplink path loss of the first path and a second uplink path loss of the second path and determine a first uplink transmit power corresponding to the first path and a second uplink transmit power corresponding to the second path. The UE performs an uplink transmission on the first path based on the first uplink transmit power and on the second path based on the second uplink transmit power.

IPC Classes  ?

  • H04W 52/14 - Separate analysis of uplink or downlink
  • H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets

70.

Method and Apparatus Deriving Merge Candidate from Affine Coded Blocks for Video Coding

      
Application Number 18727516
Status Pending
Filing Date 2023-01-06
First Publication Date 2025-03-20
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chuang, Tzu-Der
  • Chen, Ching-Yeh

Abstract

Methods and apparatus of video coding are disclosed. According to this method, input data comprising pixel data for a current block to be encoded at an encoder side or encoded data of the current block to be decoded at a decoder side is received. When one or more reference blocks or sub-blocks of the current block are coded in an affine mode, the following coding process is applied: one or more derived MVs (Motion Vectors) are determined for the current block according to one or more affine models associated with said one or more reference blocks or sub-blocks; a merge list comprising at least one of said one or more derived MVs as one translational MV candidate is generated; and predictive encoding or decoding is applied to the input data using information comprising the merge list.

IPC Classes  ?

  • H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
  • H04N 19/137 - Motion inside a coding unit, e.g. average field, frame or block difference
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock

71.

Methods And Apparatus For Enhanced User Equipment Route Selection Policy With Green Incentives For Environmental Conservation

      
Application Number 18773576
Status Pending
Filing Date 2024-07-16
First Publication Date 2025-03-13
Owner MediaTek Inc. (Taiwan, Province of China)
Inventor
  • Yang, Chien-Sheng
  • Lin, Yuan-Chieh
  • Lin, Yu-Hsin
  • Lai, Chia-Lin
  • Fu, I-Kang

Abstract

Various solutions for enhanced user equipment (UE) route selection policy (URSP) with green incentives for environmental conservation are described. An apparatus may receive information of an application associated with one or more eco-friendly requirements. Then, the apparatus may select a URSP rule from a list of URSP rules, and the selected URSP rule includes one or more descriptors matching the one or more eco-friendly requirements. Also, the apparatus may determine a data session for routing traffic of the application between the apparatus and a wireless network based on one or more parameters included in a route selection descriptor (RSD) of the selected URSP rule.

IPC Classes  ?

  • H04W 40/04 - Communication route or path selection, e.g. power-based or shortest path routing based on wireless node resources

72.

PIPELINE SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER RESIDUE AMPLIFIER OFFSET CANCELLATION

      
Application Number 18788603
Status Pending
Filing Date 2024-07-30
First Publication Date 2025-03-13
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor Ramachandra, Nikhil

Abstract

A controller obtains a first calibrated gain of a residue amplifier. The residue amplifier amplifies a first residue voltage to a voltage corresponding to a first output code of a second stage of the pipelined ADC. The first residue voltage is output from a capacitive digital-to-analog converter (CDAC) of a first stage of the pipelined ADC. The controller obtains a second calibrated gain of the residue amplifier. The residue amplifier amplifies a second residue voltage to a voltage corresponding to a second output code of the second stage of the pipelined ADC. The second residue voltage is output from the CDAC of the first stage of the pipelined ADC. The controller determines a final calibrated gain of the residue amplifier based on the first calibrated gain and the second calibrated gain.

IPC Classes  ?

  • H03M 1/10 - Calibration or testing
  • H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

73.

MIMO ANTENNA SYSTEM

      
Application Number 18821119
Status Pending
Filing Date 2024-08-30
First Publication Date 2025-03-13
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor Chiang, Chung-Hsin

Abstract

A MIMO (multiple input and multiple output) antenna system is provided. The MIMO antenna system includes a dielectric substrate, a first MIMO antenna, and a second MIMO antenna. The first MIMO antennas is mounted on the dielectric substrate. The second MIMO antenna is mounted on the dielectric substrate and located beside the first MIMO antenna. The first MIMO antenna and the second MIMO antenna are configured to wirelessly access a set of first signals.

IPC Classes  ?

  • H01Q 21/24 - Combinations of antenna units polarised in different directions for transmitting or receiving circularly and elliptically polarised waves or waves linearly polarised in any direction
  • H01Q 1/27 - Adaptation for use in or on movable bodies

74.

DUAL ACCESS/STEER CAPABILITY INFORMATION FOR NETWORK AND DEVICES DUAL ACCESS/STEER SERVICE

      
Application Number 18826648
Status Pending
Filing Date 2024-09-06
First Publication Date 2025-03-13
Owner MEDIA TEK INC. (Taiwan, Province of China)
Inventor
  • Tan, Tze Jie
  • Lin, Yuan-Chieh
  • Lin, Yu-Hsin
  • Lai, Chia-Lin

Abstract

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The method may be performed by a mobile device. In certain configurations, the mobile device provides device capability information indicating that the mobile device supports a dual access service. The mobile device transmits a registration request message for registering to a first network access of a first public land mobile network (PLMN). The registration request message includes the device capability information. The mobile device receives a registration response message. The mobile device determines whether the registration response message includes network capability information indicating that the first network access supports the dual access service. In response to determining that the first network access supports the dual access service, the mobile device registers to a second network access.

IPC Classes  ?

  • H04W 48/16 - DiscoveringProcessing access restriction or access information
  • H04W 60/00 - Affiliation to network, e.g. registrationTerminating affiliation with the network, e.g. de-registration

75.

Thermal Power Budget Optimization Method, Heating device and Thermal Power Budget Optimization System

      
Application Number 18788086
Status Pending
Filing Date 2024-07-29
First Publication Date 2025-03-13
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chang, Yu-Chia
  • Huang, Chien-Chih
  • Liao, Ta-Chang
  • Yeh, Chia-Feng
  • Hsiao, Ching-Lin
  • Wu, Wei-Te

Abstract

A thermal power budget optimization method includes acquiring sensor log information from a plurality of sensors of a heating device, generating a virtual surface temperature of the heating device according to the sensor log information, setting a target surface temperature of the heating device, and dynamically adjusting a thermal power budget of the heating device according to the virtual surface temperature and the target surface temperature over time.

IPC Classes  ?

76.

UE ASSISTED INFORMATION FOR DUAL ACCESS/STEER FEATURE

      
Application Number 18826606
Status Pending
Filing Date 2024-09-06
First Publication Date 2025-03-13
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Lai, Chia-Lin
  • Tan, Tze Jie
  • Lin, Yuan-Chieh
  • Lin, Yu-Hsin

Abstract

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The method may be performed by a mobile device. In certain configurations, the mobile device registers a first network access of a first public land mobile network (PLMN). After registering to the first network access, the mobile device determines, based on first information, whether a second network access of a PLMN or a Standalone Non-Public Network (SNPN) is allowed for the UE to register thereto. In response to determining the second network access is allowed, the mobile device selects the second network access based on the first information, and registers to the second network access. The second network access may be a network access of the first PLMN, or may be a network access of a second different PLMN or the SNPN.

IPC Classes  ?

  • H04W 48/18 - Selecting a network or a communication service

77.

MEMORY CONTROL SYSTEM AND MEMORY CONTROL METHOD FOR REDUCING MEMORY TRAFFIC

      
Application Number 18827870
Status Pending
Filing Date 2024-09-09
First Publication Date 2025-03-13
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Liu, Hsing-Chuang
  • Hsiao, Cheng-Chih
  • Hsieh, Hsien-Hua

Abstract

A memory control method includes a processor initiating a memory access instruction to a cache controller to search a cache memory, an address detector checking if the memory access instruction is corresponding to predetermined conditions if a cache miss occurs, the address detector transmitting a signal to inform a replacement mask logic unit if the memory access instruction is corresponding to the predetermined conditions, and the replacement mask logic unit providing predetermined data to store the predetermined data into the cache memory.

IPC Classes  ?

  • G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

78.

Minimum Integrated Circuit Operating Voltage Searching Method and Minimum Integrated Circuit Operating Voltage Searching System Capable of Blending Two Prediction Models

      
Application Number 18637448
Status Pending
Filing Date 2024-04-16
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Ho, Ronald Kuo-Hua
  • Wang, Kun-Yu
  • Shih, Yen-Chang
  • Chen, Sung-Te
  • Wu, Cheng-Han
  • Liao, Yi-Ying
  • Huang, Chun-Ming
  • Lu, Yen-Feng
  • Tsai, Ching-Yu
  • Tung, Tai-Lai
  • Lin, Kuan-Fu
  • Lai, Bo-Kang
  • Lee, Yao-Syuan
  • Lin, Tsyr-Rou
  • Tsai, Ming-Chao
  • Chiu, Li-Hsuan

Abstract

A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G06N 3/08 - Learning methods
  • H03K 3/01 - Circuits for generating electric pulsesMonostable, bistable or multistable circuits Details

79.

Method and Apparatus for Cross Component Linear Model for Inter Prediction in Video Coding System

      
Application Number 18720901
Status Pending
Filing Date 2022-12-20
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chiang, Man-Shu
  • Chubach, Olena
  • Hsiao, Yu-Ling
  • Tsai, Chia-Ming
  • Chen, Chun-Chia
  • Hsu, Chih-Wei
  • Chuang, Tzu-Der
  • Chen, Ching-Yeh
  • Huang, Yu-Wen

Abstract

A method and apparatus for inter prediction in video coding system are disclosed. According to the method, one or more model parameters of one or more cross-color models for the second-color block are determined. Then, cross-color predictors for the second-color block are determined, wherein one cross-color predictor value for the second-color block is generated for each second-color pixel of the second-color block by applying said one or more cross-color models to corresponding reconstructed or predicted first-color pixels. The input data associated with the second-color block is encoded using prediction data comprising the cross-color predictors for the second-color block at the encoder side, or the input data associated with the second-color block is decoded using the prediction data comprising the cross-color predictors for the second-color block at the decoder side.

IPC Classes  ?

  • H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component

80.

BUCK CONVERTER WITH ADAPTIVE TURN-ON FREQUENCY OF PULL-UP TRANSISTOR

      
Application Number 18799344
Status Pending
Filing Date 2024-08-09
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Li, Chih-Chen
  • Syu, Jin-Yan

Abstract

A buck converter with an adaptive turn-on frequency of a pull-up transistor is shown. The buck converter uses a pulse-width modulation (PWM) control signal generator to generate a PWM control signal that drives a power transistor driver to generate PWM signals driving the pull-up transistor and pull-down transistor of the buck converter. Especially, the PWM control signal generator generates the PWM control signal based on feedback of an output voltage of the buck converter as well as feedback of a sensed current about a power transformation component of the buck converter, to modify a turn-on frequency of the pull-up transistor in response to a change in the sensed current.

IPC Classes  ?

  • H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

81.

INTEGRATED CIRCUIT DEVICE AND CHIP DEVICE

      
Application Number 18952224
Status Pending
Filing Date 2024-11-19
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Lung, Bo-Ren
  • Yang, Jen-Hang

Abstract

An integrated circuit device includes a plurality of selecting modules, wherein each of the plurality of selecting modules is configured to receive a first input signal, a second input signal, a first selecting signal and a second selecting signal, and select the first input signal or the second input signal to generate an output signal according to a first selecting signal and a second selecting signal; and a selecting signal providing module, configured to provide the first selecting signal and the second selecting signal.

IPC Classes  ?

  • H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
  • H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only

82.

SYSTEM AND METHOD FOR DYNAMICALLY ADJUSTING NEURAL NETWORK EFFICIENCY OF DYNAMIC NEURAL NETWORK RUNNING ON DEVICE

      
Application Number 18239753
Status Pending
Filing Date 2023-08-29
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Liu, Chia-Hsiang
  • Chan, Cheng-Sheng
  • Horng, Min-Fong
  • Hsu, Jui-Yang
  • Hung, Sheng-Je
  • Chen, Hung-Jen

Abstract

A system for dynamically adjusting neural network efficiency of a dynamic neural network running on a device includes a detector and a signal generator. The detector is arranged to detect a change of a status of the device, to generate a trigger signal. The signal generator is arranged to generate a control signal according to the trigger signal, to dynamically adjust the neural network efficiency of the dynamic neural network.

IPC Classes  ?

83.

METHOD FOR GENERATING DYNAMIC NEURAL NETWORK AND ASSOCIATED NON-TRANSITORY MACHINE-READABLE MEDIUM

      
Application Number 18239764
Status Pending
Filing Date 2023-08-30
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Liu, Chia-Hsiang
  • Chan, Cheng-Sheng
  • Horng, Min-Fong
  • Hung, Sheng-Je
  • Chen, Hung-Jen
  • Hsu, Jui-Yang

Abstract

A method for generating a dynamic neural network includes: utilizing a neural architecture search (NAS) method to obtain a searched result, wherein the searched result comprises a plurality of sub-networks; combining the plurality of sub-networks to generate a combined neural network; and fine-tuning the combined neural network to generate the dynamic neural network.

IPC Classes  ?

  • G06N 3/045 - Combinations of networks
  • G06N 3/082 - Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections

84.

POWER MANAGEMENT SYSTEM OF INPUT-OUTPUT MEMORY MANAGEMENT UNIT AND ASSOCIATED METHOD

      
Application Number 18241909
Status Pending
Filing Date 2023-09-04
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Hsiao, Chih-Hsiang
  • Su, Chih-Pin

Abstract

A power management system includes at least one device, at least one memory management unit (MMU), a processor, and at least one device controller, wherein the at least one MMU corresponds to the at least one device, respectively. The processor is arranged to execute at least one access control power manager, an operating system (OS), and a hypervisor, wherein the OS is arranged to generate a trigger signal, and the hypervisor is arranged to generate a first hint according to the trigger signal. The at least one device controller is arranged to control the at least one access control power manager according to the first hint, to manage at least one power of the at least one MMU.

IPC Classes  ?

  • G06F 1/28 - Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
  • G06F 1/30 - Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations

85.

PCIE CLOCK DETECTION CIRCUIT AND METHOD THEREOF

      
Application Number 18817233
Status Pending
Filing Date 2024-08-28
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Kuo, Hung-Chang
  • Jeng, Wei-De
  • Chiu, Mao-Cheng

Abstract

A PCIe clock detection circuit includes a clock detector, a clock receiver, a counter coupled to the clock receiver, a multiplexer coupled to the counter, and an AND gate coupled to the clock detector and the multiplexer. The clock detector is used to detect amplitude of a clock signal and generate a clock detection signal accordingly. The clock receiver is used to generate a reference clock signal according to the clock signal. The counter is used to generate a counter signal according to the reference clock signal. The multiplexer is used to generate a MUX output signal according to the counter signal and a reference signal. The AND gate is used to generate a clock detection output signal according to the clock detection signal and the MUX output signal.

IPC Classes  ?

  • G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
  • G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
  • H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

86.

NON-COHERENT NOISE REDUCTION METHOD AND NON-COHERENT NOISE REDUCTION DEVICE

      
Application Number 18818610
Status Pending
Filing Date 2024-08-29
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Lin, Yun-Shao
  • Lee, Tsung-Han
  • Sun, Liang-Che
  • Cheng, Yiou-Wen

Abstract

A non-coherent noise reduction method, comprising: (a) receiving a plurality of input audio sensing signals by a processor, wherein the input audio sensing signals correspond to a plurality of channels responsive to sensing by a plurality of audio sensors; (b) detecting whether non-coherent noise exists in at least one of the channels by a non-coherent noise detector; (c) estimating at least one noise power of the non-coherent noise by a noise power estimator, if the non-coherent noise exists in at least one of the channels; (d) deriving at least one noise contour of the non-coherent noise by a noise contour estimator, if the non-coherent noise exists in at least one of the channels; and (e) enhancing the input audio sensing signals according to the noise power and the noise contour if the non-coherent noise exists in at least one of the channels.

IPC Classes  ?

  • G10K 11/178 - Methods or devices for protecting against, or for damping, noise or other acoustic waves in general using interference effectsMasking sound by electro-acoustically regenerating the original acoustic waves in anti-phase

87.

CALL DATA TRANSMISSION METHOD AND APPARATUS THEREOF

      
Application Number 18818922
Status Pending
Filing Date 2024-08-29
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Hao, Jie
  • Zhao, Guoyi
  • Yang, Yizheng

Abstract

A call data transmission method is provided. The call data transmission method may include the following steps. An apparatus may establish a first connection and a second connection with a second apparatus. The first connection may be a third generation partnership project (3GPP) connection and the second connection is a Wi-Fi connection, or the first connection may be a Wi-Fi connection and the second connection is a 3GPP connection. The apparatus may also perform a voice call or a video call with the second apparatus through the first connection. The apparatus may also determine whether the first connection meets a quality condition. The apparatus may further transmit data packets of the voice call or the video call to the second apparatus through the first connection and the second connection in the event that the first connection meets a quality condition.

IPC Classes  ?

  • H04M 3/22 - Arrangements for supervision, monitoring or testing
  • H04M 7/00 - Arrangements for interconnection between switching centres

88.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

      
Application Number 18797902
Status Pending
Filing Date 2024-08-08
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Huang, Cheng Lin
  • Yang, Ting-Li

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes an interconnect structure, a passivation layer and a conductive bump structure. The interconnect structure includes a conductive pad located at a top of the interconnect structure. The passivation layer is disposed on the interconnect structure. The conductive bump structure is disposed on and embedded into the passivation layer and the conductive pad. In a first direction, a first interface between the passivation layer and the conductive pad is located beside and misaligned with a second interface between the conductive bump structure and the conductive pad.

IPC Classes  ?

  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

89.

ANTENNA DEVICE HAVING A PLURALITY OF RADIATION DIRECTIONS AND IMPROVED GAIN

      
Application Number 18806667
Status Pending
Filing Date 2024-08-15
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor Chiang, Chung-Hsin

Abstract

An antenna device can include an antenna and a supporting member. The antenna is used to radiate an electromagnetic wave. The supporting member is used to accommodate and support the antenna. The supporting member has a storage space where the antenna is disposed. The supporting member further has a first aperture facing the first direction, and a second aperture facing a second direction different from the first direction. The antenna radiates the electromagnetic wave in the first direction through the first aperture and in the second direction through the second aperture.

IPC Classes  ?

  • H01Q 9/04 - Resonant antennas
  • H01Q 1/24 - SupportsMounting means by structural association with other equipment or articles with receiving set

90.

Distributed-Tone Resource Unit Based Enhanced Long Range Communication Schemes In WLAN

      
Application Number 18817198
Status Pending
Filing Date 2024-08-27
First Publication Date 2025-03-06
Owner MediaTek Inc. (Taiwan, Province of China)
Inventor
  • Liu, Jianhan
  • Hu, Shengquan
  • Pare, Jr., Thomas Edward

Abstract

Various schemes pertaining to distributed-tone resource unit (DRU)-based enhanced long range (ELR) communication schemes in wireless local area networks (WLANs) are described. An apparatus (e.g., an access point (AP) or a non-AP station (STA)) generates a DRU-based PPDU. The apparatus transmits the PPDU in an ELR communication.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 28/26 - Resource reservation

91.

BIT-PARALLEL DIGITAL COMPUTE-IN-MEMORY MACRO AND ASSOCIATED METHOD

      
Application Number 18820312
Status Pending
Filing Date 2024-08-30
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Lin, Ming-Hung
  • Shih, Ming-En
  • Hsieh, Shih-Wei
  • Tsai, Ping-Yuan
  • Nian, You-Yu
  • Tsung, Pei-Kuei
  • Liang, Jen-Wei
  • Chang, Shu-Hsin
  • Chang, En-Jui
  • Chen, Chih-Wei
  • Huang, Po-Hua
  • Huang, Chung-Lun

Abstract

A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.

IPC Classes  ?

  • G06F 7/505 - AddingSubtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
  • G06F 7/57 - Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups or for performing logical operations

92.

DIGITAL COMPUTE-IN-MEMORY SYSTEM WITH WEIGHT LOCALITY HAVING HIGHER ROW DIMENSION AND ASSOCIATED METHOD

      
Application Number 18820342
Status Pending
Filing Date 2024-08-30
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Lin, Ming-Hung
  • Shih, Ming-En
  • Hsieh, Shih-Wei
  • Tsai, Ping-Yuan
  • Nian, You-Yu
  • Tsung, Pei-Kuei
  • Liang, Jen-Wei
  • Chang, Shu-Hsin
  • Chang, En-Jui
  • Chen, Chih-Wei
  • Huang, Po-Hua
  • Huang, Chung-Lun

Abstract

A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.

IPC Classes  ?

  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 17/15 - Correlation function computation

93.

CURRENT STEERING DIGITAL-TO-ANALOG CONVERTER WITH REDUCED INTER-CELL INTERFERENCE

      
Application Number 18822479
Status Pending
Filing Date 2024-09-03
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Billa, Sujith Kumar
  • Wen, Sung-Han

Abstract

A DAC cell circuit includes: at least a DAC cell, including: a first MOSFET having a drain coupled to a first switch for receiving a first current and coupled to a second switch for generating a second current, a source coupled to ground, and a gate coupled to a first bias voltage; a capacitor coupled between the gate and the drain of the first MOSFET; and a dead-band switch coupled between the gate of the first MOSFET and the bias node. The dead-band switch is controlled by a signal which is periodic with respect to a frequency equal to an input data rate of the DAC cell, and the dead-band switch is open during a data transition.

IPC Classes  ?

  • H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise

94.

NEURAL NETWORK OPTIMIZATION WITH PREVIEW MECHANISM

      
Application Number 18239759
Status Pending
Filing Date 2023-08-30
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Yang, Chun-Wei
  • Chan, Cheng-Sheng
  • Horng, Min-Fong
  • Hsu, Jui-Yang
  • Hung, Sheng-Je

Abstract

A neural network optimization method with a preview mechanism includes: in a preview stage, building an optimization space and obtaining multiple previewed results from the optimization space; generating an updating signal according to a reference value corresponding to the multiple previewed results, and processing the optimization space received in the preview stage according to the reference value; and in a view stage, receiving the optimization space and the updating signal, and processing the optimization space received in the view stage according to the updating signal to generate an optimization result.

IPC Classes  ?

  • G06N 3/0985 - Hyperparameter optimisationMeta-learningLearning-to-learn

95.

METHOD FOR BEAM MANAGEMENT OF AN ANTENNA ARRAY IN AN ELECTRONIC DEVICE

      
Application Number 18242012
Status Pending
Filing Date 2023-09-05
First Publication Date 2025-03-06
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chiu, Chih-Wei
  • Chang, Wei-Hsuan
  • Kao, Yeh-Chun
  • Lee, Chih-Wei

Abstract

A beam management method of an electronic device includes transmitting a detecting signal, receiving a reflecting signal of the detecting signal, determining blocked antennas of an antenna array of the electronic device according to the reflecting signal, and exciting only unblocked antennas of the antenna array. This will improve the radiation efficiency of the antenna array.

IPC Classes  ?

  • H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
  • H04B 1/3827 - Portable transceivers
  • H04B 7/0404 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas the mobile station comprising multiple antennas, e.g. to provide uplink diversity
  • H04B 17/10 - MonitoringTesting of transmitters

96.

Method and Apparatus Using Boundary Matching for Overlapped Block Motion Compensation in Video Coding System

      
Application Number 18727004
Status Pending
Filing Date 2023-01-10
First Publication Date 2025-02-27
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chen, Chun-Chia
  • Chubach, Olena
  • Hsu, Chih-Wei
  • Chuang, Tzu-Der
  • Chen, Ching-Yeh
  • Huang, Yu-Wen

Abstract

A method and apparatus for video coding are disclosed. According to the method, a set of MC (Motion Compensation) candidates with each MC candidate comprising predicted samples for coding boundary pixels of the current block are determined. The set of MC candidates comprises a first candidate, and wherein the first candidate corresponds to a weighted sum of first predicted pixels generated according to first motion information of the current block and second predicted pixels generated according to second motion information of a neighbouring boundary block of the current block. Boundary matching costs associated with the set of MC candidates are determined respectively. A final candidate is determined from the set of MC candidates based on the boundary matching costs. The current block is encoded or decoded using the final candidate.

IPC Classes  ?

  • H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • H04N 19/182 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel

97.

Method and Apparatus of Cross-Component Linear Model Prediction with Refined Parameters in Video Coding System

      
Application Number 18728992
Status Pending
Filing Date 2023-01-18
First Publication Date 2025-02-27
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Tsai, Chia-Ming
  • Chen, Chun-Chia
  • Hsu, Chih-Wei
  • Chen, Ching-Yeh
  • Chuang, Tzu-Der

Abstract

A method and apparatus for video coding are disclosed. According to the method for the decoder side, encoded data associated with a current block comprising a first-colour block and a second-colour block are received. An inherited model parameter set is determined from a previously coded block coded in a first CCLM related mode, wherein the inherited model parameter set comprises a first scaling parameter associated with the first CCLM related mode. A final inherited model parameter set is derived if an update value for the inherited model parameter set is determined, where the final inherited model parameter set is determined based on the first scaling parameter and the update value. Then, the encoded data associated with the second-colour block are decoded using prediction data based on an updated CCLM related model associated with the final inherited model parameter set. A method and apparatus for the encoder side are also disclosed.

IPC Classes  ?

  • H04N 19/136 - Incoming video signal characteristics or properties
  • H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component

98.

Method and Apparatus of Cross-Component Linear Model Prediction in Video Coding System

      
Application Number 18728999
Status Pending
Filing Date 2023-01-18
First Publication Date 2025-02-27
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Tsai, Chia-Ming
  • Chen, Chun-Chia
  • Hsu, Chih-Wei
  • Chen, Ching-Yeh
  • Chuang, Tzu-Der

Abstract

A method and apparatus for video coding are disclosed. According to the method for the decoder side, a first syntax, related to whether the current block is coded in a CCLM related mode, is parsed from a bitstream comprising the encoded data for the current block. If the first syntax indicates the current block being coded in the CCLM related mode, a second syntax is parsed from the bitstream, wherein the second syntax is related to whether a multiple model CCLM mode is used or whether one or more model parameters are explicitly signalled or implicitly derived. The model parameters for the second-colour block are determined if the first syntax indicates the current block being coded in a CCLM related mode. The encoded data associated with the second-colour block is then decoded using prediction data comprising the cross-colour predictor for the second-colour block.

IPC Classes  ?

  • H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
  • H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
  • H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
  • H04N 19/196 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters
  • H04N 19/33 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability in the spatial domain

99.

DEVICE RESOURCES MANAGING METHOD AND IMAGE RENDERING SYSTEM

      
Application Number 18787971
Status Pending
Filing Date 2024-07-29
First Publication Date 2025-02-27
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor
  • Chen, Wei-Shuo
  • Yeh, Tsai-Yuan
  • Chen, Cheng-Che

Abstract

A device resource provisioning method is provided. The method leverages intra-frame information to optimize device resource utilization. The method involves obtaining intra-frame information of the current frame from a running application during rendering the current frame, and adjusting the device resources provided to the running application dynamically based on the intra-frame information of the current frame.

IPC Classes  ?

  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]

100.

CSI REPORTING FOR CHANNEL PART AND INTERFERENCE PART SEPARATELY

      
Application Number 18948891
Status Pending
Filing Date 2024-11-15
First Publication Date 2025-02-27
Owner MEDIATEK INC. (Taiwan, Province of China)
Inventor Tsai, Lung-Sheng

Abstract

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE measures a first set of reference signals to determine a first channel state of a first channel between a first TRP and the UE. The UE measures interference received at the UE. The UE sends a first CSI report generated corresponding to the first channel state. The UE sends a second CSI report generated corresponding to the interference.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path
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