Systems and methods for pixel-circuit supply voltage noise cancellation are described herein. In one embodiment, a pixel circuit of an imaging sensor includes: a front-end circuit having a photodiode configured to generate electrical charges that accumulate at a floating diffusion FD0 as a photodiode voltage. The pixel circuit also includes a signal storage circuit coupled to the front-end circuit, the signal storage circuit including a common floating diffusion FDC configured to store a common floating diffusion voltage corresponding to the photodiode voltage. A unity gain circuit is coupled to the signal storage circuit. The unity gain circuit includes an operational amplifier that generates a control voltage VCTRL as an output voltage. The control voltage VCTRL includes the voltage noise component of the supply voltage PIXVDD. An output circuit is configured for outputting a signal voltage VS corresponding to the floating diffusion voltage.
A micro light-emitting diode (LED) display includes a first pixel, a second pixel, and an opaque conductive element. The first pixel includes a first LED, a third LED, and a first common-interconnection electrically connected to each of the first LED and the third LED. The second pixel includes a second LED, a fourth LED, and a second common-interconnection electrically connected to each of the second LED and the fourth LED. The opaque conductive element is electrically connected to each of the first common-interconnection and the second common-interconnection.
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
3.
METHOD TO IMPLEMENT GLOBAL DIMMING FOR MICROLED DISPLAY
A micro-LED display, including a display panel with pixel circuits, wherein each pixel circuit includes at least one LED, a frame buffer configured to store display data of the display panel, a first gate driver configured to select a row of the display panel, a bit plane generator configured to and generate a plurality of bitplanes and write the display data to each pixel circuit in the row of the display panel, wherein each bitplane corresponds to a bit of the display data, where the plurality of bitplanes generates a GPWM signal for each pixel circuit of the display panel, a second gate driver configured to output a DPWM signal to each row of the display panel based on the dimming value, where each pixel circuit of the display panel is configured to merge the GPWM and DPWM signals into an FPWM to adjust a brightness of the pixel circuit.
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
4.
ON-CHIP OPEN, SHORT, AND LED VOLTAGE DETECTION METHOD FOR MICROLED OR MICROOLED
A micro-light-emitting diode (micro-LED) display comprising a plurality of rows of light-emitting diodes (LEDs), each LED of the LEDs in a row including a channel wherein each channel includes a feedback path configured to feed an anode voltage of each LED to an input of a voltage comparator, a column driver comprising a digital to analog converter (DAC) and the voltage comparator, wherein the DAC is configured to receive a plurality of voltage inputs from the resistor ladder and to provide a corresponding plurality of voltage outputs to the input of the voltage comparator, and wherein the voltage comparator is configured to successively compare individual voltage outputs of the plurality of voltage outputs received from the DAC with the anode voltage of each LED, a data latch configured to store comparison results from the voltage comparator.
G09G 3/00 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
5.
IMAGE SENSOR AND IMAGE SENSOR MANUFACTURING METHOD
A multilayer wiring layer is laminated over a wafer. Wirings formed in the multilayer wiring layer include a capacitance control wiring and an FD-SF wiring. The capacitance control wiring is capacitively coupled with a floating diffusion, and a boost signal which increases a potential of the floating diffusion is transmitted on the capacitance control wiring. The FD-SF wiring connects the floating diffusion and a source follower transistor. The multilayer wiring layer includes an FD connection layer and a first control line layer. The FD-SF wiring is formed in the FD connection layer. The capacitance control wiring is formed in the first control line layer. In the multilayer wiring layer, the first control line layer is the wiring layer closest to the FD connection layer.
An image sensor comprises a 4-cell DPD pixel array having a first group of pixels, a second group of pixels, a third group of pixels, and a fourth group of pixels. The first group of pixels comprises a first pixel, a second pixel, a third pixel, and a fourth pixel. The first pixel comprises a first photodiode, a second photodiode, a third photodiode, and a fourth photodiode. The four photodiodes are covered by a microlens. The first photodiode is diagonally binned with the fourth photodiode, and the second photodiode is counter-diagonally-binned with the third photodiode.
H04N 25/46 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
A pixel circuit includes: a phototransistor configured to receive, by one region of a source and a drain, inflow of photo-carriers generated by light entering a substrate, and configured to output a voltage signal from the one region; and a blocking layer provided on another region of the drain and the source and on a side of a channel far from a surface. The phototransistor causes a sub-threshold current to flow between the source and the drain in a pinch-off state where the photo-carriers pass through a bulk channel at a position separated from the surface in the channel. Each source and the drain of the phototransistor is periodically reset to a reset voltage. The reset voltage is set to a voltage between a voltage at which a dark current of the phototransistor becomes zero and a voltage at which a bias voltage of the phototransistor becomes zero.
Pixel designs with reduced LOFIC reset and settling times are disclosed herein. In one embodiment, a pixel cell includes a photosensor configured to photogenerate image charge in response to incident light, a floating diffusion to receive the image charge from the photosensor, a transfer transistor coupled between the floating diffusion and the photosensor to transfer the image charge to the floating diffusion, and a first reset transistor coupled between the floating diffusion and the voltage supply. The pixel cell further includes a capacitor having two ends, and a second reset transistor. A first end of the capacitor is coupled to the floating diffusion. The second reset transistor is coupled between a second end of the capacitor and the voltage supply.
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
An image sensor including a plurality of pixels arranged in a matrix. Each of the pixels includes a photodiode configured to operate both in a linear mode in which the photodiode shows a linear response to a light incident amount and in a photovoltaic mode in which the photodiode shows a logarithmic response to the light incident amount, a pixel source follower transistor configured to output a signal voltage corresponding to a signal generated based on an output of the photodiode, a pixel switch transistor configured to turn on/off an output of the pixel source follower transistor, a holding capacitor connected to an output end of the pixel switch transistor and configured to hold a voltage corresponding to the output of the photodiode, and an output source follower circuit configured to output the voltage held by the holding capacitor as a signal voltage to an AD converter.
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 25/63 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
H04N 25/65 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
A phase detection autofocus (PDAF) pixel cell and an image sensor including a PDAF pixel cell is described. The PDAF pixel cell includes a photosensitive region including one or more photodiodes formed within a semiconductor material proximate to a backside surface of the semiconductor material, a microlens optically aligned with the photosensitive region; and a spectral filter disposed between the microlens and the metal shield. A first lateral width of the spectral filter is less than a second lateral width of the metal shield along a direction parallel to the backside surface to form a gap extending from an edge of the spectral filter toward an edge of the metal shield when viewed from a plan view.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
An image sensor includes a photodiode, a floating diffusion, a ground region, a transfer channel, and an insulation film. The photodiode is formed in a lower layer of a substrate. The floating diffusion and the ground region are formed in or on top of an upper layer of the substrate. The transfer channel has a lower end connected to the photodiode. An upper end of the transfer channel is connected to the floating diffusion. The insulation film blocks at least a shortest path between the transfer channel and the ground region
A charge pump includes a flying capacitor; a push-pull driver connected to a first end of the flying capacitor; a first switch provided between the first end of the flying capacitor and a first reference conductor; a second switch provided between a second end of the flying capacitor and the first reference conductor; and a third switch provided between the second end of the flying capacitor and an output terminal. The push-pull driver includes a fourth switch and a fifth switch, each of the fourth switch and the fifth switch having a first end connected to the first end of the flying capacitor. The fourth switch has a second end connected to a second reference conductor, the second reference conductor being different from the first reference conductor. The fifth switch has a second end connected to the first reference conductor.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
An image sensor comprising a photodiode, an inter-layer dielectric layer, and a deep trench isolation structure is described. The photodiode is disposed within a semiconductor substrate having a front side and a backside opposite the front side. The inter-layer dielectric layer is disposed over the front side of the semiconductor substrate such that the front side is disposed between the inter-layer dielectric layer and the backside. The deep trench isolation structure is configured to isolate the photodiode from adjacent photodiodes included in the image sensor. The deep trench isolation structure includes a trench disposed within the inter-layer dielectric layer and the semiconductor substrate and a fill material disposed within the trench. The trench extends through the inter-layer dielectric layer and the front side of the semiconductor substrate towards the backside of the semiconductor substrate.
A liquid crystal on silicon (LCOS) device includes a liquid crystal on silicon (LCOS) module with a thermal sensor disposed on a circuit board. A compensator with a rotatable device is disposed on top of the LCOS module, and a processing device is formed on the circuit board and responsive to color-specific response trend of thermal signals to control rotation angles of the compensator according to the thermal signals received from the thermal sensor.
G02F 1/133 - Constructional arrangementsOperation of liquid crystal cellsCircuit arrangements
G02F 1/13 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
A local ramp buffer includes a deep N− well layer disposed in a P− substrate beneath a surface of the P− substrate, a P− well disposed between the surface of the P− substrate and the deep N− well layer, and an N− well structure disposed in the P− substrate and coupled to the deep N− well layer. The N− well structure is disposed between the surface of the P− substrate and the deep N− well layer. The P− well is disposed inside an opening in the N− well structure. The N− well structure and the deep N− well layer are configured to isolate the P− well within the opening. A source follower transistor is disposed in the P− well. The source follower transistor includes a gate terminal coupled to the N− well structure and a ramp generator.
A micro-LED display panel includes a pixel array that includes a plurality of pixels arranged in a plurality of rows and columns, wherein each pixel of the pixel array includes a blue LED, a green LED, and a red LED. The display further includes a frame buffer and a bitplane generator. The bitplane generator is configured to receive display data from the frame buffer and to output a color updating schedule according to the display data. The color updating schedule updates a luminance and a color of the display data for each pixel in the pixel array during each of a plurality of time intervals that define a frame time of a frame. The color updating schedule row-shifts and frame-rotates at least one row of the frame.
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
17.
PIXEL CELL FOR IMAGE SENSOR WITH VERTICAL TRANSFER GATE
A pixel cell for an image sensor is described. The pixel cell comprises a photodiode disposed within a semiconductor substrate and a transfer gate coupled to the photodiode. The photodiode includes a shallow doped region and a deep doped region, each having a same conductivity type. The shallow doped region is disposed between a first side of the semiconductor substrate and the deep doped region. The transfer gate includes a vertical portion extending into the semiconductor substrate adjacent to the shallow doped region and from the first side towards the deep doped region of the photodiode. When the pixel cell is viewed from a plan view, the shallow doped region includes a base segment and a protrusion extending from the base segment. The protrusion is separated from the vertical portion by a first lateral separation distance and the base segment is separated from the vertical portion by a second lateral separation distance different from the first lateral separation distance.
An event-based vision sensor is provided. The event-based vision sensor comprises an event-based vision sensor pixel array, an always-on row scanner, an always-on column scanner, a major row scanner and a major column scanner. The event-based vision sensor pixel array comprises a plurality of always-on pixels and a plurality of major pixels. The always-on row scanner and the always-on column scanner are for the plurality of always-on pixels. The major row scanner and the major column scanner are for the plurality of major pixels. When the event-based vision sensor is configured to be operated in an always-on mode, the plurality of major pixels are powered down, and the plurality of always-on pixels, the always-on row scanner and the always-on column scanner are in operation.
H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data
H04N 25/42 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
H04N 25/702 - SSIS architectures characterised by non-identical, non-equidistant or non-planar pixel layout
H04N 25/709 - Circuitry for control of the power supply
19.
Quad-Photodiode (QPD) Image Deblurring Using Convolutional Neural Network
A blurred QPD image is divided into an Up-left (Ul) view, an Up-right (Ur) view, a Down-left (Dl) view, and a Down-right (Dr) view. A U view is the mean of the Ul view and the Ur view, a D view is the mean of the Dl view and the Dr view, a L view is the mean of the Ul view and the Dl view; and a R view is the mean of the Ur view and the Dr view. The U view, the D view, the L view, and the R view are input into a convolutional neural network (CNN). The CNN outputs an output Bayer image, which is a deblurred image of the blurred QPD image.
An image sensor for color imaging using arbitrary-color-filter-array event data is provided. The image sensor comprises: a plurality of color imaging pixels and a plurality of color event pixels. An image signal of a first color imaging pixel included in the plurality of color imaging pixels is determined based on a first color signal of the first color image pixel and at least a color event data of one or more color event pixels included in the plurality of color event pixels. The color event data is generated in a temporal relation to the generation of the first color signal.
An image sensor is described. The image sensor includes a plurality of pixel cells arranged to form an image sensor array disposed in or on a semiconductor substrate, a proximal metal layer, and a light balancing structure. Each pixel cell included in the plurality of pixel cells includes one or more photodiodes disposed between a first side and a second side, opposite of the first side, of the semiconductor substrate. The proximal metal layer is included in an interconnect stack disposed proximate to the second side of the semiconductor substrate. The light balancing structure is disposed between the second side of the semiconductor substrate and the proximal metal layer. The light balancing structure includes a plurality of discrete segments optically aligned with a first type of pixel cells included in the plurality of pixel cells.
In a case where a photodiode is in a saturated state, the photodiode can be transited from the saturated state to an unsaturated state during a period when a knee pulse is supplied from a knee pulse supplying unit. The knee pulse supplying unit preferably supplies the knee pulse a plurality of times during one frame period.
An image sensor includes a sensor substrate and a circuit substrate. The sensor substrate includes a plurality of sensor substrate-side pixels. Each of the sensor substrate-side pixels includes a photodiode configured to operate in a photovoltaic mode, a reset transistor configured to reset the photodiode, and a pixel source follower transistor connected to an output of the photodiode. The circuit substrate includes circuit substrate-side pixels corresponding to the respective sensor substrate-side pixels of the sensor substrate. Each of the circuit substrate-side pixels includes a peak hold circuit configured to hold a peak of an output of the pixel source follower transistor by receiving the output of the pixel source follower transistor, and a readout source follower transistor configured to read out a voltage held in a holding capacitor. The sensor substrate-side pixels and the respective corresponding circuit substrate-side pixels are connected to each other.
H04N 25/60 - Noise processing, e.g. detecting, correcting, reducing or removing noise
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
A pixel circuit, including a pixel array comprising a plurality of pixels, a plurality of analog to digital converters (ADCs), where during a pixel data readout the plurality of ADCs is communicatively coupled to a respective pixel of the plurality of pixels to receive image data from the respective pixel of the plurality of pixels, a plurality of judge blocks, wherein each judge block is communicatively coupled to a respective ADC of the plurality of ADCs and wherein each judge block is configured to select and transmit gain data based on comparing an output of the respective ADC to a predetermined threshold for the respective ADC, and an image signal processor (ISP) configured to receive outputs from the plurality of ADCs, and combine the outputs of the plurality of ADCs to produce a combined converted value for the respective pixel.
The present disclosure provides a camera system and an event-assisted image processing method. The camera system includes an image sensor, an event-based sensor, and a processing unit. The image sensor is configured to capture visual images of a targeted scene to obtain image sensing frames with a first frequency. The event-based sensor is configured to capture event data of the targeted scene to obtain event frames with a second frequency higher than the first frequency. The processing unit is configured to: receiving the image sensing frames within a predetermined time period; accumulating the event frames within the predetermined time period; generating a temporal-spatial mask indicating interested areas for the event frames; determining geometric features in the temporal-spatial masks; synchronizing the image sensing frames and the event frames at timestamps within the predetermined time period; and fusing the temporal-spatial mask with the image sensing frames to obtain a masked visual image.
H04N 23/45 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
An example liquid crystal display device includes a reflective display backplane and one or more integrated circuit substrates arranged in a stacked configuration. The reflective display backplane includes an array of reflective pixel mirrors and a corresponding array of data latches. The top face of one integrated circuit substrate is connected to the back side of the reflective display backplane and is configured as a display driver, providing control signals to the reflective display backplane using a set of through-silicon-vias. Optionally, another integrated circuit substrate is connected (face-to-back) to the one integrated circuit substrate and is configured to provide virtual reality, augmented reality, and/or other video processing support to the display driver. An example embodiment is provided with a chip-scale-package structure formed on the bottom integrated circuit substrate of the stack.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
27.
LOFIC ANTI-LAG METHODS WITH REVERSE BIAS OPTIMIZATION, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
Lateral overflow integration capacitor (LOFIC) anti-lag methods with reverse bias optimization (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a method comprises, during a pixel LOFIC idle period for a pixel, applying a reverse bias to a LOFIC of the pixel for a first time period and applying a 0V bias to the LOFIC of the pixel for a second time period. Applying the reverse bias to the LOFIC can include (i) coupling a first metal electrode of the LOFIC to a power source and (ii) coupling a second metal electrode of the LOFIC to a bias voltage source. Applying the 0V bias to the LOFIC can include shorting the first metal electrode and the second metal electrode of the LOFIC to the power source.
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
A pixel circuit includes a pixel array and a color filter. The pixel array includes a plurality of pixels arranged in rows and columns, each pixel including four photodiodes, a floating diffusion, and four transfer transistors. The color filter array includes a plurality of color filters each having one of a plurality of colors and disposed over at least one of the pixels. Each of the plurality of pixels is coupled to a first readout circuit, and the plurality of pixels includes (i) a first subset of the pixels not coupled to a second readout circuit and (ii) a second subset of the pixels coupled to the second readout circuit. Floating diffusions of two diagonally arranged pixels are coupled together, and the two diagonally arranged pixels coupled together are disposed underneath color filters of a same color.
Hybrid image sensors with multiple operating modes are disclosed herein. In one embodiment, a pixel arrangement includes a first photosensor, a first floating diffusion, a second photosensor, a second floating diffusion, and a mode switch. The mode switch can include (a) a first switch selectively coupling the second floating diffusion to the first floating diffusion, and (b) a second switch configured to selectively couple the second floating diffusion to event vision sensor (EVS) readout circuitry. The mode switch can be used to transition the pixel arrangement between (i) a first mode in which the pixel arrangement is controllable to output intensity information corresponding to first light incident on the first photosensor and/or second light incident on the second photosensor, and (ii) a second mode in which the pixel arrangement is controllable to output contrast information corresponding to the first light and/or the second light.
H04N 23/667 - Camera operation mode switching, e.g. between still and video, sport and normal or high and low resolution modes
H04N 25/42 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
30.
PIXELS WITH MULTIPLE OPERATING MODES, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
Pixels with multiple operating modes (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a pixel arrangement includes a pixel including a first photosensor, a second photosensor, a floating diffusion, a first event vision sensor (EVS) connection coupling the pixel to first EVS readout circuitry and configured to receive first charge from the first photosensor, and a second EVS connection coupling the pixel to second EVS readout circuitry and configured to receive second charge from the second photosensor. The pixel further includes a first transfer transistor selectively coupling the first photosensor to the floating diffusion, a second transfer transistor selectively coupling the first photosensor to the first EVS connection, and a third transfer transistor selectively coupling the second photosensor to the floating diffusion. In some embodiments, the pixel further includes a fourth transfer transistor selectively coupling the second photosensor to the second EVS connection.
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 23/667 - Camera operation mode switching, e.g. between still and video, sport and normal or high and low resolution modes
H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data
H04N 25/621 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
A pixel circuit includes a pixel array and a color filter. The pixel array includes pixels arranged in rows and columns, and each pixel includes a photodiode configured to photogenerate image charge in response to incident light, and a transfer transistor coupled to the photodiode to transfer the image charge out from the photodiode. The color filter array includes color filters each having one of a plurality of colors and disposed over at least one of the pixels. Each of the pixels is coupled to a first readout circuit, and the plurality of pixels includes a first subset of the pixels not coupled to a second readout circuit and a second subset of the pixels coupled to the second readout circuit. Two diagonally arranged pixels are coupled together to share a floating diffusion, and the two diagonally arranged pixels coupled together are disposed underneath color filters of a same color.
H04N 25/11 - Arrangement of colour filter arrays [CFA]Filter mosaics
H04N 23/667 - Camera operation mode switching, e.g. between still and video, sport and normal or high and low resolution modes
H04N 25/42 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
32.
HYBRID IMAGING SENSOR WITH HIGH SAMPLING POINT DISTRIBUTION
A pixel array includes photodiodes and a color filter array. A first fraction of the photodiodes is included in CIS pixels and a second fraction of the photodiodes is included in hybrid CIS/EVS pixels. The photodiodes are arranged into groupings. The color filter array includes first, second, and third color filters arranged in a mosaic pattern over the photodiodes. Each grouping includes a plurality of subgroupings including a first subgrouping disposed under at least one of the first color filters, a second subgrouping disposed under at least one of the second color filters, and a third subgrouping disposed under at least one of the third color filters. Each of the first, second, and third subgroupings includes at least one CIS pixel, and at least one of the first subgrouping of photodiodes further includes at least one hybrid CIS/EVS pixel disposed under at least one of the first color filters.
A pixel circuit includes a pixel array and a color filter. The pixel array includes a plurality of pixels each comprising two photodiodes, a floating diffusion coupled between the two photodiodes, and two transfer transistor coupled between the two photodiodes and the floating diffusion. The color filter array includes a plurality of color filters each having one of a plurality of colors and disposed over at least one of the pixels. Each pixel is coupled to a first readout circuit. The pixels include a second subset of the pixels coupled to a second readout circuit and a first subset of the pixels not coupled to the second readout circuit. Each pair of pixels arranged in two adjacent rows includes a first pixel included in the second subset of the pixels and a second pixel included in the first subset of the pixels and disposed underneath one of the color filters.
H04N 25/42 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
An image sensor includes: a photodiode configured to be reset for each one frame period, to accumulate charges corresponding to incident light for one frame period, and to output an output voltage corresponding to the accumulated charges; and a holding capacitor configured to accumulate charges corresponding to an output signal of the photodiode. The output signal of the photodiode for one frame is integrated, the integrated output signal is accumulated in the holding capacitor, and a first signal is output. After the holding capacitor is refreshed, a voltage corresponding to the output voltage of the photodiode is held in the holding capacitor, and a second signal is output.
H04N 23/745 - Detection of flicker frequency or suppression of flicker wherein the flicker is caused by illumination, e.g. due to fluorescent tube illumination or pulsed LED illumination
H04N 25/65 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
An image sensor includes a plurality of pixels and includes a photodiode configured to operate in both modes of a linear mode for linearly responding to a light incident amount and a photo-voltaic mode for logarithmically responding to the light incident amount, a source follower circuit configured to output a signal voltage according to a signal generated according to an output of the photodiode, an AD converter configured to convert the signal voltage output from the source follower circuit into digital signal data, a frame memory configured to store signal data of one frame, and a conversion function configured to generate, from signal data of a current frame and signal data of a previous frame, an optical signal relating to the light incident amount.
H04N 25/65 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
H04N 23/667 - Camera operation mode switching, e.g. between still and video, sport and normal or high and low resolution modes
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
36.
HYBRID IMAGE SENSORS WITH VIDEO FRAME INTERPOLATION
Hybrid image sensors with video frame interpolation (and associated systems, devices, and methods) are disclosed herein. In one embodiment, an imaging system comprises one or more event vision sensor (EVS) pixels, and a plurality of CMOS image sensor (CIS) pixels. Each EVS pixel can be configured to capture event data corresponding to contrast information of light incident on the EVS pixel. Each CIS pixel can be configured to capture CIS data corresponding to intensity of light incident on the CIS pixel. The imaging system can further comprise a deblur circuit configured to deblur the CIS data captured by the plurality of CIS pixels using a first portion of the event data captured by the one or more EVS pixels, and a system processor configured to interpolate a video frame using the deblurred CIS data and all or a subset of the event data.
H04N 23/68 - Control of cameras or camera modules for stable pick-up of the scene, e.g. compensating for camera body vibrations
H04N 23/84 - Camera processing pipelinesComponents thereof for processing colour signals
H04N 25/531 - Control of the integration time by controlling rolling shutters in CMOS SSIS
H04N 25/766 - Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
37.
HYBRID IMAGE SENSORS WITH ADJUSTABLE CONTRAST THRESHOLDS
Hybrid image sensors with adjustable contrast thresholds (and associated systems, devices, and methods) are disclosed herein. In one embodiment, an imaging system comprises one or more event vision sensor (EVS) pixels, and a plurality of CMOS image sensor (CIS) pixels. Each EVS pixel can be configured to, based on a contrast threshold, capture event data corresponding to contrast information of light incident on the EVS pixel. Each CIS pixel can be configured to capture CIS data corresponding to intensity of light incident on the CIS pixel. The imaging system can further comprise (i) a contrast threshold calibration circuit configured to adjust a value of the contrast threshold over time, and (ii) a deblur circuit configured to generate deblurred image data by deblurring the CIS data captured by the plurality of CIS pixels using at least a portion of the event data captured by the one or more EVS pixels.
H04N 23/45 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data
H04N 25/531 - Control of the integration time by controlling rolling shutters in CMOS SSIS
H04N 25/62 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
H04N 25/76 - Addressed sensors, e.g. MOS or CMOS sensors
38.
METHODS FOR OPERATING HYBRID IMAGE SENSORS HAVING DIFFERENT CIS-TO-EVS RESOLUTIONS
Methods for operating hybrid image sensors having different CIS-to-EVS resolutions (and associated systems, devices, and methods) are disclosed herein. In one embodiment, an imaging system includes a hybrid image sensor including (a) an event driven sensing array including one or more event vision sensor (EVS) pixels arranged in one or more EVS pixel rows and configured to capture EVS data having an EVS resolution, and (b) a pixel array including a plurality of CMOS image sensor (CIS) pixels arranged in one or more CIS pixel rows and configured to capture CIS data having a CIS resolution. The imaging system can further include control circuitry configured to adjust the CIS resolution of the CIS data and/or the EVS resolution of the EVS data such that a mismatch between the CIS resolution and the EVS resolution is reduced.
H04N 25/42 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
H04N 25/46 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data
Hybrid image sensors with on-chip image deblur and rolling shutter distortion correction (and associated systems, devices, and methods) are disclosed herein. In one embodiment, an image sensor includes (a) an event driven sensing array including one or more event vision sensor (EVS) pixels, each configured to capture event data corresponding to contrast information of light incident on the EVS pixel; (b) a pixel array including a plurality of CMOS image sensor (CIS) pixels arranged in one or more CIS pixel rows, each CIS pixel configured to capture CIS data corresponding to intensity of light incident on the CIS pixel, and (c) a rolling shutter distortion correction circuit configured to correct the CIS data for rolling shutter distortion using the event data.
H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data
H04N 25/531 - Control of the integration time by controlling rolling shutters in CMOS SSIS
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/767 - Horizontal readout lines, multiplexers or registers
H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
Hybrid image sensors with on-chip image deblur (and associated systems, devices, and methods) are disclosed herein. In one embodiment, an image sensor includes (a) a plurality of CMOS image sensor (CIS) pixels configured to capture CIS data corresponding intensity of light incident on CIS pixels of the plurality of CIS pixels, (b) an event vision sensor (EVS) pixel configured to capture EVS data corresponding to events detected in light incident on the EVS pixel, and (c) a deblur circuit configured to generate deblurred image data based on the CIS data and an accumulation of events in the EVS data. The deblur circuit can be configured to compute the accumulation of events, such as using an event-based double integral model.
An image sensor comprises a pixel array having a color filter array including a minimal repeating unit, where the minimal repeating unit consists of 4×4 pixels including two red pixels, four green pixels, two blue pixels, and eight clear pixels. When clear pixels are saturated and blooming, a blue pixel is affected by three or two clear pixels, but not four clear pixels.
H04N 25/621 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
H04N 25/11 - Arrangement of colour filter arrays [CFA]Filter mosaics
A pixel circuit includes: a photodiode configured to operate in a photovoltaic mode and to accumulate charges corresponding to an incident light amount; a reset transistor configured to reset the accumulated charges of the photodiode; and a peak hold circuit configured to hold an output corresponding to the accumulated charges of the photodiode, the peak hold circuit including a peak hold transistor connected to an output end of the photodiode, a switching transistor configured to turn on/off an output of the peak hold transistor, and a holding capacitor configured to hold an output of the switching transistor. The peak hold transistor operates in a state where no carrier charge or only one carrier charge is present on a channel.
Image sensors with improved memory effect are disclosed herein. In one embodiment, a method for reducing image lag associated with a pixel included in a plurality of pixels is described. The pixel includes a photodiode, a first floating diffusion coupled to the photodiode through a transfer transistor, a second floating diffusion coupled to the first floating diffusion through a dual floating diffusion transistor, and a lateral overflow integration capacitor coupled between the second floating diffusion and a bias voltage source. The lateral overflow integration capacitor is further coupled to a pixel reference voltage source through a reset transistor. Operation of the pixel comprises an idle period and an integration period after the idle period. The method also includes configuring the lateral overflow integration capacitor to be either zero-biased or forward-biased during the idle period.
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/709 - Circuitry for control of the power supply
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
44.
EVENT VISION SENSORS WITH DEFECT PIXEL SUPPRESSION, INCLUDING EVENT VISION SENSORS WITH IN-PIXEL DEFECT PIXEL SUPPRESSION BASED ON NOISE EVENT OCCURRENCE FIRING RATES, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
Event vision sensors with defect pixel suppression (and associated methods) are disclosed herein. In one embodiment, an event vision sensor includes an array of event vision pixels and an event signal processor. The event signal processor is configured to identify event vision pixels of the array that are defective based on noise event occurrence firing rates corresponding to the event vision pixels. The noise event occurrence firing rate for each event vision pixel can be based on inter-arrival times or a noise event rate corresponding to that event vision pixel. Each event vision pixel can include internal circuitry (e.g., a memory component, such as a latch) that can, when the event vision pixel is identified as defective, be used to disable the event vision pixel from detecting events or to mask an output of the event vision pixel such that events are not read out of the event vision pixel.
H04N 25/68 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to defects
H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data
45.
EVENT VISION SENSORS WITH DEFECT PIXEL SUPPRESSION, INCLUDING EVENT VISION SENSORS WITH IN-PIXEL DEFECT PIXEL SUPPRESSION BASED ON PROBABILISTIC DETERMINATION OF NOISE EVENT OCCURRENCE FIRING RATES, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
Event vision sensors with defect pixel suppression (and associated methods) are disclosed herein. In one embodiment, an event vision sensor includes an array of event vision pixels and an event signal processor. The event signal processor is configured to identify event vision pixels of the array that are defective based on noise event occurrence firing rates corresponding to the event vision pixels. The noise event occurrence firing rate for each event vision pixel can be based on measurements of a probability of that event vision pixel detecting a noise event over time. Each event vision pixel can include internal circuitry (e.g., a memory component, such as a latch) that can, when the event vision pixel is identified as defective, be used to disable the event vision pixel from detecting events or to mask an output of the event vision pixel such that events are not read out of the pixel.
H04N 25/683 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to defects by defect estimation performed on the scene signal, e.g. real time or on the fly detection
A pixel of an image sensor includes a photodiode, a reset transistor, a peak hold transistor, and a first capacitor and a second capacitor. The pixels include, a first mode in which the noise and image output voltages of the photodiode are held in the first and second capacitors, respectively, and a second mode in which the output voltage of the photodiode in a state where the reset transistor is turned on to reset the photodiode is held in the first capacitor or the second capacitor. In the first mode, an image signal corresponding to the light incident amount of the photodiode and a noise signal when the light incident amount is relatively low are obtained. In the second mode, a noise signal when the light incident amount of the photodiode is relatively high is obtained.
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/65 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
An image sensor is an image sensor including a plurality of pixels. Each of the pixels includes a photodiode configured to generate charges based on a light incident amount, a reset transistor configured to reset the photodiode by supplying a reset voltage to the photodiode, a first capacitor configured to hold an output voltage of the photodiode immediately after the reset, and a second capacitor configured to hold the output voltage of the photodiode after a predetermined exposure period. An image signal is obtained from the voltage held by the first capacitor and the voltage held by the second capacitor.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/62 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
H04N 25/65 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
48.
MULTIPLE READ IMAGE SENSORS, AND ASSOCIATED METHODS FOR THE SAME
Multiple read image sensors, and associated methods for the same, are disclosed herein. In one embodiment, a method comprises reading out a reset level from a pixel to a corresponding sample and hold circuit; storing the reset level to a first storage device and to a second storage device of the sample and hold circuit; reading out a signal level from the pixel to the sample and hold circuit; and storing the signal level to a third storage device and to a fourth storage device of the sample and hold circuit. The reset level and the signal level can correspond to a same correlated double sampling of an image data signal captured by the pixel. The method can further include reading out the reset level from the first storage device; reading out the signal level from the third storage device; and recovering a first copy of the image data signal.
A method of counting photons using a plurality of single photon avalanche diodes (SPADs), including initiating a detection phase, enabling each single photon avalanche diode (SPAD) of the plurality of SPADs for a period of time within the detection phase, accumulating a SPAD event from each SPAD of the plurality of SPADs, wherein each SPAD event corresponds to a detection of a single photon, determining a counter code at an end of the detection phase, where the counter code corresponds to accumulated SPAD events, and enabling one or more SPADs of the plurality of SPADs within an exposure phase based on the counter code, where the counter code is greater than an expected number of the SPAD events during the exposure phase, and where the expected number of SPAD events during the exposure phase is based on the counter code that is determined at the end of the detection phase.
A pixel circuit including a transistor, a blocking layer and an output circuit is disclosed. The transistor includes a first doped region and a second doped region disposed on opposite sides of a channel of the transistor proximate to a first surface of a semiconductor substrate such that photo-carriers generated inside the semiconductor substrate in response to incident light flow into one region of the first and second doped regions. The blocking layer is disposed between the other region of the first and second doped regions and a second surface of the semiconductor substrate opposite to the first surface. The blocking layer configured to block the photo-carriers from flowing into the other region of the first doped region and the second doped region directly. The output circuit outputs an image signal according to a voltage signal outputted from the transistor.
A pixel circuit includes: a phototransistor configured to receive, by one region of a source and a drain, inflow of photo-carriers generated by light entering a substrate, and configured to output a voltage signal from the one region; and a blocking layer provided on another region of the drain and the source and on a side of a channel far from a surface, and configured to prevent the photo-carriers from directly flowing into the other region. The phototransistor causes a sub-threshold current to flow between the source and the drain in a pinch-off state. Each of the source and the drain of the phototransistor is periodically reset to a reset voltage. The reset voltage is set to a voltage between a voltage at which a dark current of the phototransistor becomes zero and a voltage at which a bias voltage of the phototransistor becomes zero.
An image sensor is described. The image sensor comprises a plurality of pixels arranged to form an active pixel array, a plurality of contact pads disposed within a peripheral region of the image sensor that surrounds the active pixel array, and an optical structure disposed within the peripheral region between the plurality of contact pads and the active pixel array. The optical structure is adapted to mitigate stray light from reaching the active pixel array.
A sample and hold readout system and method for ramp analog to digital conversion is presented in which an optical array is read out using a sample and hold circuit such that each sample is used to charge a sample and hold capacitor and is read out during a hold phase using an amplifier that drives an ramp analog to digital converter. The sample and hold circuit transitions to a tracking phase wherein the optical array input drives an amplifier that drives the sample and hold capacitor then transitions to a sample phase where the sample and hold capacitor is connected to the optical array output directly.
H03M 1/34 - Analogue value compared with reference values
H03M 1/56 - Input signal compared with linear ramp
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
An imaging system comprises a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells. Each column unit cell comprises at least one of a plurality of comparators, wherein each comparator is coupled to receive the ramp signal from the ramp generator through a ramp signal line. Each column unit cell also comprises a compensation current unit coupled to the ramp signal line, each compensation current unit comprising a compensation current source and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node on the ramp signal line and a second node.
An imaging system comprises a pixel array and readout circuitry coupled to the pixel array. The readout circuitry includes a ramp generator and a plurality of column unit cells, each comprising a column ramp buffer and a column comparator, and each column ramp buffer comprising an input node coupled to receive a ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator, and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit comprises a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor.
H04N 25/677 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction for reducing the column or line fixed pattern noise
H04N 25/766 - Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
A multichannel endoscope system includes a light module configured to emit illumination light on an object, an image module configured to capture an image of the object, and a multichannel sensor module configured to obtain a spectral information of the object. The multichannel sensor module includes an image lens, a light homogenizer and a multichannel array sensor, where the light homogenizer is formed between the multichannel array sensor and the image lens.
A61B 1/05 - Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopesIlluminating arrangements therefor combined with photographic or television appliances characterised by the image sensor, e.g. camera, being in the distal end portion
A61B 1/06 - Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopesIlluminating arrangements therefor with illuminating arrangements
A pixel array includes a plurality of pixel cells, each including a photodiode configured to photogenerate image charge in response to the incident light, a first floating diffusion (FD) coupled to receive the image charge from the photodiode, a reset transistor coupled between a voltage source and the first FD, a second FD coupled between the first FD and ground, a first dual FD transistor coupled between the first and second FDs. Second FDs of first and second pixel cells are coupled. Second FDs of third and fourth pixel cells are coupled.
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
An image sensor comprises: a control block generating a video interface enabled signal, a video interface for receiving the video interface enabled signal, a pixel array for providing a video stream to the video interface, an output port for receiving the video stream from the video interface and outputting the video stream to outside of the image sensor, a stream indicator pin for receiving the video interface enabled signal from the control block when the video interface is receiving the video interface enabled signal from the control block, where a terminal of the video interface receiving the video interface enabled signal is connected to the stream indicator pin by a conductor, and they are sealed in a package of the image sensor.
09 - Scientific and electric apparatus and instruments
10 - Medical apparatus and instruments
Goods & Services
Integrated circuits; video processors; microchip image
processors; optical image sensors; optical lenses for use
with image sensors; optical aspheric lenses and lens
assemblies being optical lenses for use in combination with
digital signal processing to produce and improve images;
semiconductor chips and optical lenses for capturing and
processing digital images and video; optical sensors with
integrated optical lenses for capturing and processing
digital images and video; optical inspection apparatuses for
imaging; image signal processing semiconductor chips for use
with image sensors to capture, process or improve digital
images and video; integrated circuits, semiconductor chips
and optical lenses for capturing and processing digital
images and video; optical sensors with integrated optical
lenses for capturing and processing digital images and
video; image signal processing semiconductor chips for use
with image sensors to capture, process or improve digital
images and video; optical sensors, namely, wafer level
optics in the nature of wafer level image sensor modules for
use in mobile phones, tablets, notebook computers, personal
computers, digital video camcorders, video cameras and
recorders, video game consoles used with televisions,
automobiles, medical devices, namely, endoscopes and
catheters, disposable medical guidewires, security systems,
robotic devices, drones, and augmented reality (AR) and
virtual reality (VR) devices, namely, headsets, glasses,
data gloves, and electrical controllers; endoscope cameras
for non-medical use; rigid and flexible endoscopes for
non-medical use; guidewires being electric wires for
non-medical use; interface circuits for video cameras;
electronic display interfaces; interfaces and peripheral
devices for computers. Medical imaging endoscopy cameras for medical purposes,
namely, encephaloscopes, esophagoscopes, thoracoscopes,
angioscopes, gastroscopes, proctoscopes, colonoscopes,
arthroscopes, rhinoscopes, laryngoscopes, bronchoscopes,
mediastinoscopes, nephroscopes, laparoscopes, amnioscopes,
cystoscopes, hysteroscopes; endoscopy medical imaging
cameras for endoscopes and medical purposes, namely,
catheter cameras; endoscope cameras for medical use; medical
endoscopes; catheters; medical guidewires; medical imaging
apparatus.
60.
COLOR ROUTER BASED PHOTODIODES AND INTEGRATED PIXEL CIRCUIT
Color router based photodiodes and integrated pixel circuit. In one embodiment, a plurality of pixels arranged in rows and columns of a pixel array are disposed in a semiconductor material. In some embodiments, each pixel comprises a plurality of photodiodes and a color router covering the plurality of photodiodes. In some embodiments, the plurality of pixels is configured to receive an incoming light through the color router. In some embodiments, the integrated pixel circuit includes a plurality of pixel circuits, where each pixel circuit is associated with a corresponding pixel of the plurality of pixels. In some embodiments, the pixel circuits are configured on a same horizontal plane as the plurality of photodiodes.
A gated imaging system includes a pulsed illuminator configured to generate a plurality of light pulses and a pixel circuit. The pixel circuit includes a photodiode configured to collect photogenerated image charge in response to incident light, a floating diffusion coupled to receive the image charge from the photodiode, a sense node amplifier includes a gate terminal coupled to the floating diffusion, and a storage network coupled between the photodiode and the floating diffusion. The storage network includes a plurality of memory nodes coupled between the photodiode and the floating diffusion in parallel. The storage network is configured to capture a plurality of depth slices between two successive ones of the light pulses.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 23/56 - Cameras or camera modules comprising electronic image sensorsControl thereof provided with illuminating means
A time-of-flight pixel array includes first transistors to transfer a first phase portion of charge from photodiodes responsive to reflected modulated light during a first subframe, and a second phase portion of the charge during a second subframe. The second phase is an inverted first phase. Second transistors transfer the second phase portion of the charge during the first subframe, and the first phase portion of the charge during the second subframe. Third transistors transfer a third phase portion of the charge during the first subframe, and a fourth phase portion of the charge during the second subframe. The fourth phase is an inverted third phase. The third phase is ninety degrees out of phase with the first phase. Fourth transistors transfer the fourth phase portion of the charge during the first subframe, and the third phase portion of the charge during the second subframe.
G01S 7/4863 - Detector arrays, e.g. charge-transfer gates
G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
G01S 17/26 - Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves wherein the transmitted pulses use a frequency-modulated or phase-modulated carrier wave, e.g. for pulse compression of received signals
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
63.
Full green interpolation in remosaicing Bayer pattern
A method for full interpolating green pixels from an input image having a first minimum repeating unit comprising 4×4 pixels, where 2×2 pixels of same color are grouped together, comprises down sampling of the input image to a first down sampled image, down sampling of the input image to a second down sampled image, and interpolating green pixels resulting in an interpolated green down sampled image, where the interpolating uses jointly the first down sampled image and the second down sampled image. The interpolated green pixels in an interpolated green down sampled image are further up sampled resulting in a full interpolated green image.
An image sensor comprising a semiconductor substrate, a first source region, a second source region, and a shared gate electrode is described. The semiconductor substrate includes a first side and a second side opposite the first side. The first source region and the second source region are each disposed within the semiconductor substrate proximate to the first side. The first source region is separated from the second source region by an isolation structure disposed within the semiconductor substrate between the first source region and the second source region. The shared gate electrode is disposed proximate to the first side of the semiconductor substrate and coupled to the first source region and the second source region to respectively form a first transistor and a second transistor.
Event vision sensors with event data compression, including event vision sensors with in-pixel event data compression, and associated systems, devices, and methods
Event vision sensors with event data compression (and associated systems, devices, and methods) are disclosed herein. In one embodiment, an event vision sensor includes a plurality of event vision pixels. Each event vision pixel of the plurality is configured to generate event data based on events indicated in incident light received from an external scene, and includes a compression circuit configured to compress the event data prior to readout of the event data from the event vision pixel. Each compression circuit can include a time aggregation circuit that is configured to track a number of the events detected by the corresponding event vision pixel over a specified timing window. The compressed event data can be read out from the event vision sensors and used to generate a pseudo-frame. The event vision sensor can optionally perform frame-level compression on the pseudo-frame.
H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 25/42 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.
H03K 5/22 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
67.
SPARSE 4C2+ PHASE DETECTION AUTO FOCUS AND CORRELATED MULTIPLE SAMPLING
An arithmetic logic unit includes a GC to binary stage, an adder stage, an adder output stage, an adder input latch stage coupled to latch outputs of the GC to binary stage, a feedback multiplexer stage coupled to receive the outputs of the GC to binary stage, a latch output multiplexer coupled to receive outputs of the first adder input latches, where the latch output multiplexer is configured to multiply the outputs of the first adder input latches by either −1 or −2, and an adder input multiplexer stage, where first inputs of the adder input multiplexer stage are coupled to receive outputs of the latch output multiplexer and second inputs of the adder input multiplexer stage are coupled to receive outputs of the second adder input latches. The arithmetic logic performs adaptive correlated multiple sampling for image sensing pixels and phase detection auto focus for other pixels.
An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
An imaging system comprising a phase-detection image sensor comprising a plurality of phase-detection pixel units and a processor configured to: interpolate a green image to obtain a full resolution interpolated green image including defocused portions having artifacts and in-focus portions having sharp image, low-pass filter the full resolution interpolated green image to obtain a blurred image of the interpolated green image, combine the full resolution interpolated green image and the blurred image of the full resolution interpolated green image to obtain a corrected full resolution interpolated green image, where the artifacts of the defocused portions of the full resolution interpolated green image are removed, and the sharp image of the in-focus portions of the full resolution interpolated green image is unaffected.
A pixel array substrate includes a semiconductor substrate including a pixel array, a first side, and a second side opposite the first side, a guard ring region in the semiconductor substrate, formed of a doped semiconductor, enclosing the pixel array, and extending into the semiconductor substrate from the first side, and a peripheral region in the semiconductor substrate and enclosing the guard ring region. The peripheral region includes at least one device and a deep trench isolation (DTI) structure region disposed between the guard ring region and the at least one device and proximate to the second side of the semiconductor substrate. The DTI structure region is configured to block an electric current path between a P-N junction in the guard ring region and the at least one device.
An image sensor package with a multi-step cavity formed in or on a substrate, which includes an image sensor bonded onto bottom of the multi-step cavity, and a cover glass placed and sealed on a lower portion of the multi-step cavity. Lower portion of the multi-step cavity includes at least a first and a second raised-step structures protruding from the bottom of the multi-step cavity, and the cover glass is placed and sealed over the first raised-step structure.
An imaging system includes a pixel array with odd and even pixel cells. Each of the odd and even pixel cells includes a photodiode, a floating diffusion, a transfer transistor, a reset transistor, a lateral overflow integration capacitor (LOFIC), and an overflow gate (OFG) transistor. The imaging system further includes a readout circuit with a sample and hold (SH) circuit and an analog to digital converter. The OFG transistor of each of the odd and even pixel cells is configured to direct the image charge photogenerated by the respective photodiode away from the respective transfer transistor and reduce photodiode exposure shift during LOFIC readouts during a global transfer period.
A method for convolution calculation in a neural network is provided. The method comprises: decomposing each weight into multiple sub-weights, each with only one valid bit, representing different bit significance (bit plane); accumulating input feature map units corresponding to each of the sub-weights with the same bit significance to obtain intermediate sums; shifting each of the intermediate sums according to the bit significance of the corresponding sub-weights to obtain shifted intermediate sums; and accumulating the shifted intermediate sums.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
A pixel includes a semiconductor substrate having a first side and a second side. Extending from the first side is a first deep trench isolation (DTI) structure and a second DTI structure. The first DTI structure includes a wide portion and a narrow portion extending from the wide portion. A first width of the wide portion is greater than a second width of the narrow portion, and the wide portion extends to a first depth. The pixel further includes a photodiode region disposed in the semiconductor substrate between the first DTI structure and the second DTI structure. A cell deep trench isolation (CDTI) structure is disposed between the wide portion of the first DTI structure and the second DTI structure. The CDTI structure extends to a second depth. The first depth and the second depth extend a substantially equal distance from the first side of the semiconductor substrate.
A curved-surface image-sensor assembly has a porous carrier having a concave surface with a thinned image sensor bonded by an adhesive to its concave surface of the porous carrier; the porous carrier is mounted into a water-resistant package. The sensor assembly is made by fabricating a thinned, flexible, image-sensor integrated circuit (IC) and applying adhesive to a non-illuminated side of the IC; positioning the IC over a concave surface of a porous carrier; applying vacuum through the porous carrier to suck the IC onto the concave surface of the porous carrier; and curing the adhesive to bond the IC to the concave surface of the porous carrier.
A pixel circuit includes a photodiode configured to photogenerate charge in response to reflected modulated light incident upon the photodiode. A first floating diffusion is configured to store a first portion of charge photogenerated in the photodiode. A first transfer transistor is configured to transfer the first portion of charge from the photodiode to the first floating diffusion in response to a first phase signal. A first storage node is configured to store the first portion of charge from the first floating diffusion. A first decoupling circuit has a first output responsive to a first input. The first input is coupled to the first floating diffusion and the first output is coupled to first storage node. A voltage swing at the first output is greater than a voltage swing at the first input.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
H04N 25/705 - Pixels for depth measurement, e.g. RGBZ
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
77.
STACKED SEMICONDUCTOR DEVICE WITH CONNECTION PAD SHIELD
A stacked semiconductor device comprising a first semiconductor substrate, a second semiconductor substrate, an insulating medium disposed between the first semiconductor substrate and the second semiconductor substrate, a plurality of connection pads including a first connection pad and a second connection pad adjacent to the first connection pad, and a first connection pad shield structure disposed within the insulating medium between at least the first connection pad and the second connection pad is described. The plurality of connection pads is disposed within the insulating medium and configured to provide one or more electrical connections extending between the first semiconductor substrate and the second semiconductor substrate.
A stacked semiconductor device comprising a first semiconductor substrate, a second semiconductor substrate, an insulating medium disposed between the first semiconductor substrate and the second semiconductor substrate, a plurality of connection pads including a first connection pad and a second connection pad, a first connection pad shield structure, and a second connection pad shield structure. The plurality of connection pads is disposed within the insulating medium and configured to provide one or more electrical connections extending between the first semiconductor substrate and the second semiconductor substrate. The first connection pad is disposed between the first connection pad shield structure and the second connection pad shield structure.
A computing device is provided. The computing device includes a system-on-chip (SoC) device, and the SoC device includes a plurality of master devices and a stacked memory. The master devices are arranged on a die. The master devices are grouped in space into a plurality of logic device clusters with a clustering scheme defined according to operating requirements of the master devices. The stacked memory is disposed above the die. Connections between the stacked memory and the plurality of logic device clusters are established according to the clustering scheme defined.
A pixel circuit includes a photodiode configured to photo generate image charge in response to incident light, a floating diffusion coupled to receive the image charge from the photodiode, a transfer transistor coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion, a reset transistor coupled between a variable voltage source and the floating diffusion, wherein the reset transistor is configured to be switched in response to a reset control signal, and a lateral overflow integration capacitor (LOFIC) coupled between the variable voltage source and the floating diffusion. The variable voltage source is configured to output a high-voltage level during a high conversion gain (HCG) reset signal readout and an HCG image signal readout, and a mid-voltage level during a LOFIC image signal readout and a LOFIC reset signal readout.
An image sensor comprises a plurality of high sensitivity photoelectric conversion elements, a plurality of low sensitivity photoelectric conversion elements, and a processor for processing signals read out from the plurality of low sensitivity photoelectric conversion elements and the plurality of high sensitivity photoelectric conversion elements, where the processor is configured to read out signals from the plurality of low-sensitivity photoelectric conversion elements multiple times in a single frame after multiple exposures and obtain a plurality of images of low-sensitivity in the single frame at different times.
H04N 23/743 - Bracketing, i.e. taking a series of images with varying exposure conditions
H04N 23/68 - Control of cameras or camera modules for stable pick-up of the scene, e.g. compensating for camera body vibrations
H04N 23/73 - Circuitry for compensating brightness variation in the scene by influencing the exposure time
H04N 23/741 - Circuitry for compensating brightness variation in the scene by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
H04N 25/58 - Control of the dynamic range involving two or more exposures
82.
Optimized pixel design for mitigating MIM image lag
A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a pixel voltage source and the floating diffusion. A lateral overflow integration capacitor (LOFIC) network includes a first LOFIC coupled between the floating diffusion and the first bias voltage source, and a second LOFIC coupled between the floating diffusion and the second bias voltage source. The first LOFIC is configured to be forward biased and the second LOFIC is configured to be reverse biased at an end of an integration period, and image charge discharged from the first LOFIC and image charge discharged from the second LOFIC compensate each other during a readout period.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
83.
IMAGE SENSOR WITH VARYING THICKNESS DIELECTRIC LAYER
An image sensor includes an active pixel photodiode, a black pixel photodiode, a metal grid structure, a light shield, and a varying thickness dielectric layer. The varying thickness dielectric layer includes a first portion having a first dielectric layer thickness and a second portion having a second dielectric layer thickness different from the first dielectric layer thickness. The metal grid structure is disposed between the first portion of the varying thickness dielectric layer and a semiconductor material. The light shield is disposed between the second portion of the varying thickness dielectric layer and the black pixel photodiode.
An imaging device includes a pixel array with 2×2 pixel circuits arranged in rows and columns. Each 2×2 pixel circuit includes 4 photodiodes. Bitlines are coupled to the 2×2 pixel circuits and a color filter array is disposed over photodiodes of the pixel array. The color filter array includes color filters having a first color, color filters having a second color, color filters having a third color. The photodiodes of each 2×2 pixel circuits are covered by one of the color filters. Photodiodes covered by color filters having the first color and photodiodes covered by color filters having the second color are configured to provide non-phase detection (non-PD) information. Photodiodes covered by color filters having the third color are configured to provide phase detection (PD) information. Half of the 2×2 pixel circuits have the photodiodes covered by color filters having the third color.
H04N 25/13 - Arrangement of colour filter arrays [CFA]Filter mosaics characterised by the spectral characteristics of the filter elements
H04N 25/44 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array
H04N 25/704 - Pixels specially adapted for focusing, e.g. phase difference pixel sets
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
85.
High dynamic range CMOS image sensor pixel with reduced metal-insulator-metal lateral overflow integration capacitor lag
A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a bias voltage source and the floating diffusion. A drain of the reset transistor is coupled to the bias voltage source. The reset transistor is configured to be switched in response to a reset control signal. A lateral overflow integration capacitor (LOFIC) including an insulating region is disposed between a first metal electrode and a second metal electrode. The first metal electrode is coupled to the drain of the reset transistor. The second metal electrode is coupled to a source of the reset transistor and selectively coupled to the floating diffusion.
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
A pixel includes a photosensor configured to photogenerate charge in response to incident light. A floating diffusion is configured to receive the charge photogenerated by the photosensor. A transfer transistor is coupled between the floating diffusion and the photosensor. A dual floating diffusion (DFD) transistor is coupled to the floating diffusion. A binning node is coupled to the DFD transistor. A floating diffusion interconnect grid is coupled to the binning node of the pixel and a binning node of a second pixel. The pixel and the second pixel are included in a pixel array. The DFD transistor is configured to couple the binning node to the floating diffusion when activated during a readout operation of the pixel array to provide a binned readout, and the DFD transistor is configured not to couple the binning node to the floating diffusion when deactivated to provide a full resolution readout.
H04N 25/46 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
87.
Trench balance structure pattern in red photodiodes of a pixel array with quad bayer color filter
A pixel array includes 2×2 groupings of photodiodes to generate image charge in response to incident light directed through a back side of the semiconductor layer. A Quad Bayer filter is disposed over the back side of the semiconductor layer over the 2×2 groupings of photodiodes. Each color filter of the Quad Bayer CFA is disposed over a respective one of the plurality of 2×2 groupings of photodiodes. Trench balance structures are disposed in the semiconductor layer. Each of the trench balance structures is disposed in the semiconductor layer between one of the photodiodes and a respective one of the red color filters of the Quad Bayer filter. None of the trench balance structures are disposed between any of the photodiodes and respective green color filters or blue color filters of the Quad Bayer filter.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
A pixel cell includes a photodiode disposed in a semiconductor material. A floating diffusion is disposed in the semiconductor material. A transfer gate includes a vertical transfer gate structure disposed in the semiconductor material between the photodiode and the floating diffusion. The transfer gate is coupled between the photodiode and the floating diffusion. A passivation layer is disposed in the semiconductor material and proximate to the vertical transfer gate. The passivation layer has a region with a non-uniformly distributed doping profile proximate to the vertical gate structure such that a first doping concentration of the region in the passivation layer proximate to the vertical gate structure along a first direction is less than a second doping concentration of the region in the passivation layer proximate to the vertical gate structure along a second direction.
Methods for transmitting asynchronous event data via synchronous communications interfaces (and associated imaging systems) are disclosed herein. In one embodiment, an imager comprises an array of event vision pixels, a synchronous communications transmitter configured to transmit frames of data to a synchronous communications receiver, and a timer configured to indicate when a threshold amount of time has elapsed. The pixels can generate event data based on activity within an external scene. The imager can be configured to insert available event data into a payload of the current frame during a first time period before the frame timer indicates that the threshold amount of time has elapsed, pad the payload with dummy data during a second time period after the frame timer indicates that the threshold amount of time has elapsed, and transmit (using the synchronous communications transmitter) the current frame of data to the synchronous communications receiver.
In an embodiment, an image sensor comprises a pixel array having a minimal repeating unit, where the minimal repeating unit consists of 4×4 pixels including 12 green pixels, 2 blue pixels, and 2 red pixels, where a minimal repeating unit is immediately next to another minimal repeating unit in row and column directions. In another embodiment, an image sensor comprises a pixel array having a minimal repeating unit, where the minimal repeating unit consists of 8×8 pixels including 48 green pixels, 8 blue pixels, and 8 red pixels.
Methods for transmitting asynchronous event data via synchronous communications interfaces using anticipated event rates, and associated imaging systems
Methods for transmitting asynchronous event data via synchronous communications interfaces (and associated imaging systems) are disclosed herein. In one embodiment, an imager comprises an array of event vision pixels, and a synchronous communications transmitter configured to transmit frames of data to a synchronous communications receiver. The pixels generate event data based on activity within an external scene. The imager communicates, at a first time and to the receiver, an anticipated amount of data that will be included in a frame transmitted to the receiver at a second time. The anticipated amount of data can be based on a prediction of an amount of event data that will be generated at a future point in time for transmission to the receiver in the frame. The imager can then transmit the frame to the receiver at the second time with an amount of data corresponding to the anticipated amount of data.
A pixel cell includes a front deep trench isolation (FDTI) structure extending into a semiconductor material from a frontside. The FDTI structure isolates a first region of the semiconductor material from a second region of the semiconductor material. The FDTI structure includes a first conductive material coupled to receive a first bias voltage. A back deep trench isolation (BDTI) extends into the semiconductor material from a backside. The BDTI structure isolates the first region of the semiconductor material from the second region of the semiconductor material. The BDTI structure includes a second conductive material coupled to receive a second bias voltage. The FDTI structure and BDTI structure are at least partially aligned in a depthwise direction of the semiconductor material. A photodiode is disposed in the first region of the semiconductor material proximate to at least a portion of the FDTI structure and a portion of the BDTI structure.
Multiple read image sensors, and associated methods for the same, are disclosed herein. In one embodiment, a method comprises reading out a reset level from a pixel to a corresponding sample and hold circuit; storing the reset level to a first storage device and to a second storage device of the sample and hold circuit; reading out a signal level from the pixel to the sample and hold circuit; and storing the signal level to a third storage device and to a fourth storage device of the sample and hold circuit. The reset level and the signal level can correspond to a same correlated double sampling of an image data signal captured by the pixel. The method can further include reading out the reset level from the first storage device; reading out the signal level from the third storage device; and recovering a first copy of the image data signal.
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
A tail current source of a comparator includes a first transistor and a second transistor configured to operate as current sources, wherein the first and second transistors are coupled between a tail node of the comparator and a voltage node, and wherein the tail comprises a node coupled to first and second inputs of the comparator. The tail current source also includes a switch configured to selectively couple the second transistor between the tail and the voltage node, and a bias voltage source coupled to gates of the first and second transistors. The switch is configured to be on during an analog-to-digital conversion (ADC) reset signal period and an ADC image signal period, and the switch is configured to be off during an auto-zero period, a period between the ADC reset signal and image signal periods, and a period after the ADC image signal period.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
95.
MULTIPLE READ IMAGE SENSORS, AND ASSOCIATED METHODS FOR THE SAME
Multiple read image sensors, and associated methods for the same, are disclosed herein. In one embodiment, a method comprises reading out a reset level from a pixel to a corresponding sample and hold circuit; storing the reset level to a first storage device and to a second storage device of the sample and hold circuit; reading out a signal level from the pixel to the sample and hold circuit; and storing the signal level to a third storage device and to a fourth storage device of the sample and hold circuit. The reset level and the signal level can correspond to a same correlated double sampling of an image data signal captured by the pixel. The method can further include reading out the reset level from the first storage device; reading out the signal level from the third storage device; and recovering a first copy of the image data signal.
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/40 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data
H04N 25/65 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
A pixel cell readout circuit comprises a ramp generator having a ramp generator output. A first gain network is coupled to the ramp generator output and configured to provide a first variable comparator gain. A second gain network is coupled to the ramp generator output and configured to provide a second variable comparator gain. A first comparator has a first input coupled to the first gain network. The first comparator further has a second input selectively coupled to a first bitline and selectively coupled to a second bitline. A second comparator has a first input coupled to the second gain network. The second comparator further has a second input selectively coupled to the first bitline and selectively coupled to the second bitline.
A pixel cell readout circuit comprises a comparator with a current mirror having first and second current paths, a first input transistor coupled to the first current path, a low conversion gain (LCG) second input transistor selectively coupled to the second current path, and a high conversion gain (HCG) second input transistor selectively coupled to the second current path. The pixel cell readout circuit further comprises a gain network coupled between a gate node of the first input transistor and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator, an LCG auto-zero switch coupled between a drain node and a gate node of the LCG second input transistor, and an HCG auto-zero switch coupled between a drain node and a gate node of the HCG second input transistor.
An image sensor comprises an image sensor chip comprising a semiconductor substrate having a top surface and a plurality of microlenses disposed on the top surface; a cover glass having a first side in contact with air and a second side opposite to the first side; and a multi-layer structure disposed between the plurality of microlenses and the cover glass, which comprises: a bottom layer directly in contact with the plurality of microlenses, where the refractive index of the bottom layer is lower than the refractive index of the plurality of microlenses, and a top layer directly in contact with the second side of the cover glass, where the top layer is an optical glue made for bonding two optical elements.
A local ramp buffer includes a deep N− well layer disposed in a P− substrate beneath a surface of the P− substrate, a P− well disposed between the surface of the P− substrate and the deep N− well layer, and an N− well structure disposed in the P− substrate and coupled to the deep N− well layer. The N− well structure is disposed between the surface of the P− substrate and the deep N− well layer. The P− well is disposed inside an opening in the N− well structure. The N− well structure and the deep N− well layer are configured to isolate the P− well within the opening. A source follower transistor is disposed in the P− well. The source follower transistor includes a gate terminal coupled to the N− well structure and a ramp generator.
An image sensor includes a pixel array including at least one light-shielded area where no light enters and an imaging area where light enters, wherein each pixel includes a photoelectric conversion element, a black level processing unit that corrects an output of each pixel in the imaging area, and a memory that stores a predetermined black level reference for each pixel in the imaging area. The processing unit calculates a Slope, which is determined by an average output value at imaging of pixels in the at least one light-shielded area taken during imaging and a reference average output value of pixels in the at least one light-shielded area under certain conditions taken prior to imaging, and correct an output of each pixel in the imaging area using the predetermined black level reference and the Slope.
