A pixel of an image sensor includes a photodiode, a reset transistor, a peak hold transistor, and a first capacitor and a second capacitor. The pixels include, a first mode in which the noise and image output voltages of the photodiode are held in the first and second capacitors, respectively, and a second mode in which the output voltage of the photodiode in a state where the reset transistor is turned on to reset the photodiode is held in the first capacitor or the second capacitor. In the first mode, an image signal corresponding to the light incident amount of the photodiode and a noise signal when the light incident amount is relatively low are obtained. In the second mode, a noise signal when the light incident amount of the photodiode is relatively high is obtained.
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/65 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
An image sensor is an image sensor including a plurality of pixels. Each of the pixels includes a photodiode configured to generate charges based on a light incident amount, a reset transistor configured to reset the photodiode by supplying a reset voltage to the photodiode, a first capacitor configured to hold an output voltage of the photodiode immediately after the reset, and a second capacitor configured to hold the output voltage of the photodiode after a predetermined exposure period. An image signal is obtained from the voltage held by the first capacitor and the voltage held by the second capacitor.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/62 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
H04N 25/65 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
3.
MULTIPLE READ IMAGE SENSORS, AND ASSOCIATED METHODS FOR THE SAME
Multiple read image sensors, and associated methods for the same, are disclosed herein. In one embodiment, a method comprises reading out a reset level from a pixel to a corresponding sample and hold circuit; storing the reset level to a first storage device and to a second storage device of the sample and hold circuit; reading out a signal level from the pixel to the sample and hold circuit; and storing the signal level to a third storage device and to a fourth storage device of the sample and hold circuit. The reset level and the signal level can correspond to a same correlated double sampling of an image data signal captured by the pixel. The method can further include reading out the reset level from the first storage device; reading out the signal level from the third storage device; and recovering a first copy of the image data signal.
A method of counting photons using a plurality of single photon avalanche diodes (SPADs), including initiating a detection phase, enabling each single photon avalanche diode (SPAD) of the plurality of SPADs for a period of time within the detection phase, accumulating a SPAD event from each SPAD of the plurality of SPADs, wherein each SPAD event corresponds to a detection of a single photon, determining a counter code at an end of the detection phase, where the counter code corresponds to accumulated SPAD events, and enabling one or more SPADs of the plurality of SPADs within an exposure phase based on the counter code, where the counter code is greater than an expected number of the SPAD events during the exposure phase, and where the expected number of SPAD events during the exposure phase is based on the counter code that is determined at the end of the detection phase.
A pixel circuit including a transistor, a blocking layer and an output circuit is disclosed. The transistor includes a first doped region and a second doped region disposed on opposite sides of a channel of the transistor proximate to a first surface of a semiconductor substrate such that photo-carriers generated inside the semiconductor substrate in response to incident light flow into one region of the first and second doped regions. The blocking layer is disposed between the other region of the first and second doped regions and a second surface of the semiconductor substrate opposite to the first surface. The blocking layer configured to block the photo-carriers from flowing into the other region of the first doped region and the second doped region directly. The output circuit outputs an image signal according to a voltage signal outputted from the transistor.
A pixel circuit includes: a phototransistor configured to receive, by one region of a source and a drain, inflow of photo-carriers generated by light entering a substrate, and configured to output a voltage signal from the one region; and a blocking layer provided on another region of the drain and the source and on a side of a channel far from a surface, and configured to prevent the photo-carriers from directly flowing into the other region. The phototransistor causes a sub-threshold current to flow between the source and the drain in a pinch-off state. Each of the source and the drain of the phototransistor is periodically reset to a reset voltage. The reset voltage is set to a voltage between a voltage at which a dark current of the phototransistor becomes zero and a voltage at which a bias voltage of the phototransistor becomes zero.
An image sensor is described. The image sensor comprises a plurality of pixels arranged to form an active pixel array, a plurality of contact pads disposed within a peripheral region of the image sensor that surrounds the active pixel array, and an optical structure disposed within the peripheral region between the plurality of contact pads and the active pixel array. The optical structure is adapted to mitigate stray light from reaching the active pixel array.
A sample and hold readout system and method for ramp analog to digital conversion is presented in which an optical array is read out using a sample and hold circuit such that each sample is used to charge a sample and hold capacitor and is read out during a hold phase using an amplifier that drives an ramp analog to digital converter. The sample and hold circuit transitions to a tracking phase wherein the optical array input drives an amplifier that drives the sample and hold capacitor then transitions to a sample phase where the sample and hold capacitor is connected to the optical array output directly.
H03M 1/34 - Analogue value compared with reference values
H03M 1/56 - Input signal compared with linear ramp
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
An imaging system comprises a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells. Each column unit cell comprises at least one of a plurality of comparators, wherein each comparator is coupled to receive the ramp signal from the ramp generator through a ramp signal line. Each column unit cell also comprises a compensation current unit coupled to the ramp signal line, each compensation current unit comprising a compensation current source and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node on the ramp signal line and a second node.
An imaging system comprises a pixel array and readout circuitry coupled to the pixel array. The readout circuitry includes a ramp generator and a plurality of column unit cells, each comprising a column ramp buffer and a column comparator, and each column ramp buffer comprising an input node coupled to receive a ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator, and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit comprises a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor.
H04N 25/677 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction for reducing the column or line fixed pattern noise
H04N 25/766 - Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
A multichannel endoscope system includes a light module configured to emit illumination light on an object, an image module configured to capture an image of the object, and a multichannel sensor module configured to obtain a spectral information of the object. The multichannel sensor module includes an image lens, a light homogenizer and a multichannel array sensor, where the light homogenizer is formed between the multichannel array sensor and the image lens.
A61B 1/05 - Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopesIlluminating arrangements therefor combined with photographic or television appliances characterised by the image sensor, e.g. camera, being in the distal end portion
A61B 1/06 - Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopesIlluminating arrangements therefor with illuminating arrangements
A pixel array includes a plurality of pixel cells, each including a photodiode configured to photogenerate image charge in response to the incident light, a first floating diffusion (FD) coupled to receive the image charge from the photodiode, a reset transistor coupled between a voltage source and the first FD, a second FD coupled between the first FD and ground, a first dual FD transistor coupled between the first and second FDs. Second FDs of first and second pixel cells are coupled. Second FDs of third and fourth pixel cells are coupled.
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
An image sensor comprises: a control block generating a video interface enabled signal, a video interface for receiving the video interface enabled signal, a pixel array for providing a video stream to the video interface, an output port for receiving the video stream from the video interface and outputting the video stream to outside of the image sensor, a stream indicator pin for receiving the video interface enabled signal from the control block when the video interface is receiving the video interface enabled signal from the control block, where a terminal of the video interface receiving the video interface enabled signal is connected to the stream indicator pin by a conductor, and they are sealed in a package of the image sensor.
09 - Scientific and electric apparatus and instruments
10 - Medical apparatus and instruments
Goods & Services
Integrated circuits; video processors; microchip image
processors; optical image sensors; optical lenses for use
with image sensors; optical aspheric lenses and lens
assemblies being optical lenses for use in combination with
digital signal processing to produce and improve images;
semiconductor chips and optical lenses for capturing and
processing digital images and video; optical sensors with
integrated optical lenses for capturing and processing
digital images and video; optical inspection apparatuses for
imaging; image signal processing semiconductor chips for use
with image sensors to capture, process or improve digital
images and video; integrated circuits, semiconductor chips
and optical lenses for capturing and processing digital
images and video; optical sensors with integrated optical
lenses for capturing and processing digital images and
video; image signal processing semiconductor chips for use
with image sensors to capture, process or improve digital
images and video; optical sensors, namely, wafer level
optics in the nature of wafer level image sensor modules for
use in mobile phones, tablets, notebook computers, personal
computers, digital video camcorders, video cameras and
recorders, video game consoles used with televisions,
automobiles, medical devices, namely, endoscopes and
catheters, disposable medical guidewires, security systems,
robotic devices, drones, and augmented reality (AR) and
virtual reality (VR) devices, namely, headsets, glasses,
data gloves, and electrical controllers; endoscope cameras
for non-medical use; rigid and flexible endoscopes for
non-medical use; guidewires being electric wires for
non-medical use; interface circuits for video cameras;
electronic display interfaces; interfaces and peripheral
devices for computers. Medical imaging endoscopy cameras for medical purposes,
namely, encephaloscopes, esophagoscopes, thoracoscopes,
angioscopes, gastroscopes, proctoscopes, colonoscopes,
arthroscopes, rhinoscopes, laryngoscopes, bronchoscopes,
mediastinoscopes, nephroscopes, laparoscopes, amnioscopes,
cystoscopes, hysteroscopes; endoscopy medical imaging
cameras for endoscopes and medical purposes, namely,
catheter cameras; endoscope cameras for medical use; medical
endoscopes; catheters; medical guidewires; medical imaging
apparatus.
15.
COLOR ROUTER BASED PHOTODIODES AND INTEGRATED PIXEL CIRCUIT
Color router based photodiodes and integrated pixel circuit. In one embodiment, a plurality of pixels arranged in rows and columns of a pixel array are disposed in a semiconductor material. In some embodiments, each pixel comprises a plurality of photodiodes and a color router covering the plurality of photodiodes. In some embodiments, the plurality of pixels is configured to receive an incoming light through the color router. In some embodiments, the integrated pixel circuit includes a plurality of pixel circuits, where each pixel circuit is associated with a corresponding pixel of the plurality of pixels. In some embodiments, the pixel circuits are configured on a same horizontal plane as the plurality of photodiodes.
A gated imaging system includes a pulsed illuminator configured to generate a plurality of light pulses and a pixel circuit. The pixel circuit includes a photodiode configured to collect photogenerated image charge in response to incident light, a floating diffusion coupled to receive the image charge from the photodiode, a sense node amplifier includes a gate terminal coupled to the floating diffusion, and a storage network coupled between the photodiode and the floating diffusion. The storage network includes a plurality of memory nodes coupled between the photodiode and the floating diffusion in parallel. The storage network is configured to capture a plurality of depth slices between two successive ones of the light pulses.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 23/56 - Cameras or camera modules comprising electronic image sensorsControl thereof provided with illuminating means
A method for full interpolating green pixels from an input image having a first minimum repeating unit comprising 4×4 pixels, where 2×2 pixels of same color are grouped together, comprises down sampling of the input image to a first down sampled image, down sampling of the input image to a second down sampled image, and interpolating green pixels resulting in an interpolated green down sampled image, where the interpolating uses jointly the first down sampled image and the second down sampled image. The interpolated green pixels in an interpolated green down sampled image are further up sampled resulting in a full interpolated green image.
A time-of-flight pixel array includes first transistors to transfer a first phase portion of charge from photodiodes responsive to reflected modulated light during a first subframe, and a second phase portion of the charge during a second subframe. The second phase is an inverted first phase. Second transistors transfer the second phase portion of the charge during the first subframe, and the first phase portion of the charge during the second subframe. Third transistors transfer a third phase portion of the charge during the first subframe, and a fourth phase portion of the charge during the second subframe. The fourth phase is an inverted third phase. The third phase is ninety degrees out of phase with the first phase. Fourth transistors transfer the fourth phase portion of the charge during the first subframe, and the third phase portion of the charge during the second subframe.
G01S 7/4863 - Detector arrays, e.g. charge-transfer gates
G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
G01S 17/26 - Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves wherein the transmitted pulses use a frequency-modulated or phase-modulated carrier wave, e.g. for pulse compression of received signals
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
19.
IMAGE SENSOR WITH SHARED GATE ARCHITECTURE FOR METAL LAYER REDUCTION
An image sensor comprising a semiconductor substrate, a first source region, a second source region, and a shared gate electrode is described. The semiconductor substrate includes a first side and a second side opposite the first side. The first source region and the second source region are each disposed within the semiconductor substrate proximate to the first side. The first source region is separated from the second source region by an isolation structure disposed within the semiconductor substrate between the first source region and the second source region. The shared gate electrode is disposed proximate to the first side of the semiconductor substrate and coupled to the first source region and the second source region to respectively form a first transistor and a second transistor.
EVENT VISION SENSORS WITH EVENT DATA COMPRESSION, INCLUDING EVENT VISION SENSORS WITH IN-PIXEL EVENT DATA COMPRESSION, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
Event vision sensors with event data compression (and associated systems, devices, and methods) are disclosed herein. In one embodiment, an event vision sensor includes a plurality of event vision pixels. Each event vision pixel of the plurality is configured to generate event data based on events indicated in incident light received from an external scene, and includes a compression circuit configured to compress the event data prior to readout of the event data from the event vision pixel. Each compression circuit can include a time aggregation circuit that is configured to track a number of the events detected by the corresponding event vision pixel over a specified timing window. The compressed event data can be read out from the event vision sensors and used to generate a pseudo-frame. The event vision sensor can optionally perform frame-level compression on the pseudo-frame.
H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.
H03K 5/22 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
22.
SPARSE 4C2+ PHASE DETECTION AUTO FOCUS AND CORRELATED MULTIPLE SAMPLING
An arithmetic logic unit includes a GC to binary stage, an adder stage, an adder output stage, an adder input latch stage coupled to latch outputs of the GC to binary stage, a feedback multiplexer stage coupled to receive the outputs of the GC to binary stage, a latch output multiplexer coupled to receive outputs of the first adder input latches, where the latch output multiplexer is configured to multiply the outputs of the first adder input latches by either −1 or −2, and an adder input multiplexer stage, where first inputs of the adder input multiplexer stage are coupled to receive outputs of the latch output multiplexer and second inputs of the adder input multiplexer stage are coupled to receive outputs of the second adder input latches. The arithmetic logic performs adaptive correlated multiple sampling for image sensing pixels and phase detection auto focus for other pixels.
An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.
G06F 7/57 - Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups or for performing logical operations
An imaging system comprising a phase-detection image sensor comprising a plurality of phase-detection pixel units and a processor configured to: interpolate a green image to obtain a full resolution interpolated green image including defocused portions having artifacts and in-focus portions having sharp image, low-pass filter the full resolution interpolated green image to obtain a blurred image of the interpolated green image, combine the full resolution interpolated green image and the blurred image of the full resolution interpolated green image to obtain a corrected full resolution interpolated green image, where the artifacts of the defocused portions of the full resolution interpolated green image are removed, and the sharp image of the in-focus portions of the full resolution interpolated green image is unaffected.
A pixel array substrate includes a semiconductor substrate including a pixel array, a first side, and a second side opposite the first side, a guard ring region in the semiconductor substrate, formed of a doped semiconductor, enclosing the pixel array, and extending into the semiconductor substrate from the first side, and a peripheral region in the semiconductor substrate and enclosing the guard ring region. The peripheral region includes at least one device and a deep trench isolation (DTI) structure region disposed between the guard ring region and the at least one device and proximate to the second side of the semiconductor substrate. The DTI structure region is configured to block an electric current path between a P-N junction in the guard ring region and the at least one device.
An image sensor package with a multi-step cavity formed in or on a substrate, which includes an image sensor bonded onto bottom of the multi-step cavity, and a cover glass placed and sealed on a lower portion of the multi-step cavity. Lower portion of the multi-step cavity includes at least a first and a second raised-step structures protruding from the bottom of the multi-step cavity, and the cover glass is placed and sealed over the first raised-step structure.
An imaging system includes a pixel array with odd and even pixel cells. Each of the odd and even pixel cells includes a photodiode, a floating diffusion, a transfer transistor, a reset transistor, a lateral overflow integration capacitor (LOFIC), and an overflow gate (OFG) transistor. The imaging system further includes a readout circuit with a sample and hold (SH) circuit and an analog to digital converter. The OFG transistor of each of the odd and even pixel cells is configured to direct the image charge photogenerated by the respective photodiode away from the respective transfer transistor and reduce photodiode exposure shift during LOFIC readouts during a global transfer period.
A method for convolution calculation in a neural network is provided. The method comprises: decomposing each weight into multiple sub-weights, each with only one valid bit, representing different bit significance (bit plane); accumulating input feature map units corresponding to each of the sub-weights with the same bit significance to obtain intermediate sums; shifting each of the intermediate sums according to the bit significance of the corresponding sub-weights to obtain shifted intermediate sums; and accumulating the shifted intermediate sums.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
A pixel includes a semiconductor substrate having a first side and a second side. Extending from the first side is a first deep trench isolation (DTI) structure and a second DTI structure. The first DTI structure includes a wide portion and a narrow portion extending from the wide portion. A first width of the wide portion is greater than a second width of the narrow portion, and the wide portion extends to a first depth. The pixel further includes a photodiode region disposed in the semiconductor substrate between the first DTI structure and the second DTI structure. A cell deep trench isolation (CDTI) structure is disposed between the wide portion of the first DTI structure and the second DTI structure. The CDTI structure extends to a second depth. The first depth and the second depth extend a substantially equal distance from the first side of the semiconductor substrate.
A curved-surface image-sensor assembly has a porous carrier having a concave surface with a thinned image sensor bonded by an adhesive to its concave surface of the porous carrier; the porous carrier is mounted into a water-resistant package. The sensor assembly is made by fabricating a thinned, flexible, image-sensor integrated circuit (IC) and applying adhesive to a non-illuminated side of the IC; positioning the IC over a concave surface of a porous carrier; applying vacuum through the porous carrier to suck the IC onto the concave surface of the porous carrier; and curing the adhesive to bond the IC to the concave surface of the porous carrier.
A pixel circuit includes a photodiode configured to photogenerate charge in response to reflected modulated light incident upon the photodiode. A first floating diffusion is configured to store a first portion of charge photogenerated in the photodiode. A first transfer transistor is configured to transfer the first portion of charge from the photodiode to the first floating diffusion in response to a first phase signal. A first storage node is configured to store the first portion of charge from the first floating diffusion. A first decoupling circuit has a first output responsive to a first input. The first input is coupled to the first floating diffusion and the first output is coupled to first storage node. A voltage swing at the first output is greater than a voltage swing at the first input.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
H04N 25/705 - Pixels for depth measurement, e.g. RGBZ
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
32.
STACKED SEMICONDUCTOR DEVICE WITH CONNECTION PAD SHIELD
A stacked semiconductor device comprising a first semiconductor substrate, a second semiconductor substrate, an insulating medium disposed between the first semiconductor substrate and the second semiconductor substrate, a plurality of connection pads including a first connection pad and a second connection pad adjacent to the first connection pad, and a first connection pad shield structure disposed within the insulating medium between at least the first connection pad and the second connection pad is described. The plurality of connection pads is disposed within the insulating medium and configured to provide one or more electrical connections extending between the first semiconductor substrate and the second semiconductor substrate.
A stacked semiconductor device comprising a first semiconductor substrate, a second semiconductor substrate, an insulating medium disposed between the first semiconductor substrate and the second semiconductor substrate, a plurality of connection pads including a first connection pad and a second connection pad, a first connection pad shield structure, and a second connection pad shield structure. The plurality of connection pads is disposed within the insulating medium and configured to provide one or more electrical connections extending between the first semiconductor substrate and the second semiconductor substrate. The first connection pad is disposed between the first connection pad shield structure and the second connection pad shield structure.
A computing device is provided. The computing device includes a system-on-chip (SoC) device, and the SoC device includes a plurality of master devices and a stacked memory. The master devices are arranged on a die. The master devices are grouped in space into a plurality of logic device clusters with a clustering scheme defined according to operating requirements of the master devices. The stacked memory is disposed above the die. Connections between the stacked memory and the plurality of logic device clusters are established according to the clustering scheme defined.
A pixel circuit includes a photodiode configured to photo generate image charge in response to incident light, a floating diffusion coupled to receive the image charge from the photodiode, a transfer transistor coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion, a reset transistor coupled between a variable voltage source and the floating diffusion, wherein the reset transistor is configured to be switched in response to a reset control signal, and a lateral overflow integration capacitor (LOFIC) coupled between the variable voltage source and the floating diffusion. The variable voltage source is configured to output a high-voltage level during a high conversion gain (HCG) reset signal readout and an HCG image signal readout, and a mid-voltage level during a LOFIC image signal readout and a LOFIC reset signal readout.
An image sensor comprises a plurality of high sensitivity photoelectric conversion elements, a plurality of low sensitivity photoelectric conversion elements, and a processor for processing signals read out from the plurality of low sensitivity photoelectric conversion elements and the plurality of high sensitivity photoelectric conversion elements, where the processor is configured to read out signals from the plurality of low-sensitivity photoelectric conversion elements multiple times in a single frame after multiple exposures and obtain a plurality of images of low-sensitivity in the single frame at different times.
A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a pixel voltage source and the floating diffusion. A lateral overflow integration capacitor (LOFIC) network includes a first LOFIC coupled between the floating diffusion and the first bias voltage source, and a second LOFIC coupled between the floating diffusion and the second bias voltage source. The first LOFIC is configured to be forward biased and the second LOFIC is configured to be reverse biased at an end of an integration period, and image charge discharged from the first LOFIC and image charge discharged from the second LOFIC compensate each other during a readout period.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
38.
IMAGE SENSOR WITH VARYING THICKNESS DIELECTRIC LAYER
An image sensor includes an active pixel photodiode, a black pixel photodiode, a metal grid structure, a light shield, and a varying thickness dielectric layer. The varying thickness dielectric layer includes a first portion having a first dielectric layer thickness and a second portion having a second dielectric layer thickness different from the first dielectric layer thickness. The metal grid structure is disposed between the first portion of the varying thickness dielectric layer and a semiconductor material. The light shield is disposed between the second portion of the varying thickness dielectric layer and the black pixel photodiode.
An imaging device includes a pixel array with 2×2 pixel circuits arranged in rows and columns. Each 2×2 pixel circuit includes 4 photodiodes. Bitlines are coupled to the 2×2 pixel circuits and a color filter array is disposed over photodiodes of the pixel array. The color filter array includes color filters having a first color, color filters having a second color, color filters having a third color. The photodiodes of each 2×2 pixel circuits are covered by one of the color filters. Photodiodes covered by color filters having the first color and photodiodes covered by color filters having the second color are configured to provide non-phase detection (non-PD) information. Photodiodes covered by color filters having the third color are configured to provide phase detection (PD) information. Half of the 2×2 pixel circuits have the photodiodes covered by color filters having the third color.
H04N 25/13 - Arrangement of colour filter arrays [CFA]Filter mosaics characterised by the spectral characteristics of the filter elements
H04N 25/44 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
40.
HIGH DYNAMIC RANGE CMOS IMAGE SENSOR PIXEL WITH REDUCED METAL-INSULATOR-METAL LATERAL OVERFLOW INTEGRATION CAPACITOR LAG
A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a bias voltage source and the floating diffusion. A drain of the reset transistor is coupled to the bias voltage source. The reset transistor is configured to be switched in response to a reset control signal. A lateral overflow integration capacitor (LOFIC) including an insulating region is disposed between a first metal electrode and a second metal electrode. The first metal electrode is coupled to the drain of the reset transistor. The second metal electrode is coupled to a source of the reset transistor and selectively coupled to the floating diffusion.
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
41.
METHOD AND APPARATUS TO EFFICIENTLY READ SUPER-BINNED ARRAY OUT FROM SENSOR OF HIGHER RESOLUTION
A pixel includes a photosensor configured to photogenerate charge in response to incident light. A floating diffusion is configured to receive the charge photogenerated by the photosensor. A transfer transistor is coupled between the floating diffusion and the photosensor. A dual floating diffusion (DFD) transistor is coupled to the floating diffusion. A binning node is coupled to the DFD transistor. A floating diffusion interconnect grid is coupled to the binning node of the pixel and a binning node of a second pixel. The pixel and the second pixel are included in a pixel array. The DFD transistor is configured to couple the binning node to the floating diffusion when activated during a readout operation of the pixel array to provide a binned readout, and the DFD transistor is configured not to couple the binning node to the floating diffusion when deactivated to provide a full resolution readout.
H04N 25/46 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
42.
VERTICAL TRANSFER GATE DOPING DISTRIBUTION FOR CHARGE TRANSFER FROM A PHOTODIODE
A pixel cell includes a photodiode disposed in a semiconductor material. A floating diffusion is disposed in the semiconductor material. A transfer gate includes a vertical transfer gate structure disposed in the semiconductor material between the photodiode and the floating diffusion. The transfer gate is coupled between the photodiode and the floating diffusion. A passivation layer is disposed in the semiconductor material and proximate to the vertical transfer gate. The passivation layer has a region with a non-uniformly distributed doping profile proximate to the vertical gate structure such that a first doping concentration of the region in the passivation layer proximate to the vertical gate structure along a first direction is less than a second doping concentration of the region in the passivation layer proximate to the vertical gate structure along a second direction.
A pixel array includes 2×2 groupings of photodiodes to generate image charge in response to incident light directed through a back side of the semiconductor layer. A Quad Bayer filter is disposed over the back side of the semiconductor layer over the 2×2 groupings of photodiodes. Each color filter of the Quad Bayer CFA is disposed over a respective one of the plurality of 2×2 groupings of photodiodes. Trench balance structures are disposed in the semiconductor layer. Each of the trench balance structures is disposed in the semiconductor layer between one of the photodiodes and a respective one of the red color filters of the Quad Bayer filter. None of the trench balance structures are disposed between any of the photodiodes and respective green color filters or blue color filters of the Quad Bayer filter.
Methods for transmitting asynchronous event data via synchronous communications interfaces (and associated imaging systems) are disclosed herein. In one embodiment, an imager comprises an array of event vision pixels, a synchronous communications transmitter configured to transmit frames of data to a synchronous communications receiver, and a timer configured to indicate when a threshold amount of time has elapsed. The pixels can generate event data based on activity within an external scene. The imager can be configured to insert available event data into a payload of the current frame during a first time period before the frame timer indicates that the threshold amount of time has elapsed, pad the payload with dummy data during a second time period after the frame timer indicates that the threshold amount of time has elapsed, and transmit (using the synchronous communications transmitter) the current frame of data to the synchronous communications receiver.
In an embodiment, an image sensor comprises a pixel array having a minimal repeating unit, where the minimal repeating unit consists of 4×4 pixels including 12 green pixels, 2 blue pixels, and 2 red pixels, where a minimal repeating unit is immediately next to another minimal repeating unit in row and column directions. In another embodiment, an image sensor comprises a pixel array having a minimal repeating unit, where the minimal repeating unit consists of 8×8 pixels including 48 green pixels, 8 blue pixels, and 8 red pixels.
METHODS FOR TRANSMITTING ASYNCHRONOUS EVENT DATA VIA SYNCHRONOUS COMMUNICATIONS INTERFACES USING ANTICIPATED EVENT RATES, AND ASSOCIATED IMAGING SYSTEMS
Methods for transmitting asynchronous event data via synchronous communications interfaces (and associated imaging systems) are disclosed herein. In one embodiment, an imager comprises an array of event vision pixels, and a synchronous communications transmitter configured to transmit frames of data to a synchronous communications receiver. The pixels generate event data based on activity within an external scene. The imager communicates, at a first time and to the receiver, an anticipated amount of data that will be included in a frame transmitted to the receiver at a second time. The anticipated amount of data can be based on a prediction of an amount of event data that will be generated at a future point in time for transmission to the receiver in the frame. The imager can then transmit the frame to the receiver at the second time with an amount of data corresponding to the anticipated amount of data.
A pixel cell includes a front deep trench isolation (FDTI) structure extending into a semiconductor material from a frontside. The FDTI structure isolates a first region of the semiconductor material from a second region of the semiconductor material. The FDTI structure includes a first conductive material coupled to receive a first bias voltage. A back deep trench isolation (BDTI) extends into the semiconductor material from a backside. The BDTI structure isolates the first region of the semiconductor material from the second region of the semiconductor material. The BDTI structure includes a second conductive material coupled to receive a second bias voltage. The FDTI structure and BDTI structure are at least partially aligned in a depthwise direction of the semiconductor material. A photodiode is disposed in the first region of the semiconductor material proximate to at least a portion of the FDTI structure and a portion of the BDTI structure.
A tail current source of a comparator includes a first transistor and a second transistor configured to operate as current sources, wherein the first and second transistors are coupled between a tail node of the comparator and a voltage node, and wherein the tail comprises a node coupled to first and second inputs of the comparator. The tail current source also includes a switch configured to selectively couple the second transistor between the tail and the voltage node, and a bias voltage source coupled to gates of the first and second transistors. The switch is configured to be on during an analog-to-digital conversion (ADC) reset signal period and an ADC image signal period, and the switch is configured to be off during an auto-zero period, a period between the ADC reset signal and image signal periods, and a period after the ADC image signal period.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
49.
Multiple read image sensors, and associated methods for the same
Multiple read image sensors, and associated methods for the same, are disclosed herein. In one embodiment, a method comprises reading out a reset level from a pixel to a corresponding sample and hold circuit; storing the reset level to a first storage device and to a second storage device of the sample and hold circuit; reading out a signal level from the pixel to the sample and hold circuit; and storing the signal level to a third storage device and to a fourth storage device of the sample and hold circuit. The reset level and the signal level can correspond to a same correlated double sampling of an image data signal captured by the pixel. The method can further include reading out the reset level from the first storage device; reading out the signal level from the third storage device; and recovering a first copy of the image data signal.
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
50.
MULTIPLE READ IMAGE SENSORS, AND ASSOCIATED METHODS FOR THE SAME
Multiple read image sensors, and associated methods for the same, are disclosed herein. In one embodiment, a method comprises reading out a reset level from a pixel to a corresponding sample and hold circuit; storing the reset level to a first storage device and to a second storage device of the sample and hold circuit; reading out a signal level from the pixel to the sample and hold circuit; and storing the signal level to a third storage device and to a fourth storage device of the sample and hold circuit. The reset level and the signal level can correspond to a same correlated double sampling of an image data signal captured by the pixel. The method can further include reading out the reset level from the first storage device; reading out the signal level from the third storage device; and recovering a first copy of the image data signal.
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/40 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data
H04N 25/65 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
A pixel cell readout circuit comprises a ramp generator having a ramp generator output. A first gain network is coupled to the ramp generator output and configured to provide a first variable comparator gain. A second gain network is coupled to the ramp generator output and configured to provide a second variable comparator gain. A first comparator has a first input coupled to the first gain network. The first comparator further has a second input selectively coupled to a first bitline and selectively coupled to a second bitline. A second comparator has a first input coupled to the second gain network. The second comparator further has a second input selectively coupled to the first bitline and selectively coupled to the second bitline.
A pixel cell readout circuit comprises a comparator with a current mirror having first and second current paths, a first input transistor coupled to the first current path, a low conversion gain (LCG) second input transistor selectively coupled to the second current path, and a high conversion gain (HCG) second input transistor selectively coupled to the second current path. The pixel cell readout circuit further comprises a gain network coupled between a gate node of the first input transistor and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator, an LCG auto-zero switch coupled between a drain node and a gate node of the LCG second input transistor, and an HCG auto-zero switch coupled between a drain node and a gate node of the HCG second input transistor.
An image sensor comprises an image sensor chip comprising a semiconductor substrate having a top surface and a plurality of microlenses disposed on the top surface; a cover glass having a first side in contact with air and a second side opposite to the first side; and a multi-layer structure disposed between the plurality of microlenses and the cover glass, which comprises: a bottom layer directly in contact with the plurality of microlenses, where the refractive index of the bottom layer is lower than the refractive index of the plurality of microlenses, and a top layer directly in contact with the second side of the cover glass, where the top layer is an optical glue made for bonding two optical elements.
A local ramp buffer includes a deep N− well layer disposed in a P− substrate beneath a surface of the P− substrate, a P− well disposed between the surface of the P− substrate and the deep N− well layer, and an N− well structure disposed in the P− substrate and coupled to the deep N− well layer. The N− well structure is disposed between the surface of the P− substrate and the deep N− well layer. The P− well is disposed inside an opening in the N− well structure. The N− well structure and the deep N− well layer are configured to isolate the P− well within the opening. A source follower transistor is disposed in the P− well. The source follower transistor includes a gate terminal coupled to the N− well structure and a ramp generator.
An image sensor includes a pixel array including at least one light-shielded area where no light enters and an imaging area where light enters, wherein each pixel includes a photoelectric conversion element, a black level processing unit that corrects an output of each pixel in the imaging area, and a memory that stores a predetermined black level reference for each pixel in the imaging area. The processing unit calculates a Slope, which is determined by an average output value at imaging of pixels in the at least one light-shielded area taken during imaging and a reference average output value of pixels in the at least one light-shielded area under certain conditions taken prior to imaging, and correct an output of each pixel in the imaging area using the predetermined black level reference and the Slope.
A method includes capturing an image from a scene with an image sensor. The image sensor has a plurality of spectral pixels and a plurality of image pixels. The method also includes collecting gathered data from the spectral-imaging array based on the light received. The gathered data is separated into spectral pixel data and image pixel data. The spectral pixel data is provided by the spectral pixels and the image pixel data is provided by the image pixels. The method includes both generating spectral information of the image based on the spectral pixel data and generating image information of the image based on the image pixel data.
A camera lens module includes an image sensor and a sandwiched lens structure formed over the image sensor, the sandwiched lens structure including a layer lens between a first glass substrate and a second glass substrate, and a baffle formed between the layer lens and the first glass substrate or between the layer lens and the second glass substrate.
A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion. The transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a reset voltage and the floating diffusion. A lateral overflow integration capacitor (LOFIC) network is coupled between the reset transistor and a bias voltage source. The LOFIC network includes a main LOFIC coupled between the reset transistor and the bias voltage source, and a plurality of subordinate capacitor-switch pairs, each including a subordinate LOFIC and a switch transistor coupled to the subordinate LOFIC. Each of the plurality of subordinate capacitor-switch pairs is coupled between the reset transistor and the bias voltage source.
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
A compound lens includes four coaxially aligned lenses: first lens and, in order of increasing distance therefrom and on a same side thereof, a second lens, a third lens, and a fourth lens. The first lens and the third lens are negative lenses. The second lens and the fourth lens are positive lenses. An image-side surface of the second lens and an object-side surface of the third lens have respective radii of curvature of equal magnitude.
G02B 13/00 - Optical objectives specially designed for the purposes specified below
G02B 9/34 - Optical objectives characterised both by the number of the components and their arrangements according to their sign, i.e. + or – having four components only
60.
THIN, MULTI-LENS, OPTICAL FINGERPRINT SENSOR ADAPTED TO IMAGE THROUGH CELL PHONE DISPLAYS
A multiple-lens optical fingerprint reader for reading fingerprints through a display has an image sensor integrated circuit with photosensor array(s); a spacer; and multiple lenses in a microlens array, each lens of multiple lenses focuses light arriving at that lens from a finger adjacent the display through the spacer to form an image on associated photosensors on a photosensor array of the integrated circuit. A method of verifying identity of a user includes illuminating a finger of the user with an OLED display; focusing light from the fingerprint through arrayed microlenses onto a photosensor array of an integrated circuit, reading the array to overlapping electronic fingerprint images; extracting features from the overlapping electronic fingerprint images or from a stitched fingerprint image, and comparing the features to features of at least one user in a library of features and associated with one or more fingers of one or more authorized users.
A compound lens includes four coaxially aligned lenses: (i) first lens and, in order of increasing distance therefrom, and on a same side thereof, (ii) a second lens, an inter-lens substrate, a third lens, and a fourth lens. The first lens and the third lens are negative lenses. The second lens and the fourth lens are positive lenses.
G02B 15/177 - Optical objectives with means for varying the magnification by axial movement of one or more lenses or groups of lenses relative to the image plane for continuously varying the equivalent focal length of the objective with interdependent non-linearly related movements between one lens or lens group, and another lens or lens group having a negative front lens or group of lenses
G02B 13/18 - Optical objectives specially designed for the purposes specified below with lenses having one or more non-spherical faces, e.g. for reducing geometrical aberration
A self-illuminating camera includes a camera and an illuminator. The camera includes an image sensor and a first lens of a pair of two identical lenses. The illuminator is adjacent to the camera and includes a light source and a second lens of the pair of two identical lenses. The illuminator has a field of illumination that at least partially overlaps a field of view of the camera.
Image sensors with improved negative pump voltage settling, and circuitry for the same, are disclosed herein. In one embodiment, a power supply settling circuit includes a negative charge pump and a reference voltage generator. An output of the negative charge pump is selectively coupled to a first node of the negative pump settling circuit via a first switch, and an output of the reference voltage generator is selectively coupled to a second node of the negative pump settling circuit via a second switch. The first node is further selectively coupled to ground via a third switch, and the second node is further selectively coupled to ground via a fourth switch. The first node can additionally be coupled to a first pad, and the second node can additionally be coupled to a second pad. The pads can each be coupled to a capacitor, such as an off-chip capacitor.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
G05F 3/20 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations
09 - Scientific and electric apparatus and instruments
10 - Medical apparatus and instruments
Goods & Services
Integrated circuits; video processors; microchip image processors; optical image sensors; optical lenses for use with image sensors; optical aspheric lenses and lens assemblies being optical lenses for use in combination with digital signal processing to produce and improve images; semiconductor chips and optical lenses for capturing and processing digital images and video; optical sensors with integrated optical lenses for capturing and processing digital images and video; optical inspection apparatuses for imaging; image signal processing semiconductor chips for use with image sensors to capture, process or improve digital images and video; integrated circuits, semiconductor chips and optical lenses for capturing and processing digital images and video; optical sensors with integrated optical lenses for capturing and processing digital images and video; image signal processing semiconductor chips for use with image sensors to capture, process or improve digital images and video; optical sensors, namely, wafer level optics in the nature of wafer level image sensor modules for use in mobile phones, tablets, notebook computers, personal computers, digital video camcorders, video cameras and recorders, video game consoles used with televisions, automobiles, medical devices, namely, endoscopes and catheters, disposable medical guidewires, security systems, robotic devices, drones, and augmented reality (AR) and virtual reality (VR) devices, namely, headsets, glasses, data gloves, and electrical controllers; endoscope cameras for non-medical use; rigid and flexible endoscopes for non-medical use; guidewires being electric wires for non-medical use; interface circuits for video cameras; electronic display interfaces; interfaces and peripheral devices for computers Medical imaging endoscopy cameras for medical purposes, namely, encephaloscopes, esophagoscopes, thoracoscopes, angioscopes, gastroscopes, proctoscopes, colonoscopes, arthroscopes, rhinoscopes, laryngoscopes, bronchoscopes, mediastinoscopes, nephroscopes, laparoscopes, amnioscopes, cystoscopes, hysteroscopes; endoscopy medical imaging cameras for endoscopes and medical purposes, namely, catheter cameras; endoscope cameras for medical use; medical endoscopes; catheters; medical guidewires; medical imaging apparatus
65.
MULTI-ELEMENT WIDE-FIELD LENS FOR WAFER-ASSEMBLED CHIP-CUBE CAMERAS
A chip-level camera includes an image sensor; a concave L1 lens element on an inside surface of a first substrate; a convex L2 lens element on a first surface of a second substrate; a diaphragm stop on a second surface of the second substrate or on a first surface of a third substrate, the diaphragm stop between the second and third substrates; a convex L3 lens element on a second surface of the third substrate spaced from the image sensor; a first spacer holding first substrate at a predetermined distance from the second substrate; and a second spacer holding the second substrate a predetermined distance from the image sensor. In embodiments, lens element L1 has concave aspheric radius of R1, and lens L2 convex aspheric radius of R2, such that 1.3
A device has a first and second PPD sensor configured for placement over an artery; a camera between the first and second PPD sensors; and a processor having memory with firmware for determining pulse transit time (PTT) between the PPD sensors, and determines blood pressure (BP) therefrom using a calibrated conversion from PTT to BP. The firmware also obtains initial and subsequent images of the artery, extracts features, and adjusts calibrated conversion from PTT to BP based upon features extracted from the initial and subsequent images of the artery. In embodiments the processor enhances the initial and subsequent images of the artery using a structured light tomographic enhancement process. A method uses first and second PPD sensors placed over an artery to determine pulse transit time; obtains initial and subsequent images of the artery with a camera; and uses features extracted from the initial and subsequent images of the artery to adjust a calibrated conversion from PTT to BP.
A61B 5/0295 - Measuring blood flow using plethysmography, i.e. measuring the variations in the volume of a body part as modified by the circulation of blood therethrough, e.g. impedance plethysmography
A61B 5/00 - Measuring for diagnostic purposes Identification of persons
A61B 5/021 - Measuring pressure in heart or blood vessels
67.
FLOATING DIFFUSION REGION FORMED VIA SHARED PHOTOMASK AND METHODS THEREOF
An image sensor including a plurality of photodiodes disposed within a semiconductor substrate proximate to a first side of the semiconductor substrate, a first transfer gate and a second transfer gate that are each disposed proximate to the first side of the semiconductor substrate and coupled to a respective one of the plurality of photodiodes, and a floating diffusion region coupled to the first transfer gate and the second transfer gate is described. The first transfer gate is laterally separated from the second transfer gate by a separation distance. The floating diffusion region extends laterally within the semiconductor substrate a distance greater than the separation distance between the first transfer gate and the second transfer gate. The floating diffusion region includes a central portion surrounded by a peripheral portion. A first dopant concentration of the central portion is greater than a second dopant concentration of the peripheral portion.
The pixel circuit of the image sensor includes one or more photoelectric conversion elements that generates charges in response to incident light, a first capacitance that receives and stores the charges generated in the one or more photoelectric conversion elements, a second capacitance that is connected to the first capacitance via a switch, and a comparator that compares the amount of charges stored in the first capacitance with a predetermined value. The second capacitance is connected to the first capacitance via the switch, and the pixel circuit includes a comparator that compares the amount of the charges stored in the first capacitance with a predetermined value. When the amount of the charges accumulated in the first capacitance in the comparator is greater than the predetermined value, the switch is turned on and the charges are accumulated by the capacitance that is the sum of the first capacitance and the second capacitance.
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
69.
MULTILAYER REFLECTIVE STACK FOR REDUCING CROSSTALK IN SPLIT PIXEL IMAGE SENSORS
An image sensor comprising a semiconductor substrate, a plurality of photodiodes, a multilayer reflective stack, and a dielectric layer is disclosed. The plurality of photodiodes is disposed within the semiconductor substrate and includes a first photodiode and a second photodiode adjacent to the first photodiode. The multilayer reflective stack comprises a first material having a first refractive index and a second material having a second refractive index. The dielectric layer has a third refractive index and is disposed between the first photodiode and the multilayer reflective stack. The first material is disposed between the second material and the dielectric layer. The first refractive index is greater than the second refractive index and the third refractive index.
Image sensors include a pixel die that is stacked on a logic die. The logic die includes at least one function logic element disposed on a bond side thereof, and a logic oxide array of raised logic oxide features also disposed on the bond side. The pixel die includes a pixel array disposed on a light receiving side thereof, and a pixel oxide array of raised pixel oxide features disposed on a bond side of the pixel die. A plurality of outer bonds is disposed between an outer region of the logic die and an outer region of the pixel die. A plurality of inner bonds is formed at an inner region of the image sensor between the pixel oxide array and the logic oxide array, the inner bonds being spaced apart by a plurality of fluidly connected air gaps that extend between the logic die and the pixel die.
H01L 23/467 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing gases, e.g. air
H01L 31/024 - Arrangements for cooling, heating, ventilating or temperature compensation
09 - Scientific and electric apparatus and instruments
Goods & Services
Integrated circuits, semiconductor chips and optical lenses
for capturing and processing digital images and video;
optical sensors with integrated optical lenses for capturing
and processing digital images and video; semiconductor chips
and sensors with near infrared technology for capturing,
processing and enhancing digital images and video;
semiconductor chips and sensors with adaptive charge
detection and conversion technology for capturing extremely
high-contrast scenes for optimum content and image quality
with single exposure; semiconductor chips and sensors with
no-motion-ghost high dynamic range and LED flicker
mitigation technologies to realize crisp image capture even
with extremely bright and dark areas in the same scene;
optical inspection apparatus for imaging; computer hardware
and software sold as a unit for capturing digital images and
video.
72.
CMOS DEVICES WITH ASYMMETRICALLY PASSIVATED ISOLATION STRUCTURE AND METHODS THEREOF
A pixel for an image sensor is described. The pixel comprises a photodiode and an isolation structure disposed within a semiconductor substrate and between a first and second side of the semiconductor substrate. The isolation structure includes a bottom sidewall coupled to a first sidewall and a second sidewall is the isolation structure. The isolation structure is disposed, at least in part, between a gate electrode and the second side of the semiconductor substrate. A first implant region of the semiconductor substrate is disposed proximate to the first sidewall of the isolation. The first implant region is disposed between the photodiode and the first sidewall. A first dopant concentration of the first implant region is greater than a bulk dopant concentration of the semiconductor substrate.
In some embodiments, an image sensor is provided. A signal processing unit of the image sensor is configured with executable instructions that cause the signal processing unit to perform actions comprising: reading a captured scene from a pixel array; reading a value from a test initiation register; in response to determining that the value indicates a test mode: processing the captured scene to detect a region of interest associated with the value; and providing the region of interest to a first interface for transmission to a host device; and in response to determining that the value does not indicate the test mode: analyzing the captured scene using a computer vision technique to selectively generate a signal based on the analysis of the captured scene; and selectively providing the signal to a second interface for transmission to the host device.
A pixel array includes pixel circuits including a first pixel circuit having a first split floating diffusion receiving charge from first and third photodiodes through first and third transfer transistors, and a second split floating diffusion receiving the charge from second and fourth photodiodes through second and fourth transfer transistors. A first shared gate structure includes gates of first transfer transistors of first and second pixel circuits. A third shared gate structure includes gates of third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of second transfer transistors of first and third pixel circuit. A fourth shared gate structure includes gates of fourth transfer transistors the first and third pixel circuits.
A global-shutter pixel includes a semiconductor substrate that has a storage node and a photodiode region. A front surface of the substrate has a first recessed region between the photodiode region and the storage node in a first direction parallel to the front surface, and a second recessed region between the first recessed region and the storage node in the first direction. The first and second recessed regions extend into the substrate to a respective first recess-depth and a second recess-depth that exceeds the first recess-depth. The photodiode region includes (i) a first doped-section spanning a depth-range and having a first dopant concentration, and (ii) a second doped-section between the front surface and the first doped-section and having a second dopant concentration that is less than the first dopant concentration. The first doped-section includes a protrusion that extends at least partially beneath the first recessed region in the first direction.
A pixel array includes pixel circuits including a first pixel circuit having first and second split floating diffusions receiving charge from first and third photodiodes through first and third transfer transistors, and from second and fourth photodiodes through second and fourth transfer transistors, respectively. A first shared gate structure includes gates of first transfer transistors of first and second pixel circuits. A third shared gate structure includes gates of third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of second transfer transistors of first and third pixel circuit. A fourth shared gate structure includes gates of fourth transfer transistors the first and third pixel circuits. A dual floating diffusion transistor is coupled between the first and second split floating diffusions and the third and fourth split floating diffusions to bin charges in the first, second, third, and fourth floating diffusions.
H04N 25/46 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
H04N 25/587 - Control of the dynamic range involving two or more exposures acquired sequentially, e.g. using the combination of odd and even image fields
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/779 - Circuitry for scanning or addressing the pixel array
A multi-band imager includes a first light source that illuminates an area of interest during a first time period and a second light source that illuminates the area of interest during a second time period, the second light source comprising a multi-band pass filter, an image sensor capturing first and second images during the first and second time periods. An enhanced image of the area of interest is generated by combining the first image and the second image.
A61B 1/06 - Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopesIlluminating arrangements therefor with illuminating arrangements
A61B 1/00 - Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopesIlluminating arrangements therefor
An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. An adder input latch stage includes first and second adder input latches including first and second inputs coupled to receive outputs of the GC to binary stage. An adder input multiplexer stage includes an output coupled to second inputs of the adder stage, and first and second inputs coupled to outputs the first and second adder input latches, respectively.
H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
G06F 7/501 - Half or full adders, i.e. basic adder cells for one denomination
G06F 7/57 - Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups or for performing logical operations
79.
Single bitline SRAM pixel and method for driving the same
A novel bit storage circuit includes a first voltage supply line, a second voltage supply line, a bit line, a latch, a first switching transistor, and a blocking transistor. The latch includes an input and an output. The first switching transistor includes a first terminal, a second terminal, and a control terminal. The first switching transistor is operative to provide a conductive path and a non-conductive path between the bit line and the input of the latch responsive to a first control signal being asserted on the control terminal of the first switching transistor. The blocking transistor includes a control terminal and is operative to selectively provide a conductive path and a non-conductive path between the input of the latch and the second voltage supply line responsive to a second control signal. The blocking transistor facilitates the use of a single bit line.
G09G 5/393 - Arrangements for updating the contents of the bit-mapped memory
G09G 3/00 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
A method of operating an imaging system is described. The method comprising transferring first image charges accumulated during a long exposure period of a first image frame to respective floating diffusion regions of a first pixel and a second pixel, reading out long exposure image signals from the respective floating diffusion regions to a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel, transferring second image charges accumulated during a short exposure period of the first image frame to the respective floating diffusion regions of the first pixel and the second pixel, reading out a short exposure image signal from a corresponding one of the floating diffusion regions to the second storage capacitor, and reading out storage charge signals from the first storage capacitor and the second storage capacitor to generate image data for the first image frame.
An imaging system including a sensor wafer and a logic wafer. The sensor wafer includes a plurality of pixels arranged in rows and columns, the plurality of pixels arranged in rows and columns and including at least a first pixel and a second pixel positioned in a first row included in the rows. The sensor wafer includes a first transfer control line associated with the first row, the first transfer control line coupled to both a first transfer gate of the first pixel and a second transfer gate of the second pixel. The logic wafer includes a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel, a first storage control line coupled to a first storage gate associated with the first pixel and a second storage control line coupled to a second storage gate associated with the second pixel.
SiGe photodiode for crosstalk reduction. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor material. Each pixel includes a plurality of photodiodes. The plurality of pixels are configured to receive an incoming light through an illuminated surface of the semiconductor material. Each pixel includes a first photodiode comprising a silicon (Si) material; and a second photodiode having the Si material and a silicon germanium (SiGe) material.
Column arithmetic logic unit design for dual conversion gain sensor supporting correlated multiple sampling and three readout phase detection autofocus
An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage. The feedback stage includes first conversion gain feedback latches configured to latch outputs of the pre-latch stage having a first conversion gain and second conversion gain feedback latches configured to latch outputs of the pre-latch stage having a second conversion gain.
A global shutter image sensor with improved pixel failure coverage detects failures caused by the pixel chip of the image sensor. The global shutter image sensor includes a pixel chip including an array of photodiodes and associated logic, and a logic chip, bonded to the pixel chip, including an array of logic blocks for processing the images detected by the photodiodes. A failure detection circuit coupled to a reference voltage node of the image sensor detects a failure in the pixel chip by capturing a first level of pixel bias current and a second level of pixel bias current wherein a difference between the first level and the second level drives an output of the failure detection circuit either as logic high or as logic low.
H04N 5/367 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response applied to defects, e.g. non-responsive pixels
H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters
Electrical Phase Detection Auto Focus. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor material. Each pixel includes a plurality of photodiodes configured to receive incoming light through an illuminated surface of the semiconductor material. The plurality of pixels includes at least one autofocusing phase detection (PDAF) pixel having: a first subpixel without a light shielding, and a second subpixel without the light shielding. Autofocusing of the image sensor is at least in part determined based on different electrical outputs of the first subpixel and the second sub pixels.
Fixed pattern noise (FPN) reduction techniques in image sensors operated with pulse illumination are disclosed herein. In one embodiment, a method includes, during a first sub-exposure period of a frame, (a) operating a first tap of a pixel to capture a first signal corresponding to first charge at a first floating diffusion, the first charge corresponding to first light incident on a photosensor, and (b) operating a second tap of the pixel to capture a first parasitic signal corresponding to FPN at a second floating diffusion. The method further includes, during a second sub-exposure period of the frame, (a) operating the second tap to capture a second signal corresponding to second charge at the second floating diffusion, the second charge corresponding to second light incident on the photosensor, and (b) operating the first tap to capture a second parasitic signal corresponding to FPN at the first floating diffusion.
H04N 25/67 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/706 - Pixels for exposure or ambient light measuring
H04N 25/709 - Circuitry for control of the power supply
H04N 25/76 - Addressed sensors, e.g. MOS or CMOS sensors
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
87.
FIXED PATTERN NOISE REDUCTION IN IMAGE SENSORS OPERATED WITH PULSED ILLUMINATION
Fixed pattern noise (FPN) reduction techniques in image sensors operated with pulse illumination are disclosed herein. In one embodiment, a method includes, during a first sub-exposure period of a frame, (a) operating a first tap of a pixel to capture a first signal corresponding to first charge at a first floating diffusion, the first charge corresponding to first light incident on a photosensor, and (b) operating a second tap of the pixel to capture a first parasitic signal corresponding to FPN at a second floating diffusion. The method further includes, during a second sub-exposure period of the frame, (a) operating the second tap to capture a second signal corresponding to second charge at the second floating diffusion, the second charge corresponding to second light incident on the photosensor, and (b) operating the first tap to capture a second parasitic signal corresponding to FPN at the first floating diffusion.
H04N 25/671 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
09 - Scientific and electric apparatus and instruments
Goods & Services
(1) Integrated circuits, semiconductor chips and optical lenses for capturing and processing digital images and video; optical sensors with integrated optical lenses for capturing and processing digital images and video; semiconductor chips and sensors with near infrared technology for capturing, processing and enhancing digital images and video; semiconductor chips and sensors with adaptive charge detection and conversion technology for capturing extremely high-contrast scenes for optimum content and image quality with single exposure; semiconductor chips and sensors with no-motion-ghost high dynamic range and LED flicker mitigation technologies to realize crisp image capture even with extremely bright and dark areas in the same scene; optical inspection apparatus for imaging; computer hardware and software sold as a unit for capturing digital images and video.
89.
IMAGE SENSOR STRUCTURE FOR REDUCED PIXEL PITCH AND METHODS THEREOF
A pixel cell for an image sensor including a first semiconductor substrate, a photodiode, and a transfer gate is described. The first semiconductor substrate includes a first side and a second side. The first side is opposite the second side. The photodiode is disposed within the first semiconductor substrate between the first and the second side. The transfer gate is disposed proximate to the first side of the first semiconductor substrate. The transfer gate includes a planar region. The first side of the semiconductor substrate is disposed between the planar region and the photodiode. A lateral area of the photodiode is less than or equal to a lateral area of the planar region of the transfer gate.
An image sensor comprising a semiconductor substrate and pixel cell circuitry is described. The semiconductor substrate includes a first side and a second side opposite the first site. The pixel cell circuitry is disposed proximate to the first side of the semiconductor substrate. The pixel cell circuitry includes an arrangement of individual groups of components, each including a reset gate, a source-follower gate, and a row select gate. The individual groups of components included in the pixel cell circuitry includes a first group and a second group adjacent to the first group, and wherein the source-follower gate of the first group is disposed adjacent to the source-follower of the second group.
A method of detecting an object in an image includes (i) processing, with a machine-learned model, pixel intensities of a pixel pair in a first region of the image, to determine a first confidence score representing a likelihood of the object being present within the first region, and (ii) determining, based on the first confidence score, presence of the object in the first region.
G06V 40/16 - Human faces, e.g. facial parts, sketches or expressions
G06V 10/22 - Image preprocessing by selection of a specific region containing or referencing a patternLocating or processing of specific regions to guide the detection or recognition
G06V 10/24 - Aligning, centring, orientation detection or correction of the image
G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries
92.
Low power event driven pixels with passive, differential difference detection circuitry, and reset control circuits for the same
Low power event driven pixels with passive, differential difference detection circuitry (and reset control circuits for the same) are disclosed herein. In one embodiment, an event driven pixel comprises a photosensor, a photocurrent-to-voltage converter, and a difference circuit. The difference circuit includes (a) a first circuit branch configured to sample a reference light level based on a voltage output by the photocurrent-to-voltage converter, and to output a first analog light level onto a first column line that is based on the reference light level; and (b) a second circuit branch configured to sample a light level based on the voltage, and to output a second analog light level onto a second column line that is based on the light level. A difference between the second analog light level and the first analog light level indicates whether the event driven pixel has detected an event in an external scene.
H04N 25/74 - Circuitry for scanning or addressing the pixel array
H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
93.
LOW POWER EVENT DRIVEN PIXELS WITH ACTIVE DIFFERENCE DETECTION CIRCUITRY, AND RESET CONTROL CIRCUITS FOR THE SAME
Low power event driven pixels and reset control circuits for the same are disclosed herein. In one embodiment, an event driven pixel comprises a photosensor; a photocurrent-to-voltage converter coupled to the photosensor; and a difference circuit coupled to the photocurrent-to-voltage converter. The difference circuit includes a source follower transistor and is configured to generate a signal at a gate of the source follower transistor that is based on a voltage output from the photocurrent-to-voltage converter. The difference circuit is further configured to output a difference signal in response to assertion of a row select signal. The event driven pixel can further include a reset control circuit coupled to the difference circuit and configured to initialize the difference circuit, and to reset the difference circuit when the difference signal output from the event driven pixel indicates a change in the voltage greater than a threshold amount.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H03F 3/16 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
H04N 5/343 - Extracting pixel data from an image sensor by controlling scanning circuits, e.g. by modifying the number of pixels having been sampled or to be sampled by switching between different modes of operation using different resolutions or aspect ratios, e.g. between still and video mode or between interlaced and non-interlaced mode
A pixel circuit includes a first photodiode and a second photodiode. The first and second photodiodes photogenerate charge in response to incident light. A first transfer transistor is coupled to the first photodiode. A first floating diffusion is coupled to the first transfer transistor. A second transfer transistor is coupled to the second photodiode. A second floating diffusion is coupled to the second transfer transistor. A dual floating diffusion transistor is coupled between the first and second floating diffusions. An overflow transistor is coupled to the second photodiode. A capacitor is coupled between a voltage source and the overflow transistor. A capacitor readout transistor is coupled between the capacitor and the second floating diffusion. An anti-blooming transistor coupled between the first photodiode and a power line.
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/46 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
H04N 25/585 - Control of the dynamic range involving two or more exposures acquired simultaneously with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes
H04N 25/621 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
95.
High dynamic range CMOS image sensor pixel with reduced metal-insulator-metal lateral overflow integration capacitor lag
A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a bias voltage source and the floating diffusion. The reset transistor is configured to be switched in response to a reset control signal. A lateral overflow integration capacitor (LOFIC) including an insulating region disposed between a first metal electrode and a second metal electrode is also included. The first metal electrode is coupled to a bias voltage source. The second metal electrode is coupled to the reset transistor and selectively coupled to the floating diffusion.
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
96.
PIXEL DESIGNS WITH REDUCED LOFIC RESET AND SETTLING TIMES
Pixel designs with reduced LOFIC reset and settling times are disclosed herein. In one embodiment, a pixel cell includes a photosensor configured to photogenerate image charge in response to incident light, a floating diffusion to receive the image charge from the photosensor, a transfer transistor coupled between the floating diffusion and the photosensor to transfer the image charge to the floating diffusion, and a first reset transistor coupled between the floating diffusion and the voltage supply. The pixel cell further includes a capacitor having two ends, and a second reset transistor. A first end of the capacitor is coupled to the floating diffusion. The second reset transistor is coupled between a second end of the capacitor and the voltage supply.
A compact camera includes an image sensor, a transparent layer, and a microlens (ML) layer, between the image sensor and the transparent layer. The ML layer forms (a) a first ML array having a plurality of first MLs, and (b) a second ML array with a plurality of second MLs interleaved with the plurality of first MLs. The compact camera also includes a baffle layer, between the ML layer and the image sensor, that forms a plurality of first aperture stops each aligned with a different one of the first MLs and a plurality of second aperture stops each aligned with a different one of the second MLs. The first MLs each have a first set of optical characteristics and the second MLs each have a second set of optical characteristics that are different from the first set of optical characteristics.
H04N 25/131 - Arrangement of colour filter arrays [CFA]Filter mosaics characterised by the spectral characteristics of the filter elements including elements passing infrared wavelengths
H04N 23/45 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
H04N 23/80 - Camera processing pipelinesComponents thereof
98.
Thin, multi-lens, optical fingerprint sensor adapted to image through cell phone displays and with multiple photodiode groups each having separate fields of view for each microlens
An image sensor for imaging fingerprints has multiple photodiode groups each with field of view through a microlens determined by optical characteristics of the microlens and locations of the microlens and openings of upper and lower mask layers. Many photodiode groups have fields of view outwardly splayed from a center-direct field of view. A diameter of openings of the upper mask layer distant from the group having a center-direct field of view is larger than openings of a photodiode group having a center-direct field of view. A method of matching illumination of a group of photodiodes with center-direct field of view to illumination of photodiode groups having outwardly splayed fields of view includes sizing openings in the upper mask layer of photodiode groups with outwardly splayed fields of view larger than openings in the upper mask layer associated with photodiode groups having center-direct field of view.
An imaging system includes a pixel array with pixel circuits, each including a photodiode, a floating diffusion, a source follower transistor, and a row select transistor. The imaging system further includes rolling clamp (RC) drivers, each coupled to a gate terminal of a row select transistor of one of the pixel circuits and each including first and second PMOS transistors coupled between a clamp voltage and the gate terminal of the row select transistor of the one of the pixel circuits, and first, second, and third NMOS transistors coupled between the clamp voltage and the gate terminal of the row select transistor of the one of the pixel circuits. The PMOS transistors and the NMOS transistors are coupled in parallel. The PMOS transistors are configured to provide an upper clamp voltage range, and the NMOS transistors are configured to provide a lower clamp voltage range.
Image sensors for Phase-Detection Auto Focus (PDAF) are provided. An image sensor includes a pixel including a plurality of photodiodes disposed in a semiconductor material according to an arrangement. The arrangement defines a first image subpixel comprising a plurality of first photodiodes, a second image subpixel comprising a plurality of second photodiodes, and a third image subpixel including a plurality of third photodiodes, and a phase detection subpixel comprising a first photodiode, a second photodiode, or a third photodiodes. The pixel can include a plurality of first micro-lenses disposed individually overlying at least a subset of the plurality of photodiodes of the first, second and third image subpixels. The pixel can also include a second micro-lens disposed overlying the phase detection subpixel, a first micro-lens of the first micro-lenses having a first radius less than a second radius of the second micro-lens.
