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2024
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Invention
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Method to induce strain in finfet channels from an adjacent region. Methods and structures for fo... |
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2023
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Invention
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Method to co-integrate sige and si channels for finfet devices.
A method for co-integrating finF... |
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Invention
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Multi-fin finfet device including epitaxial growth barrier on outside surfaces of outermost fins ... |
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2022
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Invention
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Method of making a semiconductor device using a dummy gate.
A method of making a semiconductor d... |
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2019
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Invention
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Method to co-integrate sige and si channels for finfet devices. A method for co-integrating finFE... |
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2018
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Invention
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Self-aligned silicon germanium finfet with relaxed channel region. A self-aligned SiGe FinFET dev... |
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Invention
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Fully substrate-isolated finfet transistor. Channel-to-substrate leakage in a FinFET device is pr... |
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2017
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Invention
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Method to form localized relaxed substrate by using condensation. Methods and structures for form... |
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2016
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Invention
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Method of making a semiconductor device using a dummy gate. A method of making a semiconductor de... |
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Invention
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Finfet device having a partially dielectric isolated fin structure. A semiconductor material is p... |
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2015
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Invention
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Facet-free strained silicon transistor. The presence of a facet or a void in an epitaxially grown... |
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Invention
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Method of making a semiconductor device using spacers for source/drain confinement. A method of m... |
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Invention
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Method for the formation of a finfet device having partially dielectric isolated fin structure. A... |
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Invention
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Method of using a sacrificial gate structure to make a metal gate finfet transistor. A self-align... |
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Invention
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Stacked interconnect heat sink.
A method is provided. The method includes providing an integrate... |
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2014
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Invention
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Fully substrate-isolated finfet transistor. Channel-to-substrate leakage in a FinFET device can b... |
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Invention
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Transistor having a stressed body. A transistor includes a body and a semiconductor region config... |
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Invention
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Methods for designing integrated circuits employing voltage scaling and integrated circuits desig... |
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Invention
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Integration of shallow trench isolation and through-substrate vias into integrated circuit design... |
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Invention
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Multi-layer strained channel finfet. Methods and structures for forming a localized, strained reg... |
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2013
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Invention
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Circuit timing analysis incorporating the effects of temperature inversion.
Methods and apparatu... |
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Invention
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Circuits and methods for efficient clock and data delay configuration for faster timing closure. ... |
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Invention
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System and method for variable frequency clock generation. A variable frequency clock generator. ... |
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Invention
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Finfet with multiple concentration percentages. An apparatus of a semiconductor is provided where... |
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2012
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Invention
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Method of forming a fully substrate-isolated finfet transistor. Channel-to-substrate leakage in a... |
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Invention
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Finfet device with isolated channel. Despite improvements in FinFETs and strained silicon devices... |
