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2023
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Invention
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Multi-layer random access memory and methods of manufacture.
A semiconductor structure for a DRA... |
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2021
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Invention
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3d memory array clusters and resulting memory architecture. A memory architecture for 3-dimension... |
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Invention
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Multi-layer thyristor random access memory with silicon-germanium bases. A semiconductor structur... |
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Invention
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Formation of stacked lateral semiconductor devices and the resulting structures. A method of maki... |
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Invention
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Multi-layer horizontal thyristor random access memory and peripheral circuitry. A semiconductor s... |
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2020
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Invention
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Thyristor volatile random access memory and methods of manufacture. A method of writing data into... |
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Invention
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Multi-layer random access memory and methods of manufacture. A semiconductor structure for a DRAM... |
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Invention
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3d stacked high-density memory cell arrays and methods of manufacture. Integrated circuit devices... |
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2019
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Invention
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Thyristor volatile random access memory and methods of manufacture.
A method of writing data int... |
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2018
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Invention
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High-speed data transfer periods for thyristor memory cell arrays. Aspects of DDR and thyristor m... |
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Invention
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High-density volatile random access memory cell array and methods of fabrication.
Thyristor memo... |
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Invention
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Thyristor memory cell with assist device.
A vertical thyristor memory array including: a vertica... |
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Invention
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Methods of reading and writing data in a thyristor random access memory. A volatile memory array ... |
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Invention
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Thyristor volatile random access memory and methods of manufacture. Operations with reduced curre... |
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Invention
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Methods of reading and writing data in a thyristor random access memory. Single thyristor memory ... |
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Invention
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Thyristor volatile random access memory and methods of manufacture. Memory cells are formed with ... |
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Invention
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Methods of operation for cross-point thyristor memory cells with assist gates. This invention rel... |
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2017
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Invention
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High density vertical thyristor memory cell array with improved isolation. Isolation between vert... |
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Invention
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Method of writing into and refreshing a thyristor volatile random access memory. A method of writ... |
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Invention
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Vertical thyristor memory with minority carrier lifetime reduction. Apparatus and methods for red... |
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Invention
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Six-transistor sram semiconductor structures and methods of fabrication. A two-transistor memory ... |
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Invention
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Two-transistor sram semiconductor structure and methods of fabrication. A two-transistor memory c... |
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2016
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Invention
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Memory disturb recovery scheme for cross-point memory arrays. Methods and systems are described h... |
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Invention
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Systems and methods for managing read voltages in a cross-point memory array. Techniques are prov... |
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Invention
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Memory array having segmented row addressed page registers. The access speeds of new memory techn... |
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Invention
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Systems and methods for managing write voltages in a cross-point memory array. Techniques are pro... |
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Invention
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Thyristor volatile random access memory and methods of manufacture. A volatile memory array using... |
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Invention
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Methods of retaining and refreshing data in a thyristor random access memory. A volatile memory a... |
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Invention
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Methods and systems for reducing electrical disturb effects between thyristor memory cells using ... |
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Invention
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Thyristor memory cell with gate in trench adjacent the thyristor.
A volatile memory array using ... |
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Invention
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Cross-coupled thyristor sram semiconductor structures and methods of fabrication. A memory cell b... |
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2015
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Invention
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Six-transistor thyristor sram circuits and methods of operation. A memory cell based upon cross-c... |
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Invention
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Two-transistor thyristor sram circuit and methods of operation. A two-transistor memory cell base... |
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Invention
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Cross-coupled thyristor sram circuits and methods of operation. A memory cell based upon thyristo... |
