|
2019
|
Invention
|
Estimating pitch of harmonic signals. A time-varying pitch of a signal may be estimated by proces... |
|
2018
|
Invention
|
Uniform system wide addressing for a computing system. A computing system may comprise a pluralit... |
|
|
Invention
|
System and method for analyzing audio information to determine pitch and/or fractional chirp rate... |
|
2017
|
Invention
|
Inclusion monitors. Systems, devices, and techniques for processor synchronization are described.... |
|
|
Invention
|
Exclusion monitors. Systems, devices, and techniques for processor synchronization are described.... |
|
|
Invention
|
Machine learning aggregation. Methods, systems, and apparatus, including computer programs encode... |
|
|
Invention
|
Machine learning aggregation.
Methods, systems, and apparatus, including computer programs encod... |
|
|
Invention
|
Segmentation using prior distributions.
The technology described in this document can be embodie... |
|
|
Invention
|
Classifying signals using mutual information.
Input data may be classified using one or both of ... |
|
|
Invention
|
Harmonic feature processing for reducing noise. Devices, systems and methods are disclosed for re... |
|
|
Invention
|
Affinity data collection in a computing system. A data collecting instrument including an input c... |
|
2016
|
Invention
|
Segmenting utterances within speech.
The technology described in this document can be embodied i... |
|
|
Invention
|
Memory controller for a network on a chip device. Systems and methods may be provided to support ... |
|
|
Invention
|
Disjointed virtual memory scheme with block bypass. An improved virtual memory scheme designed fo... |
|
|
Invention
|
Dedicated fifos in a multiprocessor system.
A semiconductor chip with a first processing element... |
|
|
Invention
|
Flow control through packet router. A router requests a reservation for an egress port prior to d... |
|
|
Invention
|
Packet router buffer management. A router that requests a reservation for an egress port prior to... |
|
|
Invention
|
Network processor inter-device packet source id tagging for domain security.
Systems and techniq... |
|
|
Invention
|
Arbitrating access to a resource that is shared by multiple processors.
In an illustrative examp... |
|
|
Invention
|
Router path selection and creation in a single clock cycle. Systems, devices, and techniques for ... |
|
|
Invention
|
Application domain security.
Methods, systems, and apparatus, including computer programs encode... |
|
|
Invention
|
Encoding for frameless packet transmissions. Methods, systems, and apparatus, including computer ... |
|
|
Invention
|
Classifying signals using correlations of segments. An input signal may be classified by computin... |
|
|
Invention
|
Performing a synchronization operation on an electronic device.
In an illustrative example, a me... |
|
|
Invention
|
Network on chip with task queues.
A network on a chip architecture uses hardware queues to distr... |
|
|
Invention
|
Compute unit including thread dispatcher and event register and method of operating same to enabl... |
|
|
Invention
|
Content addressable memory (cam) implemented tuple spaces. A multi-processor system with a portio... |
|
|
Invention
|
Distributed contiguous reads in a network on a chip architecture. Systems and techniques for netw... |
|
|
Invention
|
Estimating clean speech features using manifold modeling.
The technology described in this docum... |
|
|
Invention
|
Asynchronous interface for communications between computing resources that are in different clock... |
|
|
Invention
|
Chained packet sequences in a network on a chip architecture. Systems and techniques for network ... |
|
|
Invention
|
Synchronization in a multi-processor computing system. In one aspect, a method implemented by a f... |
|
|
Invention
|
Generating models for text-dependent speaker verification.
In one aspect, a method includes rece... |
|
|
Invention
|
Memory-attached computing resource in network on a chip architecture to perform calculations on d... |
|
|
Invention
|
Data routing and buffering in a processing system. In a computing system where an incoming packet... |
|
|
Invention
|
Determining an operation state within a computing system with multi-core processing devices.
Sys... |
|
|
Invention
|
Classifying signals using feature trajectories.
An input signal may be classified by comparing a... |
|
2015
|
Invention
|
Microprocessor including permutation instructions.
Combinational circuits in a microprocessor ex... |
|
|
Invention
|
Dma engine for transferring data in a network-on-a-chip processor. A multiprocessor architecture ... |
|
|
Invention
|
Multiple processor access to shared program memory.
A shared program memory and related componen... |
|
|
Invention
|
Multiple operation interface to shared coprocessor.
In a multi-processor architecture, a plurali... |
|
|
Invention
|
Writing to contiguous memory addresses in a network on a chip architecture. Devices, systems and ... |
|
|
Invention
|
Register communication in a network-on-a-chip architecture.
A network on a chip processor uses u... |
|
|
Invention
|
Performing write operations in a network on a chip device. Systems and methods are provided for p... |
|
|
Invention
|
Performing read operations in network on a chip architecture. Systems and methods to be used by a... |
|
|
Invention
|
Access code obfuscation using speech input. In one aspect, a method includes receiving an identif... |
|
2014
|
Invention
|
I/o data interface for packet processors. Systems and methods to process packets of information u... |
|
2013
|
Invention
|
Reducing octave errors during pitch determination for noisy audio signals. Octave errors may be r... |
