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2025
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G/S
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Semiconductor chips; cryptocurrency hardware wallets;
computer hardware for cryptographic key cr... |
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2024
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G/S
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Semiconductor chips; cryptocurrency hardware wallets; computer hardware for cryptographic key cre... |
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Invention
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Cell cycling to minimize resistive memory random number correlation. Stochastic or near-stochasti... |
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2023
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Invention
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Flexible and configurable bit error rate reduction for non-volatile memory.
Improved bit error c... |
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Invention
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Differential programming of two-terminal memory with program detection and multi-path disablement... |
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Invention
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Matrix multiplication with resistive memory circuit having good substrate density. Configurable a... |
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Invention
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Erase algorithm with a weak program pulse for non-volatile memory.
Improved erase techniques and... |
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Invention
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Non-stoichiometric resistive switching memory device and fabrication methods. Providing for a res... |
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2022
|
Invention
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Generating physical unclonable function data from a transistor of a semiconductor device. A physi... |
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Invention
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Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a c... |
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Invention
|
Differential programming of two-terminal memory with intrinsic error suppression and wordline cou... |
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Invention
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Differential programming of two-terminal resistive switching memory with intrinsic error suppress... |
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Invention
|
Differential programming of two-terminal resistive switching memory with program soaking and adja... |
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Invention
|
Matrix multiplication with resistive memory circuit having good substrate density.
Configurable ... |
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Invention
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Dynamic host allocation of physical unclonable feature operation for resistive switching memory. ... |
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Invention
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Error correction for identifier data generated from unclonable characteristics of resistive memor... |
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Invention
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Reverse programmed resistive random access memory (ram) for one time programmable (otp) applicati... |
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Invention
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Metadata handling for two-terminal memory.
One potential result of differing characteristics for... |
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Invention
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Configuration bit using rram. A field programmable gate array (FPGA) utilizing resistive switchin... |
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2021
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G/S
|
Computer hardware, namely, integrated circuits,
microprocessors, microprocessor cores, memory ci... |
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Invention
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Physically unclonable function (puf) generation involving programming of marginal bits. Stochasti... |
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Invention
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Physically unclonable function (puf) generation involving high side programming of bits. Stochast... |
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Invention
|
Secure circuit integrated with memory layer. A secure integrated circuit comprises a lower logic ... |
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Invention
|
Resistive random access memory erase techniques and apparatus. A method for erasing a memory cell... |
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Invention
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Distinct chip identifier utilizing unclonable characteristics of on-chip resistive memory array. ... |
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Invention
|
Resistive switching memory devices and method(s) for forming the resistive switching memory devic... |
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Invention
|
Varying nitrogen content in switching layer of two-terminal resistive switching devices.
Two-ter... |
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Invention
|
Resistive switching memory having confined filament formation and methods thereof. Resistive swit... |
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Invention
|
Selector device for two-terminal memory. Disclosed is a solid state memory having a non-linear cu... |
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Invention
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Methods and apparatus for facilitated program and erase of two-terminal memory devices. A method ... |
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2020
|
Invention
|
Using aluminum as etch stop layer. A two-terminal resistive switching device (TTRSD) such as a no... |
|
|
Invention
|
Non-stoichiometric resistive switching memory device and fabrication methods.
Providing for a re... |
|
|
Invention
|
Capacitance measurement and apparatus for resistive switching memory devices. A semiconductor dev... |
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|
Invention
|
Resistive random-access memory and architecture with select and control transistors. A semiconduc... |
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Invention
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Computing memory architecture. Provided herein is a computing memory architecture. The non-volati... |
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2019
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Invention
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Formation of structurally robust nanoscale ag-based conductive structure. Providing for improved ... |
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Invention
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Method for fabricating an array of 4f2 resistive non-volatile memory in a nand architecture. 2 ar... |
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Invention
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Non-volatile memory bank with embedded inline computing logic. A non-volatile memory device havin... |
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Invention
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Non-volatile memory cell utilizing volatile switching two terminal device and a mos transistor. A... |
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Invention
|
State change detection for two-terminal memory. A detection circuit that can detect a two-termina... |
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2018
|
Invention
|
Resistive random access memory and fabrication techniques. A self-aligned memory device includes ... |
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|
Invention
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Integrating a resistive memory system into a multicore cpu die to achieve massive memory parallel... |
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2017
|
Invention
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Cache management for memory module comprising two-terminal resistive memory. Cache memory for res... |
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|
Invention
|
Reduced diffusion in metal electrode for two-terminal memory. Providing for two-terminal memory t... |
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G/S
|
Computer hardware, namely, integrated circuits, microprocessors, microprocessor cores, memory cir... |
