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2025
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Invention
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Issuing of chip-configuration requests to an on-chip configuration control bus.
A plurality of c... |
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Invention
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Efficient error detection code.
A device comprising circuitry for determining a plurality of err... |
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2024
|
Invention
|
Execution unit, processing device and method of generating random samples.
An execution unit, th... |
|
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Invention
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Execution unit, processing device and method for approximating a function.
An execution unit con... |
|
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Invention
|
Execution unit, processing device and method of generating random samples. An execution unit, the... |
|
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Invention
|
Execution unit, processing device and method for approximating a function. An execution unit conf... |
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Invention
|
Processing unit.
A processing unit is provided with circuitry enabling execution quick evaluatio... |
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Invention
|
A machine learning system enabling effective training. A machine learning system implements a mac... |
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2023
|
Invention
|
Rotating data blocks.
An execution unit performs a byte-wise rotation of an input data block. An... |
|
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Invention
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Rotating data blocks. An execution unit performs a byte-wise rotation operation of an input data ... |
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Invention
|
Virtual channel buffer bypass. A bypass path is provided in the node for reducing the latency and... |
|
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Invention
|
Overflow event counter. A processing device comprises a register configured to store a count valu... |
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Invention
|
System and method for synchronising access to shared memory.
A read and notify request is issued... |
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Invention
|
Barrier sync signalling.
A data processing device comprising: a plurality of processors, each of... |
|
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Invention
|
Controlling a processor clock. There is disclosed a method of controlling the frequency of a cloc... |
|
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Invention
|
Network computer with two embedded rings. A computer comprising a plurality of interconnected pro... |
|
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Invention
|
Machine learning system enabling effective training.
A machine learning system implements a mach... |
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Invention
|
Machine code instruction. A processing device comprising a plurality of operand registers, wherei... |
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Invention
|
Global event aggregation. Each of the processing devices stores an event vector, which is updated... |
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Invention
|
Heatsink for a memory and routing module.
A heatsink is provided for a memory and routing module... |
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Invention
|
Processing device for intermediate value scaling. A processing device comprising: a control regis... |
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Invention
|
Reset of a multi-node system. Each of the nodes stores a number, referred to herein as a generati... |
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Invention
|
Device event notification.
An error event vector is defined for the device, where each element o... |
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Invention
|
Communication in a computer having multiple processors. A computer comprising a plurality of proc... |
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Invention
|
Floating point norm instruction. A hardware module is provided in an execution unit and is respon... |
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Invention
|
Computer system having a chip configured for memory attachment and routing. A memory attachment a... |
|
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Invention
|
Computer system having multiple computer devices each with routing logic and memory controller an... |
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|
Invention
|
A computer system. A memory attachment and routing chip includes a single die having a set of ext... |
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Invention
|
Dual-mode floating point processor operation.
By providing a mode indication, an execution unit ... |
|
2022
|
Invention
|
Data processing in a machine learning computer.
A computer-implemented method of training a mult... |
|
|
Invention
|
Data processing in a machine learning computer.
A computer-implemented method comprising: proces... |
|
|
Invention
|
Variable format floating point logic.
Logic circuitry for multiplying floating point numbers is ... |
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|
Invention
|
Memory and routing module for use in a computer system. A memory and routing module includes a su... |
|
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Invention
|
Processing device for handling misaligned data. A new type of instruction and a control register ... |
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Invention
|
Fair arbitration between multiple sources targeting a destination. A hardware module comprises at... |
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Invention
|
Initialisation of worker threads.
A processing device comprising: at least one execution unit co... |
|
|
Invention
|
Providing capacitors in analogue circuits.
A computer structure comprises a first silicon substr... |
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Invention
|
A module.
A module (100) includes a package substrate (170) for receiving a flip chip-attached s... |
|
|
Invention
|
Dram module with data routing logic. A memory and routing module (100) includes a substrate (170)... |
|
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Invention
|
A module. A module (100) includes a package substrate (170) for receiving a flip chip-attached se... |
|
|
Invention
|
Variable frame headers.
In order to provide for the extension of either the MAC address or the V... |
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Invention
|
Initialisation of worker threads. A processing device comprising: at least one execution unit con... |
|
|
Invention
|
Generation number for handling resets. One or more bits of the destination MAC address indicate a... |
|
|
Invention
|
Method of testing a stacked integrated circuit device. A method for testing a stacked integrated ... |
|
|
Invention
|
Location based medium access control address.
A data processing system having an address resolut... |
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Invention
|
External exchange connectivity. A processing device has a plurality of interfaces and a plurality... |
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G/S
|
Downloadable computer software for performing analysis of computer applications |
|
|
G/S
|
Computer hardware all being used in an offsite or onsite server data center and all being special... |
|
2021
|
G/S
|
Computer chips; silicon chips; microprocessor chips; semiconductor chips; integrated circuit chip... |
|
|
G/S
|
Computer chips, silicon chips, microprocessor chips,
semiconductor chips, integrated circuit chi... |
|
2018
|
G/S
|
Computer chips, silicon chips, microprocessor chips, semiconductor chips, integrated circuit chip... |
|
|
G/S
|
Software for operating and running computer processors and chips. |
|
2017
|
G/S
|
Software for operating and running computer processors and
chips. |
|
2016
|
G/S
|
Software for operating and running computer processors and chips. |
