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2025
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Invention
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Minimizing shorting between finfet epitaxial regions.
The present invention relates generally to... |
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Invention
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Stacked transistors with different channel widths.
A semiconductor device includes a first stack... |
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2024
|
Invention
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Selective ild deposition for fully aligned via with airgap.
A method is presented forming a full... |
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Invention
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Selective recessing to form a fully aligned via.
A method of forming a semiconductor device havi... |
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Invention
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Nanosheet channel-to-source and drain isolation.
A method and structures are used to fabricate a... |
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Invention
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Forming nanosheet transistor using sacrificial spacer and inner spacers.
Fabricating a nanosheet... |
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Invention
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Fabrication of a vertical fin field effect transistor with reduced dimensional variations.
A met... |
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Invention
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Punch through stopper in bulk finfet device.
A method of forming a semiconductor device that inc... |
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Invention
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Self aligned pattern formation post spacer etchback in tight pitch configurations.
A method of f... |
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Invention
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Semiconductor interconnect structure with double conductors.
Embodiments are directed to a semic... |
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Invention
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Gate cut with integrated etch stop layer.
A method of forming a power rail to semiconductor devi... |
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Invention
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Self aligned replacement metal source/drain finfet.
A fin-shaped field effect transistor (finFET... |
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|
Invention
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Structure and method to improve fav rie process margin and electromigration.
A method of forming... |
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Invention
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Two-color self-aligned double patterning (sadp) to yield static random access memory (sram) and d... |
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Invention
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Semiconductor device including a porous dielectric layer, and method of forming the semiconductor... |
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2023
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Invention
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Nanosheet transistor. Inner and outer spacers for nanosheet transistors are formed using techniqu... |
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Invention
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Advanced copper interconnects with hybrid microstructure.
A device relates to a semiconductor de... |
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Invention
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Forming a sacrificial liner for dual channel devices.
A semiconductor device includes one or mor... |
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Invention
|
Selective recessing to form a fully aligned via. A method of forming a semiconductor device havin... |
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Invention
|
Package-on-package assembly with wire bonds to encapsulation surface.
Apparatuses relating to a ... |
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|
Invention
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Hybrid-channel nano-sheet fets.
Semiconductor devices and methods of forming a first layer cap a... |
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|
Invention
|
Method of forming copper interconnect structure with manganese barrier layer.
Low capacitance an... |
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Invention
|
Fabrication of a vertical fin field effect transistor with reduced dimensional variations. A meth... |
|
|
Invention
|
Gate cut with integrated etch stop layer. A method of forming a power rail to semiconductor devic... |
|
|
Invention
|
Structure and method to improve fav rie process margin and electromigration. A method of forming ... |
|
|
Invention
|
Forming nanosheet transistor using sacrificial spacer and inner spacers. Fabricating a nanosheet ... |
|
|
Invention
|
Self aligned pattern formation post spacer etchback in tight pitch configurations. A method of fo... |
|
|
Invention
|
Selective ild deposition for fully aligned via with airgap. A method is presented forming a fully... |
|
|
Invention
|
Minimizing shorting between finfet epitaxial regions. The present invention relates generally to ... |
|
|
Invention
|
Nanosheet channel-to-source and drain isolation. A method and structures are used to fabricate a ... |
|
|
Invention
|
Air gap spacer formation for nano-scale semiconductor devices. Semiconductor devices having air g... |
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|
Invention
|
Finfet devices.
FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in... |
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Invention
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Alternating hardmasks for tight-pitch line formation. A method for forming fins includes forming ... |
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Invention
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Fabrication of fins using variable spacers.
A method of fabricating semiconductor fins, includin... |
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2022
|
Invention
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Air gap spacer for metal gates.
A method of forming a semiconductor device that includes forming... |
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Invention
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Self-forming barrier for use in air gap formation.
An etch back air gap (EBAG) process is provid... |
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Invention
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Semiconductor structures including middle-of-line (mol) capacitance reduction for self-aligned co... |
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|
Invention
|
Stacked transistors with different channel widths. A semiconductor device includes a first stack ... |
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Invention
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Semiconductor device with reduced via resistance.
A semiconductor interconnect structure having ... |
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|
Invention
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Stable work function for narrow-pitch devices.
A work function setting metal stack includes a co... |
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Invention
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Bulk nanosheet with dielectric isolation. Techniques for dielectric isolation in bulk nanosheet d... |
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Invention
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Package-on-package assembly with wire bonds to encapsulation surface. Apparatuses relating to a m... |
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|
Invention
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Forming self-aligned vias and air-gaps in semiconductor fabrication.
A semiconductor device incl... |
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Invention
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Structure and process to tuck fin tips self-aligned to gates. A semiconductor structure is provid... |
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2021
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Invention
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Fabrication of nano-sheet transistors with different threshold voltages. A method of forming two ... |
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2020
|
Invention
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Sram design to facilitate single fin cut in double sidewall image transfer process. A double side... |
