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2024
|
Invention
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Processor cluster address generation.
Techniques for data manipulation using processor cluster a... |
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2023
|
Invention
|
Integer matrix multiplication engine using pipelining. Techniques for data manipulation using int... |
|
|
Invention
|
Processor graph execution using interrupt conservation.
Techniques for data manipulation using p... |
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2021
|
Invention
|
Processor graph execution using interrupt conservation. Techniques for data manipulation using pr... |
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2020
|
Invention
|
Processor cluster address generation. Techniques for data manipulation using processor cluster ad... |
|
|
Invention
|
Multidimensional address generation for direct memory access. Techniques for data manipulation us... |
|
|
Invention
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Matrix multiplication engine using pipelining. Techniques for data manipulation using a matrix mu... |
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2019
|
Invention
|
Data flow graph computation using exceptions. Techniques are disclosed for data manipulation with... |
|
|
Invention
|
Neural network output layer for machine learning. Techniques for a neural network output layer fo... |
|
|
Invention
|
Data flow graph node update for machine learning.
Techniques are disclosed for data flow graph n... |
|
|
Invention
|
Data flow graph node parallel update for machine learning.
Techniques are disclosed for data flo... |
|
|
Invention
|
Power control for a dataflow processor. Techniques are disclosed for power conservation. A plural... |
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2018
|
Invention
|
Logical elements with switchable connections in a reconfigurable fabric. Techniques are disclosed... |
|
|
Invention
|
Branchless instruction paging in reconfigurable fabric. Circular buffers containing instructions ... |
|
|
Invention
|
Joining data within a reconfigurable fabric. Techniques are disclosed for managing data within a ... |
|
|
Invention
|
Reconfigurable processor fabric implementation using satisfiability analysis. Disclosed technique... |
|
|
Invention
|
Selectively combinable directional shifters. An apparatus for mathematical manipulation is descri... |
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2017
|
Invention
|
Reconfigurable fabric direct memory access with multiple read or write elements. Techniques are d... |
|
|
Invention
|
Power control within a dataflow processor. Techniques are disclosed for power conservation. A plu... |
|
|
Invention
|
Communication between dataflow processing units and memories. A combination of memory units and d... |
|
|
Invention
|
Timing analysis and optimization of asynchronous circuit designs. Methods and systems for timing ... |
|
|
Invention
|
Hum generation using representative circuitry. Disclosed embodiments select a proper hum frequenc... |
|
|
Invention
|
Reconfigurable interconnected programmable processors. A plurality of software programmable proce... |
|
|
Invention
|
Logical elements with switchable connections for multifunction operation. Clusters of logical ele... |
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2016
|
Invention
|
Data transfer circuitry given multiple source elements. An interface circuit is disclosed for the... |
|
|
Invention
|
Data uploading to asynchronous circuitry using circular buffer control. Disclosed embodiments pro... |
|
|
Invention
|
Instruction paging in reconfigurable fabric. Circular buffers containing instructions that enable... |
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2015
|
Invention
|
Compact logic evaluation gates using null convention. Compact logic evaluation gates are built us... |
|
|
Invention
|
Computing resource allocation based on flow graph translation. Systems and methods are disclosed ... |
|
|
Invention
|
Multi-threshold flash ncl logic circuitry with flash reset. Multi-threshold flash Null Convention... |
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2014
|
Invention
|
Logical elements with switchable connections. Clusters of logical elements are interconnected by ... |
|
|
Invention
|
Multi-threshold circuitry based on silicon-on-insulator technology. Multiple threshold voltage ci... |
|
|
Invention
|
Software based application specific integrated circuit. A processing device is provided. A cluste... |
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2013
|
Invention
|
Selectively combinable shifters. An apparatus for mathematical manipulation is described allowing... |
|
|
Invention
|
Extensible iterative multiplier. An extensible iterative multiplier design is provided. Embodimen... |
|
|
Invention
|
Hum generation circuitry. Systems and methods for clock generation and distribution are disclosed... |
|
|
Invention
|
Implementation method for fast ncl data path. An implementation method for a fast Null Convention... |
|
|
Invention
|
Self-ready flash null convention logic. A self-ready flash null Convention Logic (NCL) gate inclu... |
|
|
Invention
|
Multi-threshold flash ncl circuitry. Multi-threshold flash Null Convention Logic (NCL) includes o... |
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2012
|
Invention
|
Method and apparatus for ensuring data cache coherency. A multithreaded processor can concurrentl... |
