NEO Semiconductor, Inc.

United States of America

 
Total IP 59
Total IP Rank # 23,079
IP Activity Score 2.5/5.0    47
IP Activity Rank # 15,616
Dominant Nice Class Scientific and electric apparatu...

Patents

Trademarks

33 0
0 0
25 0
1
 
Last Patent 2024 - 3d cell and array structures
First Patent 2012 - Method and system for adaptive p...
Last Trademark 2024 - 3D X-DRAM
First Trademark 2024 - 3D X-DRAM

Industry (Nice Classification)

Latest Inventions, Goods, Services

2024 G/S Semi-conductor memories; Semi-conductor memory units; Semiconductor chip sets; Semiconductor chip...
Invention 3d cell and array structures. Various 3D cells, array structures, and processes are disclosed. In...
Invention 3d cell and array structures. Various 3D cells, array structures, and processes are disclosed. I...
Invention 3d memory cells and array architectures. Various 3D memory cells, array architectures, and proces...
Invention 3d memory cells and array architectures. Various 3D memory cells, array architectures, and proce...
2023 Invention 3d memory cells and array architectures and processes. Various 3D memory cells, array architectu...
Invention 3d memory cells and array architectures and processes. Various 3D memory cells, array architectur...
2022 Invention Methods and apparatus for nand flash memory. Methods and apparatus for NAND flash memory are disc...
Invention Methods and apparatus for nand flash memory. Methods and apparatus for NAND flash memory are dis...
Invention Methods and apparatus for a novel memory array. Methods and apparatus for a novel memory array ar...
2021 Invention Methods and apparatus for nand flash memory. Methods and apparatus for memory operations disclose...
2020 Invention Methods and apparatus for reading nand flash memory. Methods and apparatus for reading NAND flash...
2019 Invention Methods and apparatus for a three-dimensional (3d) array having aligned deep-trench contacts. Met...
Invention Methods and apparatus for a three-dimensional (3d) array having aligned deep-trench contacts. Me...
Invention Cmos anti-fuse cell. A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an ...
Invention Methods and apparatus for writing nonvolatile 3d nand flash memory using multiple-page programmin...
2018 Invention Method and apparatus for providing multi-page read and write using sram and nonvolatile memory de...
2017 Invention Method and apparatus for storing information using a memory able to perform both nvm and dram fun...
2016 Invention Compact anti-fuse memory cell using cmos process. A compact CMOS anti-fuse memory cell. In one as...
Invention Vehicle vision system. Vehicle visual systems are disclosed to produce seamless and uniform surro...
Invention Dual function hybrid memory cell. A dual function hybrid memory cell is disclosed. In one aspect,...
Invention A cmos anti-fuse cell. A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes a...
Invention Two transistor sonos flash memory. A two transistor SONOS flash memory is disclosed. In one aspec...
Invention Three-dimensional double density nand flash memory. A three-dimensional double-density NAND flas...
Invention Sonos byte-erasable eeprom. A SONOS byte-erasable EEPROM is disclosed. In one aspect, an apparatu...