Arteris, Inc.

United States of America


 
Total IP 122
Total IP Rank # 10,630
IP Activity Score 2.9/5.0    134
IP Activity Rank # 5,112
Stock Symbol AIP (nasdaq)
ISIN US04302A1043
Market Cap. 361M  (USD)
Dominant Nice Class Scientific and electric apparatu...

Patents

Trademarks

97 14
0 0
0 4
7
 
Last Patent 2024 - Tool for supporting use of regul...
First Patent 2014 - Estimation of chip floorplan act...
Last Trademark 2023 - FlexWay
First Trademark 2002 - ARTERIS

Industry (Nice Classification)

Latest Inventions, Goods, Services

2024 Invention Automatic configuration of pipeline modules in a network-on-chip (noc). Generation of a full reg...
Invention System and method for transaction broadcast in a network on chip. A broadcast adapter in a netwo...
Invention Tool for supporting use of regular network topologies in generating a network-on-chip topology. ...
Invention System and method for generation of a network using physical awareness data from an image of a ch...
Invention Design tool for automated placement constraint generation, adapter insertion process, and local a...
Invention Design tool for interactive incremental placement of elements on floorplan. A tool is disclosed ...
Invention Design tool for interactive wire routing during the generation of a network-on-chip. System and ...
Invention Incremental topology modification of a network-on-chip. An initial Network on Chip (NoC) topolog...
2023 Invention System and method for using interface protection parameters. A system and method for adding inte...
Invention Constraints and objectives used in synthesis of a network-on-chip (noc). A tool for executing per...
Invention System and method for predicting performance, power and area behavior of soft ip components in in...
Invention System and method to generate a network-on-chip (noc) description using incremental topology synt...
Invention Network-on-chip (noc) with a broadcast switch system. A system and methods of use for a broadcas...
G/S Computer software used as a development tool for use in the design of integrated circuits and sys...
Invention Process for generating physical implementation guidance during the synthesis of a network-on-chip...
G/S Electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits,...
Invention Model-driven approach for failure mode, effects, and diagnostic analysis (fmeda) automation for h...
Invention Quality metrics for optimization tasks in generation of a network. Qualifying networks properties...
Invention System and method for deterministic and incremental physically-aware network-on-chip generation. ...
2022 Invention Cache coherent system implementing victim buffers. In accordance with various aspects of the inve...
Invention System and method for event messages in a cache coherent interconnect. A cache coherent interconn...
Invention Testbenches for electronic systems with automatic insertion of verification features. A system an...
Invention Network-on-chip (noc) using deadline based arbitration. A system and method to arbitrate based o...
Invention Unique identifier creation and management for elaborated platform. Systems and methods are discl...
Invention Mechanism to control order of tasks execution in a system-on-chip (soc) by observing packets in a...
Invention System and method for deadlock detection in network-on-chip (noc) having external dependencies. ...
Invention Multi-level partitioned snoop filter. A system and method that partitions a snoop filter into sub...
Invention Synthesis of a network-on-chip (noc) for insertion of pipeline stages. A tool makes modification...
Invention System and method for editing a network-on-chip (noc). A system and method implemented by tool is...
Invention System and method for area and timing assessment of a network-on-chip (noc) implementation. A sy...
Invention Broadcast adapters in a network-on-chip. A broadcast adapter in a network-on-chip (NoC) is used f...
Invention System and method for scripting generators. A system (and method) is disclosed that automate cre...
Invention System and method to determine optimal path(s) and use load balancing in an interconnect. A syste...
Invention System and method for data loss and data latency management in a network-on-chip with buffered sw...
Invention System and method for generation of a report and debug of address transformations in electronic s...
Invention Switch with virtual channels for soft locking in a network-on-chip (noc). A system and method for...
G/S downloadable computer software used as a development tool for use in the design of integrated cir...
G/S Development of new electronic technology for others in the fields of system-on-chip devices, inte...
Invention System and method to enter and exit a cache coherent interconnect. A cache coherent interconnect ...
Invention Automatic configuration of pipeline modules in an electronics system. Generation of a full regist...
Invention System and method for round robin arbiters in a network-on-chip (noc). In a network-on-chip (NoC)...
Invention Incremental topology modification of a network-on-chip. An initial Network on Chip (NoC) topology...
Invention Optimization of parameters for synthesis of a topology using a discriminant function module. A to...
Invention System and method for synthesis of connectivity to an interconnect in a multi-protocol system-on-...
2021 G/S Downloadable computer software used as a development tool for use in the design of integrated cir...
G/S Providing temporary use of online, non-downloadable software for delivery and configuration of i...
2020 Invention System and method for generating and using a context block based on system parameters. A system a...
Invention Broadcast switch system in a network-on-chip (noc). A system and methods of use for a broadcast s...
Invention Synthesis of a network-on-chip (noc) using performance constraints and objectives. Systems and me...
Invention Management of a buffered switch having virtual channels for data transmission within a network. A...
Invention Queue management system, starvation and latency management system, and methods of use. A quality ...
Invention Generation of hardware design using a constraint solver module for topology synthesis. In accorda...
Invention System and method for using soft lock with virtual channels in a network-on-chip (noc). A system ...
Invention System and method for generation of quality metrics for optimization tasks in topology synthesis ...
G/S Providing temporary use of online, non-downloadable software for delivery and configuration of in...
G/S Providing temporary use of online, non-downloadable computer software for use as a development to...
2019 G/S Electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits...
2018 G/S Computer software, namely, software application design tools for use in configuring on-chip cache...
2015 G/S Interconnect IP technology, namely, protocol adapters, switching elements, data path converters, ...
G/S Computer software used as a development tool for the design of integrated circuits and system-on-...
2012 G/S Computer software used as a development tool for use in the design of integrated circuits and sy...
2011 G/S Computer software used as a simulation and analysis tool for use in the design of integrated circ...
2009 G/S computer software used as a development tool for use in the design of integrated circuits and sys...
G/S [ computer software used as a development tool for use in the design of integrated circuits and s...
2002 G/S Electric and electronic components, namely semiconductors, electronic circuits, microcircuits, in...