[Problem] To reduce the size of a semiconductor device by improving the area utilization efficiency of a circuit laid out between a through-electrode mounting region (or a bump-electrode mounting region) and an internal circuit. [Solution] This semiconductor device is provided with the following: nine surface micro-bumps (MFB1 through MFB9) laid out in a 3×3 matrix on a semiconductor substrate; a transistor (621) that contains first and second diffusion layers formed on the semiconductor substrate; and power-supply wiring (81) laid out on the semiconductor substrate. The aforementioned first diffusion layer is connected to one of the surface micro-bumps (MFB1), the second diffusion layer is connected to the power-supply wiring (81), and the transistor (621) is laid out in the region between the surface micro-bumps (MFB4 through MFB6) located on one edge in an X direction and the surface micro-bumps (MFB7 through MFB9) located on the other edge in said X direction.
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
This semiconductor device comprises the following: a semiconductor substrate (10) that contains a pillar (11); an element isolator (15) formed next to part of a side surface of said pillar (11); an epilayer (14) formed on top of the pillar (11); a first contact plug (31) that supplies a first voltage to the epilayer (14); a fuse electrode (12) formed along the part of the aforementioned pillar (11) side surface next to which the element isolator (15) is not formed; a fuse-insulating film (22) formed between the fuse electrode (12) and the pillar (11); and a second contact plug (32) that is electrically connected to the fuse electrode (12) and supplies a second voltage thereto.
H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
3.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device which is provided with: a wiring substrate which has a first region, and a relay pad and a connection pad that are arranged outside the first region; a first semiconductor chip which has an electrode pad that is formed on one surface, and which is mounted on the first region of the wiring substrate; a first wire that connects the electrode pad and the relay pad with each other; and a second wire that connects the relay pad and the connection pad with each other.
H01L 23/12 - Supports, p. ex. substrats isolants non amovibles
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
[Problem] To provide a highly noise-resistant high-precision duty regulator circuit. [Solution] A semiconductor device comprises a plurality of clocked inverters (CV1, CV2, CV4, CV8) which are inserted into a clock signal propagation path and are mutually connected in parallel. Pull-up circuits (UP) of the clocked inverters (CV1, CV2, CV4, CV8) are respectively controlled in isolation by control signals (P11, P12, P14, P18) which are generated on the basis of a clock signal duty ratio. Pull-down circuits (DN) of the clocked inverters (CV1, CV2, CV4, CV8) are respectively controlled in isolation by control signals (N11, N12, N14, N18) which are generated on the basis of the clock signal duty ratio. With the present invention, it is possible to change the duty ratio of a transiting clock signal without making fine adjustments to the bias level, as the plurality of clocked inverters which are controlled in isolation from one another are connected in parallel.
H03K 5/04 - Mise en forme d'impulsions par augmentation de duréeMise en forme d'impulsions par diminution de durée
G11C 11/407 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation pour des cellules de mémoire du type à effet de champ
This semiconductor device is formed by stacking a plurality of semiconductor chips that each have a plurality of bump electrodes, each of the plurality of semiconductor chips being provided with an identification section formed on a respective side face. Each semiconductor chip has a similar arrangement for its respective plurality of bump electrodes, and each identification section is formed so that the positional relationship with a respective reference bump electrode provided at a specific location among the respective plurality of bump electrodes is the same in each semiconductor chip. The plurality of semiconductor chips are stacked such that the bump electrodes provided thereon are electrically connected in the order of stacking of the semiconductor chips, while the side faces on which the identification sections are formed are oriented in the same direction.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
6.
SEMICONDUCTOR DEVICE, DATA PROGRAMMING DEVICE, AND METHOD FOR IMPROVING THE RECOVERY OF BIT LINES OF UNSELECTED MEMORY CELLS FOR PROGRAMMING OPERATION
A device comprises a non-volatile memory array, a first selection circuit selecting whether to make a first connection path between a first bit line and a first circuit node, and selecting whether to make a second connection path between the first bit line and a second circuit node, a power supplying circuit supplying a power supply voltage to the first circuit node, the power supply voltage being, when the first connection path is selected to be made, supplied to the first bit line, and a first voltage supplying circuit supplying a first voltage to the second circuit node, the first voltage being, when the second connection path is selected to be made, supplied to the first bit line, the first voltage and the power supply voltage being higher than a ground potential, and the first voltage being higher than the power supply voltage.
[Problem] To optimize a balance between signal line remedy and transmission speed in a layered semiconductor device. [Solution] An interface chip (IF) comprises a plurality of driver circuits (30). Each core chip (CC) comprises a plurality of receiver circuits (40). The interface chip (IF) and the plurality of core chips (CC) are connected by through-silicon vias (TSV). A first driver circuit (30) is connected to a second receiver circuit (40) by way of a first TSV. A second driver circuit (30) is connected to a second receiver circuit (40) by way of a second TSV. A signal (F1) among various signals is inputted into both the first and second driver circuits (30), and is outputted from both the first and second receiver circuits (40).
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
G11C 5/00 - Détails de mémoires couverts par le groupe
G11C 29/00 - Vérification du fonctionnement correct des mémoiresTest de mémoires lors d'opération en mode de veille ou hors-ligne
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
[Problem] To achieve a reduction in the power consumption of a semiconductor device. [Solution] A semiconductor device is provided with: a transistor (T1) having one end which is connected to a main input/output line (MIOB), and having another end to which a power supply potential (VDD) is supplied; a transistor (T2) having one end which is connected to a main input/output line (MIOT), and having another end to which the power supply potential (VDD) is supplied; a transistor (T3) having one end which is connected to the main input/output line (MIOB), and having another end to which a ground potential (VSS) is supplied; a transistor (T4) having one end which is connected to the main input/output line (MIOT), and having another end to which the ground potential (VSS) is supplied; and a control circuit (55) that controls the on/off states of the transistors (T1 to T4) on the basis of data to be supplied to the pair of main input/output lines (MIO). The transistors (T1, T2) are configured in such a manner that a first potential, which is lower than the power supply potential (VDD), is supplied to the corresponding main input/output lines when said transistors are on. The transistors (T3, T4) are configured in such a manner that the ground potential (VSS) is supplied to the corresponding main input/output lines when said transistors are on.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
The present invention provides a semiconductor device wherein the current drive capacities of transistors that are arranged in adjacent active regions can be improved without having the operations of the transistors arranged in the adjacent active regions interfere with each other. This semiconductor device comprises: first and second transistors (31-1, 31-2) that are arranged in a first active region (19-1) and have first and second word lines (74, 75); and first and second transistors (32-1, 32-2) that are arranged in the first active region (19-1) and have third and fourth word lines (98, 99). The first word line (74) that constitutes the first transistors (31-1, 32-1) is configured to be in contact with a second element isolation region (17A) or a second element isolation region (17B), and the fourth word line (99) that constitutes the second transistors (31-2, 32-2) is configured to be in contact with the second element isolation region (17B) or a second element isolation region (17C).
This semiconductor device is configured to comprise a capacitor that is provided with: a lower electrode (601) which is arranged on a semiconductor substrate; a second protective film (602); a dielectric film (603) which has a defect (610) that extends in the film thickness direction from an upper surface (603S) that faces the second protective film; a third protective film (604) which has at least a defect filling film (604B) that is formed of an insulating body filling the defect (610); a first protective film (605) which covers the dielectric film (603) and the third protective film (604); and an upper electrode (606) which covers the first protective film (605).
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
H01L 21/316 - Couches inorganiques composées d'oxydes, ou d'oxydes vitreux, ou de verres à base d'oxyde
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
The present invention realizes a highly versatile input circuit having a simple configuration and includes: first and second input terminals; a first transistor in which a control terminal is connected to the first input terminal; a second transistor in which a control terminal is connected to the second input terminal; third and fourth transistors in which the respective control terminals are connected to each other at a first node, the third and fourth transistors being respectively connected to the first and second transistors; a fifth transistor in which a control terminal is connected to the first input terminal; a sixth transistor in which a control terminal is connected to the second input terminal; seventh and eighth transistors in which the respective control terminals are connected to each other at a second node, the seventh and eighth transistors being respectively connected to the fifth and sixth transistors; and a switch connected between the first node and the second node.
The invention relates to a semiconductor device that can realize a layout suited for miniaturization and which facilitates reading of the information written to a memory cell located furthest from a bit line impurity diffusion region. The semiconductor device includes a bit line (43) extending in a straight line in the horizontal direction and an active region (19-1) comprising a first and a second horizontal active region (81, 82), and a sloped active region (83) arranged between the first and the second horizontal regions. A bit line impurity diffusion region (41) is arranged at the center of the active region, a first and a second word line (89, 103) are arranged in the first and second horizontal active region segments, respectively. A third and a fourth word line (95, 98) are arranged in the sloped active region segment with the bit line impurity diffusion region interposed therebetween.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
G11C 5/02 - Disposition d'éléments d'emmagasinage, p. ex. sous la forme d'une matrice
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c.-à-d. rafraîchissement externe avec une porte à transfert de charges, p. ex. un transistor MOS, par cellule
13.
SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREFOR
[Problem] To inhibit the occurrence of data retention failures. [Solution] A semiconductor device (50) is provided with: a semiconductor substrate (1) provided with a main surface (1a); an active region (K) partitioned by element-isolation regions provided to the main surface (1a); a trench (8a) provided to the semiconductor substrate (1) so as to extend in a Y direction and intersect the active region (K); and a saddle fin (4a) which protrudes from a bottom surface of an active-region (K) intersecting portion of the trench (8a), and extends in an X direction. One end (4aa) of the saddle fin (4a) in the X direction is in contact with a trench side surface (8aa), i.e. one side surface of the trench (8a) in the X direction. Another end (4ab) of the saddle fin (4a) in the X direction is in contact with a trench side surface (8ab), i.e. another side surface of the trench (8a) in the X direction. An upper surface (4ac) of the saddle fin (4a) is inclined towards the trench side surface (8ab) from the trench side surface (8aa).
A first space partitioned by first and second line patters (52, 53) is filled with a multilayer film that is composed of a first silicon film (55) having a high impurity concentration (a first concentration) relative to a standard plug impurity concentration (a third concentration) and a second silicon film (57) having a low impurity concentration (a second concentration) relative to the standard plug impurity concentration, and is divided by forming a groove (59) using a mask film (58) on the side wall of the second line pattern (53). As a result, expansion of a seam, which is formed only on the second silicon film (57) having a low impurity concentration, is suppressed. After that, an isolation insulating film is embedded in the groove and impurity diffusion is carried out by a heat treatment, so that divided plugs (60) as a whole are made to have the third concentration.
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
[Problem] To stop a writing operation when an error is present in write data. [Solution] The present invention comprises: a latch circuit (L20) which latches a data mask signal (DM) in response to a one-shot signal (NS), and changes the data mask signal (DM) to an active level in response to an error signal (ERR), which indicates that an error is present in write data (DQ), being at an active level; a buffer circuit (BF2) which outputs the data mask signal (DM) that has been latched by the latch circuit (L20), said data mask signal (DM) being output in response to a write clock signal (WCLK2); and a main amplifier (80) which outputs the write data (DQ) to an internal circuit on the condition that the data mask signal (DM) which has been output from the buffer circuit (BF2) is at an inactive level. The present invention can prevent the writing of erroneous write data, and is capable of preventing increased chip surface area.
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques
G11C 11/407 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation pour des cellules de mémoire du type à effet de champ
Provided is a semiconductor device with which the impact of optical proximity effects in lithography can be avoided and the ease of forming a contact hole can be ensured. A semiconductor device having one parallel transistor for connecting in parallel a plurality of vertical transistors disposed in an active region on a semiconductor substrate, wherein the parallel transistor is constituted of: a plurality of semiconductor pillars that project out in a direction perpendicular to a main surface of the semiconductor substrate; a lower diffusion layer that is disposed below the plurality of semiconductor pillars; a plurality of upper diffusion layers that are each disposed on an upper section of the plurality of semiconductor pillars; and gate electrodes disposed, with a gate insulator film therebetween, on the entire side surfaces of the plurality of semiconductor pillars. The plurality of upper diffusion layers are connected to one upper contact plug that is disposed over the plurality of upper diffusion layers.
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
17.
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Provided is a technology of reducing generation of peeling between a sealing resin and a semiconductor chip due to pressure relating to a semiconductor chip end section where internal stress of the sealing resin specially concentrates. The present invention provides a semiconductor device wherein at least a rear surface end section of a semiconductor chip has a rough surface portion, and a method for manufacturing the semiconductor device.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
18.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Provided is a semiconductor device that is provided with: a semiconductor substrate (10) having a main surface (S); a plurality of bit lines (BL1) that extend in the first direction parallel to the main surface (S), said bit lines being at positions at a distance (L1) in the normal line direction of the main surface (S) from the main surface (S); and a plurality of bit lines (BL2) that extend in the first direction at positions at a distance (L2) in the normal line direction of the main surface (S) from the main surface (S). The distance (L1) and the distance (L2) are different from each other, and the bit lines (BL1) and the bit lines (BL2) are parallel to the main surface (S), and are alternately disposed when viewed from the second direction perpendicular to the first direction.
A method for manufacturing a semiconductor device, wherein: a electroconductive layer including a protruding part having a top face and side faces is formed on a semiconductor substrate; a plate electrode layer, a mask layer, and a photoresist layer are conformally formed in that order on the electroconductive layer; the photoresist layer is patterned to expose a part of the mask layer so that the portions of the photoresist layer facing the top face and side faces of the protruding part are caused to remain; the mask layer is etched using the patterned photoresist layer as a mask; the exposed portions of the mask layer are removed; the edge sections of the mask layer thus formed are caused to recede; and the mask layer remaining after etching is used as a mask in etching the plate electrode layer.
This invention makes it possible to apply, as an embedded insulation film on a gate electrode in a semiconductor device, an insulation film that has excellent etching properties and yet has a low groove-embedding performance, and to ensure sufficient insulation with regard to the gate electrode and reliably prevent short-circuiting with a contact plug or wiring. A semiconductor device having a groove formed on one surface of a semiconductor substrate (105), a gate electrode (109) formed on the lower part of the groove with a gate insulation film (107) interposed therebetween, a side wall insulation film (110) made of a nitride film formed on the inner wall of the groove above the gate electrode (109), and an embedded insulation film (111) formed in the groove enclosed by the side wall insulation film (110) above the gate electrode (109). The side wall insulation film (110) is shaped so that the width increases closer the bottom part of the groove.
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 29/41 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
[Problem] To test whether or not an input buffer or an output buffer performs normally. [Solution] The present invention is provided with: a microbump (MFBa); a test pad (TP); an output buffer (OB) in which an output node is connected to the microbump (MFBa); an input buffer (IB) in which an input node is connected to the microbump (MFBa); a memory cell array (60); a data comparison circuit (65) in which an output node is connected to the test pad (TP); a read/write bus (RWBS) which connects an input node of the output buffer (OB) with the memory cell array (60); and a test bus (TBS) which connects an output node of the input buffer (IB) with an input node of the data comparison circuit (65). According to the present invention, it is possible to assess, by way of a performance test, whether or not the output buffer (OB) and the input buffer (IB) are performing normally, without using the microbump (MFBa).
G11C 29/12 - Dispositions intégrées pour les tests, p. ex. auto-test intégré [BIST]
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
G11C 5/00 - Détails de mémoires couverts par le groupe
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques
22.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
[Problem] To provide a semiconductor device suitable for use as an upper-side package of a semiconductor device having a PoP structure. [Solution] This invention is provided with a semiconductor chip (10) flip-chip mounted on one surface (32) of a wiring board (30), and a semiconductor chip (20) flip-chip mounted on the other surface (33) of the wiring board (30), the semiconductor chips (10, 20) being installed in directions that differ by 90°. It is thereby possible to prevent the layout of wiring patterns (41, 42) on the wiring board (30) from becoming locally congested and enhance the freedom of layout. In addition, when the semiconductor chips (10, 20) are mounted on the wiring board (30), the location at which the load concentrates can be held by a stage, thereby making it possible to prevent the wiring board from deforming.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
This method for manufacturing a device comprises: a step wherein a plurality of element isolation regions, each having a projection part that protrudes above the upper surface of a semiconductor substrate, are formed and a first recessed part is formed between adjacent projection parts; a step wherein a charge trapping layer and a protective insulating film are formed as a laminate so as to cover the bottom surface of the first recessed part and the lateral surfaces and the upper surfaces of the projection parts, thereby forming a second recessed part, which is configured of the protective insulating film, within the first recessed part; a step wherein a sacrificial film is formed on the entire surface so that the second recessed part is buried; and a step wherein the sacrificial film, the protective insulating film, the charge trapping layer and the projection part are etched and removed with use of a dry etching method until the surface of the protective insulating film serving as the bottom surface of the second recessed part is exposed.
H01L 27/115 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
24.
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING SAME
The present invention implements an efficient page mode in a semiconductor device provided with resistance-change memory cells. Said semiconductor device is provided with the following: a word line; a plurality of bit lines; a plurality of resistance-change memory cells laid out so as to correspond to the points where the bit lines intersect the word line, one end of each of said resistance-change memory cells being connected to the corresponding bit line; a plurality of data control circuits connected to the plurality of bit lines, respectively; and a command control circuit. The command control circuit activates the word line in response to a first command being inputted, holds data in each of one or more selected data control circuits in response to a second command being inputted, and simultaneously writes the data held in the one or more selected data control circuits to the corresponding resistance-change memory cells in response to a third command being inputted.
This semiconductor device (1) comprises a wiring board (2), a semiconductor chip (3), and an encapsulation body (4). The wiring board (2) comprises an insulating base (2a), a conductive pattern (12) that is formed on one surface of the insulating base (2a), and a heat dissipation via (13) that is connected to the conductive pattern (12). The heat dissipation via (13) is provided so as to penetrate through the insulating base (2a) from one surface to the other surface, while being exposed from the lateral side of the insulating base (2a). The semiconductor chip (3) is mounted on the wiring board (2) so as to overlap the conductive pattern (12). The encapsulation body (4) is formed on the wiring board (2) so as to cover the semiconductor chip (3).
H01L 23/12 - Supports, p. ex. substrats isolants non amovibles
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
When using a diffusion layer with a high resistance in a source terminal, there had been a possibility that high speed operations become difficult by the current required to write to a memory cell not flowing. A semiconductor device according to the present invention comprises: memory cells which are located near the intersections of local bit lines and word lines, each memory cell being electrically connected between a corresponding local bit line and a shared source line and being selected by a corresponding word line; first transistors that are electrically connected between the shared source line and the local bit lines; second transistors that are electrically connected between a global bit line and the local bit lines; and a control circuit that controls each of the first transistors and the second transistors. The control circuit places a second transistor that corresponds to a selected local bit line into a conducting state and the first transistor into a non-conducting state, and places the second transistors corresponding to non-selected local bit lines into a non-conducting state and the first transistors into a conducting state.
G11C 11/15 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments à pellicules minces utilisant des couches magnétiques multiples
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
H01L 21/8246 - Structures de mémoires mortes (ROM)
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 43/08 - Résistances commandées par un champ magnétique
27.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME
Provided is a semiconductor device that can prevent an increase in bit line contact resistance. Each of a plurality of bit line contact plugs at which the upper surface of a plurality of bit line contact regions and the bottom surface of a bit line extending in a first direction contact is configured from: a first plug that contacts the upper surface of the bit line contact region; and a second plug that contacts the upper surface of the first plug. The first plug has a first lateral surface and second lateral surface that oppose each other in the first direction. The second plug has a first end section and second end section that oppose each other in the first direction. The gap between the first end sections and second end sections is wider than the gap between the first lateral surfaces and second lateral surfaces.
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
The present invention stably supplies a current to each memory cell in a semiconductor device in which writes to a plurality of memory cells are performed simultaneously, even when the number of bits to which first data is written is not uniform. The semiconductor device is provided with a plurality of memory cells, a plurality of write registers for retaining a plurality of write data to be written to the plurality of memory cells, a ratio determination circuit for determining a ratio of first data to second data in the plurality of write data retained in the plurality of write registers, and a voltage regulator circuit for generating a first power source voltage used in writing the first data and a second power source voltage used in writing the second data. The voltage regulator circuit controls the electrical current supply capacity of the first power source voltage and/or the second power source voltage on the basis of output from the ratio determination circuit.
In order to address the problem of maintaining depth of focus as wiring patterns are miniaturised, the present invention comprises: first to fourth wirings which are four wirings that are disposed within a prescribed interval in a first direction, extend in a second direction, and are arranged at a first pitch in the first direction; first to third lead-out wirings which are three wirings that are disposed within the prescribed interval in the first direction, extend in the second direction, and are arranged at a second pitch in the first direction; a bridge part which is disposed between the first lead-out wiring, and the second lead-out wiring, and is connected to the first lead-out wiring, and the second lead-out wiring; a first contact part which is in contact with at least one part of the bridge part; and a second contact part which is in contact with the third lead-out wiring. One of either the first lead-out wiring, or the second lead-out wiring is connected to the second wiring, and the third lead-out wiring is connected to the fourth wiring.
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
The purpose of the present invention is to decrease the layout size of a sense amplifier and reduce the current consumption of bit lines in a semiconductor memory device that uses a memory cell that inverts the voltage supplied during writing and the voltage detected during reading. A semiconductor memory device comprises the memory cell that is connected between the bit lines and a power source node, and a word line that is connected to a control terminal of the memory cell. Moreover, the device comprises a sense amplifier having a retaining circuit that temporarily stores data read from the memory cell, and a read-write switch that is connected between the bit lines and a first node of the retaining circuit. Furthermore, the device comprises a counter that is provided to correspond to a word line, counts the number of times the word line is activated, and outputs a data inversion control signal indicating whether the count is odd or even, and an external output circuit that performs inversion/non-inversion of data on the basis of the data inversion control signal when data in the sense amplifier retaining circuit is externally input or output.
G11C 11/36 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des diodes, p. ex. comme éléments à seuil
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c.-à-d. rafraîchissement externe avec une porte à transfert de charges, p. ex. un transistor MOS, par cellule
H01L 27/102 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants bipolaires
31.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
Provided is a semiconductor device in which a voltage does not need to be applied to an element-isolating region that self-aligns with word lines (WL). This method for manufacturing said semiconductor device has the following steps: a step in which provisional active regions that are shaped such that active regions (3a) that are adjacent in an X direction are connected to each other are formed; a step in which a sacrificial film is formed; a step in which etching is performed, including the sacrificial film, so as to form a plurality of first trenches that separate the active regions (3a); a step in which element-isolating insulating films (10) are embedded in the first trenches and the sacrificial film is then removed; a step in which first side-wall insulating films that cover the exposed side surfaces of the element-isolating insulating films (10) and second side-wall insulating films that cover the side surfaces of the first side-wall insulating films are formed; a step in which cap insulating films are embedded in second trenches that appear due to the formation of the second side-wall insulating films; and a step in which a plurality of third trenches are formed at the positions of the second side-wall insulating films and word lines (WL) are formed thereunder.
The objective of the present invention is to provide a semiconductor device having a structure that can be suppressed in warping even in cases where semiconductor chips are laminated. A semiconductor device (200) according to the present invention comprises: a wiring substrate (201); a first semiconductor chip (203) that is mounted on one surface of the wiring substrate (201); a second semiconductor chip (205) that is laminated on the first semiconductor chip (203) so as to form exposed surfaces (210a, 210b) where the surface of the first semiconductor chip (203) is partially exposed; silicon substrates (211a, 211b) that are mounted on the exposed surfaces (210a, 210b) and serve as warping control members; and an encapsulation body (220) that is formed on the wiring substrate (201) so as to cover the first semiconductor chip (203), the second semiconductor chip (205) and the silicon substrates (211a, 211b).
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
[Problem] To quickly start an internal voltage generating circuit after a control signal has been made active. [Solution] A semiconductor device comprises a comparator circuit (CP) that compares a reference voltage (VREFD) and an internal voltage (VPERD) during an activation period of a start signal (INIT) and controls the electric potential level of a gate potential (GN) in accordance with the comparison results, a transistor (N3) that receives the gate potential (GN) at a gate electrode and outputs the internal voltage (VPERD), and a transistor (P3) that puts the transistor (N3) into a conducting state regardless of the results of the comparison by the comparator circuit (CP) during a fixed period from when the start signal (INIT) is made active. By virtue of the present invention, the internal voltage generating circuit can quickly start because the transistor (N3) is forcibly placed into a conducting state during the fixed period from when the start signal (INIT) is made active.
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
G11C 11/413 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation
34.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
The present invention has a memory cell region in which memory cells are aligned in a first direction (Y direction) and a second direction (X direction) orthogonal to the first direction, a word line contact region adjacent to the memory cell region in the first direction (Y direction) interposed by a dummy pattern region, and first and second word lines that span a plurality of active regions aligned in the first direction (Y direction) and extend from the memory cell region to the word line contact region. A first word line and a second word line adjacent to each other within one active region located in the memory cell region constitute a word line pair. A gap in the second direction (X direction) between a first word line and a second word line that constitute a word line pair in the memory cell region is narrower than a gap in the second direction (X direction) in the word line contact region.
On a peripheral circuit area upon a semiconductor substrate, an NMOS gate stack, comprising a first high-dielectric film, an NMOS gate metal, and a first semiconductor film, is formed, and a PMOS gate stack, comprising a second high-dielectric film, a PMOS gate metal, and a second semiconductor film, is formed so that a predetermined step is formed between the NMOS gate stack and the PMOS gate stack. A third semiconductor film is formed over the entire surface of the semiconductor substrate so as to fill in the step. The third semiconductor film is planarized by way of CMP so as to form a fourth semiconductor film that is thinner than the third semiconductor film.
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
H01L 21/3213 - Gravure physique ou chimique des couches, p. ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
[Problem] To provide an input receiver making it possible to obtain adequate gain with respect to a broad reference potential level. [Solution] The present invention is provided with a differential circuit (110) and a current-supplying circuit (120). The differential circuit (110) includes a first input terminal to which a reference potential VREF is fed, and a second input terminal to which an input signal DQ is fed, the differential circuit (110) generating an output signal based on the difference in potential between the reference potential VREF and the input signal DQ. The current-supplying circuit (120) feeds an actuating current to the differential circuit (110). The actuating current includes the sum of first and second actuating currents. The current-supplying circuit (120) includes a common-mode feedback circuit (CMFB) and an assist circuit (TA). The common-mode feedback circuit (CMFB) changes the first actuating current in accordance with the level of the reference potential VREF. The assist circuit (TA) feeds a fixed amount of the second actuating current irrespective of the level of the reference potential VREF. It is thereby possible to obtain adequate gain with respect to a broad reference potential VREF level.
G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. mémoires tampon de données
G11C 11/407 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation pour des cellules de mémoire du type à effet de champ
H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface
37.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
A chip laminate (11) in this semiconductor device has a structure consisting of a first semiconductor chip (intermediate memory chip (2b)) and a second semiconductor chip (IF chip (3)) laminated together. The first semiconductor chip has a circuit-forming layer and a first bump electrode (top-surface bump electrode (22a)) formed on one surface and a second bump electrode (bottom-surface bump electrode (23a)) formed on the other surface. The second semiconductor chip has a circuit-forming layer and a third bump electrode (top-surface bump electrode (22b)) formed on one surface and a fourth bump electrode (bottom-surface bump electrode (23b)) formed on the other surface. The first semiconductor chip and the second semiconductor chip are laminated together such that the circuit-forming layer on the first semiconductor chip and the circuit-forming layer on the second semiconductor chip face each other and the first and third bump electrodes are electrically connected to each other.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
38.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME
A first spacer (130) is formed above a layer to be processed (100) in such a manner as to be sandwiched between a first mask layer (125) and a first embedded layer (135) in a plan view. Second spacers (150) are formed in such a manner as to cover the first spacer (130), and to be sandwiched between a second mask layer (145) and a second embedded layer (155) in a plan view. Subsequently, the second spacers (150) are selectively removed in such a manner that at least portions of the first spacer (130) are exposed. In addition, the exposed portions of the first spacer (130) are selectively removed, and the layer to be processed (100) is selectively removed through the removed portions of the first spacer (130). Thus, a pattern of fine holes (H) of less than a resolution limit can be formed in an array shape on the layer to be processed (100).
Provided is a semiconductor device manufacturing method whereby generation of a short-circuit between adjacent lower electrodes can be suppressed. The manufacturing method includes a step for forming a first interlayer insulating film (161), a step for forming cylinder holes (165) in the first interlayer insulating film (161), and a step for forming capacitors respectively having lower electrodes included in the cylinder holes (165). The step for forming the first interlayer insulating film (161) includes a step for sequentially laminating: a first insulating film (76); a second insulating film (78) having a lower wet etching rate than the first insulating film (76); a third insulating film (79), which has substantially the same wet etching rate as the second insulating film (78), and which has a smaller shrinkage ratio than the second insulating film (78), and a fourth insulating film (83) having a lower etching rate than the third insulating film (79).
[Problem] To reduce the impedance of a predetermined wiring provided in a semiconductor chip. [Solution] A semiconductor chip (100) having a plurality of pad electrodes (110a, 110c), and a wiring substrate (200) as a wiring structure provided on the semiconductor chip (100) are provided. The wiring substrate (200) has a plurality of external terminals (260), a plurality of wiring patterns (240) for electrically connecting each of the external terminals (260) and pad electrodes (110a), and a bridge wiring (290) for electrically connecting the plurality of pad electrodes (110c) in shared fashion without being electrically connected to any of the external terminals (260) in the wiring substrate (200). Through the present invention, since the bridge wiring (290) provided to the wiring structure supplements the wiring in the semiconductor chip (100), it is possible to reduce the impedance of a predetermined wiring.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 23/12 - Supports, p. ex. substrats isolants non amovibles
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
[Problem] To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. [Solution] In the present invention, the following are provided: a semiconductor chip (100) that has first and second pad electrodes (120a, 120b) disposed on the main surface thereof; insulating films (310, 330) that cover the main surface of the semiconductor chip (100); a rewiring layer (320) that is disposed between the insulating films (310, 330); and a plurality of external terminals (340) disposed on the top of the insulating film (330). The plane size of the first pad electrode (120a) and the second pad electrode (120b) differ from one another, and the first pad electrode (120a) and the second pad electrode (120b) are connected to any of the plurality of external terminals (340) via the rewiring layer (320). According to the present invention, because the pad electrodes (120a, 120b) of different sizes are intermixed, probing can be easily performed while reducing the area occupied by the pad electrodes.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 23/12 - Supports, p. ex. substrats isolants non amovibles
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
The present invention provides a novel constitution provided with an effect for suppressing a shift in a threshold voltage (Vt) for a planar MOSFET in a planar MOSFET that uses a HKMG structure. This semiconductor device adopts a constitution provided with: a first active region provided on a semiconductor substrate in which a transistor having a high dielectric constant gate insulating film, a gate electrode, and a diffusion layer is disposed; an element separation region that is in contact with and surrounds the first active region; and a dummy active region that is in contact with the element separation region. Thereby, shifts in threshold voltage (Vt) for the planar MOSFET accompanying reductions in gate width (W) can be greatly suppressed in comparison with constitutions not provided with dummy active regions.
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 21/76 - Réalisation de régions isolantes entre les composants
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
43.
SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE PROVIDED WITH SEMICONDUCTOR CHIP
Provided are: a semiconductor chip having a configuration wherein, when stacking a plurality of the semiconductor chips to form a chip stack, the semiconductor chips do not easily shift out of position in the plane direction of the semiconductor chips; and a semiconductor device provided with such a semiconductor chip. This semiconductor chip (10) is provided with a substrate (silicon substrate (21)) having insulation properties, a plurality of bump electrodes (surface bump electrodes (22)) provided on one surface of the substrate, a plurality of recesses (23) provided in the other surface of the substrate, and a solder layer (24) disposed within the recesses (23). The recesses (23) are formed such that the area of the opening decreases from the other surface side toward the one surface side of the substrate (21).
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
[Problem] To form a conductive layer on the side surface of a hole having a large aspect ratio. [Solution] A production method for semiconductor devices, whereby a stopper film (780) and a BPSG film (790A) are formed sequentially, a cylinder etch laminated mask (850) is formed upon the BPSG film (790A), openings having a prescribed pattern are formed in the cylinder etch laminated mask (850), then, using same as a mask, a cylinder hole (810) is formed that pierces from the BPSG film (790A) to the stopper film (780) in the thickness direction. Next, a conductive layer is formed that adjoins the side surfaces of the BPSG film (790A), the stopper film (780), and a polysilicon film (851) being part of the cylinder etch laminated mask (850), then the polysilicon film (851) and the BPSG film (790A) are removed. As a result of the present invention, the mask layer used in patterning is used, as is, as a side wall for the conductive layer, thereby enabling the aspect ratio to be reduced.
[Problem] To regenerate the charge of a memory cell having reduced information retention characteristics using a target row refresh operation. [Solution] A semiconductor storage device is provided with a memory cell array (11) comprising a plurality of word lines including word lines (WLI, WL2) that are adjacent to one another; and a TRR address conversion unit (53) that selects the word line (WL1) in response to the input of an address signal (IADD) indicating a first value while in a first operation mode and selects the word line (WL2) in response to the input of an address signal indicating a first value while in a target row refresh mode. Due to the fact that address conversion is performed on the semiconductor storage device side in the present invention, it is sufficient for a control device to output, for example, the address of a word line having a high access count to the semiconductor storage device during a target row refresh operation. As a result, control of the target row refresh operation on the control device side is facilitated.
A semiconductor device that has the following: an element-isolation region formed on a semiconductor substrate; an active region surrounded by said element-isolation region; a semiconductor pillar provided in said active region so as to protrude from the surface of the semiconductor substrate; a gate electrode provided on a side surface of the semiconductor pillar, with a gate-insulating film interposed therebetween, so as to extend in a first direction; a pillar-top diffusion layer provided in the top-end section of the semiconductor pillar; a pillar-bottom diffusion layer provided in the bottom-end section of the semiconductor pillar; a channel section provided between the pillar-top diffusion layer and the pillar-bottom diffusion layer; a silicide layer provided beneath the pillar-bottom diffusion layer so as to extend in a second direction, said second direction being perpendicular to the abovementioned first direction; a contact plug provided so as to contact the silicide layer in the bottom-end section; and top-layer wiring provided so as to contact the contact plug in the top-end section. The contact plug is connected to the silicide layer through the pillar-bottom diffusion layer.
This semiconductor device (1) comprises a wiring substrate (2), a semiconductor chip (3) and a sealing body (4). The wiring substrate (2) includes an insulating base material (2a), a first conductive pattern (12) formed on one surface of the insulating base material (2a), and a second conductive pattern (13) formed on one surface of the insulating base material (2a), connected to the first conductive pattern (12) and having an end face exposed to the side. The semiconductor chip (3) is mounted on the wiring substrate (2a) so as to overlap with the first conductive pattern (12). The sealing body (4) is formed on the wiring substrate (2a) so as to cover the semiconductor chip (3).
H01L 23/12 - Supports, p. ex. substrats isolants non amovibles
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p. ex. dissipateurs de chaleur
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
A memory mat (101) is configured to have a main unit portion (200) which has first capacitors (203A), a linear conductive film (204) formed between the main unit portion (200) and peripheral circuitry (104), and a second capacitor (203B) which is formed such that the linear conductive film (204) and a lower portion come into contact, said first capacitor (203A) being formed such that a contact layer (202) and the lower portion come into contact.
A semiconductor device is provided with, in a memory mat, a plurality of memory cells having a plurality of capacitors including cylindrical lower electrodes. The semiconductor device is provided with: a first support film pattern group comprising a plurality of polygonal support film patterns as seen in plan view within the memory mat, wherein each supports sidewalls of corresponding lower electrodes; and a second support film pattern group comprising a plurality of polygonal support film patterns as seen in plan view within the memory mat, wherein each supports sidewalls of corresponding lower electrodes. The second support film pattern group is formed above the first support film pattern group so that periphery vertices of the respective polygons, as seen in plan view, do not overlap with each other.
[Problem] To improve the efficiency of wire connection between a semiconductor chip and a wiring substrate which are laminated. [Solution] A semiconductor device (100) is provided with: a wiring substrate (108) which comprises a plurality of substrate electrodes (116) arranged therein; a first semiconductor chip (102) which is laminated on the wiring substrate (108) and comprises a plurality of pads (118) that are arranged along a first side that faces the plurality of substrate electrodes (116); and a second semiconductor chip (104) which is laminated on the first semiconductor chip (102) and comprises a plurality of pads (118) that are arranged along a second side that faces the plurality of substrate electrodes (116). With respect to the group of pads (118) of one of the first semiconductor chip (102) and the second semiconductor chip (104), some pads (118) arranged in the central portion are connected to the plurality of substrate electrodes (116). With respect to the group of pads (118) of the other semiconductor chip, some pads (118) arranged in the end portions are connected to the plurality of substrate electrodes (116).
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
G11C 5/00 - Détails de mémoires couverts par le groupe
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
[Problem] To reduce current consumption caused by refresh operations by fine-tuning an adjustment pitch of a refresh rate. [Solution] In response to the first activation of a refresh signal (RF), N units of word lines are selected twice, and thereby, refresh operations are performed, and then, in response to the second activation of the refresh signal (RF), N units of word lines are selected three times, and thereby, refresh operations are performed. As a result, in response to an activation of the refresh signal (RF), it is possible to perform, on average, 2.5 refresh operations, and therefore, it is possible to more finely tune the adjustment pitch of the refresh rate. As a result, in accordance with data retention time of a memory cell, it is possible to reduce current consumption more.
Alert terminals ((201-1) to (201-9)) provided on each DRAM ((200-1) to (200-9)) mounted on this memory module (100) are connected with a loop-shape transmission line. A connection point (104) on the transmission line and an output terminal (101) are connected via a resistance element (102), and a power source and a connection point (105) which is the terminal on the transmission line furthest from the connection point (104) are connected via a resistance element (103).
Provided is a semiconductor chip comprising: an input/output circuit; first and second power supply lines that supply operating voltage to the input/output circuit; and a capacitance element and a resistor that are provided in series between the first power supply line and the second power supply line.
G11C 11/413 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation
G11C 7/02 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les signaux parasites
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
The present invention is applied to a semiconductor device that includes a plurality of memory cell arrays having a multi-bank configuration, wherein the plurality of banks are each partitioned into a plurality of sub-banks, and for each sub-bank, a column control circuit is provided which generates a column selection signal. The column control circuits are provided with: a column pre-decoder unit which outputs a control signal to a column decoder in accordance with a column address included in an input address and a predetermined row address for selecting one of the plurality of sub-banks; and gate circuit means which, in performing column access, if the sub-bank has not been selected by the predetermined row address, causes the column pre-decoder unit to be non-active.
A semiconductor device (1) includes: a wiring substrate (3); a semiconductor chip (4) layered on one face of the wiring substrate (3) and having a first face (4a) facing the wiring substrate (3) and a second face (4b) positioned on a reverse side from the first face (4a), a circuit being formed on at least the second face (4b); a non-circuit-incorporating chip (11) in which a circuit is not formed, the non-circuit-incorporating chip (11) being layered on the second face (4b) of the semiconductor chip (4); and a sealing resin (2) disposed between at least the wiring substrate (3) and the non-circuit-incorporating chip (11). This configuration suppresses damage to the circuit formed in the semiconductor chip by energy applied during such processes as laser irradiation for forming a marking on the semiconductor device in which the semiconductor chip is incorporated.
[Problem] To cause a command FIFO circuit to operate normally even in a case in which a DLL circuit is suspended at standby time. [Solution] The present invention is provided with: a point shifting circuit (110) which latches an internal command (COMIN) on the basis of input point signals (IN0 to IN3), and outputs an internal command (COMOUT) on the basis of output point signals (OUT0 to OUT3); a phase difference assessment circuit (150) which generates a count value (CNT) on the basis of an amount of time from activation of the input point signal (IN0) to activation of the output point signal (OUT0); and a phase difference setting circuit (160) which, on the basis of the count value (CNT), switches relationships between the input point signals (IN0 to IN3) and the output point signals (OUT0 to OUT3). According to the present invention, it is possible to suspend, at standby time, operation of a DLL circuit used in generation of the output point signals (OUT0 to OUT3), and therefore, it is possible to achieve reduction of current consumption.
G11C 11/407 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation pour des cellules de mémoire du type à effet de champ
[Problem] To reduce current consumption caused by generation of an internal clock signal. [Solution] The present invention is provided with: a clock signal buffer circuit (90) which, in response to activation of a chip selection signal (CS_n), starts generation of an internal clock signal PCLKAR; and internal circuits (70, 100, 110, and 120) which operate in synchronization with the internal clock signal PCLKAR. The clock signal buffer circuit (90) suspends generation of the internal clock signal PCLKAR at a second timing if command signals (CA0 to CA9) indicate read commands, and suspends generation of the internal clock signal PCLKAR at a first timing which is earlier than the second timing if the command signals (CA0 to CA9) indicate active commands. According to the present invention, an internal clock signal is generated only for periods necessary in accordance with external command signals, and therefore, it is possible to reduce current consumption.
G11C 11/407 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation pour des cellules de mémoire du type à effet de champ
A method for manufacturing a semiconductor device, having a step for forming a first groove and a second groove shallower than the first groove in a semiconductor substrate, a step for forming an insulation film on an inside wall face of each of the first and second grooves, a step for filling each of the first and second grooves with a first filling material comprising an insulation material via the insulation film, a step for forming a first mask layer for covering the filling material, a step for selectively removing a portion of the first mask layer so that the first filling material filling the second groove is exposed, a step for selectively removing the first filling material for filling the second groove by etching using the first mask layer, a step for filling a bottom part of the second groove with a first conducting material, and a step for filling a top part of the second groove with a second filling material so as to cover the first conducting material.
H01L 21/76 - Réalisation de régions isolantes entre les composants
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
The purpose of the present invention is to reduce chip area. The present invention is provided with a bit line pair, sense amplifier circuits which are connected between the bit line pair and which are configured with 2 CMOS inverter circuits for which input and output are mutually connected, an equalizer circuit connected between the bit line pair, and a drive transistor which drives a drive line of the sense amplifier circuits; wherein one transistor configuring the CMOS inverter circuits, a transistor group configuring the equalizer circuit, and the drive transistor are of a first conductivity type and have the same first threshold.
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
60.
METHOD AND DEVICE FOR STORING AND READING RELIABLE INFORMATION IN A NAND ARRAY
A method (and device) includes producing first data in a page region of a memory, the first data including a first number of memory sets, each of the memory sets having a second number of bits, where the first number is a positive number more than one and the second number is a positive number more than three. After the producing the first data in the page region of the memory, second data is produced in response to the produced first data, the second data having the first number of bits, each of the bits of the second data having a logic value that is determined by a majority of the bits included in a corresponding one of the memory sets.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/20 - InitialisationPrésélection de donnéesIdentification de puces
G11C 29/00 - Vérification du fonctionnement correct des mémoiresTest de mémoires lors d'opération en mode de veille ou hors-ligne
61.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME
This semiconductor device is provided with: an active region demarcated at a semiconductor substrate; a trench that is formed at the active region and that has a bottom and a top; a gate insulating film that covers the inner wall surface of both the top and the bottom of the trench; a seed layer that opposes the inner wall surface of the bottom of the trench with the gate insulating film therebetween; and a metal electrode having a first section, which is embedded in the trench and opposes the inner wall surface of the bottom of the trench with the seed layer and gate insulating film therebetween, and a second section, which opposes the inner wall surface of the top of the trench with the gate insulating layer therebetween and without the seed layer therebetween.
[Problem] To reset, in a short amount of time, a memory-cell array for analyzing an access history. [Solution] The following are provided: a memory-cell array (110) that stores an access history for a memory-cell array that stores user data; and a reset circuit (120, 150, 160, 170) that, in response to a reset signal (RESET), erases the access history stored in the aforementioned memory-cell array (110). Said memory-cell array (110) contains a plurality of word lines (RWL), a plurality of bit lines (RBL), and a plurality of memory cells at the intersections thereof. A row decoder (120) activates a plurality of word lines (RWL), and in the resulting state, a write circuit (150) supplies an initialization value to the bit lines (RBL). This makes it possible to reset an access history in a short amount of time.
Provided is a semiconductor device that is provided with a plurality of unit transistors, each of which has: element isolation regions (103) formed on a semiconductor substrate (101); and a gate electrode (12), which is formed in a frame shape, and which is disposed on an active region (11) such that both the ends of the outer circumference of the gate electrode extend onto the element isolating regions, and the inner circumference thereof closes the active region, said active region being sandwiched between the element isolating regions. The active regions of the unit transistors adjacent to each other in the first direction (X) are electrically isolated from each other by means of the element isolating regions, and the active regions of the unit transistors adjacent to each other in the second direction (Y) intersecting the first direction are connected to each other.
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
This semiconductor device comprises a first cell transistor (25) and a second cell transistor (27). The first cell transistor (25) includes: first and second side-wall-section channel regions (63, 64) that are arranged so as to sandwich a first groove (21); and a first bottom-section channel region (66) that is arranged between the bottom surface (21a) of the first groove (21) and an insulating layer (13-2). The second cell transistor (27) includes: the second side-wall-section channel region and a third side-wall-section channel region (64, 76) that are arranged so as to sandwich a second groove (22); and a second bottom-section channel region (77) that is arranged between the bottom surface (22a) of the second groove (22) and the insulating layer (13-2). The second cell transistor is provided in the same active region (19) as the first cell transistor (25).
[Problem] In a semiconductor device for which it is necessary to maintain information for a refresh operation, preventing refresh malfunction due to a reduction in information maintaining characteristics. [Solution] Provided are the following: a refresh counter (41) for outputting a first raw address (RADDa) that indicates the raw address of a word line to be refreshed; an address generation section for outputting, on the basis of the access history of a memory cell array, a second raw address (RADDb) that indicates the raw address of a word line to be additionally refreshed; and a selection circuit (42) for selecting either the raw address (RADDa) or the raw address (RADDb). In accordance with the present invention, word lines corresponding to memory cells the information maintaining characteristics of which have been reduced can be additionally refreshed, and therefore, information can be correctly maintained regardless of the history of accessing a memory cell.
[Problem] To desirably ensure signal integrity of outputted data even while being affected by crosstalk between wiring within a package. [Solution] Provided is a semiconductor device, comprising: a first power source terminal; a data I/O terminal (14); a plurality of P output units (54P1-54P4) which are mutually connected in parallel between the first power source terminal and the data I/O terminal (14), and which respectively drive the data I/O terminal (14) in response to an output signal (P0); a plurality of P output units (54P5, 54P6) which are mutually connected in parallel between the first power source terminal and the data I/O terminal (14), and which respectively drive the data I/O terminal (14) in response to an output signal (P1); and a pull-up side output circuit (41P) which outputs the output signals (P0, P1) in response to a pull-up side data signal (DATA_P). The pull-up side output circuit (41P) outputs the output signals (P0, P1) at mutually different timings.
There has been a problem of having semiconductor devices wherein measurement values as designed are not obtained even if optical proximity correction (OPC) is performed by forming dummy patterns. Disclosed is a semiconductor device wherein dummy patterns corresponding to respective gate patterns having different shapes are provided in a region having the gate patterns.
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
The present invention reduces chip surface area. The present invention is provided with: a memory cell array having a plurality of wide wires; a plurality of selection wires that respectively supply a first voltage via the source/drain bus of a transistor to the corresponding wide wire among the plurality of wide wires; a plurality of driver circuits including a first driver circuit that has a first decoder circuit connecting to a first selection wire among the plurality of selection wires, and a second driver circuit that has a second decoder circuit connecting to a second selection wire among the plurality of selection wires; and a first level shift circuit containing an input terminal connected to a first address signal wire among a plurality of address signal wires, and an output terminal connected in common to the first decoder circuit and the second decoder circuit.
G11C 11/407 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation pour des cellules de mémoire du type à effet de champ
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
Provided is a twin plug forming process in which a contact hole that is between word lines (10b, 10c) and is enclosed by a bit line (16) is filled with a second conducting material and separated in the second direction, wherein without forming a conventional dummy word line, a diffusion layer separation trench (29) is formed by further etching the surface of a semiconductor substrate exposed between twin plugs, and the trench is filled with a diffusion layer separation insulating film (30) to separate a diffusion layer, and separate contact plugs (25b, 25c).
In the present invention, a first insulating film (61) is formed with a recess portion (62) left therein in a contact hole (54), and the contact hole is surrounded by a first line pattern (52) and a second line pattern (53), the first line pattern and the second line pattern having different heights. The recess portion (62) is filled so as to form a first mask film (63), and the first insulating film (61) except for the recess portion (62) is etched back so as to be removed, thereby forming a second contact hole (64). After that, a conductive material is implanted in the second contact hole (64), and the top surface of the first line pattern (52) having a low height is exposed, thereby forming a contact plug.
[Problem] In a semiconductor device, to inhibit a reduction in operating speed in a normal mode by using a test-mode circuit. [Solution] In the present invention, a semiconductor device selects a sub word line by means of a main word driver, a sub word driver, and an FX driver (FXD). The main word driver selects one or more main word lines and the FX driver (FXD) selectively activates the sub word driver by means of an FX select signal. In accordance with the selections performed by these drivers, the sub word driver selects a sub word line. The main word driver and the FX driver (FXD) are activated by means of a low enable signal (RE) supplied from a control circuit. A clock signal (TCLK) is supplied directly to the FX driver (FXD). In a test mode, the FX driver (FXD) controls the FX select signal in synchronization with this clock signal (TCLK).
G11C 29/12 - Dispositions intégrées pour les tests, p. ex. auto-test intégré [BIST]
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
G01R 31/3185 - Reconfiguration pour les essais, p. ex. LSSD, découpage
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques
This semiconductor device (100) has: a counter (119) that outputs a temperature update command for having temperature information updated every time a predetermined number of periodically output periodic commands is counted; a temperature sensor (120) that detects and outputs the temperature information every time the temperature update command is output; and a temperature information output unit (121) that determines temperature information to be output out of the temperature information from the temperature sensor in response to a periodic command and outputs the determined temperature information in response to a temperature output command used for outputting the temperature information.
Provided is a semiconductor device allowing a barrier metal to be reduced in thickness, adhesion with a metal electrode to be ensured, and film thickness to be controlled/managed using the thin film. The semiconductor device is provided with an active region (13) on a semiconductor substrate (1), a trench (14) having a lower section and an upper section within the active region, a gate insulating film (5) that covers the inner wall surface of the trench, a first barrier metal (6a) that covers the lower section of the trench interposed by the gate insulating film, a second barrier metal (6b) that covers the first barrier metal, and a metal electrode (9) that covers the second barrier metal and fills up the lower section of the trench. The second barrier metal is thinner less than the first barrier metal.
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
74.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
In the present invention, in a twin plug-forming step, a conductive material is removed so as to form a groove for separating a diffusion layer (29), a diffusion layer-separating insulating film (30) is implanted so as to separate a diffusion layer, and contact plugs (25b) and (25c) are separated. In the twin plug-forming step, a second conductive material is implanted in a contact hole surrounded by a bit line (16) between word lines (10b) and (10d), and is separated in a second direction. The conductive material was implanted in a dummy word line in the related art.
Provided is a technology whereby it is possible to disperse pressure which is imparted to a wire in a sealing process. This semiconductor device has a configuration wherein convex members are positioned to protrude from one face of a substrate in a location near the outer side of a bonding wire, among a plurality of bonding wires which respectively connect a plurality of electrodes with a plurality of connection pads, which is in the outermost location.
H01L 23/12 - Supports, p. ex. substrats isolants non amovibles
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
76.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
Decrease in the width of a bit line caused resistance to sharply increase. In the present invention, a semiconductor device is equipped with: a common source line; a common bit line; multiple memory cells which are arranged in multiple rows and multiple columns, each of said multiple memory cells being constructed by serially connecting a selection component having first and second control electrodes and a memory component between the common source line and the common bit line; multiple first selection lines, each of said multiple first selection lines being commonly connected to the first control electrode of a respective memory cell which belongs to a corresponding row of the multiple rows; and multiple second selection lines, each of said multiple second selection lines being commonly connected to the second control electrode of a respective memory cell which belongs to a corresponding column of the multiple columns.
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
H01L 49/00 - Dispositifs à l'état solide non couverts par les groupes et et non couverts par une autre sous-classe; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
A DLL circuit comprises: a variable frequency division circuit that uses a variable frequency division ratio to frequency-divide a first clock signal, thereby generating first and second frequency-divided clock signals; a grain size change circuit that changes the count width in synchronization with the first frequency-divided clock signal; a counter circuit that updates the count value in accordance with the count width in synchronization with the second frequency-divided clock signal; and a variable delay circuit that delays the first clock signal on the basis of a delay amount that is in accordance with the count value, thereby generating a second clock signal. If the relationship in magnitude between the phase difference between the first and second clock signals and a predetermined value becomes inverse just after the updating of the count value, the grain size change circuit changes the count width, and the variable frequency division circuit sets the frequency division ratio of the second frequency-divided clock signal being greater than that of the first frequency-divided clock signal. In the DLL circuit in which the change width of the delay amount can be adjusted, a lock state is established in a short time.
H03L 7/081 - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
G11C 11/407 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation pour des cellules de mémoire du type à effet de champ
A semiconductor device which is provided with: a gate insulating film which contains a high dielectric constant insulating material and has a first width; a lower gate electrode which has a second width that is narrower than the first width; an upper gate electrode which has a third width; and a first spacer layer which covers the lateral part of the upper gate electrode, a part of the lower part of the upper gate electrode, a part of the lower gate electrode, a part of the upper surface of the gate insulating film, said part of the upper surface being out of contact with the lower gate electrode, and the lateral surface of the gate insulating film.
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
[Problem] To make it possible to position part (n-type section (AAN)) of an assist amplifier inside a sense amplifier region (SAA). [Solution] A semiconductor equipped with: first and second memory cell regions (MATA) aligned in the Y-direction; a sense amplifier region (SAA) including a plurality of sense amplifiers and formed between the first and second memory cell regions (MATA); a first wiring layer; first and second bit lines (BL0T, BL0B) extending in the Y-direction and containing a first wiring section formed as the first wiring layer in at least the sense amplifier region (SAA); and a first pad electrode extending in the X-direction and formed as the first wiring layer between the first wiring section of the first bit line (BL0T) and the first wiring section of the second bit line (BL0B).
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
[Problem] To provide a semiconductor device having high versatility and supporting diverse I/O bit counts and packaging methods. [Solution] The present invention is provided with a selection circuit (61a) that connects a read-write bus (RWBS2<31:28>) and a data terminal (DQ5) when a first operation mode is selected, and connects a read-write bus (RWBS2<23:20>) and the data terminal (DQ5) when a second operation mode is selected. By means of the present invention, the bus configuration of the read-write bus is variable, and so it is possible to provide a semiconductor device having high versatility and supporting diverse I/O bit counts and packaging methods.
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
81.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME
This semiconductor device comprises: a plurality of first element-separating regions formed on a semiconductor substrate so as to extend along a first direction (Y direction); a plurality of second element-separating regions formed so as to extend along a second direction (X direction) that intersects with the first direction (Y direction); a plurality of active regions insulated and separated by the first element-separating regions and the second element-separating regions; a plurality of gate electrodes (word lines) formed so as to extend along the first direction (Y direction); and an embedded diffusion layer that is formed in a position deeper than the first element-separating regions and the second element-separating regions, and that has an inverse characteristic to the active regions.
A semiconductor device having: first to third gate electrodes arranged inside a first active region and embedded in first to third trenches extending in a first direction; a first semiconductor pillar positioned between the first and second trenches; a second semiconductor pillar positioned between the second and third trenches; a first vertical transistor having the first and second gate electrodes as the double gate electrodes therefor; and a second vertical transistor having the second and third gate electrodes as the double gate electrodes therefor. The semiconductor device is characterized by the second gate electrode being shared by the first vertical transistor and the second vertical transistor.
[Problem] Provided is a method capable of effectively embedding insulating films in element isolation grooves without causing dislocation defects in a semiconductor substrate. [Solution] A method for manufacturing a semiconductor device is provided with: a step for forming element isolation grooves (5A) and an element isolation groove (5B) having a width greater than that of the element isolation grooves (5A) in the semiconductor substrate (2); a step for forming insulating films (6) having relatively low fluidity and having upwardly released voids (VA) inside the element isolation grooves (5A), and also covering substantially all of the interior surface of the element isolation groove (5B); a step for forming an insulating film (7) having relatively high fluidity, whereby the insulating film (7) is embedded in the interior of the voids (VA); and a step for reforming the insulating film (7).
The present invention is provided with the following: a row decoder (12) that decodes a row address, yielding a decoded signal; a plurality of sub-word lines (SWL) that are selectively activated on the basis of the decoded signal; and a reset-controlling circuit (50) that, if a refresh-state signal (REFST) is inactive, resets the value of the decoded signal to an initial value in response to a bank-active signal (MCBAT), and if the refresh-state signal (REFST) is active, stops the resetting of the decoded signal in response to the bank-active signal (MCBAT). Since the present invention has an operating mode in which the decoded signal is not reset, the amount of current consumed when high-speed access is not needed can be reduced.
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
G11C 11/407 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation pour des cellules de mémoire du type à effet de champ
The present invention has a step for sequentially forming an insulating film (5, 6, 18, 19) and a first material film (20) on a semiconductor substrate (1), a step for forming on the first material film a mask film (21, 22) having a rectangular first opening (31), and a step for dry-etching the first material film using the mask film as a mask to form an ellipsoidal second opening (31A) having its shorter side aligned in a first direction (Y) of the first material film. The step for forming the mask film includes a step for forming a second material film (21) having a side surface that faces the first direction of the first opening, and a third material film (21, 22) having side surfaces facing a second direction of the first opening, and the thickness of the third material film is greater than the thickness of the second material film.
A sample semiconductor device is manufactured and the curvature of the sample is measured. An area is set to be removed from an encapsulation resin layer on the basis of the measurement value. After forming the encapsulation resin layer during the process of manufacturing the semiconductor device, the removal area is removed.
This output-signal generation device contains the following: a phase adjustment unit that generates an output signal on the basis of an input signal and can perform an adjustment operation that sets the phase difference between the input signal and the output signal to a prescribed value; and a phase-adjustment control unit that makes the phase adjustment unit perform the aforementioned adjustment operation if the aforementioned phase difference falls outside an acceptable range that contains the aforementioned prescribed value.
Provided is a highly reliable semiconductor device and a method for manufacturing same. The method for manufacturing the semiconductor device includes: a step for forming an interlayer insulating film on a semiconductor substrate; a step for forming a conductive plug in the interlayer insulating film, the conductive plug having a top surface for forming the same plane as the top surface of the interlayer insulating film; a step for forming a first titanium film on the interlayer insulating film and the conductive plug; a step for forming an aluminum diffusion-preventing film on the first titanium film; a step for forming a second titanium film on the aluminum diffusion-preventing film; a step for forming an aluminum film on the second titanium film; and a step for shaping the area from the aluminum film to the first titanium film by etching to form wiring.
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/3065 - Gravure par plasmaGravure au moyen d'ions réactifs
H01L 21/3213 - Gravure physique ou chimique des couches, p. ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
The semiconductor device includes an input/output pad, a first resistive element having one end connected to the input/output pad, a first output circuit for outputting an output signal to the input/output pad via the first resistive element and connected to the other end of the first resistive element, and an input circuit for accepting an input signal from the input/output pad via the first resistive element and connected to the other end of the first resistive element.
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques
G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. mémoires tampon de données
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface
The problem addressed by the present invention is to provide a method for manufacturing a semiconductor device capable of evening out production efficiency during bump formation regardless of the type of product. In this method for manufacturing a semiconductor device, a conductive bump (211) is formed on the surface of a semiconductor wafer (201) so as to create a first bump opening area, and a dummy bump (213) is formed on the surface of the semiconductor wafer (201) so as to form a second bump opening area. In such a case, the dummy bump is formed such that the total of the first bump opening area and the second bump opening area is a value corresponding to the opening area of a conductive bump (411) of a semiconductor wafer (402) having only the conductive bump (411), whereby the semiconductor device (200) is manufactured.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 23/12 - Supports, p. ex. substrats isolants non amovibles
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
[Problem] To improve a precharge property while reducing the space occupied by a bitline equalizing circuit. [Solution] A semiconductor device is provided with diffusion layer regions (SDT1, SDB1) to which bitlines (BLT1, BLB1) are respectively connected, a diffusion layer region (SDEQ) to which a precharge potential (VBLP) is to be supplied, and a gate electrode (G). The gate electrode (G) includes a part (G12) that extends toward the Y direction and a part (G3) that extends toward the X direction. A part covered with the gate electrode (G12) constitutes a channel region (CH12), and a part covered with the gate electrode (G3) constitutes a channel region (CH3). The diffusion layer region (SDT1) is located between the diffusion layer regions (SDB1, SDEQ) as observed in the Y direction. The diffusion layer regions (SDT1, SDB1) are connected to the diffusion layer region (SDEQ) with the channel region (CH12) interposed therebetween, and the diffusion layer region (SDT1) is connected to the diffusion layer region (SDB1) with the channel region (CH3) interposed therebetween. According to the present invention, it becomes possible to ensure a sufficient channel width (CH3).
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
The purpose of the present invention is to reduce stand-by current and achieve high-speed operations in a semiconductor storage device of an SCRC type. The semiconductor storage device includes a first voltage supply line that transmits a first voltage, and a second voltage supply line that transmits a second voltage. Further, the semiconductor storage device has an electric path between the first voltage supply line and the second voltage supply line, and includes a switch circuit that causes, with a first voltage level of a control gate, a part between the first voltage supply line and the second voltage supply line to assume a conductive state, and with a second voltage level of the control gate, causes the part between the first voltage supply line and the second voltage supply line to assume a non-conductive state. Further, the semiconductor storage device includes a compensation capacitor circuit that is connected to the second voltage supply line. Here, the compensation capacitor circuit and the switch circuit are adjacent to each other, and share a first diffusion layer of a first conductivity type.
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques
G11C 11/413 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
93.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
There has been a possibility of generating a connection failure between a contact plug and an impurity diffusion region. This semiconductor device is provided with: a semiconductor substrate having a plurality of first trenches formed to extend in the first direction; an embedded gate electrode embedded in a lower part of each of the first trenches with a gate insulating film therebetween; an embedded insulating film embedded in each of the first trenches, said embedded insulating film being on the embedded gate electrode; an isolating insulating film, which is provided on the embedded insulating film, and which has a width smaller than that of the first trenches; a diffusion region that is provided on the semiconductor substrate by being adjacent to the first trenches; a conductive layer in contact with the diffusion region; and a contact plug in contact with the conductive layer. The conductive layer is disposed also on the embedded insulating film on the embedded gate electrode, and is partitioned by means of the isolating insulating film.
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
94.
OUTPUT SIGNAL GENERATION DEVICE, SEMICONDUCTOR DEVICE AND OUTPUT SIGNAL GENERATION METHOD
This output signal generation device includes: a phase adjustment unit that generates an output signal on the basis of an input signal and is capable of executing an adjustment operation of setting the phase difference between the input signal and the output signal to a predetermined value; a holding unit that holds a reference voltage; a comparison voltage generation unit that generates a comparison voltage that is dependent on a power supply voltage; and a control unit that intermittently compares the comparison voltage with the reference voltage held in the holding unit, causes the phase adjustment circuit to execute the adjustment operation when the comparison result satisfies a predetermined condition representing a variation in the power supply voltage, and changes the reference voltage held in the holding unit in accordance with the power supply voltage.
This semiconductor device is provided with: a silicon pillar that is provided by digging from a main surface of a semiconductor substrate; a first diffusion layer that is provided above the silicon pillar; a second diffusion layer, that is provided from a bottom portion of the silicon pillar to one region of the semiconductor substrate, said one region being continuous to the silicon pillar; a gate electrode in contact with at least a first side surface of the silicon pillar with a gate insulating film therebetween; a first embedding insulating film that surrounds the gate electrode; a second embedding insulating film in contact with a second side surface of the silicon pillar, said second side surface facing the first side surface of the silicon pillar; and a conductive layer, which is electrically connected to the second diffusion layer, and which is in contact with the second embedding insulating film at a position separated from the silicon pillar.
[Problem] To construct element isolation regions (20) by using an insulating film while forming word lines (WL) and the element isolation regions (20) by means of mutual self-alignment in an X-direction. [Solution] A semiconductor device manufacturing method has: a step of forming, on a principal surface of a semiconductor substrate (2), multiple active regions which extend in an X-direction within the principal surface and are repeatedly arranged in a Y-direction; a step of forming multiple trenches (T1) which extend in the Y-direction and define multiple active regions (silicon pillars (4a)) by respectively dividing the multiple active regions in the X-direction; a step of forming element isolation regions (20) by embedding an insulating film in the multiple trenches (T1); a step of forming trenches (T2) which extend in the Y-direction after the element isolation regions (20) are formed; and a step of forming word lines (WL) by forming a gate insulating film (27), which covers the inner surfaces of the trenches (T2), and further embedding a conductive film in the trenches (T2). The trenches (T1, T2) are formed by means of mutual self-alignment in the X-direction.
[Problem] To more precisely adjust impedance of an output terminal. [Solution] Impedance of an output buffer (unit buffer) included in an I/O circuit is adjusted on the basis of impedance of a pull-up circuit (replica circuit) included in a calibration circuit. In the calibration circuit, a pull-up circuit (310), a damping resistor (R21), a correction resistor (311), an electrostatic protection unit (312), and an external resistor (Re) are connected in series. The potential at the connection of the correction resistor (311) with the electrostatic protection unit (312) is compared with a reference potential by a comparator (360). The resistance value of the correction resistor (311) is determined on the basis of line resistances of lines which are respectively connected to a data terminal and a calibration terminal (ZQ).
The present invention provides a semiconductor device manufacturing method that reduces contact resistances in a memory cell region. This semiconductor device manufacturing method includes: a step wherein a gate insulating film and gate electrodes are formed in a second region; a step wherein a first liner film is formed so as to cover wires and the first gate electrodes in a first region and the second region; a step wherein first gate sidewalls are formed by etching back the first liner film in the second region; a step wherein a second liner film is formed so as to cover the first liner film in the first region while covering the gate electrodes in the second region; a step wherein second gate sidewalls adjoining the first gate sidewalls are formed by etching back the second liner film in the second region; a step wherein an impurity diffusion region is formed by injecting impurities into a semiconductor substrate in the second region; a step wherein the impurity diffusion region is activated by means of a thermal treatment; and a step wherein the second liner film is removed from the first region after the thermal treatment.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
99.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
A semiconductor device (1) equipped with a circuit board (10) on which multiple connection pads (13) are formed, a first semiconductor chip (20) that is mounted on the circuit board (10), a second semiconductor chip (30) that is laminated on the first semiconductor chip (20) and has multiple electrodes (31), reinforcement plates (40) that are laminated on the second semiconductor chip (30), and multiple wires that electrically connect the multiple connection pads (13) and the multiple electrodes (31) together, wherein the second semiconductor chip (30) has a laminated area (32) that overlaps with the first semiconductor chip (20) and overhang areas (33) that overhang from the first semiconductor chip (20), the electrodes (31) are formed in the overhang areas (33), and the reinforcement plates (40) are laminated on the second semiconductor chip (30) so as to straddle the laminated area (32) and the respective overhang areas (33) of the second semiconductor chip (30).
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
A semiconductor device includes a substrate and first and second semiconductor chips. Each of the first and second semiconductor chips includes: a surface that is divided according to first and second edges that are on opposite sides; an electrode group provided in a center area of the surface in parallel with the first edge, the electrode group including first and second electrodes of a command address type; third electrodes provided on the surface along the first edge; and fourth electrodes provided on the surface along the second edge. In the first semiconductor chip, the first electrodes are electrically connected with the third electrodes, and the second electrodes are electrically connected to the fourth electrodes. In the second semiconductor chip, the first electrodes are electrically connected with the fourth electrodes, and the second electrodes are electrically connected with the third electrodes. The second semiconductor chip is stacked on the first semiconductor chip in such a manner that the first edge of the second semiconductor chip is positioned on the second edge side of the first semiconductor chip and the second edge of the second semiconductor chip is positioned on the first edge side of the first semiconductor chip.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
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