An example digital-to-analog converter (DAC) circuit may comprise a plurality of single-bit DAC elements, an encoder circuit, and a multiplexer circuit. The encoder circuit may be configured to generate a control signal, where a number of asserted bits in the control signal is based at least in part on a digital input signal and an asserted bit pattern of the control signal is based at least in part on a random signal. The multiplexer circuit may be configured to modify the control signal to generate a noise-corrected control signal having a noise-corrected bit pattern. The noise-corrected bit pattern may direct a first asserted bit of the noise-corrected control signal to activate a first single-bit DAC element and a second asserted bit of the noise-corrected control signal to activate a second single-bit DAC element, where the first single-bit DAC element and the second single-bit DAC element having respective errors that at least partially cancel.
A current limiting system includes a plurality of current limiting devices electrically coupled in series to form a protected power path, where each current limiting device is configured to individually limit magnitude of an electric current flowing through the protected power path to a respective current limit value. Each current limiting device is further configured to control its respective current limit value such that (i) the respective current limit value is a respective constant current value when a magnitude of a respective supply voltage of the current limiting device is above a first voltage threshold value and (ii) the respective current limit value is less than the respective constant current value of the current limiting device when the magnitude of the respective supply voltage of the current limiting device is below the first voltage threshold value.
A test equipment system can provide signals to, or receive signals from, a device under test (DUT). The test system can include an output stage with output buffer circuitry that can be locally or externally controlled. An external controller can be used to provide precision input signals and, in response, measure current at a DUT interface node of the system, or measure voltage characteristics of various components inside the system. Using the input signals from the external controller, one or more aspects of the test system can be calibrated. For example, resistances of sense resistors in the output stage can be calibrated using current signals received from the external controller. In another example, buffer offset characteristics can be determined using signals from the external controller to control local drive circuitry of the system.
A digital-to-analog converter (DAC) calibration system for calibrating N DAC cells in a DAC, where N can be an integer number of DAC cells greater than 2, can include a processor, which can be configured to configure the DAC to generate N reference outputs, configure the DAC to generate N calibration outputs, and determine N overall error values corresponding to a difference between respective individual ones of the N calibration outputs and the N reference outputs. The processor can also be configured to determine, such as using the N overall error values, a cell error value for each of the N DAC cells.
A low input capacitance input stage for a high voltage amplifier includes a first input transistor configured to receive a first portion of a differential input signal and provide a first portion of an output signal, and a second input transistor configured to receive a second portion of the differential input signal and provide a second portion of the output signal. The amplifier can include a degeneration stage with a bias generator circuit. The degeneration stage can include first and second degeneration transistors coupled in series. The bias generator circuit can provide respective first and second bias signals to gate terminals of the first and second degeneration transistors to control an impedance of a signal path that couples source terminals of the first and second input transistors.
Examples of technology disclosed herein determine, by a serializer and a deserializer, one or more of calibration parameters and adaptive equalization (AEQ) parameters to perform calibration and AEQ for a communication link between the serializer and the deserializer. Such examples store the one or more parameters into a retention memory, and then put at least one of the serializer and deserializer into a sleep/low power mode. Upon receiving a wakeup command at each of the serializer and the deserializer put into the sleep mode, the serializer and the deserializer perform link lock of the communication link using the stored parameters.
Examples of technology disclosed herein determine, by a serializer and a deserializer, one or more of calibration parameters and adaptive equalization (AEQ) parameters to perform calibration and AEQ for a communication link between the serializer and the deserializer. Such examples store the one or more parameters into a retention memory, and then put at least one of the serializer and deserializer into a sleep/low power mode. Upon receiving a wakeup command at each of the serializer and the deserializer put into the sleep mode, the serializer and the deserializer perform link lock of the communication link using the stored parameters.
Technologies are provided for monitoring a medical condition using variability of respiratory parameters. The medical condition may include a pulmonary condition or an autonomic disorder that impairs respiratory function. Examples of variability of respiratory parameters include respiratory rate variability (RVV) and tidal volume variability (TVV). Monitoring the medical condition may result in a device being directed to implement a notification procedure that is based on a status of the medical condition.
Devices and associated method are shown that include a mass movably coupled over a substrate. In selected configurations, a controlled contact system is coupled between the mass and the at least one stopper. Examples are also shown where the controlled contact system includes a first stage contact coupled to a flexible beam and a second stage contact.
A semiconductor die for an inductor-based switching power converter includes a semiconductor layer stack, a first enhancement mode, N-channel metal oxide semiconductor field effect transistor (first NMOS FET) formed in the semiconductor layer stack, a second enhancement mode, N-channel metal oxide semiconductor field effect transistor (second NMOS FET) formed in the semiconductor layer stack, first driver circuitry formed in the semiconductor layer stack, second driver circuitry formed in the semiconductor layer stack, and bootstrap capacitance. The first driver circuitry is configured to drive the first gate from a bootstrap power rail in response to a first control signal, and the second driver circuitry is configured to drive the second gate in response to a second control signal. The bootstrap capacitance includes one or more bootstrap trench capacitors formed in the semiconductor layer stack, and each bootstrap capacitor is electrically coupled between the bootstrap power rail and the switching node.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H01L 29/94 - Dispositifs à métal-isolant-semi-conducteur, p.ex. MOS
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
11.
PREDICTING PHYSICAL MODALITIES OF POWER ELECTRONIC DEVICES
Power electronic device prediction systems and methods for using power electronic device models to predict the physical modalities of unknown power electronic devices. These unknown power electronic devices have not been seen previously by the power electronic device models. For example, if the class of power electronic devices is power converters, then a power converter model is trained on known physical modalities from different power converters and the model is used to predict an unknown physical modality of a power converter that the model has not seen before. In some examples, the training is unsupervised, such that the training data is unlabeled. In other examples, the training uses self-supervised techniques using unlabeled training data and then the model is refined using few-shot learning techniques and a small amount of labeled training data. This allows the models to quickly adapt to predict the physical modalities of unknown power electronic devices.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 119/06 - Analyse de puissance ou optimisation de puissance
12.
ERROR POLARITY DETECTION FOR TIMING SKEW CALIBRATION
An electronic circuit comprises multiple analog-to-digital converters (ADCs), clock circuitry, and calibration circuitry. The clock circuitry is configured to provide clock signals to the multiple ADCs to advance the multiple ADCs through time-interleaved analog-to-digital (A/D) conversions. The calibration circuitry is configured to determine a magnitude of timing skew error between any two of the clock signals; apply a dither sequence to a first clock signal of the any two clock signals, wherein the first clock signal is applied to a first ADC; determine a polarity of the timing skew error by determining a polarity of gain experienced by the dither sequence from the time-interleaved A/D conversions.
Successive approximation register (SAR) analog-to-digital converters (ADCs) with direct decision feedback loops are disclosed herein. In certain embodiments, a SAR ADC includes a digital-to-analog converter (DAC) that generates an analog output signal, a comparator including an input that receives the analog output signal of the DAC and an output that generates a comparison signal, and an array of switches coupled to the output of the comparator and operable to provide a non-latched feedback signal to a digital input of the DAC.
Aspects of this disclosure relate to voltage modulators with staged activation of switches. A voltage modulator can receive supply voltages and provide a selected one of the supply voltages as an output voltage. The voltage modulator can include switches in parallel where one of the switches in parallel activates before another switch in parallel in association by transitioning the output voltage between different supply voltages. Embodiments of this disclosure relate to symbol-based envelope tracking. Related systems and methods are disclosed.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
15.
ISOLATION USING MICRO/NANOSCALE PIEZOELECTRIC ACOUSTIC RESONATOR STRUCTURES
Described herein are techniques for enhancing isolation in on-chip piezoelectric-based isolators. Several techniques are described that improve isolation in piezoelectric isolators. According to an aspect of the present disclosure, a piezoelectric isolator may include structures arranged to decrease the occurrence of pockets of high electric field and/or to increase the breakdown electric field in the path from the transmitter to the receiver. Further aspects of the present disclosure relate to techniques for increasing the efficiency of piezoelectric isolators while also limiting the formation of spurious signals. The inventors have developed techniques for promoting propagation of surface acoustic waves toward the receiver while limiting propagation in the opposite direction.
16.
WIRELESS MULTI-USER COMMUNICATIONS SYSTEMS USING BLIND SOURCE SEPARATION
Wireless communications systems using blind source separation are disclosed. In certain embodiments, a wireless communications system includes a digital front end (DFE) that processes two or more input signals received from the wireless communications system's antennas. The input signals reflect a mixture of transmitted signals (which can have a common frequency) received over a wireless channel from transmitting devices. The DFE applies an adjustable weight matrix to the received input signals to generate output signals corresponding to estimates of the transmitted signals from each of the transmitting devices. The DFE determines coefficients of the adjustable weight matrix using blind source separation in which the coefficients of the matrix are iteratively adjusted based on computations performed on the input signals, such as by utilizing an independent component analysis (ICA) technique. The embedded DFE system enables a multimodal communication experience by simultaneously supporting and running different stacks of inhomogeneous wireless standards.
H04B 1/18 - Circuits d'entrée, p. ex. pour le couplage à une antenne ou à une ligne de transmission
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
Techniques for decoding a pulse width modulation (PWM) signal transmitted across an isolation barrier, such as within a gate driver, are described. The techniques utilize a PWM modulation scheme that uses four or more levels to encode and decode data, ensuring accurate and efficient communication across the isolation barrier. Using these techniques, the pulse modulator generates a PWM signal with four or more distinct modulation levels, where each level represents different combinations of AC and DC components, allowing the encoding of two bits of data per modulation cycle.
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
18.
FAULT PROTECTION OF SYMBOL BASED ENVELOPE TRACKERS
Aspects of this disclosure relate to a power amplifier system with symbol-based envelope tracking and fault protection. The system can include a power amplifier and a voltage modulator. The voltage modulator can include switches configured to provide the bias voltage and to provide electric circuit breaker protection. The voltage modulator can include a fault detection circuit that can cause a switch of the switches to provide electric circuit breaker protection in response to detecting a circuit fault. Related methods and voltage modulators are disclosed.
Linear regression data may describe the processing task with a target vector describing an output of the hardware component, a measurement vector describing measurements on which the output of the hardware component is based, and a weight vector describing weights applied to the measurement vector to generate the target vector. The linear regression data may be modified to describe the processing task based on the target vector, the measurement vector, the weight vector, and a binary constraint vector describing a hardware constraint limiting access by the hardware component to at least a portion of the weight vector. The modified linear regression data may be relaxed based on a relaxed constraint vector that is based at least in part on the binary constraint vector. A convex solver algorithm may be used to determine a set of values for the weight vector and a set of values for the binary constraint vector.
System and techniques to enable transfer learning for machine-learning model interoperability are described herein. Data in a target domain is subjected to a transport process that shifts the data towards a source domain. The transport process includes creating synthetic data based on a portion of the target domain data and a constraint. A transformation is applied to a combination of the synthetic data and the original data that shifts the combination into the source domain. An ML model, trained on the source domain, is invoked on the data that results from the transformation.
Described herein are techniques for enhancing isolation in on-chip piezoelectric-based isolators. Several techniques are described that improve isolation in piezoelectric isolators. According to an aspect of the present disclosure, a piezoelectric isolator may include structures arranged to decrease the occurrence of pockets of high electric field and/or to increase the breakdown electric field in the path from the transmitter to the receiver. Further aspects of the present disclosure relate to techniques for increasing the efficiency of piezoelectric isolators while also limiting the formation of spurious signals. The inventors have developed techniques for promoting propagation of surface acoustic waves toward the receiver while limiting propagation in the opposite direction.
Described herein are techniques for enhancing isolation in on-chip piezoelectric-based isolators. Several techniques are described that improve isolation in piezoelectric isolators. According to an aspect of the present disclosure, a piezoelectric isolator may include structures arranged to decrease the occurrence of pockets of high electric field and/or to increase the breakdown electric field in the path from the transmitter to the receiver. Further aspects of the present disclosure relate to techniques for increasing the efficiency of piezoelectric isolators while also limiting the formation of spurious signals. The inventors have developed techniques for promoting propagation of surface acoustic waves toward the receiver while limiting propagation in the opposite direction.
H03H 9/25 - Détails de réalisation de résonateurs utilisant des ondes acoustiques de surface
H03H 3/08 - Appareils ou procédés spécialement adaptés à la fabrication de réseaux d'impédance, de circuits résonnants, de résonateurs pour la fabrication de résonateurs ou de réseaux électromécaniques pour la fabrication de résonateurs ou de réseaux utilisant des ondes acoustiques de surface
H03H 9/145 - Moyens d'excitation, p. ex. électrodes, bobines pour réseaux utilisant des ondes acoustiques de surface
Described herein are techniques for enhancing isolation in on-chip piezoelectric-based isolators. Several techniques are described that improve isolation in piezoelectric isolators. According to an aspect of the present disclosure, a piezoelectric isolator may include structures arranged to decrease the occurrence of pockets of high electric field and/or to increase the breakdown electric field in the path from the transmitter to the receiver. Further aspects of the present disclosure relate to techniques for increasing the efficiency of piezoelectric isolators while also limiting the formation of spurious signals. The inventors have developed techniques for promoting propagation of surface acoustic waves toward the receiver while limiting propagation in the opposite direction.
H03H 9/02 - Réseaux comprenant des éléments électromécaniques ou électro-acoustiquesRésonateurs électromécaniques Détails
H03H 3/08 - Appareils ou procédés spécialement adaptés à la fabrication de réseaux d'impédance, de circuits résonnants, de résonateurs pour la fabrication de résonateurs ou de réseaux électromécaniques pour la fabrication de résonateurs ou de réseaux utilisant des ondes acoustiques de surface
H03H 9/145 - Moyens d'excitation, p. ex. électrodes, bobines pour réseaux utilisant des ondes acoustiques de surface
H03H 9/25 - Détails de réalisation de résonateurs utilisant des ondes acoustiques de surface
24.
ISOLATION USING MICRO/NANOSCALE PIEZOELECTRIC ACOUSTIC RESONATOR STRUCTURES
Described herein are techniques for enhancing isolation in on-chip piezoelectric-based isolators. Several techniques are described that improve isolation in piezoelectric isolators. According to an aspect of the present disclosure, a piezoelectric isolator may include structures arranged to decrease the occurrence of pockets of high electric field and/or to increase the breakdown electric field in the path from the transmitter to the receiver. Further aspects of the present disclosure relate to techniques for increasing the efficiency of piezoelectric isolators while also limiting the formation of spurious signals. The inventors have developed techniques for promoting propagation of surface acoustic waves toward the receiver while limiting propagation in the opposite direction.
Apparatus and methods for equalizing microelectromechanical systems (MEMS) sensors are disclosed. In certain embodiments, measured sensor parameters of a MEMS sensor are stored in a non-volatile memory (NVM) of a sensor signal processor used to process a sensor output signal of the MEMS sensor. The measured sensor parameters are retrieved by a digital signal processor (DSP) and used for equalizing sensor data provided to the DSP by the sensor signal processor during operation. The measured sensor parameters can be determined at test, per individual part, by measurements of the MEMS sensor's characteristics, and thus equalize the MEMS sensor while accounting for manufacturing and/or processing variations.
Fully symmetric sensing structures for MEMS devices are disclosed herein. In certain embodiments, a MEMS sensor includes a proof mass that moves in a first direction. The proof mass includes moveable fingers that move with the proof mass. The MEMS sensor further includes fixed fingers that are fixed with respect to the moveable fingers, and the fixed fingers and moveable fingers serve to detect movement of the proof mass. For example, the moveable fingers and the fixed fingers can be interdigitated to form a comb finger set for sensing changes in capacitance arising from movement of the proof mass relative to a substrate. A layout of the fixed fingers is fully symmetric in at least the first direction.
Described herein are on-chip isolator devices that can be employed in high-power applications and that are designed to enhance high common-mode transient immunity (CMTI) without sacrificing isolator gain. An isolator device includes two dies. A first die supports an isolation barrier and the second die is barrierless. The second die is barrierless in that it lacks isolation materials that are commonly used to sustain isolation barriers in on-chip isolator devices (e.g., polyimide). To enhance CMTI despite the absence of a further isolation barrier formed on the second die, the second die is provided with a tapped impedance element, an impedance element having a tap that couples the impedance element to a reference potential (e.g., to ground). The secondary side of the isolator of the first die is coupled to the tapped impedance element of the second die, thus creating a discharge path for common-mode transients.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés
H03H 7/00 - Réseaux à plusieurs accès comportant comme composants uniquement des éléments électriques passifs
A desaturation detection circuit is described that uses two or more desaturation circuit threshold values, which shifts the desaturation threshold value in a normal operational mode to a higher voltage when the active short circuit (ASC) signal is present in a faulted operational mode. Including two or more desaturation detection circuit threshold values allows a lower desaturation threshold value during a normal operational mode and a higher voltage in a faulted operational mode, or mode-dependent threshold value selection.
Encoding techniques are described for gate driving that take advantage of having multiple data channels to encode data and use a symbol-based encoding system to enhance data transmission speed and reliability. By encoding logic inputs (0, 1) into symbols and using a dedicated synchronization mechanism, the techniques ensure accurate data framing and synchronization, effectively overcoming the limitations of traditional methods. This approach not only facilitates faster transmission of fault data across an isolation barrier but also significantly improves the system's overall efficiency and reliability in controlling gates for traction drives.
H03M 13/45 - Décodage discret, c.-à-d. utilisant l'information de fiabilité des symboles
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
Systems and methods are provided for operating one or more power converters. The systems and methods extract a plurality of metrics from an output of a power supply and obtain a plurality of objectives and/or constraints of an optimization function. The systems and methods automatically generate a solution to the optimization function based on the plurality of metrics extracted from the output of the power supply, the solution comprising one or more compensation parameters. The systems and methods automatically modify one or more tunable parameters of the power supply based on the one or more compensation parameters of the automatically generated solution to the optimization function.
Systems and methods are provided for verifying operation of one or more power converters. The systems and methods obtain one or more outputs of a power supply and generate a set of metrics based on the one or more outputs of the power supply. The systems and methods store a first set of metadata corresponding to the power supply, the first set of metadata associating a current setting for a plurality of tunable parameters and the set of metrics, and generate, for display, a graphical user interface (GUI) comprising the first set of metadata corresponding to the power supply.
Example implementations include a method, apparatus and computer-readable medium for automated analog electronic system design and analysis, comprising receiving a user query via a user interface. The implementations further include identifying, by a conversation agent of a machine learning model (MLM), at least one attribute of the user query. Additionally, the implementations further include selecting from a plurality of agents, by the conversation agent of the MLM, two or more agents that can collectively generate a response to the user query when executed in a specific sequence based on the at least one attribute of the user query. Additionally, the implementations further include prompting, by the conversation agent of the MLM, the two or more agents in the specific sequence to collectively generate the response. Additionally, the implementations further include outputting, by the conversation agent of the MLM, the response via the user interface.
Techniques for automatic parameter tuning of active road noise cancellation systems are described herein. The system can automatically search for an optimal set of algorithm parameters based on recorded data. An active road noise cancellation algorithm and simulation can be embedded in an auto-differentiation framework, which allows gradients of the algorithm parameters to guide the automatic search and calculations of the algorithm parameters.
G10K 11/178 - Procédés ou dispositifs de protection contre le bruit ou les autres ondes acoustiques ou pour amortir ceux-ci, en général utilisant des effets d'interférenceMasquage du son par régénération électro-acoustique en opposition de phase des ondes acoustiques originales
34.
SYSTEMS AND METHODS FOR ANALOG ELECTRONIC DESIGN AND ANALYSIS USING A MULTI-MODAL, MULTI-AGENT ARTIFICIAL INTELLIGENCE (AI) MODEL
Example implementations include a method, apparatus and computer-readable medium for automated analog electronic system design and analysis, comprising receiving a user query via a user interface. The implementations further include identifying, by a conversation agent of a machine learning model (MEM), at least one attribute of the user query. Additionally, the implementations further include selecting from a plurality of agents, by the conversation agent of the MEM, two or more agents that can collectively generate a response to the user query when executed in a specific sequence based on the at least one attribute of the user query. Additionally, the implementations further include prompting, by the conversation agent of the MEM, the two or more agents in the specific sequence to collectively generate the response. Additionally, the implementations further include outputting, by the conversation agent of the MEM, the response via the user interface.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/36 - Conception de circuits au niveau analogique
G06F 30/38 - Conception de circuits au niveau mixte des signaux analogiques et numériques
A method is provided for pretraining a hyper model configured for use in predicting a state of power (SoP) of a vehicle battery. The method includes performing electrochemical impedance spectroscopy (EIS) scans on a plurality of batteries having a set of similar operating characteristics to the vehicle battery. The EIS scans are performed across various states of the vehicle battery. The method further includes fitting parameters of the hyper model by applying an optimization technique to results of the EIS scans. The hyper model includes a family of models that each define a voltage response of a respective cell from among a plurality of cells of the vehicle battery to a current profile over the various states of the vehicle battery.
G01R 31/367 - Logiciels à cet effet, p. ex. pour le test des batteries en utilisant une modélisation ou des tables de correspondance
B60L 58/18 - Procédés ou agencements de circuits pour surveiller ou commander des batteries ou des piles à combustible, spécialement adaptés pour des véhicules électriques pour la surveillance et la commande des batteries de plusieurs modules de batterie
G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge combinant des mesures de tension et de courant
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/396 - Acquisition ou traitement de données pour le test ou la surveillance d’éléments particuliers ou de groupes particuliers d’éléments dans une batterie
37.
LOW-NOISE VOLTAGE REGULATORS AND ASSOCIATED METHODS
A low-noise voltage regulator includes (i) an error amplifier configured to generate an error signal that is proportional to a difference between a voltage at a ground node and a voltage at a set node, (ii) a reference resistor electrically coupled between an output power node and the set node, (iii) a capacitor is connected in parallel with the reference resistor, (iv) a reference current source electrically coupled to the set node, and (v) a control and power stage electrically coupled between an input power node and the output power node. The control and power stage is configured to convert an input voltage to an output voltage in response to the error signal to minimize a magnitude of the error signal.
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
38.
SERIALIZER-DESERIALIZER SENSOR SYSTEM CONFIGURATIONS
Aspects of the present disclosure include a serializer, a method, and/or a non-transitory computer readable medium for receiving an indication indicating the sensor circuit is connected to a controller circuit, identifying a sensor identifier associated with the sensor circuit from an internal memory of the serializer, transmitting the sensor identifier from the serializer to the controller circuit to a deserializer to identify and load a sensor circuit driver associated with the sensor identifier, transmitting sensor calibration data from the memory circuit on the sensor circuit to the controller circuit, and transmitting sensor data to the deserializer.
A method includes an operation to collect radar signals reflected from objects in a field of view. Range-angle-doppler bins representing three-dimensional objects in the field of view and formed. A local median operation is used across a selected dimension of the range-angle-doppler bins to eliminate background noise in the range-angle-doppler bins. Low energy peak regions are masked by removing radial velocity values in the selected dimension to form a sparse range-angle two-dimensional grid. The radar signals reflected from objects in the view of view are processed to extract reflection point detections. Reflection point detections are tracked in accordance with short-term filter rules to form tracked reflection point detections. The tract reflection point detections are formed into clusters. The clusters are processed with long-term filter rules.
Apparatus and methods for touch screen motion compensation are disclosed herein. In certain embodiments, a touch screen motion compensation system for a vehicle includes an accelerometer that generates accelerometer data indicating a motion of the vehicle, a touch screen display that generates touch location data in response to tactile input from a user, and a computing system that generates compensated touch location data by compensating the touch location data based on the accelerometer data.
B60K 35/28 - Dispositions de sortie, c.-à-d. du véhicule à l'utilisateur, associées aux fonctions du véhicule ou spécialement adaptées à celles-ci caractérisées par le type d’informations de sortie, p. ex. divertissement vidéo ou informations sur la dynamique du véhiculeDispositions de sortie, c.-à-d. du véhicule à l'utilisateur, associées aux fonctions du véhicule ou spécialement adaptées à celles-ci caractérisées par la finalité des informations de sortie, p. ex. pour attirer l'attention du conducteur
G01P 13/00 - Indication ou enregistrement de l'existence ou de l'absence d'un mouvementIndication ou enregistrement de la direction d'un mouvement
G06F 3/044 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens capacitifs
Aspects of the present disclosure include a biometric device configured to receive biometric signals from sensors placed on a subject, and attenuate at frequencies causing noise in the biometric signals. Aspects are directed to a finite impulse response (FIR) filter configured to attenuate noise frequencies caused by line frequencies and/or flicker frequencies. Aspects of the FIR filter may be configured based on an analog-to-digital (ADC) sampling rate.
A61B 5/024 - Mesure du pouls ou des pulsations cardiaques
A61B 5/00 - Mesure servant à établir un diagnostic Identification des individus
A61B 5/145 - Mesure des caractéristiques du sang in vivo, p. ex. de la concentration des gaz dans le sang ou de la valeur du pH du sang
A61B 5/1455 - Mesure des caractéristiques du sang in vivo, p. ex. de la concentration des gaz dans le sang ou de la valeur du pH du sang en utilisant des capteurs optiques, p. ex. des oxymètres à photométrie spectrale
An apparatus for providing variable end user control of a handheld tool function includes a trigger member arranged for travel during user depression relative to a tool body. A first inertial sensor, affixed to either the trigger member or body, maintains a fixed orientation and provides motion data along at least first and second axes. A second inertial sensor, arranged on the trigger member or body, rotates relative to the first inertial sensor during trigger depression, with the rotation amount varying based on depression amount. Throughout its entire range of rotation, the second inertial sensor rotates about a third axis that remains askew with respect to both the first and second axes of the first inertial sensor.
G01P 15/18 - Mesure de l'accélérationMesure de la décélérationMesure des chocs, c.-à-d. d'une variation brusque de l'accélération dans plusieurs dimensions
B25F 5/02 - Structure des boîtiers, corps ou poignées
G01P 15/02 - Mesure de l'accélérationMesure de la décélérationMesure des chocs, c.-à-d. d'une variation brusque de l'accélération en ayant recours aux forces d'inertie
The present subject matter relates to an electronic system including multiple power supply circuits connected in parallel. A first power supply circuit includes a current sensing circuit configured to measure current to the first power supply circuit and total current drawn by the multiple power supply circuits. A second power supply circuit is connected in parallel to the first power supply circuit and includes a current sensing circuit configured to measure current to the second power supply circuit and the total current drawn by the multiple power supply circuits. Each of the first and second power supply circuits are configured to change operation of the power supply circuit to reduce current drawn by the power supply circuit when either the current to the power supply circuit or the total current drawn by the multiple power supply circuits exceeds a specified current limit level.
H02M 1/00 - Détails d'appareils pour transformation
B60R 16/033 - Circuits électriques ou circuits de fluides spécialement adaptés aux véhicules et non prévus ailleursAgencement des éléments des circuits électriques ou des circuits de fluides spécialement adapté aux véhicules et non prévu ailleurs électriques pour l'alimentation des sous-systèmes du véhicule en énergie électrique caractérisé par l'utilisation de cellules électriques ou de batteries
An electrical assembly includes a first substrate, a second substrate, and a magnetic device disposed between the first substrate and the second substrate. The magnetic device includes (1) a magnetic core, (2) a first primary winding extending through the magnetic core and electrically coupling the first substrate to the second substrate, (3) a second primary winding extending through the magnetic core and electrically coupling the first substrate to the second substrate, (4) a first secondary winding wound around at least a portion of the magnetic core, and (5) a second secondary winding wound around at least a portion of the magnetic core. The electrical assembly further includes one or more electrical conductors on the first substrate electrically coupling the first secondary winding in series with the second secondary winding.
H01F 27/30 - Fixation ou serrage de bobines, d'enroulements ou de parties de ceux-ci entre euxFixation ou montage des bobines ou enroulements sur le noyau, dans l'enveloppe ou sur un autre support
A low noise amplifier topology can achieve very low noise figure by applying multiple magnetic coupling between gate matching inductors and source degeneration inductor of a field effect transistor. The resulting low noise amplifier has smaller inductors, which can have lower thermal noise contribution, and can maintain good gain and linearity performance. For example, a low noise amplifier includes a first inductor to receive an input; a second inductor coupled to the first inductor in series; a first field effect transistor device whose gate receives a signal from the second inductor; and a third inductor coupled to a source of the first field effect transistor device, where the third inductor is magnetically positively coupled to the first inductor and the second inductor.
A gyroscopic sensor system can include a proof mass, which can be configured to vibrate in a first primary mode and a second primary mode, where the first primary mode can be driven into resonance, where an in-phase signal can be induced in the second primary mode in response to a rotation of the gyroscopic sensor system. The gyroscopic sensor system can also include a quadrature force circuit, which can be configured to force the second primary mode of the proof mass. The gyroscopic sensor system can also include control circuitry, which can be configured to drive the quadrature force circuit using a quadrature test signal which can be configured to generate a quadrature response in the proof mass that can be in quadrature with the in-phase signal. The control circuitry can also be configured to measure the quadrature response of the proof mass to the quadrature test signal.
G01C 25/00 - Fabrication, étalonnage, nettoyage ou réparation des instruments ou des dispositifs mentionnés dans les autres groupes de la présente sous-classe
G01C 19/56 - Dispositifs sensibles à la rotation utilisant des masses vibrantes, p. ex. capteurs vibratoires de vitesse angulaire basés sur les forces de Coriolis
A measurement system and method can include: a signal generator configured to provide a transmit voltage; a transmit electrode connected to the signal generator; a trans-impedance amplifier having a trans-impedance amplifier input and a trans-impedance amplifier output; a receive electrode connected to the trans-impedance amplifier input; voltage measurement circuitry configured to: acquire a transmit voltage measurement from a first connection connected between the signal generator and the transmit electrode and from a second connection connected to the trans-impedance amplifier input, and acquire a receive voltage measurement from a third connection connected to the trans-impedance amplifier input and from a fourth connection connected to the trans-impedance amplifier output; and a digital processing unit configured to determine an impedance based on the electrodes being in direct contact with a body, the impedance based on a ratio of the transmit voltage measurement and the receive voltage measurement.
ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY (Irlande)
Inventeur(s)
Kurfiss Ii, Neal T.
Hurwitz, Jonathan Ephraim David
Abrégé
A method and apparatus can include: a fan vented enclosure with cooling fans for creating air columns, each of the air columns corresponding to one of the cooling fans; a detector coupled to the fan vented enclosure; and an angled channel coupled to the fan vented enclosure, the angled channel configured to redirect a sample across at least one of the air columns to the detector such that a number of detectors is less than a number of air columns, the angled channel further configured to allow bypass air to flow around the angled channel.
A sensor module may include a housing comprising a channel extending through a longitudinal axis of the housing. The channel is configured to receive a fluid substance. The sensor module includes an outlet valve in fluid communication with the channel and a capacitive sensor positioned inside the channel. The sensor module can include an actuator at least partially surrounded by the capacitive sensor, and a pump including a fluid reservoir configured to contain a solution. During operation of the sensor module, activation of the pump pushes at least some of the solution from the fluid reservoir into the channel to advance the actuator into the chamber.
A61M 5/172 - Moyens pour commander l'écoulement des agents vers le corps ou pour doser les agents à introduire dans le corps, p. ex. compteurs de goutte-à-goutte électriques ou électroniques
52.
DEVICES FOR DIGITAL-DOMAIN TEMPERATURE COMPENSATION IN LOGARITHMIC TRANSIMPEDANCE AMPLIFIERS
Technologies are provided to calculate a logarithm of an input current to a logarithmic transimpedance amplifier device at a particular temperature. The logarithm of the current is calculated in digital domain based on sampling of analog signals that are internal to the logarithmic transimpedance amplifier device. The sampling can be performed, in some cases, by an analog-to-digital converter device integrated into the logarithmic transimpedance amplifier device. The calculation in digital domain is performed by one or more processor external to the logarithmic transimpedance amplifier device. The calculation includes a determination of a temperature compensation factor based on an internal analog signal indicative of temperature of the logarithmic transimpedance amplifier device. The temperature compensation factor permits removing temperature dependence from a logarithmic output voltage originating from the input current. Operating in the digital domain permits applying corrections that account for residual leakage current and an emitter-resistance correction at high input currents.
A gain stage circuit can include first and second follower circuits arranged as a differential pair and configured to receive respective input signals. The gain stage circuit can include or use a pass stage circuit including an adjustable-impedance signal path that couples the first and second follower circuits. The gain stage circuit can further include or use a control circuit to receive the input signals and, in response, provide a control signal to the pass stage circuit to control an impedance of the signal path that couples the first and second follower circuits.
A measurement system and method can include: a signal generator configured to provide a transmit voltage; a transmit electrode connected to the signal generator; a trans-impedance amplifier having a trans-impedance amplifier input and a trans-impedance amplifier output; a receive electrode connected to the trans-impedance amplifier input; voltage measurement circuitry configured to: acquire a transmit voltage measurement from a first connection connected between the signal generator and the transmit electrode and from a second connection connected to the trans-impedance amplifier input, and acquire a receive voltage measurement from a third connection connected to the trans-impedance amplifier input and from a fourth connection connected to the trans-impedance amplifier output; and a digital processing unit configured to determine an impedance based on the electrodes being in direct contact with a body, the impedance based on a ratio of the transmit voltage measurement and the receive voltage measurement.
A61B 5/053 - Mesure de l'impédance ou de la conductivité électrique d'une partie du corps
A61B 5/00 - Mesure servant à établir un diagnostic Identification des individus
G16H 40/63 - TIC spécialement adaptées à la gestion ou à l’administration de ressources ou d’établissements de santéTIC spécialement adaptées à la gestion ou au fonctionnement d’équipement ou de dispositifs médicaux pour le fonctionnement d’équipement ou de dispositifs médicaux pour le fonctionnement local
G16H 50/30 - TIC spécialement adaptées au diagnostic médical, à la simulation médicale ou à l’extraction de données médicalesTIC spécialement adaptées à la détection, au suivi ou à la modélisation d’épidémies ou de pandémies pour le calcul des indices de santéTIC spécialement adaptées au diagnostic médical, à la simulation médicale ou à l’extraction de données médicalesTIC spécialement adaptées à la détection, au suivi ou à la modélisation d’épidémies ou de pandémies pour l’évaluation des risques pour la santé d’une personne
55.
SOFTWARE-DEFINED POWER EQUALIZATION FOR LOW-FREQUENCY SUPPRESSION IN AUDIO DEVICES
According to one non-limiting example of the present disclosure, a method for reducing power fluctuations in an audio device can include receiving, via the audio device, a power profile of an audio frame, the audio device comprising a plurality of digital subsystem circuits, dividing the audio frame into a plurality of windows, for each of the plurality of windows, adjusting a clock frequency of one or more of the plurality of digital subsystem circuits based on a plurality of predetermined clock frequency values set to reduce power fluctuations in the audio frame, and processing the audio frame via the plurality of digital subsystem circuits at the adjusted clock frequencies for each window.
Technologies are provided to calculate a logarithm of an input current to a logarithmic transimpedance amplifier device at a particular temperature. The logarithm of the current is calculated in digital domain based on sampling of analog signals that are internal to the logarithmic transimpedance amplifier device. The sampling can be performed, in some cases, by an analog-to-digital converter device integrated into the logarithmic transimpedance amplifier device. The calculation in digital domain is performed by one or more processor external to the logarithmic transimpedance amplifier device. The calculation includes a determination of a temperature compensation factor based on an internal analog signal indicative of temperature of the logarithmic transimpedance amplifier device. The temperature compensation factor permits removing temperature dependence from a logarithmic output voltage originating from the input current. Operating in the digital domain permits applying corrections that account for residual leakage current and an emitter-resistance correction at high input currents.
In some embodiments, a communication device configured to receive power and communicate data signals via a differential pair of conductors is provided. The communication device comprises circuitry configured to generate or receive a common mode voltage via the differential pair; and at least one of: circuitry configured to, in response to detecting an edge of an incoming digital signal via an input conductor, transmit an outgoing pair of pulses based on the detected edge via the differential pair; or circuitry configured to detect an incoming pair of pulses via the differential pair and adjust a signal transmitted via an output conductor indicating a logical value based on the incoming pair of pulses.
Technologies are provided to calculate a logarithm of an input current to a logarithmic transimpedance amplifier device at a particular temperature. The logarithm of the current is calculated in digital domain based on sampling of analog signals that are internal to the logarithmic transimpedance amplifier device. The sampling can be performed, in some cases, by an analog-to-digital converter device integrated into the logarithmic transimpedance amplifier device. The calculation in digital domain is performed by one or more processor external to the logarithmic transimpedance amplifier device. The calculation includes a determination of a temperature compensation factor based on an internal analog signal indicative of temperature of the logarithmic transimpedance amplifier device. The temperature compensation factor permits removing temperature dependence from a logarithmic output voltage originating from the input current. Operating in the digital domain permits applying corrections that account for residual leakage current and an emitter-resistance correction at high input currents.
A method of operating a radio frequency (RF) transceiver includes transmitting a narrowband calibration signal using a transmit channel of the RF transceiver, wherein a transmitted output signal includes a sideband of the calibration signal and a sideband of a digital-to-analog converter (DAC) image signal produced by DAC circuitry of the transmit channel; sampling the transmitted output signal using an analog-to-digital converter (ADC) circuit; filtering the transmitted output signal sampled by the ADC circuit to reduce power of the sideband of the calibration signal; attenuating DAC signals produced by the DAC circuitry to reduce power of the sideband of the DAC image signal; restoring the power of the sideband of the calibration signal sampled by the ADC circuit; and performing quadrature error correction (QEC) using the output of the ADC circuit.
An integrated circuit comprising an FPGA including programmable/configurable logic circuitry having a periphery, wherein resources (e.g., memory (e.g., high-speed local RAM), one or more busses, and/or circuitry external to the FPGA (e.g., a processor, a controller and/or system/external memory), is/are disposed outside the periphery of the programmable/configurable logic circuitry which includes a plurality of logic tiles, wherein at least one logic tile is located completely within the interior of the periphery and wherein each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile wherein a first portion of the I/Os are located on a perimeter of the logic tile that is interior to the periphery, and the first portion of I/Os of each logic tile of the plurality of the logic tiles are directly connected to the bus to provide communication between the resources and the logic tiles.
One embodiment is a method for implementing a cloud-based portable miniaturized system for performing non-invasive blood glucose level measurement in real time. The method includes using an optical source to emit optical radiations at certain wavelengths through breath in an air collection chamber; receiving the emitted optical transmissions at a photodetector; converting the received optical transmissions to digital data; accumulating the digital data for a first time period; and periodically transmitting the accumulated digital data to a cloud service for further processing.
A61B 5/145 - Mesure des caractéristiques du sang in vivo, p. ex. de la concentration des gaz dans le sang ou de la valeur du pH du sang
A61B 5/00 - Mesure servant à établir un diagnostic Identification des individus
A61B 5/08 - Dispositifs de mesure pour examiner les organes respiratoires
A61B 5/097 - Dispositifs pour faciliter la collecte du gaz respiré ou pour le diriger vers ou à travers des dispositions de mesure
A61B 5/1455 - Mesure des caractéristiques du sang in vivo, p. ex. de la concentration des gaz dans le sang ou de la valeur du pH du sang en utilisant des capteurs optiques, p. ex. des oxymètres à photométrie spectrale
Biasing techniques for reducing distortion in amplifiers are described. A regulation loop is used to keep the sum of collector currents of the input differential pair constant. The regulation loop includes an error correction amplifier that compares the sum of the input differential pair collector current with a reference current and adjusts a control voltage at a control terminal of a transistor to keep the current equal or proportional to the reference current.
A radar method, in particular a primary radar method, in which at least one first and at least one second transceiver unit (S1, S2), which are in particular spatially separated from one another, and transmit and receive signals simultaneously or overlapping in time, wherein a respective comparison signal, in particular mixed signals s1k,mix(t) or s2k,mix(t) are formed from a signal transmitted and received by the respective transceiver unit, wherein a phase correction is formed for each of a plurality of sample values, preferably a phase correction value for each of a plurality of sample values from the comparison signals s1k,mix(t) or s2k,mix(t), in particular in such a way that, preferably by a mathematical operation, a measure is formed of a phase difference per sample value between the at least two signals s1k,mix(t) or s2k,mix(t).
There is disclosed herein examples of systems and methods for compressing a signal. Samples of the signal can be segmented and the samples within each of the segments can be averaged to produce a value that can represent the samples within the segment. The number of samples to average in each segment may be determined based on an error threshold, such that the number of samples being averaged can be maximized to produce less data to be transmitted while maintaining the representation of the samples within the error threshold. In some embodiments, a signal can be separated into a timing reference, a representative periodic function, and a highly compressible error signal. The error signal can be utilized for reproducing a representation of the signal.
H04N 19/65 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant la tolérance aux erreurs
A61B 5/00 - Mesure servant à établir un diagnostic Identification des individus
A61B 5/33 - Modalités électriques se rapportant au cœur, p. ex. électrocardiographie [ECG] spécialement adaptées à l’utilisation conjointe avec d’autres dispositifs
A61B 5/364 - Détection d'intervalle ECG anormal, p. ex. des extrasystoles ou des battements cardiaques ectopiques
A61B 18/00 - Instruments, dispositifs ou procédés chirurgicaux pour transférer des formes non mécaniques d'énergie vers le corps ou à partir de celui-ci
H04N 19/20 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage d'objets vidéo
H04N 19/91 - Codage entropique, p. ex. codage à longueur variable ou codage arithmétique
66.
SILICON COMPATIBLE HIGH TEMPERATURE GALLIUM NITRIDE PROCESS
Described is a GaN fabrication process using titanium nitride (TiN) and tungsten (W) metallization optimized for high-temperature operation. An aluminum-free gate stack and backend process are disclosed. Ohmic contacts may be formed by a highly doped N+ GaN layer enabling low contact resistance with titanium nitride (TiN) and tungsten (W) metals. The gate metal thickness may be increased to counteract the higher resistivity of tungsten (W) compared to aluminum (Al). The resulting process uses only high melting point materials and is compatible with silicon carbide (SiC) or sapphire substrates for robust high-temperature GaN device performance.
H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p. ex. condensation
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
67.
METHOD FOR REDUCING INTERFERENCE EFFECTS IN A RADAR SYSTEM
The invention describes a method for reducing interference effects in a radar system, which has at least two transceiver units (S 1, S2), which are in particular spatially separated from one another, wherein the method comprises the following steps: —a transmission step (VS1), in which a first transmission signal (sigTX1) of the first transceiver unit (S1) is sent and received to and by a second transceiver unit (S2) and a second transmission signal (sigTX2) of the second transceiver unit (S2) is sent and received to and by the first transceiver unit (S 1) via a radio channel (T), wherein the transmission signals (sigTX1, sigTX2) are modulated according to an orthogonal frequency multiplex method; and—a pre-correction step (VS2), in which correction values (y1, yn, y2) are determined from the received transmission signals (sigTX1, sigTX2) and in particular are exchanged between the transceiver stations (S 1, S2), wherein the received transmission signals (sigRX1, sigRX2) are postprocessed on the basis of the correction values (y1, yn, y2), so that influences of interference variables, in particular of phase noise and/or a time offset and/or unknown initial phase positions, are reduced.
G01S 7/02 - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe
G01S 13/58 - Systèmes de détermination de la vitesse ou de la trajectoireSystèmes de détermination du sens d'un mouvement
G01S 13/90 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour la cartographie ou la représentation utilisant des techniques d'antenne synthétique
An integrated device package is disclosed. The integrated device package can include a substrate and one or more vertical interconnect arrays comprising a plurality of vertical interconnects in an array and a molding compound encapsulating the plurality of vertical interconnects. The molding compound can include a planar surface at a first end and a second end of the one or more vertical interconnect arrays. A first end and a second end of the plurality of vertical interconnects can be substantially co-planar with the molding compound at the first end and the second end of the one or more vertical interconnect arrays. The first end of the one or more vertical interconnect arrays can physically and electrically connected to a first side of the substrate and extend outwardly from the substrate.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01R 12/52 - Connexions fixes pour circuits imprimés rigides ou structures similaires se raccordant à d'autres circuits imprimés rigides ou à des structures similaires
H05K 1/11 - Éléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H05K 3/40 - Fabrication d'éléments imprimés destinés à réaliser des connexions électriques avec ou entre des circuits imprimés
Techniques for power inversion linearization are described. Specifically, in an example, a power inverter may identify a distortion in direct current (DC) to alternating current (AC) a power inversion. The power inverter may further determine a set of predistortion functions that linearizes an output AC current. The power inverter may further include apply the predistortion function to an input DC current to obtain the linearized output AC current.
H02M 7/5387 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs, p. ex. onduleurs à impulsions à un seul commutateur dans une configuration en pont
H02M 7/5395 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs, p. ex. onduleurs à impulsions à un seul commutateur avec commande automatique de la forme d'onde ou de la fréquence de sortie par modulation de largeur d'impulsions
H02M 1/00 - Détails d'appareils pour transformation
H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
70.
FINFET MULTI-DIODE THYRISTOR SWITCH FOR PROTECTING HIGH DATA RATE COMMUNICATION SYSTEM INTERFACES
FinFET multi-diode thyristor switches for protecting high data rate communication system interfaces are provided. In certain embodiments herein, high voltage tolerant FinFET thyristors are provided for handling high stress current and high RF power handling capability while providing low capacitance to allow wide bandwidth operation. Thus, the FinFET thyristors can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, while addressing tight radio frequency design window and robustness. In certain implementations, the FinFET thyristors include a first thyristor, a FinFET triggering circuitry and a second thyristor that serves to provide bidirectional blocking voltage and overstress protection. The FinFET triggering circuitry also enhances turn-on speed of the thyristor and/or reduces total on-state resistance.
H03K 17/081 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande
H10D 30/62 - Transistors à effet de champ à ailettes [FinFET]
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
71.
Low capacitance silicon controlled rectifier topology for overvoltage protection
Low capacitance silicon controlled rectifier (SCR) topologies for overvoltage protection are disclosed herein. In certain embodiments, an overvoltage protection circuit is connected between an RF signal pad and a ground signal pad. The overvoltage protection circuit includes a fin field-effect transistor (FinFET) SCR including a PNP bipolar transistor and an NPN bipolar transistor that are cross-coupled, a FinFET trigger circuit connected between an emitter of the PNP bipolar transistor and a base of the NPN bipolar transistor, and a linearity enhancement impedance connected between a reference voltage terminal and the emitter of the PNP bipolar transistor. In certain implementations, a FinFET diode is further included in series with the FinFET SCR with a cathode of the FinFET diode connected to the emitter of the PNP bipolar transistor.
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
An electronic assembly is disclosed. The electronic assembly can include a first integrated device package having a first substrate, a plurality of electronic components mounted to the first substrate, a first plurality of vertical interconnects connected to first substrate and extending outwardly, a first molding compound over at least portions of the plurality of electronic components, and an electromagnet connected to the first substrate. The electromagnet can be connected to the plurality of electronic components via one or more electrical connections. The electronic assembly can also include a second integrated device package having a second substrate, a second plurality of vertical interconnects connected to the second substrate, a second molding compound, and electrical terminals formed on a second side of the second substrate. The first and second vertical interconnects can be disposed between the first and second substrates.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
73.
BUFFER CIRCUIT WITH THRESHOLD VOLTAGE CANCELLATION
Various techniques are described to level shift an input signal from an input node to an output node of an open-loop voltage buffer circuit so that a DC offset voltage and a temperature-dependent voltage from the level shifter circuitry are mutually canceled out. By using these techniques, the output voltage of the buffer circuit tracks the input voltage with no DC offset voltage and no temperature drift.
Integrated circuits can include semiconductor devices with back-side field plates. The semiconductor devices can be formed on substrates that have conductive layers located within the substrates. The conductive layers can include at least one of a conducting material or a semi-conducting material that modifies an electric field produced by the semiconductor devices. The semiconductor devices can include one or more semiconductor layers that include one or more materials having a compound material that includes at least one Group 13 element and at least one Group 15 element.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
75.
PUSH-PULL MECHANISMS FOR HANDLING DATAFLOW BETWEEN CIRCUIT BLOCKS
Push-pull mechanisms for handling dataflow between circuit blocks are disclosed. In certain embodiments, a network of dataflow gaskets includes a source gasket coupled to a first circuit block and a destination gasket coupled to a second circuit block. The source gasket and the destination gasket are connected by a push mechanism that uses write channels to write data from the source gasket to the destination gasket, and a pull mechanism that uses read channels to read data from the source gasket to the destination gasket. The source gasket and the destination gasket can switch between a push mode and a pull mode to ease traffic based on data available to transfer at the source gasket and/or a space available to receive data in the destination gasket. For example, a transfer size register can be used to set a threshold to aid between the mode transitions.
Push-pull mechanisms for handling dataflow between circuit blocks are disclosed. In certain embodiments, a network of dataflow gaskets includes a source gasket coupled to a first circuit block and a destination gasket coupled to a second circuit block. The source gasket and the destination gasket are connected by a push mechanism that uses write channels to write data from the source gasket to the destination gasket, and a pull mechanism that uses read channels to read data from the source gasket to the destination gasket. The source gasket and the destination gasket can switch between a push mode and a pull mode to ease traffic based on data available to transfer at the source gasket and/or a space available to receive data in the destination gasket. For example, a transfer size register can be used to set a threshold to aid between the mode transitions.
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
G06F 15/82 - Architectures de calculateurs universels à programmes enregistrés commandés par des données ou à la demande
An analog-to-digital converter (ADC) system for switching between a first operating mode and a second operating mode, where both the first operating mode and the second operating mode can include post-calibration analog-to-digital conversions, where a hardware circuitry configuration of the second operating mode can differ from a hardware circuitry configuration of the first operating mode, can include hardware circuitry. The ADC system can also include a controller, which can be configured to control the hardware circuitry to control switching between the first operating mode and the second operating mode in response to a command to switch from the first operating mode to the second operating mode. This can include to transmit second mode configuration information and second mode calibration information to the hardware circuitry, where the second mode configuration information can include values to configure the hardware circuitry to operate in the second operating mode and the second mode calibration information can include values to calibrate the ADC system while operating in the second operating mode.
Gyroscopes with electrodes for tuning cross-axis sensitivity are disclosed. In certain embodiments, a MEMS gyroscope includes a resonator mass that moves in a first direction (for instance, x-direction), a sensing structure that detects a Coriolis effect in a second direction (for instance, y-direction), and a plurality of electrodes that control a cross-axis stiffness of the MEMS gyroscope by controlling motion of the resonator mass in a third direction (for instance, z-direction). For example, the electrodes can be used to reduce or eliminate cross-axis sensitivity arising from cross-axis stiffnesses, such as kxz (resonator-to-orthogonal) and/or kyz (Coriolis-to-orthogonal).
G01C 19/5712 - Dispositifs sensibles à la rotation utilisant des masses vibrantes, p. ex. capteurs vibratoires de vitesse angulaire basés sur les forces de Coriolis utilisant des masses entraînées dans un mouvement de rotation alternatif autour d'un axe les dispositifs comportant une structure micromécanique
Clips serving as vertical interconnect are disclosed herein. In certain embodiments, an electronic assembly such as an electronic module includes a first circuit board and an electronic component attached to the first circuit board. The electronic component includes a dielectric body and at least one clip secured to the dielectric body. The clip is electrically connected to the first circuit board to operate as vertical interconnect.
Systems and methods are provided for operating an electrolyzer. The systems and methods include operations comprising: determining that a first electrolytic cell in a first electrolyzer stack is associated with a first set of performance criteria that fails to satisfy one or more operating conditions; identifying a second electrolytic cell that is associated with a second set of performance criteria that satisfies the one or more operating conditions; and bypassing the first electrolytic cell and the second electrolytic cell in response to determining that the first electrolytic cell in the first electrolyzer stack is associated with the first set of performance criteria that fails to satisfy the one or more operating conditions and based on identifying the second electrolytic cell that is associated with the second set of performance criteria that satisfies the one or more operating conditions.
Aspects of the present disclosure relate to an inter-processor communication interface emulation configured to provide a user with a uniform emulation of an interface regardless of the hardware being emulated. In some examples, one or more processors may instantiate, via an emulation software, a first processor based on a first model. In some examples, the one or more processors may emulate a communication interface between the first processor and a second processor, the communication interface configured to model communication channels between the first processor and the second processor.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 13/10 - Commande par programme pour dispositifs périphériques
A low supply headroom bandgap voltage reference generation circuit for generating a bandgap reference voltage from a supply voltage can include a first delta base-to-emitter voltage generation circuit, which can include a first Darlington configuration of a first pair of transistors arranged in a differential pair with a second Darlington configuration of a second pair of transistors. A first input to the first Darlington pair of transistors can be connected to an output voltage node of the bandgap voltage reference generation circuit and a second input to the second Darlington pair of transistors can be connected to the output voltage node of the bandgap voltage reference generation circuit via a first delta base-to-emitter-voltage resistor.
G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
G05F 1/567 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p. ex. courant, tension, facteur de puissance pour compensation de température
G05F 3/30 - Régulateurs utilisant la différence entre les tensions base-émetteur de deux transistors bipolaires fonctionnant à des densités de courant différentes
83.
APPARATUS AND METHODS FOR AMPLIFIER INPUT-OVERVOLTAGE PROTECTION WITH LOW LEAKAGE CURRENT
Apparatus and methods for amplifier input-overvoltage protection with low leakage current are provided herein. In certain embodiments, amplifier input circuitry for an amplifier includes a pair of input terminals, a pair of input transistors each having a control input (for instance, a transistor gate), a pair of protection transistors each connected between one of the input terminals and the control input of a corresponding one of the input transistors, and a bidirectional clamp connected between the control inputs of the input transistors. Implementing the amplifier input circuitry in this manner provides a number of advantages including, but not limited to, robust protection against input overvoltage and low input-leakage current.
H03F 1/52 - Circuits pour la protection de ces amplificateurs
H02H 3/20 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion sensibles à un excès de tension
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
84.
TECHNIQUES FOR IMPLEMENTING TRUSTED BINARIES FOR MICROCONTROLLERS
Techniques for implementing trusted binaries for microcontrollers are provided. In one aspect, a security partitioned microcontroller includes a primary processor, a co-processor, and a memory segmented into a trusted portion and a non-trusted portion. The co-processor is configured to in response to booting the security partitioned microcontroller, scan the trusted portion of the memory for a first set of instructions, and allow the primary processor to boot in response to determining that the first set of instructions is present in the trusted portion of the memory.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
85.
LOW LATENCY AUTOMATIC CROSS TALK CANCELLATION FOR LED-BASED SENSORS
Aspects of the present disclosure provide methods and apparatuses for operating an analog-to-digital converter. A method in accordance with an aspect of the present disclosure may comprise initializing a digital-to-analog converter (DAC) value of a DAC, determining whether an analog-to-digital converter (ADC) operates within a predetermined range based on an input to the DAC, initiating a conversion at a first ADC resolution when the ADC is operating within the predetermined range, and incrementally changing the DAC value when the ADC is not operating within the predetermined range.
Described herein are electrochemical impedance spectroscopy (EIS) systems and methods that facilitate the allocation of a single stimulus generator across a number of electrolyzer stacks, each comprising a set of electrochemical cells. By distributing a stimulus signal, impedance data of the cells in each electrolyzer stack may be measured, e.g., to evaluate their condition or the condition of the stack without the need for separate stimulus blocks for each electrolyzer stack. In various embodiments, sharing the stimulus generator is enabled by sequentially directing stimulus signals to different stacks. The resulting response signals, indicative of the impedance of cells or entire stacks, are processed locally at each respective electrolyzer stack. Advantageously, the stimulus generator may be remotely located, e.g., at a location that is subject to less stringent safety measures, thereby lowering both equipment and operational expenses.
A capacitive load, an inductive load, or a transmission line coupled to an output of a closed-loop amplifier circuit can cause undesirable oscillations in a feedback signal of the amplifier circuit. The oscillations in the feedback signal can cause the amplifier circuit to exhibit instability and unpredictable behavior. Techniques are described that allow an amplifier circuit to provide a stable response while driving a capacitive load.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/52 - Circuits pour la protection de ces amplificateurs
H03F 3/193 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
H03F 3/60 - Amplificateurs dans lesquels les réseaux de couplage ont des constantes réparties, p. ex. comportant des résonateurs de guides d'ondes
88.
APPARATUSES AND METHODS FOR GENERATING PSEUDO-RANDOM NUMBER
Aspects of the present disclosure include a multiplexer having a plurality of input terminals each configured to receive a corresponding input value of a plurality of input values, an output terminal configured to output an output value of a white pseudo-random sequence and provide a delayed output value into a feedback loop, a feedback input terminal configured to receive a feedback value via the feedback loop, wherein the feedback value is the product of the delayed output value and a first value of a first pseudo-random sequence, and a select terminal configured to receive a second value of a second pseudo-random sequence and select, based on the second value, one of a combination of the plurality of input terminals and the feedback input terminal.
An electronic assembly is disclosed. The electronic assembly can include an assembly substrate of one or more electrical connections and an electronic device mounted to a first surface of the assembly substrate. The electronic device can include a plurality electronic modules mounted on and electrically connected to a first surface of a device substrate. The device substrate can have one or more traces. The electronic device can further include a busbar having a first portion extending along at least a portion of a lateral dimension of the substrate and a second portion having at least two fins extending non-parallel and away from the first portion and between the plurality of electronic modules to electrically and mechanically connect to the one or more traces disposed on the first surface of the substrate. The one or more fins can include a thermal conductive material.
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
An electronic assembly is disclosed. The electronic assembly can include an assembly substrate of one or more electrical connections and an electronic device mounted to a first surface of the assembly substrate. The electronic device can include a plurality electronic modules mounted on and electrically connected to a first surface of a device substrate. The device substrate can have one or more traces. The electronic device can further include a busbar having a first portion extending along at least a portion of a lateral dimension of the substrate and a second portion having at least two fins extending non-parallel and away from the first portion and between the plurality of electronic modules to electrically and mechanically connect to the one or more traces disposed on the first surface of the substrate. The one or more fins can include a thermal conductive material.
In an aspect, a system and method are provided for witness integrity sensing. In an aspect, the system includes structural integrity sensing elements and edge modules. Each of the edge modules is connected to a respective structural integrity sensing element. The system further includes an interface unit having a host interface side and a network interface side. The network interface side is configured to collect daisy chain sensing network data and selectively power respective structural integrity sensing elements, through selective ones of the plurality of edge modules. The system also includes a daisy-chain communication link connecting the interface unit to each of the edge modules in series, wherein each of the edge modules transmits a respective data signal to the interface unit, and wherein the daisy-chain communication link ends at a network terminator.
An integrated electronic module assembly may include a substrate comprising conductive regions on opposite surfaces of the substrate and a laminated bridge assembly. The laminated bridge assembly may include a dielectric material, the dielectric material forming a planar region and respective legs defining a cavity region, the respective legs including at least one respective inter-layer interconnection. The laminated bridge assembly may also include a conductive layer, the conductive layer defining at least one respective pad region electrically coupled to the at least one respective inter-layer interconnection. The laminated bridge assembly may be electrically and mechanically coupled to the substrate, the substrate including a first surface including a respective conductive region to which the at least one respective inter-layer interconnection is electrically coupled and an opposite second surface including respective conductive regions forming terminals of the integrated electronic module assembly.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
93.
BIDIRECTIONAL INTEGRATED LOW TEMPERATURE COEFFICIENT CURRENT SENSOR
This disclosure describes various bidirectional current sensing techniques. The solution described utilizes a matched thermal substrate, e.g., copper, in conjunction with the front two amplifiers of a three amplifier instrumentation amplifier. The bidirectional system current sensor module described utilizes the matched thermal substrate approach to cancel out temperature coefficient dependency in the sensor. Behind the lead two amplifiers, the circuits can be varied to support factory gain trim and voltage or current mode type outputs.
Described are techniques to provide a gain trim term in the numerator for a current sensor control loop. In this manner, a linear gain trim relationship is created with respect to the trim code. This linear relationship reduces the dynamic range needed for the DAC, which allows the use of lower resolution DACs to smoothly adjust the gain while maintaining stability and accuracy.
G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
Circuitry and measurement approaches are described herein that can be used to reduce or suppress sensitivity to variation of sensor properties or characteristics over time for a respective monolithically integrated resistive temperature sensor. Such measurement approaches can also help to suppress measurement variations between sensors, such as to provide stable temperature measurement characteristics across locations and over time for the respective different temperature measurement sites on or within the integrated circuit package. The approaches described herein can also reduce or suppress sensitivity to variation in excitation source characteristics, such as using a relative indication (e.g., a ratio) of measured signal values corresponding to a respective temperature sensor and a co-integrated reference device. Calibration or absolute temperature measurements can be performed, such as using an off-chip (e.g., off-die or off-package) calibration reference. The off-chip calibration reference can be used to establish calibration data for other measurements.
G01K 7/20 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments résistifs l'élément étant une résistance linéaire, p. ex. un thermomètre à résistance de platine dans un circuit spécialement adapté, p. ex. un circuit en pont
G01K 1/02 - Moyens d’indication ou d’enregistrement spécialement adaptés aux thermomètres
G01K 7/18 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments résistifs l'élément étant une résistance linéaire, p. ex. un thermomètre à résistance de platine
96.
Coarse floating point accumulator circuit, and MAC processing pipelines including same
An integrated circuit including a multiplier-accumulator circuit pipeline including a plurality of MAC circuits. Each MAC circuit includes: (A) a multiplier circuit to multiply first input data and filter weight data to generate and output first product data having a floating point data format, and (B) a coarse floating point accumulator circuit including: (1) an alignment shift circuit to shift at least one field of the first product data and generate shifted first product data, and (2) fixed point addition circuitry, coupled to the alignment shift circuit, to add second input data and the shifted first product data using the fixed point addition circuitry. The plurality of MAC circuits of the multiplier-accumulator circuit execution pipeline, in operation, each perform a plurality of multiply operations and accumulate operations to process the first input data and generate processed data therefrom.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p. ex. la justification, le changement d'échelle, la normalisation
G06F 7/509 - AdditionSoustraction en mode parallèle binaire, c.-à-d. ayant un circuit de maniement de chiffre différent pour chaque position pour opérandes multiples, p. ex. intégrateurs numériques
97.
MICROELECTROMECHANICAL SYSTEMS (MEMS) AND RELATED PACKAGES
Compact packages including microelectromechanical system (MEMS) devices and multiple application specific integrated circuits (ASICs) are described. These packages are sufficiently small to be applicable to contexts in which space requirements are particularly strict, such as in consumer electronics. These packages involve vertical die stacks. A first ASIC may be positioned on one side of the die stack and another ASIC may be positioned on the other side of the die stack. A die including a MEMS device (e.g., an accelerometer, gyroscope, switch, resonator, optical device) is positioned between the ASICs. Optionally, an interposer serving as cap substrate for the MEMS device is also positioned between the ASICs. In one example, a package of the types described herein has an extension of 2 mm×2 mm in the planar axes and less than 500-800 μm in height.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
98.
APPARATUS AND METHODS FOR GYROSCOPE SIGNAL DEMODULATION
Apparatus and methods for gyroscope signal demodulation are disclosed herein. In certain embodiments, a demodulation circuit for a microelectromechanical systems (MEMS) gyroscope includes a switched resistor filter that samples a gyroscope signal received from a microelectromechanical sensor. The switched resistor filter provides sampling with a controlled duty cycle and noise bandwidth limit to achieve high signal-to-noise ratio (SNR) performance.
Aspects of this disclosure relate to energy efficient wireless communications. Data can be wirelessly transmitted from a phased antenna array and antenna elements of the phased antenna array can be dynamically activated and/or deactivated. In certain embodiments, the antenna elements can be activated based on range and/or environmental condition(s), such as interference and/or range. As the number of active antenna elements changes, relatively low spectral efficiency and a relatively low peak to average power ratio can be maintained.
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H01Q 3/24 - Dispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier l'orientation, par commutation de l'énergie fournie, d'un élément actif rayonnant à un autre, p. ex. pour commutation du lobe
100.
IMPURITY REDUCTION TECHNIQUES IN GALLIUM NITRIDE REGROWTH
Various techniques for impurity dopant reduction in GaN regrowth are described. In a first technique, a barrier layer, such as AlN, can be formed at a regrowth interface before the regrown GaN layer. The barrier layer can bury the impurities at the regrowth interface and reduce their effect on the layers above that include the channel of the device, e.g., transistor. In a second technique, a buffer layer, such as a carbon-doped GaN layer, can be formed at the regrowth interface before the regrown GaN layer. Carbon can act as an acceptor to compensate for the dopants. e.g., silicon, and cancel their electronic effect on the above layers. In a third technique, a hydrogen bake treatment can be performed before the GaN regrowth. Hydrogen can desorb a thin layer of GaN at the regrowth interface, which is the GaN layer with the highest concentration of impurities.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
