BAE Systems Information and Electronic Systems Integration Inc.

États‑Unis d’Amérique

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Type PI
        Brevet 1 787
        Marque 34
Juridiction
        États-Unis 1 275
        International 513
        Canada 30
        Europe 3
Date
Nouveautés (dernières 4 semaines) 11
2025 juillet (MACJ) 4
2025 juin 12
2025 mai 7
2025 avril 7
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Classe IPC
F41G 7/22 - Systèmes autodirecteurs 57
H04K 3/00 - Brouillage de la communicationContre-mesures 35
F42B 15/01 - Dispositions pour le guidage ou le pilotage sur les projectiles autopropulsés ou les missiles 34
H04N 5/33 - Transformation des rayonnements infrarouges 32
F41G 7/00 - Systèmes de commande de guidage pour missiles autopropulsés 30
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Classe NICE
09 - Appareils et instruments scientifiques et électriques 27
12 - Véhicules; appareils de locomotion par terre, par air ou par eau; parties de véhicules 4
40 - Traitement de matériaux; recyclage, purification de l'air et traitement de l'eau 3
42 - Services scientifiques, technologiques et industriels, recherche et conception 3
16 - Papier, carton et produits en ces matières 2
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Statut
En Instance 151
Enregistré / En vigueur 1 670
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1.

GEODETIC FRAME KALMAN FILTER FOR TARGET GEOLOCATION AND TRACKING

      
Numéro d'application 17497404
Statut En instance
Date de dépôt 2021-10-08
Date de la première publication 2025-07-10
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Slocum, Dean C.

Abrégé

Techniques are provided for geolocation and tracking of a target emitter. A methodology implementing the techniques according to an embodiment includes receiving measurement data associated with a signal from an emitter, and receiving an estimated uncertainty associated with the measurement data. The measurement data may be provided, for example, by a radar receiver. The method further includes employing a Kalman filter to calculate a geolocation of the emitter, based on the measurement data and the estimated uncertainty. The calculation includes constraining the geolocation of the emitter to the surface of the Earth, for example in a geodetic coordinate system. The measurement data may include azimuth angle of arrival of the signal and depression angle of arrival of the signal or a time difference of arrival of the signal between two measurement platforms. The methodology may be carried out, for instance, onboard an aircraft, projectile, or missile.

Classes IPC  ?

  • G01S 5/02 - Localisation par coordination de plusieurs déterminations de direction ou de ligne de positionLocalisation par coordination de plusieurs déterminations de distance utilisant les ondes radioélectriques

2.

SIMULATING RADIO FREQUENCY SIGNALS RECEIVED BY A SIMULATED ANTENNA ARRAY ON A SIMULATED PLATFORM

      
Numéro d'application 18406619
Statut En instance
Date de dépôt 2024-01-08
Date de la première publication 2025-07-10
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Fehling, Greg M.
  • Muller, Christopher M.
  • Sherman, Christopher J.
  • Alcutt, Frank

Abrégé

A method to simulate radio frequency (RF) signals generated by one or more simulated antennas of a simulated platform is disclosed. The method includes receiving emitter parameters of a plurality of simulated emitters, the emitter parameters including geolocation of at least one of the simulated emitters. The method further includes receiving navigational parameters of the simulated platform, which are indicative of a simulated navigational path of the simulated platform relative to one or more of the plurality of simulated emitters. The method further includes receiving antenna parameters of a simulated antenna located on the simulated platform. The method further includes generating digital data representative of a RF signal that is estimated to be output by the simulated antenna during simulated traversal of the simulated platform along the navigational path, based on the simulated antenna receiving, in a simulated environment, signals from one or more of the plurality of simulated emitters.

Classes IPC  ?

  • H04B 17/391 - Modélisation du canal de propagation
  • H04B 17/00 - SurveillanceTests
  • H04B 17/13 - SurveillanceTests d’émetteurs pour l’étalonnage d’amplificateurs de puissance, p. ex. de gain ou de non-linéarité

3.

HIGH-PRECISION INFANTRY TRAINING SYSTEM (HITS)

      
Numéro d'application 17501824
Statut En instance
Date de dépôt 2021-10-14
Date de la première publication 2025-07-10
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Delmarco, Stephen P.
  • Bortolami, Simone B.
  • Webb, Helen F.

Abrégé

A method of determining a point-of-impact of a ballistic projectile comprising: within a predetermined site using a weapon comprising a barrel, a camera, and an IMU configured to provide data concerning barrel attitude: detecting a firing event associated with the weapon; obtaining metadata associated with the weapon; determining estimated pointing angles of the weapon; obtaining a reference image of the site; culling portions of the reference image not associated with the estimated pointing angles, creating a culled reference image; projecting the culled reference image onto an image plane; obtaining an image from the weapon-mounted camera, the image being centered on the pointing direction weapon at the time of firing; registering the image from the weapon-mounted camera with the culled reference image; and calculating the true pointing angles of the weapon based on the alignment of the image obtained by the weapon-mounted camera with the culled reference image.

Classes IPC  ?

  • F41G 3/14 - Dispositifs de tir indirect
  • F41G 3/26 - Appareils d'instruction ou d'entraînement pour le pointage

4.

SYSTEM AND METHOD FOR TARGETING FROM 3D DIGITAL SURFACE MODELS AND DIGITAL POINT POSITIONING DATABASE CONTROLLED STEREO IMAGERY

      
Numéro d'application US2024040263
Numéro de publication 2025/144470
Statut Délivré - en vigueur
Date de dépôt 2024-07-31
Date de publication 2025-07-03
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Devenecia, Kurt J.
  • Withee, Brett A.

Abrégé

A computer program product and corresponding method for targeting one or more points in a three dimensional (3D) model is provided. The computer program product including least one non-transitory computer readable storage medium in operative communication with a computer processing unit (CPU), the storage medium having instructions stored thereon that, when executed by the CPU, implement a process to register the 3D model with a stereoscopic image pair. The steps performed include inputting a first image and a second image that define a stereoscopic image pair into an object targeting program, wherein an object is shown in the first image and the second image, inputting a three dimensional (3D) model of the object into the object targeting program, registering the 3D model to the stereoscopic image pair, and targeting a point associated with or near the object based on the 3D model having been registered to the stereoscopic image pair.

Classes IPC  ?

  • G06T 7/33 - Détermination des paramètres de transformation pour l'alignement des images, c.-à-d. recalage des images utilisant des procédés basés sur les caractéristiques
  • G06T 7/60 - Analyse des attributs géométriques

5.

AUTOMATIC DETERMINATION OF THE PRESENCE OF BURN-IN OVERLAY IN VIDEO IMAGERY

      
Numéro d'application 18537994
Statut En instance
Date de dépôt 2023-12-13
Date de la première publication 2025-06-19
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Ramakrishnan, Sowmya
  • Chen, Wesley
  • Shorter, Francis G.
  • Jobe, Robert T.

Abrégé

Systems, methods and computer systems for the automatic determination of presence or absence of burn-in overlay data are provided. The systems, methods, and computer systems implement mask generation, edge detection, feature vector generation methods that are combined with machine learning classifiers to rapidly and automatically determine the presence or absence of burn-in overlays in the image for the purpose of removal or other forms to obfuscate burn-in overlay data so as to maintain confidential or classified information while allowing for the release of remaining image data.

Classes IPC  ?

  • G06T 5/77 - RetoucheRestaurationSuppression des rayures
  • G06T 7/00 - Analyse d'image
  • G06T 7/13 - Détection de bords
  • G06T 7/136 - DécoupageDétection de bords impliquant un seuillage
  • G06V 10/44 - Extraction de caractéristiques locales par analyse des parties du motif, p. ex. par détection d’arêtes, de contours, de boucles, d’angles, de barres ou d’intersectionsAnalyse de connectivité, p. ex. de composantes connectées
  • G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p. ex. des objets vidéo
  • G06V 10/77 - Traitement des caractéristiques d’images ou de vidéos dans les espaces de caractéristiquesDispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p. ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]Séparation aveugle de source

6.

RANDOM-ACCESS MEMORY SCRUBBING

      
Numéro d'application 18538482
Statut En instance
Date de dépôt 2023-12-13
Date de la première publication 2025-06-19
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Moser, David D.
  • Stanley, Daniel L.
  • Brown, Gregory B.

Abrégé

A memory device includes a memory module having a plurality of memory cells, a read port, a write port, and an output port; a first multiplexer having a functional read input, a scrub read input, a scrub read enable input, and a read request output, the read request output coupled to the read port; a second multiplexer having a functional write input, a scrub write input, a scrub write enable input, and a write request output, the write request output coupled to the write port; and a logic circuit configured to scrub, via the scrub write input, at least one of the memory cells based on the scrub read input while the scrub read enable input and/or the scrub write enable input are asserted.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectationRéadressage

7.

AUTOMATIC DETERMINATION OF THE PRESENCE OF BURN-IN OVERLAY IN VIDEO IMAGERY

      
Numéro d'application US2024059149
Numéro de publication 2025/128466
Statut Délivré - en vigueur
Date de dépôt 2024-12-09
Date de publication 2025-06-19
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Ramakrishnan, Sowmya
  • Chen, Wesley
  • Shorter, Francis G.
  • Jobe, Robert T.

Abrégé

Systems, methods and computer systems for the automatic determination of presence or absence of burn-in overlay data are provided. The systems, methods, and computer systems implement mask generation, edge detection, feature vector generation methods that are combined with machine learning classifiers to rapidly and automatically determine the presence or absence of burn-in overlays in the image for the purpose of removal or other forms to obfuscate burn-in overlay data so as to maintain confidential or classified information while allowing for the release of remaining image data.

Classes IPC  ?

  • G06V 30/18 - Extraction d’éléments ou de caractéristiques de l’image
  • G06T 5/00 - Amélioration ou restauration d'image
  • G06V 30/148 - Découpage de zones de caractères
  • G06T 7/11 - Découpage basé sur les zones
  • G06V 10/26 - Segmentation de formes dans le champ d’imageDécoupage ou fusion d’éléments d’image visant à établir la région de motif, p. ex. techniques de regroupementDétection d’occlusion
  • G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p. ex. des objets vidéo
  • G06V 20/40 - ScènesÉléments spécifiques à la scène dans le contenu vidéo
  • G06V 30/19 - Reconnaissance utilisant des moyens électroniques
  • H04N 5/21 - Circuits pour la suppression ou la diminution de perturbations, p. ex. moiré ou halo
  • G06N 3/02 - Réseaux neuronaux
  • G06V 30/16 - Prétraitement de l’image

8.

RANDOM-ACCESS MEMORY SCRUBBING

      
Numéro d'application US2024059157
Numéro de publication 2025/128471
Statut Délivré - en vigueur
Date de dépôt 2024-12-09
Date de publication 2025-06-19
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Moser, David D.
  • Stanley, Daniel L.
  • Brown, Gregory B.

Abrégé

A memory device includes a memory module having a plurality of memory cells, a read port, a write port, and an output port; a first multiplexer having a functional read input, a scrub read input, a scrub read enable input, and a read request output, the read request output coupled to the read port; a second multiplexer having a functional write input, a scrub write input, a scrub write enable input, and a write request output, the write request output coupled to the write port; and a logic circuit configured to scrub, via the scrub write input, at least one of the memory cells based on the scrub read input while the scrub read enable input and/or the scrub write enable input are asserted.

Classes IPC  ?

  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
  • G06F 12/02 - Adressage ou affectationRéadressage
  • G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire

9.

TWO-PIECE SEPARABLE WEDGE CLAMP FOR THERMAL MECHANICAL INTERFACE

      
Numéro d'application 18536881
Statut En instance
Date de dépôt 2023-12-12
Date de la première publication 2025-06-12
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Thoman, Jr., Edward
  • Riley, Richard A.
  • Phillips, Frank D.

Abrégé

A wedge clamp assembly includes a first wedge plate including a first planar surface, and a first sawtooth surface opposite the first planar surface. The first wedge plate is configured to be fixed with respect to an electronics module. The first sawtooth surface includes two or more inclined faces with respect to the first planar surface. The wedge clamp assembly further includes a second wedge plate including a second planar surface and a second sawtooth surface opposite the second planar surface. The second wedge plate is adjustable with respect to the first wedge plate. The second sawtooth surface includes two or more inclined faces with respect to the second planar surface. An angle of incline of the inclined faces of the first sawtooth surface is equal to or substantially equal to an angle of incline of the inclined faces of the second sawtooth surface.

Classes IPC  ?

  • H05K 7/14 - Montage de la structure de support dans l'enveloppe, sur cadre ou sur bâti
  • F16B 2/14 - Brides ou colliers, c.-à-d. dispositifs de fixation dont le serrage est effectué par des forces effectives autres que la résistance à la déformation inhérente au matériau dont est fait le dispositif utilisant des coins

10.

REDUCED LATENCY LOOK-AHEAD FOR SIGNAL DETECTOR

      
Numéro d'application 18535177
Statut En instance
Date de dépôt 2023-12-11
Date de la première publication 2025-06-12
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Lavery, Richard J.
  • Ladubec, Jr., Peter

Abrégé

Techniques are provided for reduced latency look-ahead for signal detection. An example methodology implementing the techniques according to an embodiment includes down converting a digitized signal to a first baseband signal at a first decimation rate such that the first baseband signal is provided at a first latency with a first signal to noise ratio (SNR) based on the first decimation rate. The method also includes down converting the digitized signal to a second baseband signal at a second decimation rate, greater than the first decimation rate, such that the second baseband signal is provided at a second latency with a second SNR based on the second decimation rate, the second latency greater than the first latency and the second SNR greater than the first SNR. The method continues with generating a detection threshold based on the first baseband signal prior to completion of the second baseband signal generation.

Classes IPC  ?

  • G01S 7/292 - Récepteurs avec extraction de signaux d'échos recherchés

11.

VEHICLE BASED THREAT DETECTION AND TRACKING WITH LWIR VIDEO

      
Numéro d'application US2024058215
Numéro de publication 2025/122471
Statut Délivré - en vigueur
Date de dépôt 2024-12-03
Date de publication 2025-06-12
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s) Louchard, Eric M.

Abrégé

A computer program product interacts with machine-readable mediums with instructions for automated target recognition. It captures a video of a specified region using detectors on a vehicle. Raw image frames from the video undergo pre-processing, followed by feeding through long and short-range target detection pipelines. Image frames are downscaled in the short-range pipeline, generating image windows and applying a trained convolutional neural network (CNN). Full resolution and non-redundant image chips are created. Detection region of interest (ROI) proposal lists are generated and analyzed with the CNN, producing frame detection lists with detected targets. These lists are stacked and processed using a multi-target Kalman filter, ultimately creating a track list of targets for monitoring.

Classes IPC  ?

  • G06V 10/25 - Détermination d’une région d’intérêt [ROI] ou d’un volume d’intérêt [VOI]
  • G06T 7/73 - Détermination de la position ou de l'orientation des objets ou des caméras utilisant des procédés basés sur les caractéristiques
  • G06V 10/77 - Traitement des caractéristiques d’images ou de vidéos dans les espaces de caractéristiquesDispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p. ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]Séparation aveugle de source
  • G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
  • G06N 20/00 - Apprentissage automatique
  • G01J 5/00 - Pyrométrie des radiations, p. ex. thermométrie infrarouge ou optique
  • G06V 10/00 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos

12.

INTERPOSER MODULE FOR IMPLEMENTING DENSELY PITCHED INTEGRATED CIRCUITS ON CONVENTIONAL MOTHERBOARDS

      
Numéro d'application 18524300
Statut En instance
Date de dépôt 2023-11-30
Date de la première publication 2025-06-05
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Kraemer, Andrew M.
  • Campbell, Nicholas L.
  • Bassett, Kevin S.
  • Disalvo, Peter

Abrégé

An interposer module incorporates at least one flip-chip or other densely pitched IC (DP-chip) into a motherboard assembly without placing undue requirements on the motherboard. The interposer module includes a rigid, densely pitched, multilayer circuit card having an interconnection array for attachment of the DP-chip interconnection points, and a mezzanine connector for removable mating to a compatible motherboard interconnector. Clusters of power connections, clusters of differential pairs of high frequency connections, and clusters of low frequency control connections and/or differential pairs of clock connections are each surrounded and isolated by ground connections. A compartment cover having a lid and isolating dividers can be placed over the DP-chip to isolate high frequency areas of the module from each other and from other RF sensitive areas. Thermally conductive material can extend from the cover lid to the DP-chip, and a cooling fan can circulate air past cooling fingers extending from the lid.

Classes IPC  ?

  • H01R 12/71 - Dispositifs de couplage pour circuits imprimés rigides ou structures similaires
  • H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
  • H01L 23/498 - Connexions électriques sur des substrats isolants
  • H01R 12/75 - Dispositifs de couplage pour circuits imprimés rigides ou structures similaires se raccordant à des câbles à l'exclusion des câbles plats ou à rubans
  • H01R 43/26 - Appareils ou procédés spécialement adaptés à la fabrication, l'assemblage, l'entretien ou la réparation de connecteurs de lignes ou de collecteurs de courant ou pour relier les conducteurs électriques pour engager ou séparer les deux pièces d'un dispositif de couplage

13.

BREAKOUT CONNECTOR PLATFORM FOR INTERPOSER MODULES THAT IMPLEMENT DENSELY PITCHED INTEGRATED CIRCUITS ON CONVENTIONAL MOTHERBOARDS

      
Numéro d'application 18524667
Statut En instance
Date de dépôt 2023-11-30
Date de la première publication 2025-06-05
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Kraemer, Andrew M.
  • Campbell, Nicholas L.
  • Bassett, Kevin S.
  • Disalvo, Peter

Abrégé

A breakout connector platform (BCP) increases the number of signals that can be exchanged with a densely pitched integrated circuit (DP-chip), such as a flip-chip, attached to an interposer module. The BCP is connected with the interposer module via mezzanine connectors, and includes breakout connectors and other connectors required for testing and operation of the DP-chip, including power, ground, and/or clock connectors. Mezzanine connections are arranged so that clusters of power connections, clusters of differential pairs of high frequency connections, and clusters of lower frequency control connections and/or differential pairs of clock connections are surrounded by ground connections. High frequency traces on the BCP are arranged as differential pairs. A plurality of interposer modules can be supported by the BCP. The interposer module can also include breakout connectors and/or a cover with cooling fan. Secondary mezzanine connectors can enable mounting of the BCP to an underlying motherboard.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
  • H01R 12/70 - Dispositifs de couplage
  • H01R 12/71 - Dispositifs de couplage pour circuits imprimés rigides ou structures similaires

14.

VEHICLE BASED THREAT DETECTION AND TRACKING WITH LWIR VIDEO

      
Numéro d'application 18528217
Statut En instance
Date de dépôt 2023-12-04
Date de la première publication 2025-06-05
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Louchard, Eric M.

Abrégé

A computer program product interacts with machine-readable mediums with instructions for automated target recognition. It captures a video of a specified region using detectors on a vehicle. Raw image frames from the video undergo pre-processing, followed by feeding through long and short-range target detection pipelines. Image frames are downscaled in the short-range pipeline, generating image windows and applying a trained convolutional neural network (CNN). Full resolution and non-redundant image chips are created. Detection region of interest (ROI) proposal lists are generated and analyzed with the CNN, producing frame detection lists with detected targets. These lists are stacked and processed using a multi-target Kalman filter, ultimately creating a track list of targets for monitoring.

Classes IPC  ?

  • G06T 7/292 - Suivi à plusieurs caméras
  • G06T 7/246 - Analyse du mouvement utilisant des procédés basés sur les caractéristiques, p. ex. le suivi des coins ou des segments
  • G06T 7/277 - Analyse du mouvement impliquant des approches stochastiques, p. ex. utilisant des filtres de Kalman
  • G06T 7/55 - Récupération de la profondeur ou de la forme à partir de plusieurs images
  • G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
  • G06V 20/40 - ScènesÉléments spécifiques à la scène dans le contenu vidéo
  • G06V 20/52 - Activités de surveillance ou de suivi, p. ex. pour la reconnaissance d’objets suspects

15.

RISLEY PRISM OPTICAL POINTING CONTROLLER

      
Numéro d'application 18526154
Statut En instance
Date de dépôt 2023-12-01
Date de la première publication 2025-06-05
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Jordan, David B.
  • Kingston, James L.
  • Caseley, Clifford D.

Abrégé

A controller applies iterative ray tracing and root finding to determine an orientation difference Δθd of Risley Prism Assembly (RPA) prism elements required to provide a desired light refraction angle γd. In each iteration, a linear approximation is applied between lower and upper angle difference limits to determine an approximate value Δθa, and ray tracing is applied to determine a corresponding refraction angle γa. Depending on whether γa is greater than or less than γd, the upper or lower angle difference limit is reset to Δθa, and the process continues until convergence. Ray tracing also determines an angular rotation ϕa of a refracted beam about the rotation axis at Δθd, and the orientations of the prism elements are adjusted to provide a desired pointing direction γd, ϕd according to Δθd, ϕd, and ϕa. Prism element imperfections are accommodated in the ray tracing.

Classes IPC  ?

  • G02B 26/08 - Dispositifs ou dispositions optiques pour la commande de la lumière utilisant des éléments optiques mobiles ou déformables pour commander la direction de la lumière
  • G02B 27/00 - Systèmes ou appareils optiques non prévus dans aucun des groupes ,

16.

BACKSCAN STEP-AND-STARE RISLEY PRISM OPTICAL POINTING SYSTEM

      
Numéro d'application 18526203
Statut En instance
Date de dépôt 2023-12-01
Date de la première publication 2025-06-05
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Jordan, David B.
  • Tarud, Diana
  • Kingston, James L.
  • Caseley, Clifford D.

Abrégé

An apparatus and method of step-scanning frames in a field of interest (FOI) includes continuously rotating prism elements of a Risley prism assembly (RPA) while periodically rotating and resetting a fast-steering mirror (FSM) to provide static pointing during each frame. A gain factor is calculated for each frame according to actual and hypothetical prism element orientations and ray tracing, and the RPA and/or FSM rotation rates and FSM timing are adjusted accordingly. In embodiments, light from the frames is directed to a camera, and the RPA and/or FSM rotation rates and timing are adjusted to maintain adjacent frames with minimum overlap. Calculating the gain factor can include calculating hypothetical prism element rotations by a ray trace and root finding method of false position. The RPA can be achromatic. Step-scanning can be at a constant rate. Frames can be of equal duration, or of durations proportionate to their sizes.

Classes IPC  ?

  • G02B 26/08 - Dispositifs ou dispositions optiques pour la commande de la lumière utilisant des éléments optiques mobiles ou déformables pour commander la direction de la lumière
  • G02B 26/10 - Systèmes de balayage
  • G02B 27/20 - Systèmes ou appareils optiques non prévus dans aucun des groupes , pour projection optique, p. ex. combinaison de miroir, de condensateur et d'objectif pour donner une image d'objets minuscules, p. ex. indicateur lumineux

17.

AUTOMATIC INTEGRATION AND READOUT GAIN READ OUT INTEGRATED CIRCUIT (ROIC)

      
Numéro d'application 18840208
Statut En instance
Date de dépôt 2022-02-25
Date de la première publication 2025-05-22
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Hairston, Allen W.
  • Dimitrov, Dimitre P.

Abrégé

A system for imaging includes both integration time gain and readout gain. It has a plurality of pixels comprising a frame, each pixel has a direct injection input with two Sample-and-Holds (SHs); a short integration time output; and a long integration time output. The integration time gain extends the range to higher fluxes with shorter integration times. A Read Out Integrated Circuit (ROIC) includes at least one column cell having a gain selection component where each of the short integration time output and the long integration time output are compared to a threshold, producing gain bits and an Analog to Digital Converter (ADC) producing data bits.

Classes IPC  ?

  • H04N 25/78 - Circuits de lecture pour capteurs adressés, p. ex. amplificateurs de sortie ou convertisseurs A/N
  • G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
  • H04N 25/589 - Commande de la gamme dynamique impliquant plusieurs expositions acquises de manière séquentielle, p. ex. en utilisant la combinaison de champs d'image pairs et impairs avec des temps d'intégration différents, p. ex. des expositions courtes et longues
  • H04N 25/778 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des amplificateurs partagés entre une pluralité de pixels, c.-à-d. qu'au moins une partie de l'amplificateur doit se trouver sur la matrice de capteurs elle-même

18.

System and method for clutter suppression

      
Numéro d'application 17851547
Numéro de brevet 12299952
Statut Délivré - en vigueur
Date de dépôt 2022-06-28
Date de la première publication 2025-05-13
Date d'octroi 2025-05-13
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Wallace, Jeffrey A.

Abrégé

The system and method described herein utilizes spectral data, spatial data, and temporal data, simultaneously, to provide an improved clutter suppression technique to provide an improved output for feeding into an object detection protocol. This clutter suppression technique that uses spectral data, spatial data, and temporal data, simultaneously, results in improved processing capabilities by reducing the amount of processing power needed to obtain the resultant output. The present disclosure utilizes particular protocols and processes to effectuate the usage and processing of spectral data, spatial data, and temporal data, simultaneously.

Classes IPC  ?

  • G06V 10/62 - Extraction de caractéristiques d’images ou de vidéos relative à une dimension temporelle, p. ex. extraction de caractéristiques axées sur le tempsSuivi de modèle
  • G06T 1/20 - Architectures de processeursConfiguration de processeurs p. ex. configuration en pipeline
  • G06V 10/30 - Filtrage de bruit
  • G06V 10/72 - Préparation de données, p. ex. prétraitement statistique des caractéristiques d’images ou de vidéos
  • G06V 10/75 - Organisation de procédés de l’appariement, p. ex. comparaisons simultanées ou séquentielles des caractéristiques d’images ou de vidéosApproches-approximative-fine, p. ex. approches multi-échellesAppariement de motifs d’image ou de vidéoMesures de proximité dans les espaces de caractéristiques utilisant l’analyse de contexteSélection des dictionnaires
  • G06V 20/40 - ScènesÉléments spécifiques à la scène dans le contenu vidéo

19.

MODULAR AND SCALABLE SWITCH MATRIX TOPOLOGY

      
Numéro d'application 18387181
Statut En instance
Date de dépôt 2023-11-06
Date de la première publication 2025-05-08
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Rivard, Jake H.
  • Taylor, Robert P.
  • Enderby, Randall T.
  • Cantrell, William H.
  • Tinch, Mark
  • Edwards, John M.
  • Hughes, Mark E.
  • Macdonald, Andrew G.
  • Wiltgen, Timothy E.

Abrégé

A switch matrix circuit module for routing signals. In an example, the module includes a switch matrix coupled with first and second switches. The switch matrix is configured to receive a plurality of input signals, and output a selected one of the plurality of input signals as a first intermediate signal and another selected one of the plurality of input signals as a second intermediate signal. The first switch receives the first intermediate signal and a first auxiliary signal, and outputs a first output signal, and the second switch receives the second intermediate signal and a second auxiliary signal, and outputs a second output signal. A number of the modules can be coupled together to provide a switch matrix circuit, which can be readily scaled by adding further modules. In an example, the plurality of input signals are radio frequency (RF) signals.

Classes IPC  ?

  • H04B 1/00 - Détails des systèmes de transmission, non couverts par l'un des groupes Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
  • H04B 1/04 - Circuits

20.

ANGLE AMBIGUITY MITIGATION FOR INTERFEROMETRY

      
Numéro d'application 18494332
Statut En instance
Date de dépôt 2023-10-25
Date de la première publication 2025-05-01
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Ekhaus, Ira B.

Abrégé

Techniques are provided for mitigating interferometric angle ambiguity. A methodology implementing the techniques according to an embodiment includes measuring a differential phase of a signal received at an interferometer baseline; calculating a Gaussian conditional probability of an angle of arrival of the signal based on the differential phase; calculating an angular position probability of an object in a target reference frame based on the conditional probability; aggregating the angular position probability with previously calculated angular position probabilities (based on previously selected baselines) to generate a current angular position probability; selecting a next baseline and iterating the process to calculate a next angular position probability; and selecting an angular position probability of greatest likelihood, from the current and previously calculated angular position probabilities, based on an amplitude of the Gaussian distributions, such that the selected angular position probability is associated with a disambiguated angular position of the object.

Classes IPC  ?

  • G01S 3/46 - Systèmes pour déterminer une direction ou une déviation par rapport à une direction prédéterminée en utilisant des antennes espacées et en mesurant la différence de phase ou de temps entre les signaux venant de ces antennes, c.-à-d. systèmes à différence de parcours

21.

LASER CONTROLLER

      
Numéro d'application 18495382
Statut En instance
Date de dépôt 2023-10-26
Date de la première publication 2025-05-01
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Lacroix, Daniel P.
  • Burkley, Zakary N.
  • Turner, Steven E.
  • Van Camp, Mackenzie A.
  • Srinivas, Shailendra
  • Madison, Gary M.
  • Metzner, Brendan L.

Abrégé

Laser control circuitry is described. In one example, a laser controller integrated circuit (IC) includes first and second input ports, a sideband direct digital synthesizer (DDS) coupled to the first input port and configured to produce a modulation signal and a reference signal based on an input signal received via the first input port, the modulation signal and the reference signal having a same frequency. The laser controller IC further includes a Pound-Drever-Hall frequency-locking control loop coupled to the second input port and to the sideband DDS, and configured to produce a corrected DC bias current signal based on the reference signal and a measurement signal received via the second input port, and a thermal management circuit configured to produce at least one thermal control signal.

Classes IPC  ?

22.

MULTINETTING TIME SYNCHRONIZATION

      
Numéro d'application US2024052520
Numéro de publication 2025/090576
Statut Délivré - en vigueur
Date de dépôt 2024-10-23
Date de publication 2025-05-01
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s) Chongoushian, John H.

Abrégé

A method is disclosed of efficiently synchronizing time bases of multi-netting network nodes. A first node transmits a synchronizing request on a subnet associated with the highest time quality in its source table, then simultaneously monitors that subnet and up to three additional subnets associated with lower time qualities in its source table. If the first node does not receive a response, it transmits the request on the subnet associated with the next highest time quality in its source table. A second node simultaneously monitors the subnet associated with its time quality and a plurality of subnets associate with consecutively higher time qualities. Upon receiving the synchronization request, it responds on the subnet associated with its time quality. The disclosed method is fully compatible with networks that include single-netting nodes, and can be implemented by a JTRS node exchanging RTT messages on a Link 16 network.

Classes IPC  ?

  • H04L 69/14 - Protocoles multicanaux ou multi-liaisons
  • H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
  • H04W 56/00 - Dispositions de synchronisation

23.

LAUNCH INITIATED LOW-DRAG SEEKER WINDOW COVER

      
Numéro d'application 18498623
Statut En instance
Date de dépôt 2023-10-31
Date de la première publication 2025-05-01
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Miska, Jacob W.

Abrégé

A guided vehicle that includes a body, a propulsion system operably engaged inside of the body, a housing operably engaged with the body and encasing a guidance device inside of the housing, a viewing window of the guidance device, and a cover moveably engaged with the housing, wherein the cover is moveable between a pre-flight configuration and a flight configuration. In the pre-flight configuration, the cover covers the viewing window. In the flight configuration, the cover is configured to expose the viewing window in the flight configuration in response to an impulse of acceleration generated by a launch of the guided vehicle.

Classes IPC  ?

  • F42B 10/46 - Coiffes aérodynamiquesPare-briseRadômes

24.

Multinetting time synchronization

      
Numéro d'application 18492844
Numéro de brevet 12356350
Statut Délivré - en vigueur
Date de dépôt 2023-10-24
Date de la première publication 2025-04-24
Date d'octroi 2025-07-08
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Chongoushian, John H.

Abrégé

A method is disclosed of efficiently synchronizing time bases of multi-netting network nodes. A first node transmits a synchronizing request on a subnet associated with the highest time quality in its source table, then simultaneously monitors that subnet and up to three additional subnets associated with lower time qualities in its source table. If the first node does not receive a response, it transmits the request on the subnet associated with the next highest time quality in its source table. A second node simultaneously monitors the subnet associated with its time quality and a plurality of subnets associate with consecutively higher time qualities. Upon receiving the synchronization request, it responds on the subnet associated with its time quality. The disclosed method is fully compatible with networks that include single-netting nodes, and can be implemented by a JTRS node exchanging RTT messages on a Link 16 network.

Classes IPC  ?

25.

ENDURA

      
Numéro de série 99144412
Statut En instance
Date de dépôt 2025-04-18
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. ()
Classes de Nice  ? 09 - Appareils et instruments scientifiques et électriques

Produits et services

radiation hardened or radiation tolerant integrated circuits for space products, namely single board computers, software defined radios, network routers, and command and control avionics

26.

CAVITY BACKED DIPOLE ANTENNA WITH REDUCED CAVITY SIZE

      
Numéro d'application 18486425
Statut En instance
Date de dépôt 2023-10-13
Date de la première publication 2025-04-17
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Howarth, Dean W.

Abrégé

A cavity backed antenna assembly includes a conductive lower wall and two or more conductive side walls at least in part defining a cavity. The antenna assembly further includes a first layer and a second layer each including a first dielectric material above the lower wall and within the cavity, and a third layer including a second dielectric material between and separating the first and second layers. In an example, the second dielectric material compositionally different from the first dielectric material. The antenna assembly further includes a first conductive structure and a second conductive structure separated by a third dielectric material, wherein the first conductive structure and the second conductive structure are within the cavity and above the first and second layers. In an example, the first dielectric material a relative magnetic permeability of at least 1 for a frequency between 10 MHz and 1 GHz.

Classes IPC  ?

  • H01Q 13/18 - Antennes à fentes résonnantes la fente étant adossée à, ou formée par, une paroi limite d'une cavité résonnante
  • H01Q 1/42 - Enveloppes non intimement mécaniquement associées avec les éléments rayonnants, p. ex. radome

27.

System and method for YATO/YANTO classification

      
Numéro d'application 17725149
Numéro de brevet 12272117
Statut Délivré - en vigueur
Date de dépôt 2022-04-20
Date de la première publication 2025-04-08
Date d'octroi 2025-04-08
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Wood, Benjamin P.
  • Wallace, Jeffrey A.
  • Branchaud, Jacob
  • Fredette, Marc J.

Abrégé

A passive sensor is used in conjunction with a trained machine learning classifier to make a You Are The One/You Are Not The One (YATO/YANTO) classification or determination as to whether an object, such as a threat, is moving toward a platform. The trained machine learning classifier utilizes a feature vector generated from conditioned temporal data and angular data obtained from passive sensor carried by the platform.

Classes IPC  ?

  • G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p. ex. des objets vidéo
  • G06V 10/70 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique

28.

GNSS SATELLITE SIGNAL AUTHENTICATION

      
Numéro d'application 18479272
Statut En instance
Date de dépôt 2023-10-02
Date de la première publication 2025-04-03
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Weger, John J.

Abrégé

A global navigation satellite system (GNSS) signal authentication methodology includes receiving, by one or more processors, a first digital signal and a second digital signal, the first digital signal and the second digital signal each representative of a GNSS satellite signal received from a GNSS satellite and including a ranging code that uniquely identifies the GNSS satellite, the first and second GNSS satellite signals transmitted contemporaneously from physically separate antennas onboard the GNSS satellite. The methodology continues with computing, by the one or more processors, a digital fingerprint based on the first digital signal and the second digital signal, and determining, by the one or more processors, that the first GNSS satellite signal and the second GNSS satellite signal are authentic (or not) based on the digital fingerprint. If the first and/or second GNSS satellite signals are found to not be authentic, remedial action may be taken.

Classes IPC  ?

  • G01S 19/21 - Problèmes liés aux interférences
  • G01S 5/02 - Localisation par coordination de plusieurs déterminations de direction ou de ligne de positionLocalisation par coordination de plusieurs déterminations de distance utilisant les ondes radioélectriques
  • G01S 19/08 - Éléments coopérantsInteraction ou communication entre les différents éléments coopérants ou entre les éléments coopérants et les récepteurs fournissant des informations d'intégrité, p. ex. la santé des satellites ou la qualité des éphémérides

29.

High dynamic range track and hold amplifier output stage using low voltage devices

      
Numéro d'application 18477058
Numéro de brevet 12288587
Statut Délivré - en vigueur
Date de dépôt 2023-09-28
Date de la première publication 2025-04-03
Date d'octroi 2025-04-29
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Madison, Gary M.
  • Grout, Kevin

Abrégé

A sample and hold amplifier output buffer with the low leakage of metal oxide semiconductor field effect transistors (MOSFET) combined with the linearity and dynamic range of silicon-germanium (SiGe) bipolar junction transistors (BJT). In one aspect, the present disclosure provides a sample and hold amplifier output buffer placing a MOSFET input device between the base and emitter of a high linearity SiGe BJT.

Classes IPC  ?

  • G11C 27/02 - Moyens d'échantillonnage et de mémorisation
  • H03K 17/60 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors bipolaires
  • H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
  • H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface

30.

PROGRAMMABLE GAIN TRANSIMPEDANCE AMPLIFIER HAVING A RESISTIVE T-NETWORK FEEDBACK ARCHITECTURE AND METHOD THEREOF

      
Numéro d'application 18477116
Statut En instance
Date de dépôt 2023-09-28
Date de la première publication 2025-04-03
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Notaro, Gregory S.

Abrégé

A programmable transimpedance amplifiers (TIA) having T-network feedback architectures for achieving varying levels of gain based on a magnitude of an input current signal. TIA includes an operational amplifier (op-amp), a first or T-network feedback architecture that operatively connects with the op-amp at a first input terminal of the op-amp and the output terminal of the op-amp, a second feedback architecture that operatively connects with the op-amp at the first input terminal of the operational amplifier and the output terminal of the operational amplifier, an input voltage source architecture that operatively connects with a second input terminal of the operational amplifier, and at least one controller that operatively connects with each of the first feedback architecture, the second feedback architecture, and the input voltage source architecture to switch specific architectures between operative states and inoperative states to achieve a predetermined fixed output bias voltage from the operational amplifier.

Classes IPC  ?

  • H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs
  • H03F 3/45 - Amplificateurs différentiels

31.

BIT SPREADING TECHNIQUE FOR RADIATION HARDENED ERROR RESISTANT MEMORY SYSTEM

      
Numéro d'application US2024024571
Numéro de publication 2025/064009
Statut Délivré - en vigueur
Date de dépôt 2024-04-15
Date de publication 2025-03-27
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Moser, David D.
  • Ross, Jason F.
  • Shaffer, Mark R.
  • Brown, Michael B.
  • Stanley, Daniel L.
  • Robertson, Jeffrey E.

Abrégé

Techniques are provided for an error resistant radiation hardened memory system based on spreading of data bits among multiple random access memories (RAMs). A memory system implementing the techniques according to an embodiment includes a first plurality of RAMs configured to store data bits written to the memory system, the data bits distributed over the first plurality of RAMs. The system also includes an error correction coding (ECC) circuit configured to generate ECC codes, each of the codes associated with a unique group of the data bits. The system further includes a second plurality of RAMs configured to store bits of the ECC codes such that the bits of each ECC code are distributed over the second plurality of RAMs. The system further includes a reporting circuit configured to report a single bit error correction or a double bit error detection, resulting from a read operation on the memory system.

Classes IPC  ?

  • G06F 11/08 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle
  • G11B 20/18 - Détection ou correction d'erreursTests
  • G06F 11/16 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel
  • G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
  • H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
  • H03M 13/19 - Correction d'une seule erreur sans utiliser les propriétés particulières des codes cycliques, p. ex. codes de Hamming, codes de Hamming étendus ou généralisés
  • H03M 13/09 - Détection d'erreurs uniquement, p. ex. utilisant des codes de contrôle à redondance cyclique [CRC] ou un seul bit de parité
  • G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire

32.

Time synchronization of optics using power feeds

      
Numéro d'application 18474817
Numéro de brevet 12270628
Statut Délivré - en vigueur
Date de dépôt 2023-09-26
Date de la première publication 2025-03-27
Date d'octroi 2025-04-08
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Stolle, Frank R
  • Bortolami, Simone B.
  • Mack, Larry H

Abrégé

A weapon-mountable smart optic comprising: a time reference configured to output a signal comprising a periodically-repeating feature and time metadata and comprising a first oscillator; at least two sensors configured to gather data, each comprising secondary oscillators; and at least one processor in communication with each of the at least two sensors; wherein each of the at least two sensors is in operative communication with the time reference and is configured to associate an edge of the periodically-repeating signal with a time conveyed by the time metadata, and wherein each of the at least two sensors is configured to gather data, associate time metadata with the gathered data, and to send the gathered data with time metadata to the at least one processor, and wherein the at least one processor is configured to fuse the data gathered by each of the at least two sensors.

Classes IPC  ?

  • F41G 3/06 - Dispositifs de pointage avec télémètre
  • F41G 3/08 - Dispositifs de pointage avec correcteurs de vitesse, direction, température, pression ou humidité de l'atmosphère
  • G06G 7/80 - Calculateurs analogiques pour des procédés, des systèmes ou des dispositifs spécifiques, p. ex. simulateurs pour le pointage d'armesCalculateurs analogiques pour des procédés, des systèmes ou des dispositifs spécifiques, p. ex. simulateurs pour le lancement de bombesCalculateurs analogiques pour des procédés, des systèmes ou des dispositifs spécifiques, p. ex. simulateurs pour le guidage de missiles

33.

DESIGN VERIFICATION PROCESS FOR BIT SPREADING ERROR RESISTANT MEMORY SYSTEM

      
Numéro d'application US2024047355
Numéro de publication 2025/064593
Statut Délivré - en vigueur
Date de dépôt 2024-09-19
Date de publication 2025-03-27
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s) Robertson, Jeffrey E.

Abrégé

Techniques are provided for design verification of a bit spreading memory. A methodology implementing the techniques according to an embodiment includes using a bit spreading geometry file to convert a logical address of the memory to a physical address. The geometry file defines a scheme by which bits of a data word stored at the logical address are spread over multiple RAMs. The method also includes writing data bits of a test data word to the physical address, causing a design simulator to simulate a read from the logical address, and comparing the result to the test data word for verification. The method further includes causing the design simulator to simulate a write of the test data word to the logical address, reading data bits from the physical address, arranging the bits into a retrieved data word, and comparing the test data word to the retrieved data word for verification.

Classes IPC  ?

  • G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
  • G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p. ex. compteurs de rafraîchissement défectueux
  • G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
  • G11C 29/10 - Algorithmes de test, p. ex. algorithmes par balayage de mémoire [MScan]Configurations de test, p. ex. configurations en damier
  • G11C 29/16 - Mise en œuvre d'une logique de commande, p. ex. décodeurs de mode de test utilisant des unités microprogrammées, p. ex. machines à états logiques

34.

Verification process for bit spreading error resistant memory system

      
Numéro d'application 18470111
Numéro de brevet 12332781
Statut Délivré - en vigueur
Date de dépôt 2023-09-19
Date de la première publication 2025-03-20
Date d'octroi 2025-06-17
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Robertson, Jeffrey E.

Abrégé

Techniques are provided for design verification of a bit spreading memory. A methodology implementing the techniques according to an embodiment includes using a bit spreading geometry file to convert a logical address of the memory to a physical address. The geometry file defines a scheme by which bits of a data word stored at the logical address are spread over multiple RAMs. The method also includes writing data bits of a test data word to the physical address, causing a design simulator to simulate a read from the logical address, and comparing the result to the test data word for verification. The method further includes causing the design simulator to simulate a write of the test data word to the logical address, reading data bits from the physical address, arranging the bits into a retrieved data word, and comparing the test data word to the retrieved data word for verification.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectationRéadressage
  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11

35.

Impulse cartridge cup for smart stores communication interface squib with electronics

      
Numéro d'application 18364508
Numéro de brevet 12253342
Statut Délivré - en vigueur
Date de dépôt 2023-08-03
Date de la première publication 2025-03-18
Date d'octroi 2025-03-18
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Gensler, Jeffrey A.
  • Kohl, Christopher E.

Abrégé

An impulse cartridge (IC) cup has at least one aperture defined in a cylindrical sidewall. The first aperture extends radially relative to a primary axis through the cylindrical sidewall from an inner surface to an outer surface. A first electrical connector is disposed in the first aperture. The first electrical connector is adapted to physically contact the impulse cartridge at a first location. The IC cup is adapted to be connected to a canister that houses a payload of a countermeasure defense system, wherein the payload is to be deployed in response to explosion of the impulse cartridge.

Classes IPC  ?

  • F42B 5/15 - Cartouches, c.-à-d. projectile et douille avec charge propulsive formant un tout pour libérer des gaz, des vapeurs, des poudres, des particules ou des substances à réaction chimique adaptées pour créer un effet de brouillard ou de leurre, p. ex. en utilisant des paillettes anti-radar ou des corps à action infrarouge
  • B64D 1/02 - Largage ou éjection d'objets
  • B64D 7/00 - Agencement à bord aéronefs des équipements militaires, p. ex. des armes, des accessoires d'armement ou des blindages de protectionAdaptations des installations d'armement aux aéronefs
  • F41A 9/72 - Chargeurs tubulaires, c.-à-d. chargeurs dans lesquels les munitions sont rangées longitudinalement en tandem
  • F41A 19/68 - Mécanismes de mise à feu électriques pour des armes à feu à plusieurs tubes
  • F41F 3/06 - Lanceurs de roquettes ou de torpilles pour roquettes à partir d'avions
  • F41F 3/065 - Nacelles lance-roquettes, c.-à-d. conteneurs amovibles pour lancer plusieurs roquettes
  • F41H 13/00 - Moyens d'attaque ou de défense non prévus ailleurs
  • F42B 5/02 - Cartouches, c.-à-d. projectile et douille avec charge propulsive formant un tout
  • F42B 12/70 - Projectiles ou mines caractérisés par la charge militaire, l'effet recherché ou le matériau caractérisés par la nature de la charge militaire ou par l'effet recherché pour libérer des matériaux, des corps ou des particulesProjectiles ou mines caractérisés par la charge militaire, l'effet recherché ou le matériau caractérisés par la nature de la charge militaire ou par l'effet recherché pour produire une réaction chimique ou physiqueProjectiles ou mines caractérisés par la charge militaire, l'effet recherché ou le matériau caractérisés par la nature de la charge militaire ou par l'effet recherché pour la signalisation pour la libération de corps solides individuels pour la libération de paillettes antiradar ou de matériaux à émission infrarouge

36.

Electro-optical infrared (EOIR) sensor interface and processing on a programmable real time unit (PRU)

      
Numéro d'application 18458626
Numéro de brevet 12253341
Statut Délivré - en vigueur
Date de dépôt 2023-08-30
Date de la première publication 2025-03-06
Date d'octroi 2025-03-18
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Minguy, Connor

Abrégé

A guidance system for a guided munition has an inertial measurement unit (IMU) or another type of first sensor on the guided munition, electro-optical/infrared (EO/IR) sensor on the guided munition, and a guidance computer assembly (GCA) having a Programmable Real-Time Unit Industrial Communication SubSystem (PRU-ICSS), wherein the PRU-ICSS is in operative communication with the IMU or another type of first sensor and the EO/IR. The PRU-ICSS has a first Programmable Real-Time Unit (PRU), wherein the first PRU is programmed to receive and process input data from the IMU or another type of first sensor on the guided munition, and the PRU-ICSS has a second PRU, wherein the second PRU is programmed to receive and process input data from the EO/IR sensor on the guided munition.

Classes IPC  ?

  • F42B 15/01 - Dispositions pour le guidage ou le pilotage sur les projectiles autopropulsés ou les missiles
  • F41G 7/22 - Systèmes autodirecteurs

37.

SEMICONDUCTOR DEVICE WITH REDACTED LOGIC

      
Numéro d'application 18456648
Statut En instance
Date de dépôt 2023-08-28
Date de la première publication 2025-03-06
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Moser, David D.
  • Stanley, Daniel L.
  • Gilliam, Jane O.

Abrégé

A semiconductor device includes a data port, a programmable logic block for executing a manufacturer test, and a processor operatively coupled to the data port. The processor is configured to assert, in a first modality, a configuration isolation signal to the data port. The data port is configured to be communicatively isolated from the programmable logic block while the configuration isolation signal is asserted. The processor is configured to de-assert, in a second modality, the configuration isolation signal from the data port. The data port is configured to be communicatively coupled to the programmable logic block while the configuration isolation signal is de-asserted. In some examples, the semiconductor device includes a communication interface communicatively coupled to the programmable logic block, wherein the processor is further configured to cause, in the first modality, data to be loaded into the programmable logic block from a first-in-first-out (FIFO) buffer of the communication interface.

Classes IPC  ?

38.

TARGET LEAD ESTIMATION BASED ON LAUNCHER SLEW

      
Numéro d'application 18460282
Statut En instance
Date de dépôt 2023-09-01
Date de la première publication 2025-03-06
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Batchelder, Jason H.
  • Chrobak, Matthew F.
  • Nickerson, Tyler
  • Blauvelt, Samuel C.

Abrégé

A portable launcher to launch a guided projectile at an aerial target, wherein the guided projectile has a projectile guidance kit and a target leading guidance kit that is provided with the guided projectile and the portable launcher. The target leading guidance kit includes a target lead estimation protocol stored on a computer readable media and accessible by a processor of the target leading guidance kit. When the processor executes the target lead estimation protocol, the processor is instructed to dynamically lead a reticle of an electronic sight of the target leading guidance kit from the initial target position to the lead target position in response to the projectile guidance kit detecting a speed of the aerial target and an inertial measurement unit of the target leading guidance kit that measures the slew of the guided projectile from the initial position to the translated position.

Classes IPC  ?

  • F41F 3/045 - Lanceurs de roquettes ou de torpilles pour roquettes adaptés pour être transportés et utilisés par une personne, p. ex. bazookas
  • F41G 3/16 - Dispositifs de visée adaptés pour le pointage indirect

39.

SEMICONDUCTOR DEVICE WITH REDACTED LOGIC

      
Numéro d'application US2024043053
Numéro de publication 2025/049173
Statut Délivré - en vigueur
Date de dépôt 2024-08-20
Date de publication 2025-03-06
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Moser, David, D.
  • Stanley, Daniel, L.
  • Gilliam, Jane, O.

Abrégé

A semiconductor device includes a data port, a programmable logic block for executing a manufacturer test, and a processor operatively coupled to the data port. The processor is configured to assert, in a first modality, a configuration isolation signal to the data port. The data port is configured to be communicatively isolated from the programmable logic block while the configuration isolation signal is asserted. The processor is configured to de-assert, in a second modality, the configuration isolation signal from the data port. The data port is configured to be communicatively coupled to the programmable logic block while the configuration isolation signal is de-asserted. In some examples, the semiconductor device includes a communication interface communicatively coupled to the programmable logic block, wherein the processor is further configured to cause, in the first modality, data to be loaded into the programmable logic block from a first-in-first-out (FIFO) buffer of the communication interface.

Classes IPC  ?

  • G01R 31/3163 - Tests fonctionnels
  • G01R 31/3181 - Tests fonctionnels
  • G01R 31/3187 - Tests intégrés
  • G06F 11/26 - Tests fonctionnels
  • G01R 31/3167 - Tests de circuits analogiques et numériques combinés
  • G01R 31/317 - Tests de circuits numériques
  • G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
  • G06F 11/273 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie

40.

Navigation device

      
Numéro d'application 29876509
Numéro de brevet D1064864
Statut Délivré - en vigueur
Date de dépôt 2023-05-23
Date de la première publication 2025-03-04
Date d'octroi 2025-03-04
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Cogan, Kenneth P.
  • Weighton, James K.
  • Johnson, Van
  • Stutzman, Karlin
  • Stultz, Jimmey C.
  • Smith, David
  • Mcelvogue, Matt
  • Schramm, Warren

41.

ANISOTROPIC CONDUCTIVE SUBSTRATES AND METHODS OF USE

      
Numéro d'application 18452984
Statut En instance
Date de dépôt 2023-08-21
Date de la première publication 2025-02-27
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Wyckoff, Nathaniel P.
  • Mauermann, Jacob R.
  • Terry, Benjamin
  • Smith, Justin D.

Abrégé

A method fabricating at least one universal substrate from a batch product. The method includes steps of: providing a preform having a predetermined profile; wrapping a plurality of conductors about an outer surface of the preform; injecting a nonconductive matrix between conductors of the plurality of conductors, wherein the nonconductive matrix permeates between interstitial spaces of the plurality of conductors to isolate some conductors of the plurality of conductors from one another; forming the batch product that includes the plurality of conductors and the nonconductive matrix; and wafering at least one section of the batch product to form the at least one universal substrate. The plurality of conductors of the at least one universal substrate defines a first connection surface, a second connection surface opposite to the first connection surface, and a plurality of conductive pathways defined between the first connection surface and the second connection surface.

Classes IPC  ?

  • H05K 3/36 - Assemblage de circuits imprimés avec d'autres circuits imprimés

42.

Multi-waveform steering vector computation engine

      
Numéro d'application 18455264
Numéro de brevet 12341586
Statut Délivré - en vigueur
Date de dépôt 2023-08-24
Date de la première publication 2025-02-27
Date d'octroi 2025-06-24
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Long, Ryan E.
  • Muller, Christopher M.

Abrégé

Techniques are provided for steering vector generation. A methodology implementing the techniques according to an embodiment includes converting time domain data received from an antenna array to channelized frequency domain data. The method also includes receiving a request from a signal detection system, the request including a timestamp and duration of a detected signal of interest (SOI) and an indication that the SOI is pulsed or continuous. The method further includes generating, for a pulsed SOI, steering vectors to steer the antenna array to the pulsed SOI based on a segment of the time domain data stored in a first memory and identified by the time stamp and duration; and generating, for a continuous SOI, steering vectors to steer the antenna array to the continuous SOI based on a segment of the channelized frequency domain data stored in a second memory and identified by the time stamp and duration.

Classes IPC  ?

  • H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
  • G01S 3/14 - Systèmes pour déterminer une direction ou une déviation par rapport à une direction prédéterminée

43.

CARTRIDGE CASE CRIMPING TOOL

      
Numéro d'application 18455823
Statut En instance
Date de dépôt 2023-08-25
Date de la première publication 2025-02-27
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Gensler, Jeffrey A.

Abrégé

A crimping tool for assembling a countermeasure expendable. The crimping tool includes a main body that has a top end, a bottom end vertically opposite to the top end, and an axis defined between the top end and the bottom end. The main body is configured to receive a cap of the countermeasure expendable, a spacer of the countermeasure expendable, and a cartridge case of the countermeasure expendable. The crimping tool also includes a presser that selectively operably engages with the main body and is configured to press the cap and the spacer of the countermeasure expendable into the cartridge case of the countermeasure expendable. The crimping tool also includes a set of crimpers that operably engages with the main body and is configured to crimp at least the cap, the spacer, the cartridge case with one another to collectively maintain the cap and the spacer with the cartridge case.

Classes IPC  ?

  • F42B 33/00 - Fabrication de munitionsDémontage de munitionsAppareils à cet effet

44.

ANISOTROPIC CONDUCTIVE SUBSTRATES AND METHODS OF USE

      
Numéro d'application US2024042261
Numéro de publication 2025/042650
Statut Délivré - en vigueur
Date de dépôt 2024-08-14
Date de publication 2025-02-27
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Wyckoff, Nathaniel P.
  • Mauermann, Jacob R.
  • Terry, Benjamin
  • Smith, Justin D.

Abrégé

A method fabricating at least one universal substrate from a batch product. The method includes steps of: providing a preform having a predetermined profile; wrapping a plurality of conductors about an outer surface of the preform; injecting a nonconductive matrix between conductors of the plurality of conductors, wherein the nonconductive matrix permeates between interstitial spaces of the plurality of conductors to isolate some conductors of the plurality of conductors from one another; forming the batch product that includes the plurality of conductors and the nonconductive matrix; and wafering at least one section of the batch product to form the at least one universal substrate. The plurality of conductors of the at least one universal substrate defines a first connection surface, a second connection surface opposite to the first connection surface, and a plurality of conductive pathways defined between the first connection surface and the second connection surface.

Classes IPC  ?

  • H01L 21/301 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour subdiviser un corps semi-conducteur en parties distinctes, p. ex. cloisonnement en zones séparées
  • H01B 5/04 - Barres, barreaux, fils ou rubans simplesBarres omnibus enroulés ou bobinés
  • H01B 5/16 - Conducteurs ou corps conducteurs non isolés caractérisés par la forme comprenant un matériau conducteur incorporé à un matériau isolant ou faiblement conducteur, p. ex. du caoutchouc conducteur
  • H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes

45.

SIZE EXPANDABLE DUAL POLARIZED ANTENNA ARRAY

      
Numéro d'application 18456187
Statut En instance
Date de dépôt 2023-08-25
Date de la première publication 2025-02-27
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Johnson, Alexander D.

Abrégé

Techniques are provided for fabricating an expandable tightly coupled dipole array (TCDA) antenna with dual-linear linear polarization. An antenna implementing the techniques according to an embodiment includes an array of the electrically coupled antenna elements. The antenna elements comprise a horizontally polarized planar dipole antenna disposed on a first foldable substrate and a ground plane disposed on a second foldable substrate. The second substrate is parallel to the first substrate. The antenna elements also comprise a first printed circuit board (PCB) coupling the first substrate to the second substrate, the first PCB perpendicular to the first substrate and the second substrate, and a second PCB coupling the first substrate to the second substrate, the second PCB perpendicular to the first substrate and the second substrate and parallel to the first PCB. The antenna elements further comprise a vertically polarized dipole antenna disposed on the second PCB.

Classes IPC  ?

  • H01Q 21/06 - Réseaux d'unités d'antennes, de même polarisation, excitées individuellement et espacées entre elles
  • H01Q 1/08 - Moyens pour replier tout ou partie des antennes
  • H01Q 21/24 - Combinaisons d'unités d'antennes polarisées dans des directions différentes pour émettre ou recevoir des ondes polarisées circulairement ou elliptiquement ou des ondes polarisées linéairement dans n'importe quelle direction

46.

Smart store communication interface (SSCI) compatible squib design

      
Numéro d'application 18364528
Numéro de brevet 12235061
Statut Délivré - en vigueur
Date de dépôt 2023-08-03
Date de la première publication 2025-02-25
Date d'octroi 2025-02-25
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Kohl, Christopher E.

Abrégé

A smart store communication interface (SSCI) squib of a countermeasure expendable. SSCI squib also includes a first electrical network. SSCI squib also includes a second electrical network that is isolated from the first electrical network. SSCI squib includes a fire pin contact that operably engages with the first electrical network and the second electrical network. The SSCI squib is configured to one of ignite a propellant loaded inside of a housing of the SSCI squib and communicate with a processor of the countermeasure expendable in response to receiving at least one electrical signal at the fire pin contact.

Classes IPC  ?

  • F41A 19/70 - Électrodes d'allumageLeur montage
  • F42B 5/15 - Cartouches, c.-à-d. projectile et douille avec charge propulsive formant un tout pour libérer des gaz, des vapeurs, des poudres, des particules ou des substances à réaction chimique adaptées pour créer un effet de brouillard ou de leurre, p. ex. en utilisant des paillettes anti-radar ou des corps à action infrarouge

47.

ADDITIVELY MANUFACTURED ANTENNA WITH VIVALDI ELEMENT

      
Numéro d'application 18451393
Statut En instance
Date de dépôt 2023-08-17
Date de la première publication 2025-02-20
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Johnson, Alexander D.
  • Fung, James F.

Abrégé

An antenna assembly includes a first flare arm, a second flare arm located adjacent to the first flare arm, a feed block having an opening therein, a feed slot extending from the opening to an outer periphery of the feed block, and a feed line integral with the feed block as a contiguous unitary component. The first flare arm and the second flare arm are symmetric about the feed block. The feed line can have a first portion integrated into the feed block and a second portion at least partially extending across the feed slot. A method of fabricating an antenna assembly includes additively manufacturing a feed block having a feed slot adjacent to a first flare arm and a second flare arm, and additively manufacturing a feed line having a first portion integral with the feed block, and a second portion at least partially extending across the feed slot.

Classes IPC  ?

  • H01Q 21/22 - Réseaux d'unités d'antennes, de même polarisation, excitées individuellement et espacées entre elles les unités d'antennes du réseau étant excitées d'une façon non uniforme en amplitude ou en phase, p. ex. réseau à prises ou réseau bidirectionnel
  • H01Q 5/47 - Structures imbriquées ou entrelacéesDispositions combinées ou présentant un couplage électromagnétique, p. ex. comprenant plusieurs éléments rayonnants alimentés sans connexion commune utilisant plusieurs points d’alimentation associés à un dispositif commun de réflexion, de diffraction ou de réfraction les points d’alimentation formant une disposition coaxiale

48.

ADDITIVELY MANUFACTURED ANTENNA WITH INVERTED HAT MONOPOLE ELEMENT

      
Numéro d'application 18451396
Statut En instance
Date de dépôt 2023-08-17
Date de la première publication 2025-02-20
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Johnson, Alexander D.
  • Fung, James F.

Abrégé

An antenna assembly includes an electrically conductive ground plane; a signal pin adjacent to the ground plane; and a tapered conductive surface coupled to the signal pin, the tapered conductive surface being symmetric about an axis passing through the signal pin and orthogonal to the ground plane, where the ground plane and the tapered conductive surface are an additively manufactured contiguous unitary component. The antenna assembly can further include a support structure extending from the ground plane to the tapered conductive surface. The support structure can be coupled to an outer edge of the tapered conductive surface or a center region of the tapered conductive surface. The antenna assembly can further include a cover over the tapered conductive surface thereby forming a hollow region between the cover and the tapered conductive surface.

Classes IPC  ?

  • H01Q 9/30 - Antennes résonnantes avec alimentation à l'extrémité d'un élément actif allongé, p. ex. unipôle
  • H01Q 13/02 - Cornets de guide d'onde
  • H01Q 21/00 - Systèmes ou réseaux d'antennes
  • H01Q 21/20 - Réseaux d'unités d'antennes, de même polarisation, excitées individuellement et espacées entre elles les unités étant espacées le long d'un trajet curviligne ou adjacent à celui-ci

49.

Interpolated deterministic gradient adaptive filter

      
Numéro d'application 18446084
Numéro de brevet 12224890
Statut Délivré - en vigueur
Date de dépôt 2023-08-08
Date de la première publication 2025-02-11
Date d'octroi 2025-02-11
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Schaefer, Timothy M.
  • Couto, David J.

Abrégé

An adaptive filter protocol stored on a non-transitory computer readable medium that is operatively in communication with a processor of a platform. The adaptive filter protocol includes a first processing loop that is operatively in communication with at least one receiving device of the platform for receiving at least one input signal. The adaptive filter protocol also includes a second processing loop that is operatively in communication with the first processing loop and has a deterministic gradient descent optimization logic and an interpolation logic. When the at least one receiving device receives the at least one input signal, the adaptive filter protocol enables the processor to generate a refined match filter parameters that substantially correlates with the initial parameters of the at least one input signal upon completing a plurality of refining cycles of the second processing loop.

Classes IPC  ?

  • H04L 27/34 - Systèmes à courant porteur à modulation de phase et d'amplitude, p. ex. en quadrature d'amplitude
  • G06N 3/084 - Rétropropagation, p. ex. suivant l’algorithme du gradient
  • H04L 27/148 - Circuits de démodulationCircuits récepteurs avec démodulation utilisant les propriétés spectrales du signal reçu, p. ex. en utilisant des éléments sélectifs de la fréquence ou sensibles à la fréquence utilisant des filtres, y compris des filtres du type PLL

50.

INTEGRATED WIDEBAND COMMUNICATION CIRCUIT

      
Numéro d'application US2024040264
Numéro de publication 2025/029846
Statut Délivré - en vigueur
Date de dépôt 2024-07-31
Date de publication 2025-02-06
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Jansen, Douglas S.
  • Sengele, Sean
  • Fisher, Marc A.
  • Flewelling, Gregory M.
  • Grens, Curtis M.

Abrégé

A communications circuit includes a first circuit block and a second circuit block. The first circuit block includes a first splitter, a first signal path coupled to a first output of the first splitter, a second signal path coupled to a second output of the first splitter, and a first switch configured to couple the second signal path to a third signal path or to couple a fourth signal path to the third signal path. The second circuit block includes a second splitter, a fifth signal path coupled to a first output of the second splitter, a sixth signal path coupled to a second output of the second splitter, and a second switch configured to couple the sixth signal path to the third signal path or to couple a seventh signal path to the third signal path. The third signal path extends between the first and second circuit blocks.

Classes IPC  ?

  • H04B 1/403 - Circuits utilisant le même oscillateur pour générer à la fois la fréquence de l’émetteur et la fréquence de l’oscillateur local du récepteur
  • H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés

51.

INTEGRATED WIDEBAND COMMUNICATION CIRCUIT

      
Numéro d'application 18363243
Statut En instance
Date de dépôt 2023-08-01
Date de la première publication 2025-02-06
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Jansen, Douglas S.
  • Sengele, Sean
  • Fisher, Marc A.
  • Flewelling, Gregory M.
  • Grens, Curtis M.

Abrégé

A communications circuit includes a first circuit block and a second circuit block. The first circuit block includes a first splitter, a first signal path coupled to a first output of the first splitter, a second signal path coupled to a second output of the first splitter, and a first switch configured to couple the second signal path to a third signal path or to couple a fourth signal path to the third signal path. The second circuit block includes a second splitter, a fifth signal path coupled to a first output of the second splitter, a sixth signal path coupled to a second output of the second splitter, and a second switch configured to couple the sixth signal path to the third signal path or to couple a seventh signal path to the third signal path. The third signal path extends between the first and second circuit blocks.

Classes IPC  ?

  • H04B 1/3805 - Émetteurs-récepteurs, c.-à-d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception avec des récepteurs auxiliaires intégrés
  • H04B 1/04 - Circuits

52.

SYSTEM AND METHOD FOR TARGETING FROM 3D DIGITAL SURFACE MODELS AND DIGITAL POINT POSITIONING DATABASE CONTROLLED STEREO IMAGERY

      
Numéro d'application 18363433
Statut En instance
Date de dépôt 2023-08-01
Date de la première publication 2025-02-06
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Devenecia, Kurt J.
  • Withee, Brett A.

Abrégé

A computer program product and corresponding method for targeting one or more points in a three dimensional (3D) model is provided. The computer program product including least one non-transitory computer readable storage medium in operative communication with a computer processing unit (CPU), the storage medium having instructions stored thereon that, when executed by the CPU, implement a process to register the 3D model with a stereoscopic image pair. The steps performed include inputting a first image and a second image that define a stereoscopic image pair into an object targeting program, wherein an object is shown in the first image and the second image, inputting a three dimensional (3D) model of the object into the object targeting program, registering the 3D model to the stereoscopic image pair, and targeting a point associated with or near the object based on the 3D model having been registered to the stereoscopic image pair.

Classes IPC  ?

  • G06T 7/33 - Détermination des paramètres de transformation pour l'alignement des images, c.-à-d. recalage des images utilisant des procédés basés sur les caractéristiques
  • G06T 7/60 - Analyse des attributs géométriques
  • G06T 7/73 - Détermination de la position ou de l'orientation des objets ou des caméras utilisant des procédés basés sur les caractéristiques
  • G06V 20/64 - Objets tridimensionnels

53.

POWER COMBINING FOR HIGH POWER AMPLIFIERS

      
Numéro d'application 18360409
Statut En instance
Date de dépôt 2023-07-27
Date de la première publication 2025-01-30
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Bucceri, John
  • Schmanski, Bernard J.
  • Dugas, Douglas M.
  • Mckivergan, Patrick D.
  • Doran, Michael Patrick

Abrégé

An ultra-wideband radio frequency (RF) apparatus for combining and/or dividing RF signals. RF apparatus includes a circuit board, a communication cable that operably engages with the circuit board, at least two transmission lines that are formed on the circuit board and operably engages with the communication cable, and at least two connectors that operably engages with the at least two transmission lines. The RF apparatus is operable in a first configuration and a second configuration. When the RF apparatus is provided in the first configuration, the RF apparatus is operable to divide a first RF signal into at least two RF signals. When the RF apparatus is provided in the second configuration, the RF apparatus is operable to combine the at least two RF signals into a second RF signal. The RF apparatus is capable of achieving a low insertion loss less than 1 dB over a bandwidth greater than 20:1.

Classes IPC  ?

  • H04B 1/10 - Dispositifs associés au récepteur pour limiter ou supprimer le bruit et les interférences
  • H04B 1/04 - Circuits

54.

FLEXIBLE APERTURE FED PATCH ANTENNA

      
Numéro d'application US2024037371
Numéro de publication 2025/024130
Statut Délivré - en vigueur
Date de dépôt 2024-07-10
Date de publication 2025-01-30
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Johnson, Alexander D.
  • Kubwimana, Jean L.
  • Tamasy, Jacob
  • Fung, James F.

Abrégé

An antenna assembly includes a first flexible layer including a conductive ground plane on a first layer of dielectric material, and a second flexible layer including a first array of conductive patches on a second layer of dielectric material. The antenna assembly further includes a second array of conductive patches on a third layer of dielectric material. The first, second, and third flexible layers are rollable or foldable, to provide a stowed position for the antenna assembly and a deployed position for the antenna assembly. In an example, the first array of conductive patches includes at least a first patch and a second patch, and the second array of conductive patches includes at least a third patch and a fourth patch. In the deployed position, the first patch is above the third patch and the ground plane, and the second patch is above the fourth patch and the ground plane.

Classes IPC  ?

55.

FLEXIBLE APERTURE FED PATCH ANTENNA

      
Numéro d'application 18356595
Statut En instance
Date de dépôt 2023-07-21
Date de la première publication 2025-01-23
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Johnson, Alexander D.
  • Kubwimana, Jean L.
  • Tamasy, Jacob
  • Fung, James F.

Abrégé

An antenna assembly includes a first flexible layer including a conductive ground plane on a first layer of dielectric material, and a second flexible layer including a first array of conductive patches on a second layer of dielectric material. The antenna assembly further includes a second array of conductive patches on a third layer of dielectric material. The first, second, and third flexible layers are rollable or foldable, to provide a stowed position for the antenna assembly and a deployed position for the antenna assembly. In an example, the first array of conductive patches includes at least a first patch and a second patch, and the second array of conductive patches includes at least a third patch and a fourth patch. In the deployed position, the first patch is above the third patch and the ground plane, and the second patch is above the fourth patch and the ground plane.

Classes IPC  ?

  • H01Q 21/06 - Réseaux d'unités d'antennes, de même polarisation, excitées individuellement et espacées entre elles
  • H01Q 1/08 - Moyens pour replier tout ou partie des antennes
  • H01Q 9/04 - Antennes résonnantes

56.

DIFFERENTIAL DIGITAL STEP ATTENUATORS WITH LEAKAGE CANCELLATION

      
Numéro d'application 18354354
Statut En instance
Date de dépôt 2023-07-18
Date de la première publication 2025-01-23
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Comeau, Jonathan P.
  • Jansen, Douglas S.
  • Madison, Gary M.

Abrégé

An attenuator circuit includes a differential input having first and second inputs, and a differential output having first and second outputs. The attenuator circuit further includes a first transistor coupled between the first input and the first output, a second transistor coupled between the second input and the second output, a third transistor coupled between the first input and the second output, and a fourth transistor coupled between the second input and the first output. During a pass-through state, the first and second transistors are enabled, and the third and fourth transistors may be disabled. During an attenuation state, the first, second, third, and fourth transistors are all disabled. An attenuator network (e.g., T or Pi network) may have its differential input terminals coupled to the first and second inputs of the differential input, and its differential output terminals coupled to the first and second outputs of the differential output.

Classes IPC  ?

  • H03H 7/25 - Affaiblisseurs indépendants de la fréquence comprenant un élément commandé par une variable électrique ou magnétique
  • H03H 11/24 - Atténuateurs indépendants de la fréquence

57.

ADDITIVELY MANUFACTURED PROBE FED PATCH ANTENNA

      
Numéro d'application 18222658
Statut En instance
Date de dépôt 2023-07-17
Date de la première publication 2025-01-23
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Kubwimana, Jean L.
  • Johnson, Alexander D.
  • Dinbergs, Arturs E.
  • Tamasy, Jacob
  • Fung, James F.

Abrégé

A method of manufacturing an antenna assembly includes additively manufacturing an element that is monolithic and that includes (i) a ground plane, (ii) a patch above the ground plane, and (iii) a structure having a lower end in contact with the ground plane and an upper end in contact with the patch. The method further includes applying a dielectric material between the ground plane and the patch. In an example, the dielectric material is dielectric foam. The method further includes removing a section of the ground plane around the lower end of the structure, such that the structure extends through the ground plane and not in contact with the ground plane. The method further includes connecting an inner conductor of a coaxial cable connector to the lower end of the structure, and an outer portion of the coaxial cable connector to the ground plane.

Classes IPC  ?

  • H01Q 9/04 - Antennes résonnantes
  • H01Q 1/22 - SupportsMoyens de montage par association structurale avec d'autres équipements ou objets
  • H01Q 1/36 - Forme structurale pour éléments rayonnants, p. ex. cône, spirale, parapluie

58.

TUNING DIELECTRIC MATERIAL IN A PATCH ANTENNA ARRAY

      
Numéro d'application US2024037357
Numéro de publication 2025/019229
Statut Délivré - en vigueur
Date de dépôt 2024-07-10
Date de publication 2025-01-23
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Fung, James F.
  • Johnson, Alexander D.
  • Kubwimana, Jean L.
  • Tamasy, Jacob

Abrégé

An antenna assembly includes a ground plane including conductive material, and a dielectric material above the ground plane. A patch antenna is on the dielectric material. In an example, a plurality of features extends from an upper surface or a lower surface of the dielectric material and within the dielectric material, wherein the plurality of features comprises voids filled with gas or are vacuum. Additionally, or alternatively, the dielectric material is doped with a dopant. In an example, the antenna assembly further includes a first aperture and a second aperture on the ground plane and below the patch antenna, and another dielectric material below the first and second apertures. In some such cases, a first feed line is below the first aperture, and a second feed line is below the second aperture.

Classes IPC  ?

  • H01Q 9/04 - Antennes résonnantes
  • H01Q 21/06 - Réseaux d'unités d'antennes, de même polarisation, excitées individuellement et espacées entre elles
  • H01Q 25/00 - Antennes ou systèmes d'antennes fournissant au moins deux diagrammes de rayonnement

59.

ADDITIVELY MANUFACTURED PROBE FED PATCH ANTENNA

      
Numéro d'application US2024037363
Numéro de publication 2025/019232
Statut Délivré - en vigueur
Date de dépôt 2024-07-10
Date de publication 2025-01-23
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Kubwimana, Jean L.
  • Johnson, Alexander D.
  • Dinbergs, Arturs E.
  • Tamasy, Jacob
  • Fung, James F.

Abrégé

A method of manufacturing an antenna assembly includes additively manufacturing an element that is monolithic and that includes (i) a ground plane, (ii) a patch above the ground plane, and (iii) a structure having a lower end in contact with the ground plane and an upper end in contact with the patch. The method further includes applying a dielectric material between the ground plane and the patch. In an example, the dielectric material is dielectric foam. The method further includes removing a section of the ground plane around the lower end of the structure, such that the structure extends through the ground plane and not in contact with the ground plane. The method further includes connecting an inner conductor of a coaxial cable connector to the lower end of the structure, and an outer portion of the coaxial cable connector to the ground plane.

Classes IPC  ?

  • H01Q 9/04 - Antennes résonnantes
  • B22F 10/40 - Structures destinées à soutenir des pièces ou des articles pendant la fabrication et retirées par la suite
  • B29C 64/10 - Procédés de fabrication additive
  • H01Q 21/06 - Réseaux d'unités d'antennes, de même polarisation, excitées individuellement et espacées entre elles

60.

TUNING DIELECTRIC MATERIAL IN A PATCH ANTENNA ARRAY

      
Numéro d'application 18352638
Statut En instance
Date de dépôt 2023-07-14
Date de la première publication 2025-01-16
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Fung, James F.
  • Johnson, Alexander D.
  • Kubwimana, Jean L.
  • Tamasy, Jacob

Abrégé

An antenna assembly includes a ground plane including conductive material, and a dielectric material above the ground plane. A patch antenna is on the dielectric material. In an example, a plurality of features extends from an upper surface or a lower surface of the dielectric material and within the dielectric material, wherein the plurality of features comprises voids filled with gas or are vacuum. Additionally, or alternatively, the dielectric material is doped with a dopant. In an example, the antenna assembly further includes a first aperture and a second aperture on the ground plane and below the patch antenna, and another dielectric material below the first and second apertures. In some such cases, a first feed line is below the first aperture, and a second feed line is below the second aperture.

Classes IPC  ?

61.

FIELD FLATTENING VIA INTERFERENCE FILTERS

      
Numéro d'application 18904503
Statut En instance
Date de dépôt 2024-10-02
Date de la première publication 2025-01-16
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s) Garan, Jacob D.

Abrégé

The present disclosure relates generally to a method of use for a field flattening interference filter. More particularly, the present disclosure relates a field flattening bandpass interference filter with the cut-on edge of the pass band at the system wavelength at a normal angle of incidence. Further discussed is a method to extend the field flattening design to work at multiple system wavelengths through the optimized design of a multi-band interference filter.

Classes IPC  ?

62.

HYBRID-PUMPED FIBER AMPLIFIER

      
Numéro d'application 18709678
Statut En instance
Date de dépôt 2021-11-19
Date de la première publication 2025-01-09
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Horton, Spencer L.
  • Allee, Ezra S.

Abrégé

Techniques to passively suppress or otherwise reduce stimulated Brillouin scattering (SBS) in a pumped fiber laser system. The system can be co-pumped with a tandem pumping technique, and counter-pumped with the direct diode pumping method. In an example, a pumped fiber laser system includes a fiber, a tandem pump, and a direct diode pump. The fiber has a core, an inner cladding around the core, and an outer cladding around the inner cladding. The tandem pump co-pumps light of a first wavelength in the inner cladding from a first end of the fiber, and the direct diode pump counter-pumps light of a second wavelength in the outer cladding from a second end of the fiber. A longitudinal temperature gradient can form along the fiber laser in response to this hybrid-pumping, which can combine both tandem and direct diode pumping.

Classes IPC  ?

  • H01S 3/067 - Lasers à fibre optique
  • H01S 3/094 - Procédés ou appareils pour l'excitation, p. ex. pompage utilisant le pompage optique par de la lumière cohérente
  • H01S 3/0941 - Procédés ou appareils pour l'excitation, p. ex. pompage utilisant le pompage optique par de la lumière cohérente produite par un laser à semi-conducteur, p. ex. par une diode laser
  • H01S 3/16 - Matériaux solides
  • H01S 3/23 - Agencement de plusieurs lasers non prévu dans les groupes , p. ex. agencement en série de deux milieux actifs séparés

63.

AUTHENTIFICATION DE SIGNAL SATELLITE GPS BASÉE SUR UN GAIN RELATIF À L'AIDE D'UNE ÉLECTRONIQUE D'ANTENNE DE FORMATION DE FAISCEAU

      
Numéro d'application US2024031577
Numéro de publication 2025/006115
Statut Délivré - en vigueur
Date de dépôt 2024-05-30
Date de publication 2025-01-02
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s) Weger, John J.

Abrégé

Techniques for satellite signal authentication. In an example, a Global Positioning System (GPS) or global navigation satellite system (GNSS) includes antenna electronics, a processor, and a GPS or GNSS receiver. The antenna electronics is configured to provide, to the GPS or GNSS receiver, signals, wherein the signals comprise GPS or GNSS satellite signals received from a set of GPS or GNSS satellites and/or one or more falsified signals, such as spoofer signals (falsified). The processor is configured to determine, based on an expected location of a respective GPS or GNSS satellite of the set of GPS or GNSS satellites, an expected gain or expected power for a respective signal of the signals. The GPS or GNSS receiver is configured to measure a power of the respective signal, compare the measured power to the expected gain or expected power, and determine whether the respective signal is falsified based on the comparison.

Classes IPC  ?

  • G01S 19/20 - Contrôle d'intégrité, détection ou isolation des défaillances du segment spatial
  • G01S 19/21 - Problèmes liés aux interférences
  • H04W 12/12 - Détection ou prévention de fraudes
  • G01S 19/37 - Détails de matériel ou de logiciel de la chaîne de traitement des signaux
  • H04K 3/00 - Brouillage de la communicationContre-mesures

64.

CAPACITOR STRUCTURE INTEGRATED WITH CONTACT PAD STRUCTURE

      
Numéro d'application US2024031602
Numéro de publication 2025/006117
Statut Délivré - en vigueur
Date de dépôt 2024-05-30
Date de publication 2025-01-02
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Wyckoff, Nathaniel P.
  • Mauermann, Jacob R.
  • Warren, Alexander S.
  • Klema, William J.

Abrégé

Integrated capacitor structures are described. In an example, an interconnect structure includes a first layer of conductive material and a second layer of conductive material. The first layer includes a first horizontal portion having a first opening and extending along a first horizontal plane, and a first vertical portion. The second layer includes a second horizontal portion having a second opening and extending along a second horizontal plane, and a second vertical portion. The interconnect structure also includes a dielectric extending along a third horizontal plane between the first and second horizontal portions, and having one or more openings. The first vertical component extends upward from the first horizontal portion, through one opening in the dielectric and the second opening of second layer, and the second vertical component extends downward from the second horizontal portion, through another opening in the dielectric and the first opening of first layer.

Classes IPC  ?

  • H01L 23/528 - Configuration de la structure d'interconnexion
  • H01G 4/248 - Bornes les bornes enveloppant ou entourant l'élément capacitif, p. ex. capsules
  • H01G 15/00 - Combinaisons structurelles de condensateurs ou d’autres dispositifs, couverts par au moins deux groupes principaux différents de la présente sous-classe, les uns avec les autres

65.

DIFFERENCE-BASED JAMMER DETECTION SYSTEM

      
Numéro d'application US2024031613
Numéro de publication 2025/006118
Statut Délivré - en vigueur
Date de dépôt 2024-05-30
Date de publication 2025-01-02
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Stockmaster, Michael H.
  • Lai, Ying Cho J.

Abrégé

Techniques are provided for jammer detection. A methodology implementing the techniques according to an embodiment includes steering a beam in a specified direction to generate a power measurement, the specified direction selected from a plurality of directions, such that the method comprises scanning through the plurality of directions. The method also includes adaptively steering a null in the specified direction and measuring a gain of the received signal in the null direction. The method further includes calculating a difference between the power measurement and the measured gain and generating a difference-based detection that the received signal is associated with a jammer at the specified direction. The difference-based detection is based on a comparison of the power difference to a power difference threshold value. The power difference threshold value is based on a desired probability of false alarm and probability of detection, and/or desired angular resolution.

Classes IPC  ?

  • H04K 3/00 - Brouillage de la communicationContre-mesures
  • H04N 5/232 - Dispositifs pour la commande des caméras de télévision, p.ex. commande à distance
  • G01S 3/786 - Systèmes pour déterminer une direction ou une déviation par rapport à une direction prédéterminée utilisant le réglage d'une orientation des caractéristiques de directivité d'un détecteur ou d'un système de détecteurs afin d'obtenir une valeur désirée du signal provenant de ce détecteur ou de ce système de détecteurs la valeur désirée étant maintenue automatiquement
  • G01S 19/21 - Problèmes liés aux interférences
  • G01S 19/23 - Test, contrôle, correction ou étalonnage d'un élément récepteur

66.

FEED FORWARD IMAGE BASED GUIDANCE

      
Numéro d'application US2024031617
Numéro de publication 2025/006119
Statut Délivré - en vigueur
Date de dépôt 2024-05-30
Date de publication 2025-01-02
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Batchelder, Jason H.
  • Chrobak, Matthew F.
  • Nickerson, Tyler
  • Spitsberg, Richie

Abrégé

A feed forward guidance kit for a ballistic device that includes at least one optical imaging sensor, a processor that is operatively in communication with the at least one optical imaging sensor, and a feed forward guidance protocol that is stored on a computer readable medium and that is operatively in communication with the processor. When the at least one optical imaging sensor initially intercepts an aircraft at an initial location during combat, the feed forward guidance protocol instructs the processor to proactively calculate an anticipated second position of the aircraft as an orientation of the aircraft changes from an initial orientation to a translated orientation.

Classes IPC  ?

  • F41G 9/00 - Systèmes de commande des missiles ou projectiles, non prévus ailleurs
  • F41G 7/34 - Systèmes de commande de guidage pour missiles autopropulsés basés sur des données prédéterminées de la position de la cible
  • F41G 7/22 - Systèmes autodirecteurs
  • B64C 39/02 - Aéronefs non prévus ailleurs caractérisés par un emploi spécial

67.

Feed forward image based guidance

      
Numéro d'application 18344362
Numéro de brevet 12326320
Statut Délivré - en vigueur
Date de dépôt 2023-06-29
Date de la première publication 2025-01-02
Date d'octroi 2025-06-10
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Batchelder, Jason H
  • Chrobak, Matthew F.
  • Nickerson, Tyler
  • Spitsberg, Richie

Abrégé

A feed forward guidance kit for a ballistic device that includes at least one optical imaging sensor, a processor that is operatively in communication with the at least one optical imaging sensor, and a feed forward guidance protocol that is stored on a computer readable medium and that is operatively in communication with the processor. When the at least one optical imaging sensor initially intercepts an aircraft at an initial location during combat, the feed forward guidance protocol instructs the processor to proactively calculate an anticipated second position of the aircraft as an orientation of the aircraft changes from an initial orientation to a translated orientation.

Classes IPC  ?

68.

Difference-based jammer detection system

      
Numéro d'application 18345023
Numéro de brevet 12184409
Statut Délivré - en vigueur
Date de dépôt 2023-06-30
Date de la première publication 2024-12-31
Date d'octroi 2024-12-31
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Stockmaster, Michael H.
  • Lai, Ying Cho J.

Abrégé

Techniques are provided for jammer detection. A methodology implementing the techniques according to an embodiment includes steering a beam in a specified direction to generate a power measurement, the specified direction selected from a plurality of directions, such that the method comprises scanning through the plurality of directions. The method also includes adaptively steering a null in the specified direction and measuring a gain of the received signal in the null direction. The method further includes calculating a difference between the power measurement and the measured gain and generating a difference-based detection that the received signal is associated with a jammer at the specified direction. The difference-based detection is based on a comparison of the power difference to a power difference threshold value. The power difference threshold value is based on a desired probability of false alarm and probability of detection, and/or desired angular resolution.

Classes IPC  ?

  • H04K 3/00 - Brouillage de la communicationContre-mesures
  • H01Q 3/26 - Dispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier la phase relative ou l’amplitude relative et l’énergie d’excitation entre plusieurs éléments rayonnants actifsDispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier la distribution de l’énergie à travers une ouverture rayonnante
  • H04B 7/0426 - Distribution de puissance

69.

HYBRID MB/ML TECHNIQUES FOR AUTOMATED PCB DEFECT DETECTION

      
Numéro d'application 18337827
Statut En instance
Date de dépôt 2023-06-20
Date de la première publication 2024-12-26
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Wang, Tao
  • Vo, Helen
  • Webb, Helen F.
  • Tom, Victor T.

Abrégé

Hybrid MB/ML techniques for automated printed circuit board (PCB) defect detection. In one example, a PCB inspection system implements a hybrid solution using model based (MB) and machine learning (ML) technologies to detect possible defects in a PCB via an automated image capture device and processing methodology. The processing methodology fuses features from MB and ML at the latent representation. An autoencoder can be used to learn the fused data by training a neural network to produce a reconstructed image that can be compared to an original image to generate a reconstruction error value. The system produces an output indicating detection of a defect in one or more features of interest based on the reconstruction error value transgressing a threshold value.

Classes IPC  ?

  • G06T 7/00 - Analyse d'image
  • G06V 10/44 - Extraction de caractéristiques locales par analyse des parties du motif, p. ex. par détection d’arêtes, de contours, de boucles, d’angles, de barres ou d’intersectionsAnalyse de connectivité, p. ex. de composantes connectées
  • G06V 10/774 - Génération d'ensembles de motifs de formationTraitement des caractéristiques d’images ou de vidéos dans les espaces de caractéristiquesDispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p. ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]Séparation aveugle de source méthodes de Bootstrap, p. ex. "bagging” ou “boosting”
  • G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux

70.

Collet for multiple wire elements

      
Numéro d'application 18340632
Numéro de brevet 12283801
Statut Délivré - en vigueur
Date de dépôt 2023-06-23
Date de la première publication 2024-12-26
Date d'octroi 2025-04-22
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Thoren, Matthew D.
  • Cobb, John C.

Abrégé

A collet for multiple wire elements is disclosed. In an example, the collet has a body made of a polymeric material and extends along a central axis from a first end to a second end. The body defines a first passageway extending axially through the body, the first passageway in communication with the environment via a first insertion opening extending along an entire length of the first passageway. The body defines a second passageway extending axially through the body and in communication with the environment along an entire length of the second passageway via a second insertion opening, the second passageway spaced circumferentially from the first passageway. When installed, the collet frictionally engages wire elements when a first wire element is seated in the first passageway and a second wire element is seated in the second passageway.

Classes IPC  ?

  • H02G 3/04 - Tubes ou conduits de protection, p. ex. échelles à câbles ou goulottes de câblage
  • H02G 1/06 - Méthodes ou appareils spécialement adaptés à l'installation, entretien, réparation, ou démontage des câbles ou lignes électriques pour poser les câbles, p. ex. appareils de pose sur véhicule

71.

METHODS FOR DELAYED DISPERSION OF CHAFF WITHIN COUNTERMEASURE EXPENDABLES

      
Numéro d'application 18701395
Statut En instance
Date de dépôt 2021-10-28
Date de la première publication 2024-12-19
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Dube, Mark J.
  • Elliott, William J.
  • Hyink, Parker T.
  • Plemons, Danny L.

Abrégé

Various countermeasure expendables and methods of using said countermeasure expendables are provided herein. A countermeasure expendable comprising a canister. The countermeasure expendable includes at least one countermeasure payload operably engaged inside the canister, the at least one countermeasure payload having a volume of countermeasure material. The countermeasure expendable includes a squib operably engaged inside of the canister, wherein the squib is configured to propel the at least one countermeasure payload outside of the canister. The countermeasure expendable includes at least one time delaying assembly operably engaged with the at least one countermeasure payload, wherein the time delaying assembly is configured to dispense the volume of countermeasure material from the at least one countermeasure payload at a predetermined time interval.

Classes IPC  ?

  • F42B 12/70 - Projectiles ou mines caractérisés par la charge militaire, l'effet recherché ou le matériau caractérisés par la nature de la charge militaire ou par l'effet recherché pour libérer des matériaux, des corps ou des particulesProjectiles ou mines caractérisés par la charge militaire, l'effet recherché ou le matériau caractérisés par la nature de la charge militaire ou par l'effet recherché pour produire une réaction chimique ou physiqueProjectiles ou mines caractérisés par la charge militaire, l'effet recherché ou le matériau caractérisés par la nature de la charge militaire ou par l'effet recherché pour la signalisation pour la libération de corps solides individuels pour la libération de paillettes antiradar ou de matériaux à émission infrarouge
  • F42B 5/15 - Cartouches, c.-à-d. projectile et douille avec charge propulsive formant un tout pour libérer des gaz, des vapeurs, des poudres, des particules ou des substances à réaction chimique adaptées pour créer un effet de brouillard ou de leurre, p. ex. en utilisant des paillettes anti-radar ou des corps à action infrarouge

72.

PANORAMIC MWIR LENS FOR COOLED DETECTORS

      
Numéro d'application 18333898
Statut En instance
Date de dépôt 2023-06-13
Date de la première publication 2024-12-19
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Oskotsky, Mark L.
  • Russo, Michael J.
  • Engheben, Daniel
  • Malabuyoc, Jacinto E.

Abrégé

A panoramic Mid-Wavelength Infrared (MWIR) lens has a plurality of optical elements, wherein each optical element from the plurality of elements is formed from a material that transmits in at least the MWIR band from 3 μm to 5 μm. The plurality of optical element are arranged in a manner that provides a 360 degree azimuth angle and an elevation angle that is within +/−20° from a 90° horizon. The panoramic MWIR lens is configured to be connected to a cooled Dewar, wherein the Dewar includes a cold shield and an image plane to detect light in the MWIR band transmitted through the plurality of optical elements.

Classes IPC  ?

  • G02B 13/06 - Objectifs panoramiquesLentilles dites "de ciel"
  • G02B 7/02 - Montures, moyens de réglage ou raccords étanches à la lumière pour éléments optiques pour lentilles
  • G02B 9/64 - Objectifs optiques caractérisés à la fois par le nombre de leurs composants et la façon dont ceux-ci sont disposés selon leur signe, c.-à-d. + ou — ayant plus de six composants
  • G02B 13/14 - Objectifs optiques spécialement conçus pour les emplois spécifiés ci-dessous à utiliser avec des radiations infrarouges ou ultraviolettes

73.

PANORAMIC MWIR LENS FOR COOLED DETECTORS

      
Numéro d'application US2024033208
Numéro de publication 2024/258770
Statut Délivré - en vigueur
Date de dépôt 2024-06-10
Date de publication 2024-12-19
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Oskotsky, Mark L.
  • Russo, Michael J.
  • Engheben, Daniel
  • Malabuyoc, Jacinto E.

Abrégé

A panoramic Mid-Wavelength Infrared (MWIR) lens has a plurality of optical elements, wherein each optical element from the plurality of elements is formed from a material that transmits in at least the MWIR band from 3μm to 5μm. The plurality of optical element are arranged in a manner that provides a 360 degree azimuth angle and an elevation angle that is within +/- 20° from a 90° horizon. The panoramic MWIR lens is configured to be connected to a cooled Dewar, wherein the Dewar includes a cold shield and an image plane to detect light in the MWIR band transmitted through the plurality of optical elements.

Classes IPC  ?

  • G02B 13/06 - Objectifs panoramiquesLentilles dites "de ciel"
  • G02B 9/64 - Objectifs optiques caractérisés à la fois par le nombre de leurs composants et la façon dont ceux-ci sont disposés selon leur signe, c.-à-d. + ou — ayant plus de six composants
  • G02B 13/14 - Objectifs optiques spécialement conçus pour les emplois spécifiés ci-dessous à utiliser avec des radiations infrarouges ou ultraviolettes
  • G02B 13/18 - Objectifs optiques spécialement conçus pour les emplois spécifiés ci-dessous avec des lentilles ayant une ou plusieurs surfaces non sphériques, p. ex. pour réduire l'aberration géométrique

74.

INLINE RESISTOR INTEGRATED WITH CONDUCTIVE CONTACT PAD STRUCTURE

      
Numéro d'application 18206731
Statut En instance
Date de dépôt 2023-06-07
Date de la première publication 2024-12-12
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Wyckoff, Nathaniel P.
  • Warren, Alexander S.
  • Mauermann, Jacob R.
  • Smith, Justin D.

Abrégé

An integrated circuit structure includes (i) a first layer including a first metal, (ii) a second layer above and in contact with the first layer, the second layer including a resistive material, and (iii) a third layer above and in contact with the second layer, the third layer including a second metal. In an example, the resistive material is different from one or both the first metal and the second metal. An interconnect component is above and in contact with the second layer. In an example, the interconnect component is a solder bump or a solder ball. In an example, a resistivity of the resistive material of the second layer is at least 20%, or at least 50% greater than a resistivity of each of the first and third layers. In an example, the resistive material includes a third metal different from the first and second metals and/or a metalloid.

Classes IPC  ?

  • H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

75.

INLINE RESISTOR INTEGRATED WITH CONDUCTIVE CONTACT PAD STRUCTURE

      
Numéro d'application US2024031389
Numéro de publication 2024/253912
Statut Délivré - en vigueur
Date de dépôt 2024-05-29
Date de publication 2024-12-12
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Wyckoff, Nathaniel P.
  • Warren, Alexander S.
  • Mauermann, Jacob R.
  • Smith, Justin D.

Abrégé

An integrated circuit structure includes (i) a first layer including a first metal, (ii) a second layer above and in contact with the first layer, the second layer including a resistive material, and (iii) a third layer above and in contact with the second layer, the third layer including a second metal. In an example, the resistive material is different from one or both the first metal and the second metal. An interconnect component is above and in contact with the second layer. In an example, the interconnect component is a solder bump or a solder ball. In an example, a resistivity of the resistive material of the second layer is at least 20%, or at least 50% greater than a resistivity of each of the first and third layers. In an example, the resistive material includes one or more of (i) a third metal different from the first and second metals, (ii) a metalloid, and (iii) the third metal and at least one of oxygen and nitrogen.

Classes IPC  ?

  • H01L 23/64 - Dispositions relatives à l'impédance
  • H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p. ex. contacts planaires

76.

CONDUCTIVE LINES FOR INTERCONNECTION IN STACKED DEVICE STRUCTURES

      
Numéro d'application US2024031393
Numéro de publication 2024/253914
Statut Délivré - en vigueur
Date de dépôt 2024-05-29
Date de publication 2024-12-12
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Wyckoff, Nathaniel P.
  • Terry, Benjamin
  • Warren, Alexander S.
  • Waggoner, Joseph

Abrégé

A microelectronics device structure includes a device having (i) a lower surface, (ii) an upper surface opposite the lower surface, and (iii) a side surface extending between the lower surface and the upper surface. The integrated circuit structure further includes a conductive line having (i) a first section on the upper surface, (ii) a second section on the side surface, and (iii) a third section on the lower surface. In an example, the first section and the second section of the conductive line is a monolithic conductive structure, with no seam or interface between the first section and the second section. Additionally or alternatively, in an example, the second section and the third section of the conductive line is a monolithic conductive structure, with no seam or interface between the second section and the third section.

Classes IPC  ?

  • H01L 23/498 - Connexions électriques sur des substrats isolants
  • H01L 23/49 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de structures soudées du type fils de connexion
  • H01L 23/492 - Embases ou plaques
  • H01L 23/495 - Cadres conducteurs
  • H05K 3/34 - Connexions soudées

77.

APPARATUS AND METHOD FOR AUTHENTICATING ADS-B TRACKS

      
Numéro d'application 18330880
Statut En instance
Date de dépôt 2023-06-07
Date de la première publication 2024-12-12
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Klappert, Andrew E.
  • Ringlen, David C.
  • Lavery, Richard J.
  • Saracino, Robert F.

Abrégé

A method for discriminating between spoofed and valid ADS-B tracks includes applying a plurality of spoofing detection tests to an ADS-B waveform, applying weighting factors to the resulting test scores, and combining the weighted scores to obtain a confidence level indicating whether the ADS-B track is valid or spoofed. The detection tests can include power level validation, Doppler offset, ADS-B rules-based analysis, multi-band detection, track origination detection, and antenna diversity. The selection of applied detection tests and/or weighting factors can be adjusted and/or selected from corresponding libraries, according to operating conditions. Tracks can be displayed together with confidence level indications, and/or excluded from display if their confidence levels are below an adjustable threshold. Weighting factors can be chosen and/or updated by a machine learning model according to success in detecting simulated and/or actual spoofed tracks. A spoofing attack can be declared according to the number of spoofed tracks detected.

Classes IPC  ?

  • H04W 12/122 - Contre-mesures pour parer aux attaquesProtection contre les dispositifs malveillants
  • H04L 9/40 - Protocoles réseaux de sécurité

78.

PATTERNING USING MONOMER BASED SACRIFICIAL MATERIAL LIFTOFF

      
Numéro d'application 18206325
Statut En instance
Date de dépôt 2023-06-06
Date de la première publication 2024-12-12
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Wyckoff, Nathaniel P.
  • Terry, Benjamin
  • Warren, Alexander S.

Abrégé

A method includes forming a plurality of islands of first material on a plurality of first sections of a layer. A plurality of second sections of the layer are not covered by the first material. The method further includes depositing a second material on (i) the islands of first material and (ii) the second sections of the layer that are not covered by the islands of first material. The method further includes evaporating and/or sublimating the islands of first material and removing remnants of the second material that were on the islands of the first material. In an example, the second material remains on the second sections of the layer, to thereby form a pattern of the second material on the layer. In an example, the first material is a monomer, and the second material is a conductor or a dielectric or a semiconductor.

Classes IPC  ?

  • H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
  • H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives

79.

CONDUCTIVE LINES FOR INTERCONNECTION IN STACKED DEVICE STRUCTURES

      
Numéro d'application 18206730
Statut En instance
Date de dépôt 2023-06-07
Date de la première publication 2024-12-12
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Wyckoff, Nathaniel P.
  • Terry, Benjamin
  • Warren, Alexander S.
  • Waggoner, Joseph

Abrégé

A microelectronics device structure includes a device having (i) a lower surface, (ii) an upper surface opposite the lower surface, and (iii) a side surface extending between the lower surface and the upper surface. The integrated circuit structure further includes a conductive line having (i) a first section on the upper surface, (ii) a second section on the side surface, and (iii) a third section on the lower surface. In an example, the first section and the second section of the conductive line is a monolithic conductive structure, with no seam or interface between the first section and the second section. Additionally or alternatively, in an example, the second section and the third section of the conductive line is a monolithic conductive structure, with no seam or interface between the second section and the third section.

Classes IPC  ?

  • H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

80.

ENHANCED PROCESSING TO DISCRIMINATE BETWEEN ADS B TRAFFIC/TRACKS WITH DUPLICATE AIRCRAFT ADDRESSES

      
Numéro d'application 18206905
Statut En instance
Date de dépôt 2023-06-07
Date de la première publication 2024-12-12
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Murphy, Michael S.
  • Russo, Domenico

Abrégé

A method of enhanced processing used to discriminate between ADS-B messages with a duplicate announced address comprising: receiving ADS-B messages that comprise information for display by a display of traffic information from at least two targets on a receiver; identifying the ADS-B messages having the duplicate announced address with one of the at least two targets using at least one discriminator by assigning a weighting factor to the at least one discriminator and, where the integration of the at least one discriminator and weighting factor exceeds a predetermined threshold value, considering the ADS-B messages that were subject to the at least one discriminator as being discriminated messages associated with one of the at least two targets; and displaying information provided by the discriminated messages on a display of traffic information as if the discriminated messages had been initially associated with only one of the at least two targets.

Classes IPC  ?

  • G08G 5/00 - Systèmes de contrôle du trafic aérien

81.

PATTERNING USING MONOMER BASED SACRIFICIAL MATERIAL LIFTOFF

      
Numéro d'application US2024031385
Numéro de publication 2024/253911
Statut Délivré - en vigueur
Date de dépôt 2024-05-29
Date de publication 2024-12-12
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Wyckoff, Nathaniel P.
  • Terry, Benjamin
  • Warren, Alexander S.

Abrégé

A method includes forming a plurality of islands of first material on a plurality of first sections of a layer. A plurality of second sections of the layer are not covered by the first material. The method further includes depositing a second material on (i) the islands of first material and (ii) the second sections of the layer that are not covered by the islands of first material. The method further includes evaporating and/or sublimating the islands of first material and removing remnants of the second material that were on the islands of the first material. In an example, the second material remains on the second sections of the layer, to thereby form a pattern of the second material on the layer. In an example, the first material is a monomer, and the second material is a conductor or a dielectric or a semiconductor.

Classes IPC  ?

  • H01L 21/32 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour former des couches isolantes en surface, p. ex. pour masquer ou en utilisant des techniques photolithographiquesPost-traitement de ces couchesEmploi de matériaux spécifiés pour ces couches en utilisant des masques
  • H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
  • H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou

82.

HYBRID SIGNAL ACQUISITION AND TRACKING DEVICE

      
Numéro d'application 17654308
Statut En instance
Date de dépôt 2022-03-10
Date de la première publication 2024-12-05
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Acheson, John E.
  • Dennis, Mitchell T.
  • Bader, John R.
  • Jump, Jordan M.

Abrégé

A signal acquisition and tracking device includes an input configured to receive a global navigation satellite system (GNSS) signal, a software-based processor configured to execute software instructions to acquire the GNSS signal via the input and to generate, based on the acquired signal, one or more signal tracking parameters, and a hardware logic circuit operatively coupled to the processor. The logic circuit is configured to track the GNSS signal independently of the processor using the one or more signal tracking parameters generated by the processor. In some examples, the processor is configured to pull in and center the GNSS signal in time and frequency, and the logic circuit is further configured to track the pulled in and centered GNSS signal independently of the processor. In some examples, the processor acquires the signal and then hands-off control to the logic circuit for subsequent tracking of the signal.

Classes IPC  ?

  • G01S 19/30 - Acquisition ou poursuite des signaux émis par le système lié au code
  • G01S 19/37 - Détails de matériel ou de logiciel de la chaîne de traitement des signaux

83.

RADIATION HARDENED E-FUSE MACRO

      
Numéro d'application 18800530
Statut En instance
Date de dépôt 2024-08-12
Date de la première publication 2024-12-05
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Ross, Jason F.

Abrégé

A multi-bit, asynchronous e-fuse macro, the macro comprising: an input output enable, a power on reset, a write address, an input write enable, a ground clamp enable, and a write clock; a plurality of e-fuse bits; a supply voltage configured to allow programming at least one of the e-fuse bits; at least one fuse output; and self-timing and control circuitry configured to perform signaling, wherein each of the inputs is in electrical communication with the e-fuse macro.

Classes IPC  ?

  • G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
  • G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
  • G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire

84.

ULTRA-WIDEBAND, MULTI-MODE, LOW-PROFILE, ENDFED ANTENNA

      
Numéro d'application 17877013
Statut En instance
Date de dépôt 2022-07-29
Date de la première publication 2024-12-05
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Charette, David P.
  • Fontaine, Daniel L.

Abrégé

A low profile, broadband radiator operates as a dielectric rod antenna (DRA) but is conformally mounted to a conducting sheet along its axis of symmetry. The new device exploits the imaging theory of electromagnetics to split the DRA in half while maintaining its full-height TEM feed, HE11 waveguide, and radiation taper characteristics. The disclosed device is attractive for applications requiring directed energy on or near the axis of the antenna, i.e. ‘end-fire’, and for high shock and velocity environments. Bandwidth extension is realized by adding one or more cores of higher dielectric material and by modifying the feed and mode formation regions. A second polarization is generated by configuring the feed for odd-mode transmission and creating a flared notch radiator within a metallized split launcher.

Classes IPC  ?

  • H01Q 9/04 - Antennes résonnantes
  • H01Q 13/08 - Terminaisons rayonnantes de lignes de transmission micro-ondes à deux conducteurs, p. ex. lignes coaxiales ou lignes micro-rayées

85.

SECURE PERIPHERAL SHARING DEVICE

      
Numéro d'application 18323675
Statut En instance
Date de dépôt 2023-05-25
Date de la première publication 2024-11-28
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Leibowitz, Mark E.
  • Drewitz, Jr., Edwin W.
  • Karamooz, Saeed
  • Schweikert, Jon P.
  • Aversano, William F.
  • Klavir, Susan J.

Abrégé

A peripheral sharing device includes an optical switch, a first signal interface, and a plurality of second signal interfaces. The first signal interface is coupled to the optical switch via a first optical fiber cable. The first signal interface is configured to be coupled to at least one peripheral device, such as a keyboard, pointing device, or video display. A first one of the second signal interfaces is coupled to the optical switch via a second optical fiber cable. A second one of the second signal interfaces is coupled to the optical switch via a third optical fiber cable. The first one of the second signal interfaces is configured to be coupled to a first computing device, and the second one of the second signal interfaces is configured to be coupled to a second computing device.

Classes IPC  ?

  • G06F 3/14 - Sortie numérique vers un dispositif de visualisation
  • G06F 3/023 - Dispositions pour convertir sous une forme codée des éléments d'information discrets, p. ex. dispositions pour interpréter des codes générés par le clavier comme codes alphanumériques, comme codes d'opérande ou comme codes d'instruction
  • H04Q 11/00 - Dispositifs de sélection pour systèmes multiplex

86.

HANDHELD NAVIGATION DEVICE

      
Numéro d'application 18322325
Statut En instance
Date de dépôt 2023-05-23
Date de la première publication 2024-11-28
Propriétaire BAE Systems Information and Electronic Systems Integration Inc (USA)
Inventeur(s)
  • Cogan, Kenneth P.
  • Heitz, Sean L.
  • Crockett, Kent A.
  • Graubard, Benjamin M.
  • Weighton, James K.
  • Stultz, Jimmey C.
  • Tattershall, Wayne D.
  • Smith, David R.
  • Mcelvogue, Matt
  • Schramm, Warren D.

Abrégé

A navigation device includes a display, an electromagnetic radiation (EMR) receiver, and one or more processors operatively coupled to the display and the EMR receiver. The one or more processors are configured to cause the display, in a first mode of operation, to graphically render a navigation view. The navigation view includes (i) a first informational element relating to a geographic location of the navigation device and (ii) one or both of a compass rose and a geographic map. The one or more processors are further configured to cause the display, in a second mode of operation and responsive to receiving an EMR signal via the EMR receiver, to render an informational view including a second informational element, where the informational view at least partially obscures the navigation view.

Classes IPC  ?

  • G06F 3/14 - Sortie numérique vers un dispositif de visualisation
  • G01C 21/36 - Dispositions d'entrée/sortie pour des calculateurs embarqués
  • G06F 3/02 - Dispositions d'entrée utilisant des interrupteurs actionnés manuellement, p. ex. des claviers ou des cadrans
  • G06T 11/60 - Édition de figures et de texteCombinaison de figures ou de texte

87.

LOW F NUMBER REFRACTIVE TELESCOPE WITH DYNAMIC ALTITUDE COMPENSATION

      
Numéro d'application 18319247
Statut En instance
Date de dépôt 2023-05-17
Date de la première publication 2024-11-21
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Powers, Michael J.
  • Grabowski, Matthew W.

Abrégé

A system and method are disclosed for a low F-number precision variable-focus telescope that includes a telescope housing containing an optical system. There is a first temperature sensing device to detect a temperature of the telescope housing, a second temperature sensing device to detect an ambient temperature around the telescope housing, and a pressure sensing device to detect ambient pressure around the telescope housing. A controller is in operative communication with the first temperature-sensing device, the second temperature sensing device, and the pressure sensing device. The control regulates the heater to maintain the telescope at a desired temperature to achieve diffraction limited performance in response to signals from the first temperature-sensing device, the second temperature sensing device, and the pressure sensing device.

Classes IPC  ?

  • G02B 23/16 - LogementsCouverclesMonturesSupports, p. ex. avec contrepoids
  • G02B 7/02 - Montures, moyens de réglage ou raccords étanches à la lumière pour éléments optiques pour lentilles
  • G02B 27/62 - Appareils optiques spécialement adaptés pour régler des éléments optiques pendant l'assemblage de systèmes optiques
  • G05D 23/19 - Commande de la température caractérisée par l'utilisation de moyens électriques

88.

LOW F NUMBER REFRACTIVE TELESCOPE WITH DYNAMIC ALTITUDE COMPENSATION

      
Numéro d'application US2024027986
Numéro de publication 2024/238187
Statut Délivré - en vigueur
Date de dépôt 2024-05-06
Date de publication 2024-11-21
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Powers, Michael J.
  • Grabowski, Matthew W.

Abrégé

A system and method are disclosed for a low F-number precision variable-focus telescope that includes a telescope housing containing an optical system. There is a first temperature sensing device to detect a temperature of the telescope housing, a second temperature sensing device to detect an ambient temperature around the telescope housing, and a pressure sensing device to detect ambient pressure around the telescope housing. A controller is in operative communication with the first temperature-sensing device, the second temperature sensing device, and the pressure sensing device. The control regulates the heater to maintain the telescope at a desired temperature to achieve diffraction limited performance in response to signals from the first temperature-sensing device, the second temperature sensing device, and the pressure sensing device.

Classes IPC  ?

  • G02B 23/16 - LogementsCouverclesMonturesSupports, p. ex. avec contrepoids
  • G02B 7/04 - Montures, moyens de réglage ou raccords étanches à la lumière pour éléments optiques pour lentilles avec mécanisme de mise au point ou pour faire varier le grossissement
  • G05D 23/275 - Commande de la température caractérisée par l'utilisation de moyens électriques avec l'élément sensible se dilatant, se contractant, ou fondant en fonction des variations de température
  • H04N 23/52 - Éléments optimisant le fonctionnement du capteur d'images, p. ex. pour la protection contre les interférences électromagnétiques [EMI] ou la commande de la température par des éléments de transfert de chaleur ou de refroidissement

89.

FIRMWARE EVENT STACK ROUTING

      
Numéro d'application 18319201
Statut En instance
Date de dépôt 2023-05-17
Date de la première publication 2024-11-21
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Lam, Mei I.

Abrégé

A computer firmware product improves computer processing efficiency by implementing a process to replicate at least one field index in multiple register destinations. A translation table contains data in a plurality of fields and a plurality of register destination addresses for a firmware event. The firmware product pushes data associated with one field to at least two different register destination addresses. The firmware product recompiles the translation table with the updated data pushed from one field to the two different register destination addresses. Then, the firmware product performs a function based on the translation table with the updated data pushed from the one field to the two different register destination addresses by solely changing the translation table.

Classes IPC  ?

  • G06F 9/54 - Communication interprogramme
  • G06F 8/41 - Compilation
  • G06F 16/27 - Réplication, distribution ou synchronisation de données entre bases de données ou dans un système de bases de données distribuéesArchitectures de systèmes de bases de données distribuées à cet effet

90.

INTERPOSER FOR IMPLEMENTING FLIP-CHIP DIES IN WIREBONDED CIRCUIT ASSEMBLIES

      
Numéro d'application 18313526
Statut En instance
Date de dépôt 2023-05-08
Date de la première publication 2024-11-14
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Campbell, Nicholas L.
  • Kraemer, Andrew M.

Abrégé

An interposer that enables implementation of a flip-chip die in a wirebonded chip-and-wire circuit assembly includes an insulating substrate having a solder bump pad array on its upper surface that is compatible with the solder bump array of a flip-chip die. Wirebond pads provided along upper edges of the substrate are interconnected to at least some of the solder bump pads. Bonding the interposer to the circuit assembly housing floor, or through an opening to an underlying motherboard, places the wirebond pads proximate attachment points of adjacent wirebond dies, enabling wirebonding therebetween. Attachment pads on the interposer lower surface, in combination with interconnecting traces and vias, can enable connection directly through the housing opening to the underlying motherboard. Support components can be included within an edge cavity created beneath an overhang of a multi-layer substrate. A heat absorbing plate can be attached to the top of the flip-chip die.

Classes IPC  ?

  • H01L 23/498 - Connexions électriques sur des substrats isolants
  • H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
  • H01L 23/12 - Supports, p. ex. substrats isolants non amovibles
  • H01L 23/367 - Refroidissement facilité par la forme du dispositif
  • H01L 23/495 - Cadres conducteurs
  • H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés

91.

Additive manufacturing compatible liquid-cooled PCB chassis

      
Numéro d'application 18195538
Numéro de brevet 12178010
Statut Délivré - en vigueur
Date de dépôt 2023-05-10
Date de la première publication 2024-11-14
Date d'octroi 2024-12-24
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Berkenbush, Richard E.
  • Scholl, Robert E.
  • Thanos, Meredith T.
  • Foster, Robert S.

Abrégé

A liquid-cooled printed circuit board chassis, such as a Eurocard chassis, is manufactured without brazing by 3D printing a plurality of components, smoothing and completing the components by subtractive manufacture, and then aligning and assembling the final chassis, all without application of heat. Horizontal cooling channels 3D printed within the chassis components are in thermal contact with board slots, and are divided into subchannels by closely spaced internal walls that function as thermal baffles. The baffles are tilted at oblique angles to increase their cooling efficiency, and to enable AM manufacture without temporary support structures. Elastomer seals between components can connect the cooling channels to vertical connecting channels. EMI seals can be formed between the components by EMI gaskets. The components can be aligned by alignment pins, and joined together by bolts, screws, and/or adhesives. An intermediate horizontal extension can be included to accommodate shorter printed circuit boards.

Classes IPC  ?

  • H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage
  • H05K 5/00 - Enveloppes, coffrets ou tiroirs pour appareils électriques
  • H05K 7/18 - Structure des bâtis ou des cadres
  • B33Y 10/00 - Procédés de fabrication additive
  • B33Y 40/20 - Posttraitement, p. ex. durcissement, revêtement ou polissage
  • B33Y 80/00 - Produits obtenus par fabrication additive

92.

COOLANT FLOW PARTITION FOR COOLING 3U BOARDS IN 6U CHASSIS

      
Numéro d'application US2024027976
Numéro de publication 2024/233460
Statut Délivré - en vigueur
Date de dépôt 2024-05-06
Date de publication 2024-11-14
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Berkenbush, Richard E.
  • Scholl, Robert E.
  • Thanos, Meredith T.
  • Foster, Robert S.

Abrégé

A chassis configured to hold a cards of at least two form factors comprising: slots disposed in an inner portion the chassis, wherein the slots are aligned with one another and configured to act as card guides; a mid-height structure disposed adjacent a side wall of the chassis, the mid-height structure comprising a second plurality of slots and a third plurality of slots disposed on top and bottom surfaces of the mid-height structure that are substantially parallel to top and bottom walls of the chassis; and a plurality of cooling channels disposed within the walls of the chassis as well as within the mid-height structure, wherein the second and third plurality of slots are configured to align with at least a subset of the plurality of slots disposed in the top and bottom chassis walls and to act as card guides.

Classes IPC  ?

  • H05K 7/00 - Détails de construction communs à différents types d'appareils électriques
  • H05K 7/14 - Montage de la structure de support dans l'enveloppe, sur cadre ou sur bâti
  • H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage

93.

ADDITIVE MANUFACTURING COMPATIBLE LIQUID-COOLED PCB CHASSIS

      
Numéro d'application US2024027979
Numéro de publication 2024/233463
Statut Délivré - en vigueur
Date de dépôt 2024-05-06
Date de publication 2024-11-14
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Berkenbush, Richard E.
  • Scholl, Robert E.
  • Thanos, Meredith T.
  • Foster, Robert S.

Abrégé

A liquid-cooled printed circuit board chassis, such as a Eurocard chassis, is manufactured without brazing by 3D printing a plurality of components, smoothing and completing the components by subtractive manufacture, and then aligning and assembling the final chassis, all without application of heat. Horizontal cooling channels 3D printed within the chassis components are in thermal contact with board slots, and are divided into subchannels by closely spaced internal walls that function as thermal baffles. The baffles are tilted at oblique angles to increase their cooling efficiency, and to enable AM manufacture without temporary support structures. Elastomer seals between components can connect the cooling channels to vertical connecting channels. EMI seals can be formed between the components by EMI gaskets. The components can be aligned by alignment pins, and joined together by bolts, screws, and/or adhesives. An intermediate horizontal extension can be included to accommodate shorter printed circuit boards.

Classes IPC  ?

  • H05K 7/14 - Montage de la structure de support dans l'enveloppe, sur cadre ou sur bâti
  • H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage
  • G06F 1/20 - Moyens de refroidissement
  • H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
  • B33Y 80/00 - Produits obtenus par fabrication additive

94.

Coolant flow partition for cooling 3U boards in 6U chassis

      
Numéro d'application 18195623
Numéro de brevet 12295122
Statut Délivré - en vigueur
Date de dépôt 2023-05-10
Date de la première publication 2024-11-14
Date d'octroi 2025-05-06
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Berkenbush, Richard E.
  • Scholl, Robert E.
  • Thanos, Meredith T.
  • Foster, Robert S.

Abrégé

A chassis configured to hold a cards of at least two form factors comprising: slots disposed in an inner portion the chassis, wherein the slots are aligned with one another and configured to act as card guides; a mid-height structure disposed adjacent a side wall of the chassis, the mid-height structure comprising a second plurality of slots and a third plurality of slots disposed on top and bottom surfaces of the mid-height structure that are substantially parallel to top and bottom walls of the chassis; and a plurality of cooling channels disposed within the walls of the chassis as well as within the mid-height structure, wherein the second and third plurality of slots are configured to align with at least a subset of the plurality of slots disposed in the top and bottom chassis walls and to act as card guides.

Classes IPC  ?

  • H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage
  • G06F 1/18 - Installation ou distribution d'énergie
  • G06F 1/20 - Moyens de refroidissement

95.

INTERPOSER FOR IMPLEMENTING FLIP-CHIP DIES IN WIREBONDED CIRCUIT ASSEMBLIES

      
Numéro d'application US2024027975
Numéro de publication 2024/233459
Statut Délivré - en vigueur
Date de dépôt 2024-05-06
Date de publication 2024-11-14
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s)
  • Campbell, Nicholas L.
  • Kraemer, Andrew M.

Abrégé

An interposer that enables implementation of a flip-chip die in a wirebonded chip-and-wire circuit assembly includes an insulating substrate having a solder bump pad array on its upper surface that is compatible with the solder bump array of a flip-chip die. Wirebond pads provided along upper edges of the substrate are interconnected to at least some of the solder bump pads. Bonding the interposer to the circuit assembly housing floor, or through an opening to an underlying motherboard, places the wirebond pads proximate attachment points of adjacent wirebond dies, enabling wirebonding therebetween. Attachment pads on the interposer lower surface, in combination with interconnecting traces and vias, can enable connection directly through the housing opening to the underlying motherboard. Support components can be included within an edge cavity created beneath an overhang of a multi-layer substrate. A heat absorbing plate can be attached to the top of the flip-chip die.

Classes IPC  ?

  • H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
  • H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe

96.

Non-integer interpolation for signal sampling at asynchronous clock rates

      
Numéro d'application 18309896
Numéro de brevet 12160494
Statut Délivré - en vigueur
Date de dépôt 2023-05-01
Date de la première publication 2024-11-07
Date d'octroi 2024-12-03
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s)
  • Wasson, Daniel
  • Crawford, Anthony J.
  • Zalucki, Michael A.

Abrégé

Techniques are provided for non-integer interpolation for signal sampling. A system implementing the techniques according to an embodiment includes a memory configured to store frequency values associated with an input signal sampled at a first clock rate. The system also includes a clock phase detector configured to detect phase alignment between a first clock signal associated with the first clock rate and a second clock signal associated with a second clock rate. The system further includes a read circuit configured to adjust an interpolation time interval in response to the detected phase alignment and to read the frequency values from the memory at the adjusted interpolation time interval. The system further includes a phase accumulator configured to accumulated phase as a sum of the frequency values read from the memory. The system further includes a waveform generator configured to generate an output waveform sample based on the accumulated phase.

Classes IPC  ?

  • H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur

97.

SHOCK ISOLATOR FOR NON HARDENED SYSTEMS

      
Numéro d'application 18312350
Statut En instance
Date de dépôt 2023-05-04
Date de la première publication 2024-11-07
Propriétaire BAE Systems Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Estridge, Michael R.

Abrégé

A shock absorbing apparatus that includes a baseplate adapted to be mounted on a platform, a flexure member that operably engages with the baseplate, and a mounting plate that operably engages with the flexure member. The mounting plate is free from direct engagement with the baseplate and is moveable between a neutral position and a translated position with respect to the baseplate. The mounting plate is also adapted to hold a device. The flexure member is adapted to absorb shock forces caused by a ballistic shock event or a projectile motion event in proximity to or applied on the platform.

Classes IPC  ?

  • F16F 15/02 - Suppression des vibrations dans les systèmes non rotatifs, p. ex. dans des systèmes alternatifsSuppression des vibrations dans les systèmes rotatifs par l'utilisation d'organes ne se déplaçant pas avec le système rotatif

98.

HYBRID RADAR JAMMING AND COMMUNICATION APPARATUS

      
Numéro d'application 18317618
Statut En instance
Date de dépôt 2023-05-15
Date de la première publication 2024-11-07
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Mouille, David A.

Abrégé

A hybrid electronic warfare and communications system (EW/COMM) eliminates the space, power, weight, and cost of a dedicated communication system by exchanging messages with other nodes in a network as phase modulations of radar jamming signals. Some embodiments impose message phase modulations onto CW jamming signals, while other embodiments interleave message phase modulations with pseudorandom phase modulations of the jamming signals. Message chip rates can be matched to pseudorandom phase modulation chip rates. Messages are thereby obfuscated as either phase noise or random phase modulation of the jamming signals. Messages can be encoded as BPSK or QPSK modulations. Messages can be preceded by pre-established headers known to other nodes, and distinguished thereby from random noise modulations. Some embodiments include a dedicated COMMS module and/or antenna, while other embodiments implement the communications function mostly or entirely in software. Messages can be encrypted before transmission and decrypted after reception.

Classes IPC  ?

  • G01S 7/38 - Moyens de brouillage, p. ex. production de faux échos
  • G01S 7/02 - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe
  • H04K 3/00 - Brouillage de la communicationContre-mesures

99.

SYNCHRONIZATION OF DIGITAL ANTENNA CONTROLLER DATA FOR APPLICATIONS USING ASYNCHRONOUS INTERFACES

      
Numéro d'application US2024024574
Numéro de publication 2024/226333
Statut Délivré - en vigueur
Date de dépôt 2024-04-15
Date de publication 2024-10-31
Propriétaire BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. (USA)
Inventeur(s) Weger, John J.

Abrégé

A Global Positioning System (GPS) digital antenna controller is provided, comprising antenna electronics, a code generator, and an interface. The antenna electronics can be configured to receive a GPS signal. The code generator can be configured to generate a pilot code signal that is synchronized to the DAE local clock reference. The interface can be configured to send the GPS signal and the code signal to a GPS receiver. A system may comprise the GPS digital antenna controller and GPS receiver. The GPS receiver can comprise a second code generator and a processor configured to resolve a timing difference based on the pilot code signal and a second code signal of the second code generator. The controller may be remote from the receiver. The interface may comprise an asynchronous data interface (e.g., Ethernet, USB, Infiniband, or Firewire). To resolve the timing difference may involve GPS code and carrier tracking.

Classes IPC  ?

  • G01S 1/00 - Radiophares ou systèmes de balisage émettant des signaux ayant une ou des caractéristiques pouvant être détectées par des récepteurs non directionnels et définissant des directions, situations ou lignes de position déterminées par rapport aux émetteurs de radiophareRécepteurs travaillant avec ces systèmes
  • G01S 1/08 - Systèmes pour déterminer une direction ou une ligne de position
  • G01S 1/14 - Systèmes pour déterminer une direction ou une ligne de position utilisant la comparaison d'amplitude de signaux transmis simultanément à partir d'antennes ou de systèmes d'antennes ayant des caractéristiques directionnelles de recouvrement orientées différemment
  • G01S 1/04 - Radiophares ou systèmes de balisage émettant des signaux ayant une ou des caractéristiques pouvant être détectées par des récepteurs non directionnels et définissant des directions, situations ou lignes de position déterminées par rapport aux émetteurs de radiophareRécepteurs travaillant avec ces systèmes utilisant les ondes radioélectriques Détails
  • G01S 1/20 - Systèmes pour déterminer une direction ou une ligne de position en comparant les temps de transit de signaux synchronisés provenant d'antennes non directionnelles ou de systèmes d'antennes séparés, c.-à-d. systèmes à différence de parcours
  • G01S 19/00 - Systèmes de positionnement par satellite à radiopharesDétermination de position, de vitesse ou d'attitude au moyen de signaux émis par ces systèmes
  • H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur

100.

SYNCHRONIZATION OF DIGITAL ANTENNA CONTROLLER DATA FOR APPLICATIONS USING ASYNCHRONOUS INTERFACES

      
Numéro d'application 18308095
Statut En instance
Date de dépôt 2023-04-27
Date de la première publication 2024-10-31
Propriétaire BAE SYSTEMS Information and Electronic Systems Integration Inc. (USA)
Inventeur(s) Weger, John Jay

Abrégé

A Global Positioning System (GPS) digital antenna controller is provided, comprising antenna electronics, a code generator, and an interface. The antenna electronics can be configured to receive a GPS signal. The code generator can be configured to generate a pilot code signal that is synchronized to the DAE local clock reference. The interface can be configured to send the GPS signal and the code signal to a GPS receiver. A system may comprise the GPS digital antenna controller and GPS receiver. The GPS receiver can comprise a second code generator and a processor configured to resolve a timing difference based on the pilot code signal and a second code signal of the second code generator. The controller may be remote from the receiver. The interface may comprise an asynchronous data interface (e.g., Ethernet, USB, Infiniband, or Firewire). To resolve the timing difference may involve GPS code and carrier tracking.

Classes IPC  ?

  • G01S 19/13 - Récepteurs
  • G01S 19/07 - Éléments coopérantsInteraction ou communication entre les différents éléments coopérants ou entre les éléments coopérants et les récepteurs fournissant des données pour corriger les données de positionnement mesurées, p. ex. DGPS [GPS différentiel] ou corrections ionosphériques
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