A method is provided for preparing a semiconductor-on-insulator structure comprising a silicon oxynitride layer having a gradient oxygen concentration.
A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.
A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
6.
METHODS FOR PROCESSING SEMICONDUCTOR WAFERS HAVING A POLYCRYSTALLINE FINISH
A method of processing a semiconductor wafer includes depositing a silicon layer on the semiconductor wafer. A first slurry is applied to the semiconductor wafer and the silicon layer is polished to smooth the silicon layer. A second slurry is applied to the semiconductor wafer. The second slurry includes a greater amount of a caustic agent than the first slurry.
A preheat ring (126) for use in a chemical vapor deposition system includes a first portion and a second portion selectively coupled to the first portion such that the first and second portions combine to form an opening configured to receive a susceptor therein. Each of the first and second portions is independently moveable with respect to each other.
C23C 16/458 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour supporter les substrats dans la chambre de réaction
8.
EPITAXIAL GROWTH OF DEFECT-FREE, WAFER-SCALE SINGLE-LAYER GRAPHENE ON THIN FILMS OF COBALT
THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS (USA)
Inventeur(s)
Berry, Vikas
Behura, Sanjay
Nguyen, Phong
Seacrist, Michael R.
Abrégé
A method for depositing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate is provided. Due to the strong adhesion of graphene and cobalt to a semiconductor substrate, the layer of graphene is epitaxially deposited.
DAEVAC INTERNATIONAL CO., LTD. (République de Corée)
Inventeur(s)
Yun, Seok Min
Park, Seong Su
Ji, Jun Hwan
Choi, Won-Jin
Jung, Uisung
Lee, Young Jung
Koo, Tae Su
Kim, Sung-Jin
Abrégé
A feed assembly supplies polysilicon to a growth chamber for growing a crystal ingot from a melt. An example system includes a housing having support rails for receiving one of a granular tray and a chunk tray and a feed material reservoir positioned above the support rails to selectively feed one of either the granular tray or the chunk tray. A valve mechanism and pulse vibrator are also disclosed.
C30B 15/02 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski en introduisant dans le matériau fondu le matériau à cristalliser ou les réactifs le formant in situ
The disclosed method is suitable for producing a SiGe-on-insulator structure. According to some embodiments of the method, a layer comprising SiGe is deposited on silicon-on-insulator substrate comprising an ultra-thin silicon top layer. In some embodiments, the layer comprising SiGe is deposited by epitaxial deposition. In some embodiments, the SiGe epitaxial layer is high quality since it is produced by engineering the strain relaxation at the Si/buried oxide interface. In some embodiments, the method accomplishes elastic strain relaxation of SiGe grown on a few monolayer thick Si layer that is weakly bonded to the underline oxide.
The disclosed method is suitable for producing a semiconductor-on-insulator structure, such as a Ge(Si)-on-insulator structure or a Ge-on-insulator structure. According to the method, a multilayer comprising alternating pairs of layers, comprising a layer of silicon and a layer of germanium optionally with silicon is deposited on a silicon substrate comprising a germanium buffer layer. The multilayer is completed with a silicon passivation layer. A cleave plane is formed within the multilayer, and the multilayer structure is bonded to a handle substrate comprising a dielectric layer. The multilayer structure is cleaved along the cleave plane to thereby prepare a semiconductor-on-insulator structure comprising a semiconductor handle substrate, a dielectric layer, a silicon passivation layer, and at least a portion of the alternating pairs of layers, comprising a layer of silicon and a layer of germanium optionally with silicon.
A method of processing a semiconductor wafer includes depositing a silicon layer on the semiconductor wafer. The silicon layer has a substantially uniform thickness. The silicon layer is polished to smooth the silicon layer such that the thickness is substantially uniform after polishing.
A dopant feeding device for releasing dopant into a feeder system during doping of a crystal growing system includes a dopant container for holding the dopant, a lower valve, and an upper valve. The dopant container includes a wall defining a lower opening for releasing the dopant therethrough. The lower valve is positioned adjacent to the lower opening and is movable between a closed position that is in contact with the wall to prevent passage of dopant through the lower opening and an open position that is spaced from the lower opening to allow passage of dopant therethrough. The upper valve is positioned above and connected to the lower valve. The upper valve is disposed within the dopant container and is movable between a first position that is spaced from the dopant container and a second position that is in contact with the dopant container.
C30B 15/04 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski en introduisant dans le matériau fondu le matériau à cristalliser ou les réactifs le formant in situ avec addition d'un matériau de dopage, p. ex. pour une jonction n–p
C30B 15/02 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski en introduisant dans le matériau fondu le matériau à cristalliser ou les réactifs le formant in situ
C30B 15/00 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski
A single crystal semiconductor handle substrate for use in the manufacture of semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure is etched to form a porous layer in the front surface region of the wafer. The etched region is oxidized and then filled with a semiconductor material, which may be polycrystalline or amorphous. The surface is polished to render it bondable to a semiconductor donor substrate. Layer transfer is performed over the polished surface thus creating semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure having 4 layers: the handle substrate, the composite layer comprising filled pores, a dielectric layer (e.g., buried oxide), and a device layer. The structure can be used as initial substrate in fabricating radiofrequency chips. The resulting chips have suppressed parasitic effects, particularly, no induced conductive channel below the buried oxide.
A method of growing a doped monocrystalline ingot using a crystal growing system is provided. The crystal growing system includes a growth chamber, a dopant feeding device, and a feed tube. The method includes preparing a melt of semiconductor or solar- grade material in a crucible disposed within the growth chamber, introducing a solid dopant into the feed tube with the dopant feeding device, melting the solid dopant within the feed tube to a form a liquid dopant, introducing the liquid dopant into the melt below a surface of the melt, and growing a monocrystalline ingot from the melt by contacting the melt with a seed crystal and pulling the seed crystal away from the melt.
C30B 15/04 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski en introduisant dans le matériau fondu le matériau à cristalliser ou les réactifs le formant in situ avec addition d'un matériau de dopage, p. ex. pour une jonction n–p
A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.
A system for growing a crystal ingot from a melt includes a housing and a feed system. The housing defines a growth chamber and an ingot removal chamber positioned above the growth chamber. The feed system includes an enclosure, a feed material reservoir positioned within the enclosure, and a feed channel including an intake end and an outlet end. The intake end is configured to receive feed material from the feed material reservoir. The housing has an opening in communication with the removal chamber and a connector proximate the opening, and the enclosure has an opening and a connector configured to mate with the housing connector. The feed channel is moveable between a retracted position and an extended position in which the feed channel extends through the opening in the housing and the outlet end is positioned within the removal chamber.
C30B 15/00 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski
C30B 35/00 - Appareillages non prévus ailleurs, spécialement adaptés à la croissance, à la production ou au post-traitement de monocristaux ou de matériaux polycristallins homogènes de structure déterminée
Donor structures having a germanium buffer layer for preparing silicon-germanium-on-insulator structures by layer transfer are disclosed. Bonded structures and methods for preparing silicon-germanium-on-insulator structures by a layer transfer method are also disclosed.
A method is provided for forming Group IIIA-nitride layers, such as GaN, on substrates. The Group IIIA-nitride layers may be deposited on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates. The Group IIIA-nitride layers may be deposited by heteroepitaxial deposition on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates.
Systems and methods for processing semiconductor structures are provided. The methods generally include determining a desired removal map profile for a device layer of a semiconductor structure, determining a set of process parameters for use in an epitaxial smoothing process based on the desired removal map profile, and selectively removing material from the device layer by performing an epitaxial smoothing process on an outer surface of the device layer.
A method performs phase shift interferometry to detect irregularities of a surface of a wafer after the wafer has been placed into an interferometer and while the wafer is vibrating. Additionally, a system and a non-transitory computer-readable storage medium have computer-executable instructions embodied thereon for performing phase shift interferometry to detect irregularities of a surface of a wafer after the wafer has been placed into an interferometer and while the wafer is vibrating.
A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.
A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
A method of preparing a semiconductor-on-insulator (e.g., silicon-on-insulator) structure, and more particularly a method for producing an integrated circuit device on a semiconductor-on-insulator structure is provided. The method comprises forming multiple integrated circuit device types on a semiconductor-on-insulator structure in different regions of the device layer. The integrate circuit device types include a module of radiofrequency devices and a module of CMOS devices.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
25.
HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION
A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and comprises a region of nitrogen-reacted nanovoids in the front surface region; a silicon dioxide layer on the surface of the semiconductor handle substrate; a dielectric layer in contact with the silicon dioxide layer; and a semiconductor device layer in contact with the dielectric layer.
A polishing head assembly for single side polishing of silicon wafers is provided. The polishing head assembly includes a polishing head and a cap. The polishing head has a recess along a bottom portion, the recess having a recessed surface. The cap is positioned within the recess, and has an annular wall and a floor extending across the annular wall. The floor is spaced from the recessed surface to form a chamber therebetween. The chamber is configured to be pressurized for deflecting the floor. The annular wall is attached to the polishing head with an adhesive.
A method of preparing an iron-implanted semiconductor wafer for use in surface photovoltage iron mapping and other evaluation techniques. A semiconductor wafer is implanted with iron through the at least two different regions of the front surface of the semiconductor at different iron implantation densities, and the iron-implanted semiconductor wafer is annealed at a temperature and duration sufficient to diffuse implanted iron into the bulk region of the semiconductor wafer.
A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor nitride layer in contact with the semiconductor handle substrate, the semiconductor nitride layer selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof; a dielectric layer in contact with the semiconductor nitride layer; and a semiconductor device layer in contact with the dielectric layer.
A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm: a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.
A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a silicon dioxide layer on the surface of the semiconductor handle substrate; a carbon-doped amorphous silicon layer in contact with the silicon dioxide layer; a dielectric layer in contact with the carbon-doped amorphous silicon layer; and a semiconductor device layer in contact with the dielectric layer.
NITROGEN DOPED AND VACANCY DOMINATED SILICON INGOT AND THERMALLY TREATED WAFER FORMED THEREFROM HAVING RADIALLY UNIFORMLY DISTRIBUTED OXYGEN PRECIPITATION DENSITY AND SIZE
Nitrogen-doped CZ silicon crystal ingots and wafers sliced therefrom are disclosed that provide for post epitaxial thermally treated wafers having oxygen precipitate density and size that are substantially uniformly distributed radially and exhibit the lack of a significant edge effect. Methods for producing such CZ silicon crystal ingots are also provided by controlling the pull rate from molten silicon, the temperature gradient and the nitrogen concentration. Methods for simulating the radial bulk micro defect size distribution, radial bulk micro defect density distribution and oxygen precipitation density distribution of post epitaxial thermally treated wafers sliced from nitrogen-doped CZ silicon crystals are also provided.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
32.
METHODS FOR PREPARING LAYERED SEMICONDUCTOR STRUCTURES
Methods for preparing layered semiconductor structures are disclosed. The methods may involve pretreating an ion-implanted donor wafer by annealing the ion-implanted donor wafer to cause a portion of the ions to out-diffuse prior to wafer bonding. The donor structure may be bonded to a handle structure and cleaved without re-implanting ions into the donor structure.
A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.
A method for controlling oxygen precipitation in a single crystal silicon wafer having a wafer resistivity of less than about 10 milliohm-cm is provided so that the wafer has uniformly high oxygen precipitation behavior from the central axis to the circumferential edge. The single crystal silicon wafer comprises an additional dopant selected from among carbon, arsenic, and antimony.
H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p. ex. pour produire des défectuosités internes
A dopant feeding device for releasing dopant into a feeder system during doping of a crystal growing system includes a dopant container for holding the dopant, a lower valve, and an upper valve. The dopant container includes a wall defining a lower opening for releasing the dopant therethrough. The lower valve is positioned adjacent to the lower opening and is movable between a closed position that is in contact with the wall to prevent passage of dopant through the lower opening and an open position that is spaced from the lower opening to allow passage of dopant therethrough. The upper valve is positioned above and connected to the lower valve. The upper valve is disposed within the dopant container and is movable between a first position that is spaced from the dopant container and a second position that is in contact with the dopant container.
C30B 15/02 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski en introduisant dans le matériau fondu le matériau à cristalliser ou les réactifs le formant in situ
An method for producing a silicon ingot includes melting polycrystalline silicon in a crucible enclosed in a vacuum chamber to form a melt, generating a cusped magnetic field within the vacuum chamber, dipping a seed crystal into the melt, withdrawing the seed crystal from the melt to pull a single crystal that forms the silicon ingot, wherein the silicon ingot has a diameter greater than about 150 millimeters (mm), and simultaneously regulating a plurality of process parameters such that the silicon ingot has an oxygen concentration less than about 5 parts per million atoms (ppma). The plurality of process parameters include a wall temperature of the crucible, a transport of silicon monoxide (SiO) from the crucible to the single crystal, and an evaporation rate of SiO from the melt.
The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.
A method of removing dust from granular polysilicon includes introducing a stream of granular polysilicon, dispersing the longitudinal stream of granular polysilicon by redirecting the stream into a radially outward flow having a circular pattern, and introducing a counter flow of gas in an opposite direction to that of the longitudinal stream of granular polysilicon to contact the radially outward flow to separate the dust from the granular polysilicon.
A method for reducing light point defects of a semiconductor-on-insulator structure and a method for reducing the surface roughness of a semiconductor-on-insulator structure are disclosed. The methods can include a combination of thermally annealing the structure followed by a non-contact smoothing process.
A crystal pulling apparatus for producing an ingot is provided. The apparatus includes a furnace and a gas doping system. The furnace includes a crucible for holding a melt. The gas doping system includes a feeding tube, an evaporation receptacle, and a fluid flow restrictor. The feeding tube is positioned within the furnace, and includes at least one feeding tube sidewall, a first end through which a solid dopant is introduced into the feeding tube, and an opening opposite the first end through which a gaseous dopant is introduced into the furnace. The evaporation receptacle is configured to vaporize the dopant therein, and is disposed near the opening of the feeding tube. The fluid flow restrictor is configured to permit the passage of solid dopant therethrough and restrict the flow of gaseous dopant therethrough, and is disposed within the feeding tube between the first end and the evaporation receptacle.
C30B 15/04 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski en introduisant dans le matériau fondu le matériau à cristalliser ou les réactifs le formant in situ avec addition d'un matériau de dopage, p. ex. pour une jonction n–p
41.
METHODS FOR POST - EPITAXIAL WARP PREDICTION AND CONTROL
In one aspect, a method of predicting warp in a plurality of wafers after an epitaxial layer deposition process is provided. The method includes receiving, by a processor, a measured resistivity of a first wafer of the plurality of wafers, receiving, by the processor, a measured shape of the first wafer after at least one of a grinding process and an etching process, and calculating, using the processor, a change in wafer shape during the epitaxial layer deposition process. The method further includes superposing, using the processor, the calculated shape change onto the measured shape of the first wafer to determine a post-epitaxial wafer shape and calculating, using the processor, a post-epitaxial warp value based on the determined post-epitaxial wafer shape.
A method of growing a monocrystalline silicon ingot is described. The method includes the steps of providing a monocrystalline ingot growing apparatus including a chamber having an internal pressure, and a crucible disposed within the chamber, preparing a silicon melt in the crucible, introducing an inert gas into the chamber from a gas inlet above the silicon melt, wherein the inert gas flows over the surface of the silicon melt and has a flow rate, introducing a volatile dopant including indium into the silicon melt, growing an indium-doped monocrystalline silicon ingot, and controlling the indium dopant concentration in the ingot by adjusting the ratio of the inert gas flow rate and the internal pressure of the chamber.
C30B 15/04 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski en introduisant dans le matériau fondu le matériau à cristalliser ou les réactifs le formant in situ avec addition d'un matériau de dopage, p. ex. pour une jonction n–p
A solar cell is provided, the solar cell fabricated from an indium-doped monocrystalline silicon wafer sliced from an ingot grown by the Czochralski method. The solar cell is characterized by high efficiency and low light induced degradation.
C30B 15/04 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski en introduisant dans le matériau fondu le matériau à cristalliser ou les réactifs le formant in situ avec addition d'un matériau de dopage, p. ex. pour une jonction n–p
Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p. ex. pour produire des défectuosités internes
H01L 21/463 - Traitement mécanique, p. ex. meulage, traitement par ultrasons
H01L 21/687 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension en utilisant des moyens mécaniques, p. ex. mandrins, pièces de serrage, pinces
45.
METHOD FOR LOW TEMPERATURE LAYER TRANSFER IN THE PREPARATION OF MULTILAYER SEMICONDUCTOR DEVICES
A method of preparing a monocrystalline donor substrate, the method comprising (a) implanting helium ions through the front surface of the monocrystalline donor substrate to an average depth D1 as measured from the front surface toward the central plane; (b) implanting hydrogen ions through the front surface of the monocrystalline donor substrate to an average depth D2 as measured from the front surface toward the central plane; and (c) annealing the monocrystalline donor substrate at a temperature sufficient to form a cleave plane in the monocrystalline donor substrate. The average depth D1 and the average depth D2 are within about 1000 angstroms.
Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/687 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension en utilisant des moyens mécaniques, p. ex. mandrins, pièces de serrage, pinces
H01L 21/463 - Traitement mécanique, p. ex. meulage, traitement par ultrasons
H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p. ex. pour produire des défectuosités internes
H01L 21/302 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour changer leurs caractéristiques physiques de surface ou leur forme, p. ex. gravure, polissage, découpage
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
H01L 21/687 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension en utilisant des moyens mécaniques, p. ex. mandrins, pièces de serrage, pinces
48.
LIQUID DOPING SYSTEMS AND METHODS FOR CONTROLLED DOPING OF SINGLE CRYSTAL SEMICONDUCTOR MATERIAL
A doping system for introducing liquid dopant into a melt of semiconductor or solar-grade material includes a dopant reservoir for holding dopant and a feeding tube. The dopant reservoir includes a body and a tapered end defining an opening having a smaller cross-sectional area than a cross- sectional area of the body. The feeding tube includes a first end extending from the opening of the reservoir, a second end distal from the first end, an angled tip disposed at the second end of the feeding tube, a first restriction for inhibiting the passage of solid dopant through the feeding tube, and a second restriction for controlling the flow of liquid dopant, the second restriction disposed near the second end of the feeding tube.
C30B 15/04 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski en introduisant dans le matériau fondu le matériau à cristalliser ou les réactifs le formant in situ avec addition d'un matériau de dopage, p. ex. pour une jonction n–p
A dopant funnel for loading dopant pellets into a dispenser tube of a dopant dispenser is disclosed. The dopant funnel has a cup connected through a restrictor to a shaft. The cup holds randomly oriented dopant pellets. The restrictor meters the amount and orientation of dopant pellets being removed from the cup. The shaft is in alignment with the restrictor for delivering dopant pellets from the cup to the dispenser tube.
C30B 15/04 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski en introduisant dans le matériau fondu le matériau à cristalliser ou les réactifs le formant in situ avec addition d'un matériau de dopage, p. ex. pour une jonction n–p
50.
DOUBLE SIDE POLISHER WITH PLATEN PARALLELISM CONTROL
A platen for polishing a surface of a wafer has a reaction plate, a polishing plate, and a bladder. The reaction plate has a top and bottom surface, and defines a longitudinal axis. The polishing plate is positioned coaxially with the reaction plate. The polishing plate has a second top surface and a second bottom surface. The second top surface is adjacent to the bottom surface of the reaction plate. The bladder is coaxially located along a radially outer portion of either the top or bottom surface of the reaction plate. The bladder is connected with the polishing plate and able to expand to deform the polishing plate with respect to the bottom surface of the reaction plate.
B24B 37/08 - Machines ou dispositifs de rodageAccessoires conçus pour travailler les surfaces planes caractérisés par le déplacement de la pièce ou de l'outil de rodage pour un rodage double face
B24B 37/12 - Plateaux de rodage pour travailler les surfaces planes
51.
PRODUCTION OF HIGH PRECIPITATE DENSITY WAFERS BY ACTIVATION OF INACTIVE OXYGEN PRECIPITATE NUCLEI BY HEAT TREATMENT
Processes for the treatment of silicon wafers to form a high density non-uniform distribution of oxygen precipitate nuclei therein such that, upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, the wafers form oxygen precipitates in the bulk and a precipitate-free zone near the surface are disclosed. The processes involve activation of inactive oxygen precipitate nuclei by performing heat treatments between about 400°C and about 600C for at least about 1 hour.
A method for melting granular polysilicon in a crucible to reduce silicon splatter includes melting a quantity of polysilicon in the crucible at a first pressure and a first argon flow rate to the crucible to form molten silicon, increasing pressure from the first pressure to a second pressure, and increasing the first argon flow rate to a second argon flow rate. The method also includes supplying granular polysilicon into the crucible at the second pressure and the second argon flow rate and decreasing the pressure to a pressure less than the second pressure and decreasing the argon flow rate to an argon flow rate less than the second argon flow rate after supplying the granular polysilicon into the crucible.
C30B 15/02 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski en introduisant dans le matériau fondu le matériau à cristalliser ou les réactifs le formant in situ
C30B 35/00 - Appareillages non prévus ailleurs, spécialement adaptés à la croissance, à la production ou au post-traitement de monocristaux ou de matériaux polycristallins homogènes de structure déterminée
A method of loading a crucible includes loading a first layer of polysilicon chunks into the crucible and loading a second layer of granular polysilicon into the crucible to form a polysilicon charge such that the packing density of the polysilicon charge within the crucible is greater than 0.70.
C30B 11/04 - Croissance des monocristaux par simple solidification ou dans un gradient de température, p. ex. méthode de Bridgman-Stockbarger en introduisant dans le bain fondu le matériau à cristalliser ou les réactifs le formant in situ
C30B 15/02 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski en introduisant dans le matériau fondu le matériau à cristalliser ou les réactifs le formant in situ
Apparatus and methods for wafer processes such as etching and chemical vapor deposition processes are disclosed. In some embodiments, the apparatus includes a susceptor and a ring disposed beneath the susceptor to influence a thickness of the deposited epitaxial layer.
C23C 16/458 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour supporter les substrats dans la chambre de réaction
C23C 16/52 - Commande ou régulation du processus de dépôt
H01L 21/687 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension en utilisant des moyens mécaniques, p. ex. mandrins, pièces de serrage, pinces
55.
SYSTEM FOR MACHINING SEED RODS FOR USE IN A CHEMICAL VAPOR DEPOSITION POLYSILICON REACTOR
A method for machining a profile into a silicon seed rod using a machine. The silicon seed rod is capable of being used in a chemical vapor deposition polysilicon reactor. The machine includes a plurality of grinding wheels. The method includes grinding a v-shaped profile into a first end of the silicon seed rod with one of the plurality of grinding wheels and grinding a conical profile in a second end of the silicon seed rod with another of the plurality of grinding wheels.
B24B 49/12 - Appareillage de mesure ou de calibrage pour la commande du mouvement d'avance de l'outil de meulage ou de la pièce à meulerAgencements de l'appareillage d'indication ou de mesure, p. ex. pour indiquer le début de l'opération de meulage impliquant des dispositifs optiques
B24B 19/00 - Machines ou dispositifs conçus spécialement pour une opération particulière de meulage non couverte par d'autres groupes principaux
B24B 7/16 - Machines ou dispositifs conçus pour une seule opération particulière pour meuler des faces d'extrémités de pièces, p. ex. de calibres, de rouleaux, d'écrous ou de segments de piston
Methods and systems for use in detecting an air pocket in a single crystal material are described. One example method includes providing a matrix including a plurality of data units, the plurality of data units including image data related to a region of interest of the single crystal material; determining, by a processor, a difference between data units of the matrix and a corresponding data unit of the matrix, wherein the corresponding data unit is defined by a first operation of the matrix; calculating, by the processor, a first index value based on the differences of the corresponding data units; and identifying an air pocket within the single crystal material based on the first index value and a predetermined threshold.
Systems and methods are disclosed for controlling the surface profiles of wafers cut in a wire saw machine. The systems and methods described herein are generally operable to alter the nanotopology of wafers sliced from an ingot (30) by controlling the shape of the wafers. The shape of the wafers is altered by changing the temperature and/or flow rate of a temperature-controlling fluid that comes in contact with the ingot (30). Different feedback systems can be used to determine the temperature of the fluid necessary to generate wafers having the desired shape and/or nanotopology.
B28D 5/00 - Travail mécanique des pierres fines, pierres précieuses, cristaux, p. ex. des matériaux pour semi-conducteursAppareillages ou dispositifs à cet effet
B28D 5/04 - Travail mécanique des pierres fines, pierres précieuses, cristaux, p. ex. des matériaux pour semi-conducteursAppareillages ou dispositifs à cet effet par outils autres que ceux du type rotatif, p. ex. par des outils animés d'un mouvement alternatif
58.
SYSTEMS AND METHODS FOR CONTROLLING SURFACE PROFILES OF WAFERS SLICED IN A WIRE SAW
Systems (100) and methods are disclosed for controlling the surface profiles of wafers cut in a wire saw machine (103). The systems and methods described herein are generally operable to alter the nanotopology of wafers sliced from an ingot (102) by controlling the shape of the wafers. The shape of the wafers is altered by changing the temperature and/or flow rate of a temperature-controlling fluid circulated in fluid communication with bearings (114) supporting wire guides (106) of the saw. Different feedback systems can be used to determine the temperature of the fluid necessary to generate wafers having the desired shape and/or nanotopology.
B28D 5/00 - Travail mécanique des pierres fines, pierres précieuses, cristaux, p. ex. des matériaux pour semi-conducteursAppareillages ou dispositifs à cet effet
59.
METHODS AND SYSTEMS FOR REMOVING CONTAMINATION FROM A WIRE OF A SAW
A system (100) for ultrasonically cleaning one or more wires (102) of a wire saw (104) for slicing semiconductor or solar material (105) into wafers. The system (100) includes an ultrasonic transducer (302) connected to a sonotrode (304). The system (100) also includes a sonotrode plate adjacent to one or more of the wires (102). The sonotrode plate has an opening that exposes the sonotrode (304) to one or more of the wires (102). The system (100) further includes a tank (202) for delivering a flow of liquid to contact the sonotrode (304) and one or more of the wires (102). The tank (202) is positioned on the same side of the wires (102) as the sonotrode plate. The ultrasonic transducer (302) is configured to vibrate and form cavitations in the liquid for the removal of contaminants from a surface of one or more of the wires (102).
B08B 7/02 - Nettoyage par des procédés non prévus dans une seule autre sous-classe ou un seul groupe de la présente sous-classe par distorsion, battage ou vibration de la surface à nettoyer
B08B 3/12 - Nettoyage impliquant le contact avec un liquide avec traitement supplémentaire du liquide ou de l'objet en cours de nettoyage, p. ex. par la chaleur, par l'électricité ou par des vibrations par des vibrations soniques ou ultrasoniques
B28D 5/00 - Travail mécanique des pierres fines, pierres précieuses, cristaux, p. ex. des matériaux pour semi-conducteursAppareillages ou dispositifs à cet effet
60.
SAW FOR CUTTING SILICON INTO SEED RODS FOR USE IN A CHEMICAL VAPOR DEPOSITION POLYSILICON REACTOR
Saw for cutting silicon into seed rods for use in a chemical vapor deposition polysilicon reactor Systems and methods are provided for cutting silicon into seed rods for use in a chemical vapor deposition polysilicon reactor. A method includes cutting the silicon ingot with saw blades into silicon slabs, rotating the silicon slabs, and cutting the silicon slabs into smaller-sized silicon seed rods for use in the chemical vapor deposition polysilicon reactor.
B28D 5/02 - Travail mécanique des pierres fines, pierres précieuses, cristaux, p. ex. des matériaux pour semi-conducteursAppareillages ou dispositifs à cet effet par outils rotatifs, p. ex. par forets
61.
METHODS AND SYSTEMS FOR MONITORING AND CONTROLLING SILICON ROD TEMPERATURE
Systems and methods are disclosed for monitoring and controlling silicon rod temperature. One example is a method of monitoring a surface temperature of at least one silicon rod in a chemical vapor deposition (CVD) reactor during a CVD process. The method includes capturing an image of an interior of the CVD reactor. The image includes a silicon rod. The image is scanned to identify a left edge of the silicon rod and a right edge of the silicon rod. A target area is identified midway between the left edge and the right edge. A temperature of the silicon rod in the target area is determined.
C23C 14/00 - Revêtement par évaporation sous vide, pulvérisation cathodique ou implantation d'ions du matériau composant le revêtement
C01B 33/035 - Préparation par décomposition ou réduction de composés de silicium gazeux ou vaporisés autres que la silice ou un matériau contenant de la silice par décomposition ou réduction de composés de silicium gazeux ou vaporisés en présence de filaments chauffés de silicium, de carbone ou d'un métal réfractaire, p. ex. de tantale ou de tungstène, ou en présence de tiges de silicium chauffées sur lesquelles le silicium formé se dépose avec obtention d'une tige de silicium, p. ex. procédé Siemens
C23C 16/52 - Commande ou régulation du processus de dépôt
C23C 16/46 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour le chauffage du substrat
Systems and methods are provided for cleaning an interior surface of a chemical vapor deposition reactor bell used in the production of polysilicon. In one method, the reactor bell is positioned atop a frame; a first actuator is operated such that the brush engages the interior surface of the reactor bell. A flow of liquid is directed from a nozzle against the interior surface of the reactor bell, and a second actuator is operated to rotate the brush.
Systems and methods are provided for controlling silicon rod temperature. In one example, a method of controlling a surface temperature of at least one silicon rod in a chemical vapor deposition (CVD) reactor during a CVD process is presented. The method includes determining an electrical resistance of the at least one silicon rod, comparing the resistance to a set point to determine a difference, and controlling a power supply to control a power output coupled to the at least one silicon rod to minimize an absolute value of the difference.
C23C 16/52 - Commande ou régulation du processus de dépôt
C23C 16/44 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement
C01B 33/035 - Préparation par décomposition ou réduction de composés de silicium gazeux ou vaporisés autres que la silice ou un matériau contenant de la silice par décomposition ou réduction de composés de silicium gazeux ou vaporisés en présence de filaments chauffés de silicium, de carbone ou d'un métal réfractaire, p. ex. de tantale ou de tungstène, ou en présence de tiges de silicium chauffées sur lesquelles le silicium formé se dépose avec obtention d'une tige de silicium, p. ex. procédé Siemens
64.
TOOL FOR HARVESTING POLYCRYSTALLINE SILICON-COATED RODS FROM A CHEMICAL VAPOR DEPOSITION REACTOR
A tool for harvesting polycrystalline silicon-coated rods from a chemical vapor deposition reactor includes a body including outer walls sized for enclosing the rods within the outer walls. Each outer wall includes a door for allowing access to at least one of the rods.
C01B 33/035 - Préparation par décomposition ou réduction de composés de silicium gazeux ou vaporisés autres que la silice ou un matériau contenant de la silice par décomposition ou réduction de composés de silicium gazeux ou vaporisés en présence de filaments chauffés de silicium, de carbone ou d'un métal réfractaire, p. ex. de tantale ou de tungstène, ou en présence de tiges de silicium chauffées sur lesquelles le silicium formé se dépose avec obtention d'une tige de silicium, p. ex. procédé Siemens
65.
SHELL AND TUBE HEAT EXCHANGERS AND METHODS OF USING SUCH HEAT EXCHANGERS
Shell and tube heat exchangers that include a baffle arrangement that improves the temperature profile and flow pattern throughout the exchanger and/or that are integral with a reaction vessel are disclosed. Methods for using the exchangers including methods that involve use of the exchanger and a reaction vessel to produce a reaction product gas containing trichlorosilane are also disclosed.
F28D 7/16 - Appareils échangeurs de chaleur comportant des ensembles de canalisations tubulaires fixes pour les deux sources de potentiel calorifique, ces sources étant en contact chacune avec un côté de la paroi d'une canalisation les canalisations étant espacées parallèlement
F28F 9/22 - Dispositions pour diriger les sources de potentiel calorifique dans des compartiments successifs, p. ex. aménagement des plaques de guidage
66.
BELL JAR FOR SIEMENS REACTOR INCLUDING THERMAL RADIATION SHIELD
A bell jar for a Siemens reactor of the type used to deposit polycrystalline silicon on a plurality of heated silicon rods via chemical vapor deposition process. The bell jar includes a thermally conductive inner wall having an interior surface at least partially defining an interior space adapted to receive the plurality of heated silicon rods therein. A thermal radiation shield is in the interior space generally adjacent to and in opposing relationship with the interior surface of the inner wall. The thermal radiation shield is substantially opaque to thermal radiation emitted from the plurality of heated silicon rods in the interior space of the bell jar.
C01B 33/035 - Préparation par décomposition ou réduction de composés de silicium gazeux ou vaporisés autres que la silice ou un matériau contenant de la silice par décomposition ou réduction de composés de silicium gazeux ou vaporisés en présence de filaments chauffés de silicium, de carbone ou d'un métal réfractaire, p. ex. de tantale ou de tungstène, ou en présence de tiges de silicium chauffées sur lesquelles le silicium formé se dépose avec obtention d'une tige de silicium, p. ex. procédé Siemens
brevets
