This reception device RX comprise: a first A/D converter 1 connected to an input terminal; a second A/D converter 2 connected to the input terminal; a phase detector 3 having input terminals connected to a first output terminal of the first A/D converter 1 and a second output terminal of the second A/D converter 2; a loop filter 5 connected to an output terminal of the phase detector 3; and a voltage-controlled oscillator 6 having an input terminal connected to an output terminal of the loop filter 5. A first sampling clock signal of the first A/D converter 1 and a second sampling clock signal of the second A/D converter 2 are generated from an output signal of the voltage-controlled oscillator 6 and have the phase difference of π/2.
H03L 7/08 - Détails de la boucle verrouillée en phase
H03L 7/085 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie
H03M 1/82 - Convertisseurs numériques/analogiques avec conversion intermédiaire en intervalle de temps
This amplification device 1 includes a first amplification unit 10, a second amplification unit 20, an amplitude detection unit 30, and a control unit 40. The first amplification unit 10 can be set to any gain from among a plurality of discrete gains. The first amplification unit 10 converts an input current signal into a voltage signal on the basis of the set gain, and outputs the converted voltage signal to the second amplification unit 20. The second amplification unit 20 can be set to any gain within a continuously variable gain range. The second amplification unit 20 amplifies the voltage signal output from the first amplification unit 10 on the basis of the set gain, and outputs the amplified voltage signal. The control unit 40 controls the gain of each of the first amplification unit 10 and the second amplification unit 20 so that the amplitude detected by the amplitude detection unit 30 is constant.
H03F 3/08 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs commandés par la lumière
A light-emitting element driving device 1 outputs a current signal for driving a light-emitting element 2, and includes a load 10, a differential circuit 20, a balanced-to-unbalanced conversion circuit 30, and a dummy load 40. The balanced-to-unbalanced conversion circuit 30 has a first input end 31, a second input end 32, a first output end 33, and a second output end 34. The first input end 31 is connected to a first node N1. The second input end 32 is connected to a second node N2. The first output terminal 33 is connected to the light-emitting element 2. The second output end 34 is connected to the dummy load 40. The balanced-to-unbalanced conversion circuit 30 includes a balun 50. The balun 50 has a configuration in which a first inductor and a second inductor are electromagnetically coupled to each other.
H10H 20/00 - Dispositifs individuels émetteurs de lumière à semi-conducteurs inorganiques ayant des barrières de potentiel, p. ex. diodes électroluminescentes [LED]
4.
RECEPTION DEVICE AND TRANSMISSION/RECEPTION SYSTEM
Provided is a reception device that has a deskew function which enables estimation of an accurate skew amount in a short time at wide data rates. A reception device 20 comprises a clock delay unit 21, a sampling unit 22, and a delay amount setting unit 23. The clock delay unit 21 provides a received clock with a delay and outputs the clock with the delay. The sampling unit 22 samples a received data signal at a timing indicated by the clock output from the clock delay unit 21. The delay amount setting unit 23 sequentially sets a clock delay amount to each value in a training period in which a training data signal and the clock are transmitted from a transmission device 10, acquires a data string that the sampling unit 22 has output by sampling the training data signal at each setting value, and, after the end of the training period, sets a clock delay amount within a matching range in which the data string acquired at each setting value matches the training data signal.
A current control unit 10 of a phase interpolation circuit 1 includes M slice circuits 60B0 to 60BM-1 having a common configuration. Each slice circuit 60Bm includes a selector 61, a PMOS transistor 62, an NMOS transistor 63, a PMOS transistor 64, an NMOS transistor 65, a first standby voltage set circuit 70, and a second standby voltage set circuit 80. The first standby voltage set circuit 70 has a configuration connecting the first node N1 and the voltage source via a switch the on/off of which is set according to the output signal from the selector 61, and sets the first node N1 to a standby voltage by supplementarily charging and discharging the parasitic capacitance of the first node N1 when the switch is in the on state.
A voltage/current conversion device 1A comprises a current supply circuit 10A, a differential circuit 20A, a step-up unit 30, a control unit 40A, etc. The current supply circuit 10A includes a first NMOS transistor 11, a second NMOS transistor 12, a first resistor 13, and a second resistor 14. The differential circuit 20A includes a first NPN transistor 21, a second NPN transistor 22, and a tail current source 23. The step-up unit 30 applies, to the respective gates of the first NMOS transistor 11 and the second NMOS transistor 12, a potential equal to or greater than the power source potential.
H03F 3/34 - Amplificateurs de courant continu dans lesquels tous les étages sont couplés en courant continu
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
09 - Appareils et instruments scientifiques et électriques
37 - Services de construction; extraction minière; installation et réparation
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
(Based on 44(e)): Electric wires and electric cables; telecommunication machines and apparatus, namely, telecommunication cables, telecommunication exchangers, telecommunication switches, telephone receivers, audiovisual receivers, radio receivers, GPS receivers, video receivers, optical receivers, mobile data receivers, electronic signal receivers, and telecommunication transmitters; electronic machines and apparatus and their component parts, namely, bar-code scanners, image scanners, digital film scanners, document scanners, document printers, computer printers, video printers, photo printers, display units for computers in the nature of computer monitors and large scale integrated circuits; electric and magnetic meters and testers used for reading and testing water quality, biological samples, cellular characteristics, insulation withstand voltage and large scale integration (LSI); power distribution and control machines and apparatus, namely, electrical power distribution units, power controllers and amplifiers, and electrical power supplies; downloadable and recorded computer programs used for large scale integration configuration; downloadable and recorded computer programs for use in designing integrated circuits; downloadable and recorded computer programs for use in designing semiconductor intellectual property cores as hardware and software; semiconductor intellectual property cores as hardware and software; (Based on Use in Commerce) integrated circuits Maintenance of semiconductor intellectual property cores as hardware; providing information on maintenance of semiconductor intellectual property cores as hardware; advice on maintenance of semiconductor intellectual property cores as hardware Providing temporary use of online non-downloadable computer programs for use in designing integrated circuits; providing temporary use of online non-downloadable computer programs for use in designing semiconductor intellectual property cores as hardware and software; providing temporary use of online non-downloadable software used for data networks, namely, software for transmitting data, receiving data, storing data, processing data, securing networks, optimizing networks, and managing networks; design, creation and maintenance of computer programs for use in designing integrated circuits; design, creation and maintenance of computer programs for use in designing semiconductor intellectual property cores as hardware and software; design, creation and maintenance of computer programs; design, development and maintenance of integrated circuits; providing information on design, development and maintenance of integrated circuits; instruction and advice on design, development and maintenance of integrated circuits; design and development of semiconductor intellectual property cores as hardware; design, development and maintenance of semiconductor intellectual property cores as software; providing information on design and development of semiconductor intellectual property cores as hardware; providing information on design, development and maintenance of semiconductor intellectual property cores as software; instruction and advice on design and development of semiconductor intellectual property cores as hardware; instruction and advice on design, development and maintenance of semiconductor intellectual property cores as software; designing of machines, apparatus and instruments including their component parts used for designing integrated circuits and semiconductor intellectual property cores and providing facilities comprised of the aforementioned machines, apparatus and instruments; testing and research on integrated circuits; testing and research on semiconductor intellectual property cores as hardware and software
This reception device comprises: a special code detection circuit 2 which outputs a first correction value DET-COM; a byte alignment circuit 3 which performs byte alignment according to the first correction value DET-COM outputted from the special code detection circuit 2; and a decoder 4. The decoder 4 comprises a data string generation circuit 41 which generates a plurality of data strings from an output signal from the byte alignment circuit 3, and a correction value generation circuit 43 to which a plurality of error signals that have performed error determination of the plurality of data strings outputted from the data string generation circuit 41 are inputted, and which generates a second correction value θK including information relating to a data string in which no error occurs. Even before the reception of a special code, byte alignment can be performed according to the second correction value θK.
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
H04L 7/04 - Commande de vitesse ou de phase au moyen de signaux de synchronisation
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
A phase adjustment circuit 11 of this reception signal quality monitor can perform a phase sweep of a sampling clock signal φｅof a reference sampler, within a phase range that is a multiple of a unit interval (UI) of a serial data signal. A first synchronization circuit 13A receives input of a first output signal from one sampler included in a plurality of data reception samplers, and a second output signal from a reference sampler SMe. A comparative logic circuit 15 receives input of a first output signal and a second output signal output synchronously from the first synchronization circuit 13A. The comparative logic circuit 15 outputs comparison results pertaining to the quality of the reception signal.
H04B 17/309 - Mesure ou estimation des paramètres de qualité d’un canal
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
10.
TRANSMISSION DEVICE, RECEPTION DEVICE, AND TRANSMISSION/RECEPTION SYSTEM
This transmission/reception system comprises a transmission device 10 and a reception device. The transmission device 10 comprises a combining unit 40 and a transmission unit 50. The combining unit 40 inputs a DE signal, video data (active data, blank data), and non-video data, combines the video data and the non-video data according to a prescribed rule, and outputs the combined data. The transmission unit 50 inputs the combined data that has been output from the combining unit 40, inserts BS data and BE data into this combined data, and transmits the combined data after this insertion to a transmission path 30.
H04N 21/238 - Interfaçage de la voie descendante du réseau de transmission, p. ex. adaptation du débit de transmission d'un flux vidéo à la bande passante du réseauTraitement de flux multiplexés
H04N 21/435 - Traitement de données additionnelles, p. ex. décryptage de données additionnelles ou reconstruction de logiciel à partir de modules extraits du flux de transport
H04N 21/438 - Interfaçage de la voie descendante du réseau de transmission provenant d'un serveur, p. ex. récupération de paquets du flux vidéo codé d'un réseau IP
11.
TRANSMISSION DEVICE, RECEPTION DEVICE, AND TRANSMISSION AND RECEPTION SYSTEM
In the present invention, video data including active data and sync data is transmitted from a transmission device to a reception device. In a blank period in which the sync data is sent, blank start (BS) data is transmitted in the first cycle in the blank period, blank end (BE) data is transmitted in the last cycle in the blank period, and PRE_BS data is transmitted an N1 cycle prior to the BE transmission cycle. The reception unit reproduces the BE data on the basis of the detected PRE_BS data or BE data, and reproduces the BS data on the basis of the reproduced BE data or the detected BS data. In this way, external noise resistance is further improved and it is possible to accurately separate active data and sync data from among received data.
A bidirectional communication system 1 comprises a signal transmitting and receiving device 10 and a signal transmitting and receiving device 20 that perform bidirectional communication via a transmission path 30. The signal transmitting and receiving device 20 comprises a driver 21, a filter 22, a receiver 23, and a controller 24. The receiver 23 recovers a clock signal by performing frequency locking on a training pattern signal output through the filter 22, and outputs a recovered clock to the controller 24. The controller 24 receives the recovered clock output from the receiver 23, controls a cutoff frequency of the filter 22, and controls an operation of the driver 21 based on a frequency information of the recovered clock signal.
The communication device 111 included in the active cable comprises a controller 11, a comparator 12, a resistor 13, a voltage source 14, and a redriver 16. The comparator 12 receives the voltage value of the SBU signal line and the reference voltage value output from the voltage source 14, and compares the voltage value of the SBU signal line with the reference voltage value to detect the level of the sideband signal. The controller 11 receives the detection result of the sideband signal level from the comparator 12, and sets the redriver 16, which is an active device, to the low-power-consumption state when the sideband signal level stays at L level for a predetermined period of time or longer.
0M-1mm each comprise a selector 61, a PMOS transistor 62, an NMOS transistor 63, a PMOS transistor 64, an NMOS transistor 65, a first standby voltage set circuit 70, and a second standby voltage set circuit 80. The first standby voltage set circuit 70 is configured to connect a first node N1 and a voltage source through a switch which is set to be in ON/OFF states in response to an output signal from the selector 61, and when the switch is in the ON state, sets the first node N1 to a standby voltage by complementarily charging/discharging the parasitic capacitance of the first node N1.
A reference current source includes a reference current path, a first output current path and a second output current path. The reference current path includes a diode-connected first transistor, a diode-connected second transistor, and a first resistor that are connected in series between a first fixed potential and a second fixed potential. The first output current path includes a third transistor having a gate connected to a gate of the second transistor, forming a current mirror together with the second transistor, and a second resistor interposed between the third transistor and the first fixed potential. The second output current path includes a voltage-current conversion circuit to which a potential of a third node between the third transistor and the second resistor in the first output current path is applied and through which a reference current flows.
G05F 3/24 - Régulation de la tension ou du courant là où la tension ou le courant sont continus utilisant des dispositifs non commandés à caractéristiques non linéaires consistant en des dispositifs à semi-conducteurs en utilisant des combinaisons diode-transistor dans lesquelles les transistors sont uniquement du type à effet de champ
16.
Communication device, terminal device and active optical cable
A communication device includes a controller, a differential input termination resistor, a linear laser driver, transmitted signal detector, a linear transimpedance amplifier, a linear variable gain amplifier, a linear output driver, a pulse counter, a received signal detector, and an amplitude detector. The controller outputs a Term signal for setting a resistance value of the differential input termination resistor, a TxEN signal and an LS signal for controlling an operation of the linear laser driver, an RxEN signal for controlling operations of the linear TIA, the linear VGA, and the linear output driver, and a GCTL signal for controlling a gain of the linear VGA.
A communication device 111 included in an active cable comprises a control unit 11, a comparator 12, a resistor 13, a voltage source 14, and a redriver 16. The comparator 12 receives the inputs of a voltage value of a SBU signal line and a reference voltage value output from the voltage source 14, and compares the magnitude of the voltage value of the SBU signal line with the magnitude of the reference voltage value to detect the level of a sideband signal. The control unit 11 receives the result of detection of the sideband signal level from the comparator 12, and if the sideband signal level is L level for a certain period of time or more, puts the redriver 16, which is an active device, into a low power consumption state.
G06F 3/00 - Dispositions d'entrée pour le transfert de données destinées à être traitées sous une forme maniable par le calculateurDispositions de sortie pour le transfert de données de l'unité de traitement à l'unité de sortie, p. ex. dispositions d'interface
G06F 13/38 - Transfert d'informations, p. ex. sur un bus
H04B 10/075 - Dispositions pour la surveillance ou le test de systèmes de transmissionDispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service
H04L 29/02 - Commande de la communication; Traitement de la communication
18.
Transmitting and receiving device, terminal device, and transmitting and receiving system
A transmitting and receiving device includes a controller, a driver, a specific pattern generator, a transmitting signal detector, an amplifier, a differential amplifier, an average current detector, and a received signal detector. In a non-signal period, the controller causes a current signal to be input from the driver to a laser diode and causes an optical signal to be output from the laser diode. When an optical signal of a specific pattern output from the other-side laser diode reaches a photodiode over a period of length that depends on an average value of a current signal output from the other-side photodiode that receives the optical signal, the controller adjusts a magnitude of the current signal input from the driver to the laser diode based on the length of the period of the optical signal of the specific pattern.
A transmitter 10B always transmits a signal (data in which a dock is embedded) generated by the serializer 11 to the communication link. The receiver 20B includes a recovery circuit 22, a deserializer 23, a selector 25, and a training signal generator 32. The training signal generator 32 generates and outputs a training signal for frequency synchronization of the recovering operation of the recovery circuit 22. The selector 25 receives the signal from the transmitter 10B via the communication link and receives the training signal output from the training signal generator 32. The selector 25 selects and outputs either the received signal or the training signal according to the level of the lock signal output from the recovery circuit 22.
A semiconductor device includes a semiconductor chip and a package. The semiconductor chip includes a signal processing circuit, a plurality of pads, and a first resistor which arc formed on a semiconductor substrate. On the semiconductor chip, there is no shot-circuiting between a first pad and a second pad of the plurality of pads. A signal input terminal of the signal processing circuit is connected to the second pad. The first resistor is provided between a reference potential supply terminal for supplying a power supply potential and the first pad. A specific terminal of the plurality of terminals of the package is connected to the first pad by a first bonding wire, and is connected to the second pad by a second bonding wire.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 49/02 - Dispositifs à film mince ou à film épais
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
N and a controller 20. A phase difference detector of each serializer circuit detects a phase difference between a load signal and a first clock, and outputs an abnormal detection signal to the controller 20 when the detected phase difference is abnormal. When the controller 20 receives the abnormal detection signal from any of the serializer circuits, the controller 20 transmits a batch reset instruction signal to all the serializer circuits. Then, in all the serializer circuits, when a reset signal generator receives the batch reset instruction signal output from the controller 20, the reset signal generator transmits a reset instruction signal to a load signal generator to reset the operation of a load signal generation in the load signal generator.
A linear amplifier outputs differential signals corresponding to differential signals input to a first signal input terminal and a second signal input terminal, and includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third transistor, a fourth transistor, a differential amplifier, and a signal processing circuit. The signal processing circuit includes a first transistor and a second transistor, and includes a resistor as a common voltage output part that outputs a common voltage. The differential amplifier receives the common voltage and a reference voltage, and applies a voltage corresponding to the voltage difference between the common voltage and the reference voltage to the control terminals of the transistors.
The video signal transmission and reception system performs transmission of a video signal and a control signal between the video signal transmitting device and the video signal receiving device via a common transmission line. The video signal transmitting device includes a video signal transmitter, a control signal transmitter and receiver, a filter circuit, a controller, and a camera. The video signal receiving device includes a video signal receiver, a control signal transmitter and receiver, a filter circuit, and a controller. By performing time management control performed by the controller or the controller such that the period of the transient state of transmission of the video signal is within the non-communication period of the control signal, interference between the video signal and the control signal in the period of the transient state of transmission of the video signal is suppressed.
H04N 7/08 - Systèmes pour la transmission simultanée ou séquentielle de plus d'un signal de télévision, p. ex. des signaux d'information additionnelle, les signaux occupant totalement ou partiellement la même bande de fréquence
An XTC circuit includes delay circuits, differentiated signal generating circuits, and an amplitude adjusting and adding circuit. A signal Da, which is one aggressor signal, is input to the differentiated signal generating circuit after being delayed by the delay circuit, and the differentiated signal generating circuit generates a differentiated signal having a differentiated waveform of the signal Da. In the amplitude adjusting and adding circuit, the differentiated signal generated by the differentiated signal generating circuit is amplitude-adjusted to become a current signal, and the differentiated signal after the amplitude adjustment is current-added to the signal Db.
H03K 5/1252 - Suppression ou limitation du bruit ou des interférences
H03F 3/193 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
H03K 17/693 - Dispositifs de commutation comportant plusieurs bornes d'entrée et de sortie, p. ex. multiplexeurs, distributeurs
H03K 19/094 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs à semi-conducteurs utilisant des transistors à effet de champ
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
26.
Transmitter, receiver, transmitter/receiver, and transmitting/receiving system
This embodiment relates to a transmitter and the like that prevent an increase of the number of cables of an external interface even when the types of signals to be transmitted increase. The transmitter includes a latch circuit, an encoder, a serializer, and a selector. The latch circuit keeps a level of each of a plurality of signals at the timing specified by a sampling clock, and then, outputs the plurality of signals as a parallel data signal. The encoder generates an encoded parallel data signal based on the parallel data signal from the latch circuit. The serializer generates a serial data signal based on the encoded parallel data signal from the encoder. The sampling clock has a frequency higher than a transmission rate of the fastest signal of the plurality of signals.
G06F 3/14 - Sortie numérique vers un dispositif de visualisation
H04N 5/14 - Circuits de signal d'image pour le domaine des fréquences vidéo
H04N 21/434 - Désassemblage d'un flux multiplexé, p. ex. démultiplexage de flux audio et vidéo, extraction de données additionnelles d'un flux vidéoRemultiplexage de flux multiplexésExtraction ou traitement de SIDésassemblage d'un flux élémentaire mis en paquets
H04N 21/41 - Structure de clientStructure de périphérique de client
27.
Transmitting device, receiving device, repeating device, and transmission/reception system
One embodiment relates to a transmitting device, a receiving device, and the like for preventing increases in the number of communication links, power consumption, and circuit layout area. The transmitting device includes a high-speed signal generator, a low-speed signal generator, and a signal superimposing unit. The high-speed signal generator generates a high-speed signal having a limited frequency band. The low-speed signal generator generates a low-speed signal having a frequency lower than the frequency band of the high-speed signal. The signal superimposing unit outputs a superimposed signal of the high-speed signal and the low-speed signal. The receiving device includes a signal separator and a recovery unit. The signal separator separates the received signal into the high-speed signal and the low-speed signal. The recovery unit performs frequency tracking based on the separated low-speed signal and performs phase tracking based on the separated high-speed signal.
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
H04L 27/04 - Circuits de modulationCircuits émetteurs
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
H03L 7/08 - Détails de la boucle verrouillée en phase
H04L 7/06 - Commande de vitesse ou de phase au moyen de signaux de synchronisation les signaux de synchronisation différant des signaux d'information en amplitude, polarité ou fréquence
28.
RECEPTION DEVICE AND TRANSMISSION AND RECEPTION SYSTEM
A transmission device 10B always transmits, to a communication link, a signal generated by a serializer 11 (data with a clock embedded therein). A reception device 20B includes a restoration unit 22, a deserializer 23, a selection unit 25, and a training signal generation unit 32. The training signal generation unit 32 generates and outputs a training signal for frequency-synchronizing a restoration operation of the restoration unit 22. The selection unit 25 receives a signal arriving from the transmission device 10B via the communication link, and the training signal output from the training signal generation unit 32 is input thereto. The selection unit 25 selects and outputs, in accordance with a level of a lock signal output from the restoration unit 22, one of the reception signal and the training signal.
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
A PLL circuit includes a phase comparator, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, a frequency difference determination unit, and an FV characteristics adjustment unit. The frequency difference determination unit determines whether or not a frequency difference between a feedback oscillation signal and an input signal is equal to or smaller than a threshold value. The FV characteristics adjustment unit selects a frequency band in the voltage-controlled oscillator and adjusts FV characteristics.
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/18 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle
H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
A PLL frequency synthesizer includes a voltage controlled oscillator that outputs an oscillation signal having a frequency corresponding to a control voltage value, a phase comparison unit that outputs a phase difference signal representing a phase difference between a feedback oscillation signal and a reference oscillation signal, a charge pump that outputs a charge and discharge current according to the phase difference, a loop filter that outputs the control voltage value, which is increased or decreased according to a charge and discharge amount of a capacitive element, to the voltage controlled oscillator, a detection unit that detects a change rate of the control voltage value, and a control unit that adjusts the charge and discharge current, a characteristic of the loop filter, or a characteristic of the voltage controlled oscillator based on a detection result of the detection unit.
H03L 7/10 - Détails de la boucle verrouillée en phase pour assurer la synchronisation initiale ou pour élargir le domaine d'accrochage
H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/18 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle
31.
Voltage-controlled oscillator, PLL circuit, and CDR device
Provided is a voltage-controlled oscillator capable of suppressing performance deterioration due to a leak current of a variable capacitive element. Each of the first capacitive circuit and the second capacitive circuit includes a variable capacitive element, a capacitive element, a detection circuit, and a compensation circuit. The variable capacitive element is provided between nodes. A capacitance value of variable capacitive element depends on a voltage value between the nodes. The detection circuit applies a bias voltage value to the second node, and detects an amount of leak current flowing through the variable capacitive element. The compensation circuit causes a current for compensating for the leak current of the variable capacitive element to flow through the first node on the basis of a detection result of the detection circuit.
H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03L 7/08 - Détails de la boucle verrouillée en phase
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
1NN, and a control unit 20. A phase difference detection unit of each of the serializer circuits detects a phase difference between a load signal and a first clock, and outputs an abnormality sensing signal to the control unit 20 if the detected phase difference is abnormal. The control unit 20, when the abnormality sensing signal is received from any of the serializer circuits, sends a mass reset instruction signal to all of the serializer circuits. In all of the serializer circuits, a reset signal generation unit, when the mass reset instruction signal outputted from the control unit 20 is received, passes a reset instruction signal to a load signal generation unit and causes a load signal generation operation in the load signal generation unit to be reset.
An equalizer adjusting device includes a comparator, an inequality counter, an adjuster, and the like. The comparator performs magnitude comparison between a voltage value Vout of each bit output from an equalizer and a threshold value MonLVL and outputs a logical value MonSMP according to a result of the comparison. The inequality counter inputs a logical value DatSMP output from a sampler in accordance with the result of magnitude comparison between the voltage value Vout of each bit and a reference value, and the logical value MonSMP output from the comparator and counts events in which the logical value DatSMP and the logical value MonSMP differ from each other, every period. The adjuster adjusts a gain of the equalizer and the threshold value MonLVL of the comparator based on a counted value of the inequality counter.
A PLL circuit of one embodiment has a structure for preferably setting the FV characteristic of an LC-VCO. The PLL circuit includes a voltage controlled oscillator, a phase comparator, a charge pump, a loop filter, and an FV characteristic adjustment unit setting the FV characteristic. The voltage controlled oscillator has an FV characteristic indicating the relationship between a control signal and a frequency and outputs an oscillation signal having a frequency corresponding to the control signal based on the FV characteristic. The phase comparator detects a phase difference between an input signal and the control signal. The charge pump outputs a corrected voltage value changed according to the phase difference. The loop filter outputs a control voltage value changed in response to corrected voltage value variations. The FV characteristic adjustment unit generates an FV characteristic control signal by a mean corrected voltage value.
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/097 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant un comparateur pour comparer les tensions obtenues à partir de deux convertisseurs de fréquence en tension
N and the control code candidates in which the duty specified by measurement information obtained by the duty measuring unit is within a predetermined range.
H03K 5/156 - Dispositions dans lesquelles un train d'impulsions est transformé en un train ayant une caractéristique désirée
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/091 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge
A PLL circuit includes a phase comparator, a charge pump 20, a loop filter 30, a voltage controlled oscillator 40, a frequency divider, and a phase compensator 70. The loop filter 30 includes a resistor 31, a first capacitance element 32, and a second capacitance element 33. The phase compensator 70 is provided in parallel to the charge pump 20 and adds a differentiation term to an open-loop transfer function. The phase compensator 70 includes a buffer 71 receiving a phase difference signal output from the phase comparator and a third capacitance element 72 provided between an output terminal of the buffer 71 and an input terminal of the loop filter 30.
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
H03L 7/08 - Détails de la boucle verrouillée en phase
H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
H03H 7/06 - Réseaux à deux accès sélecteurs de fréquence comprenant des résistances
37.
Video signal receiver, video signal reception module, and video signal transmission and reception system
A video signal transmission and reception system includes a video signal receiver in a video signal reception module, a video signal transmitter in a camera module, and a specific video signal transmitter in a specific camera module. In the specific camera module, a frame signal generated by a frame signal generator is sent to the video signal receiver from the specific video signal transmitter. The frame signal is sent to the video signal transmitters in a plurality of the camera modules from the video signal receiver.
H04N 5/77 - Circuits d'interface entre un appareil d'enregistrement et un autre appareil entre un appareil d'enregistrement et une caméra de télévision
H04N 7/18 - Systèmes de télévision en circuit fermé [CCTV], c.-à-d. systèmes dans lesquels le signal vidéo n'est pas diffusé
A video signal transmission and reception system includes a first video signal receiver and a second video signal receiver in a video signal reception module and a video signal transmitter in a camera module. The video signal reception module includes the first video signal receiver, the second video signal receiver, and a central operation processor. A frame signal generated in the first video signal receiver is sent to a video signal transmitter of a first group and is output to the second video signal receiver. In addition, the frame signal generated in the first video signal receiver is input into the second video signal receiver and is sent to a video signal transmitter of a second group from the second video signal receiver.
H04N 5/77 - Circuits d'interface entre un appareil d'enregistrement et un autre appareil entre un appareil d'enregistrement et une caméra de télévision
A video signal receiver includes a clock signal receiver, a frame signal generator, and a frame signal transmitter. The clock signal receiver receives a camera video signal clock sent from a video signal transmitter in a camera module and outputs the clock to the frame signal generator. The frame signal generator generates a frame signal based on the clock received by the clock signal receiver and outputs the frame signal to the frame signal transmitter. The frame signal transmitter receives input of the frame signal output from the frame signal generator and sends the frame signal to the video signal transmitter of each camera module.
H04N 7/18 - Systèmes de télévision en circuit fermé [CCTV], c.-à-d. systèmes dans lesquels le signal vidéo n'est pas diffusé
H04N 25/71 - Capteurs à dispositif à couplage de charge [CCD]Registres de transfert de charge spécialement adaptés aux capteurs CCD
H04N 5/77 - Circuits d'interface entre un appareil d'enregistrement et un autre appareil entre un appareil d'enregistrement et une caméra de télévision
The present invention relates to a video signal transmission device and the like that can support a variety of system specifications. The device includes a packer unit, an encoder unit, and a serializer. The packer unit generates, from a video signal of one or more pixels, a plurality of block signals having a packet configuration of size corresponding to the number of pixels and the number of tone bits of a color signal constituting a video signal. At this time, a control signal including a pulse having a width corresponding to the number of pixels and the number of tone bits is also generated. The encoder unit applies encoding processing having encoding efficiencies that are different between a first period and a second period of a control signal that are distinguished depending on existence or non-existence of a pulse to the block signals.
b. This first circuitry 20A includes a resistor R1 provided between a node N11 and a node N12, a resistor R2 provided between the node N12 and a node N13, a resistor R3 provided between the node N13 and a node N14, a resistor R4 provided between the node N14 and the node N11, a resistor R5 provided between the node N11 and the node N13, a switch SW0 provided in series to the resistor R4 between the node N14 and the node N11, and a switch SW1 provided in series to the resistor R2 between the node N12 and the node N13. The node N12 is connected to the first end and the node N14 is connected to the second end.
This PLL frequency synthesizer is provided with: a voltage-controlled oscillator which outputs an oscillation signal having a frequency corresponding to a control voltage value; a phase comparison unit which inputs, as a feedback oscillation signal, the oscillation signal or a signal obtained by frequency-dividing the oscillation signal and which detects a phase difference between the feedback oscillation signal and a reference oscillation signal and then outputs a phase difference signal representing the phase difference; a charge pump which outputs a charging/discharging current corresponding to the phase difference represented by the phase difference signal; a loop filter which includes a capacitative element that is charged/discharged upon input of the charging/discharging current thereto and which outputs, to the voltage-controlled oscillator, a control voltage value that is incremented/decremented in accordance with the charge/discharge amount of the capacitative element; a detection unit which detects the rate of change in the control voltage value when the charging/discharging current is inputted to the loop filter; and a control unit which, according to the detection result of the detection unit, makes adjustments to the charging/discharging current, the characteristics of the loop filter, or the characteristics of the voltage-controlled oscillator.
H03L 7/18 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle
H03L 7/10 - Détails de la boucle verrouillée en phase pour assurer la synchronisation initiale ou pour élargir le domaine d'accrochage
44.
Transmitter and transmission/reception system including the same
This embodiment relates to a transmitter that has a structure to suppress an increase in device occupancy area on a semiconductor substrate. The transmitter includes an output driver, a duplication driver, a reference voltage generation unit, a first selection unit, a second selection unit, a comparison unit, and a control unit. The first selection unit selects a first or second test voltage outputted from a duplication driver in which a resistance value is set in cooperation with the output driver. The second selection unit selects a first or second reference voltage outputted from the reference voltage generation unit. The comparison unit compares magnitudes of the first test voltage and the first reference voltage during a first operation period and compares magnitudes of the second test voltage and the second reference voltage during a second operation period different from the first operation period.
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface
A serializer device (1) includes a first latch unit (11), a second latch unit (12), a conversion unit (13), a frequency division unit (14), a load signal generation unit (15), a phase difference detection unit (16), and a reset instruction unit (17), and has a simple configuration and can reduce a bit error rate at an early stage. The phase difference detection unit (16) detects a phase difference between a first clock (CLK1) applied to the first latch unit (11) and a third clock (CLK3) applied to the second latch unit (12). The reset instruction unit (17) outputs a reset instruction signal (RSTn) to the frequency division unit (14) when the phase difference is not within a target range.
H03M 9/00 - Conversion parallèle/série ou vice versa
H03K 5/26 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale la caractéristique étant la durée, l'intervalle, la position, la fréquence ou la séquence
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
46.
Host-side transceiver device and transceiver system
2C communication scheme with a remote-side transceiver device 30 and sends the access request signal received by the first communication unit 21 to the remote-side transceiver device 30. The first communication unit 21 notifies the host device 10 that the first communication unit 21 has received the access request signal sent from the host device 10 before the access to the remote device 40 based on the access request signal sent from the second communication unit 22 ends.
The invention relates to a reception device, etc., applied to a transmission/reception system capable of performing high-speed transmission, having a structure to enable to adjust an offset without increasing a circuit area and power consumption. The reception device includes a signal input unit including an offset adjusting circuit, and an adjustment unit. When a pair of adjusting signals of which a voltage between signals is fixed to zero V is outputted from a transmission device to the reception device connected to each other via a differential signal line including at least a pair of signal lines, the signal input unit that has received the pair of adjusting signals outputs logical value data corresponding to the voltage between signals. The adjustment unit determines adjustment value data to adjust the offset of a threshold to obtain the logical value data based on the logical value data inputted in a certain period.
The present embodiments relate to a reception device that enables accurate separation of video data and SYNC data sent out from a transmission device in accordance with a data enable (DE) signal, from among reception data even if the reception data deteriorates due to noise. The reception device separates the video data and the SYNC data from the reception data in accordance with the DE signal reproduced using a detection result of the BS data and the BE data representing a transition timing of a signal level of the DE signal and a prediction result of detection timings of the BS data and the BE data or a prediction result of the transition timing of the DE signal.
G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
G09G 5/12 - Synchronisation entre l'unité d'affichage et d'autres unités, p. ex. d'autres unités d'affichage, des lecteurs de disques vidéo
H04N 21/242 - Procédés de synchronisation, p. ex. traitement de références d'horloge de programme [PCR]
A transmitter includes: an output driver that outputs differential signals to differential signal lines; first termination resistors and a first switch which are provided in series between a first reference voltage input terminal to which a reference voltage is inputted and the differential signal lines; a pulse generator that outputs a common-mode pulse to the differential signal lines; a second switch provided between the differential signal lines and the pulse generator; a detector that detects, after generation of the common-mode pulse starts, timing at which a voltage level of the common-mode pulse exceeds a threshold; and a controller that places the second switch in an on state to connect the pulse generator to the differential signal lines, and powers down the output driver and then places the first switch in an off state to allow the pulse generator to output the common-mode pulse to the differential signal lines.
H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale la caractéristique étant l'amplitude
H03K 17/60 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors bipolaires
A transmitter includes: an output driver that outputs differential signals to differential signal lines; first termination resistors and a first switch which are provided in series between a first reference voltage input terminal to which a reference voltage is inputted and the differential signal lines; a pulse generator that outputs a common-mode pulse to the differential signal lines during a period during which a pulse output instruction signal is at a significant level; and a detector that outputs a detection result signal indicating a magnitude relationship between a voltage level of the common-mode pulse and a threshold, during a period during which the pulse output instruction signal is at a significant level, and outputs a detection result signal indicating that the voltage level of the common-mode pulse does not exceed the threshold, during a period during which the pulse output instruction signal is at a non-significant level.
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale la caractéristique étant l'amplitude
H03K 17/60 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors bipolaires
51.
Input device which outputs a signal having a level corresponding to a state in which a voltage value of an input signal is higher or lower than a threshold value
The embodiment relates to an input device comprises first and second MOS transistors, first to fourth resistors, and a comparator circuit. The first MOS transistor has a drain connected to a first terminal having a first voltage, a gate connected to a signal input terminal, and a source connected to a second terminal having a second voltage via the first and third resistors. The second MOS transistor has a drain and a gate connected to the first terminal, and a source connected to the second terminal via the second and fourth resistors. The comparator circuit outputs a signal having a level corresponding to a state in which a voltage of a node between the first and third resistors is higher or lower than a voltage of a node between the second and fourth resistors.
H03K 5/22 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale
H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale la caractéristique étant l'amplitude
n is an non-significant level. A rear unit B receives signals from the front units, and outputs a signal having a different signal level in a case in which all the output signals from the front units are the same level or in the other case.
H03K 17/284 - Modifications pour introduire un retard avant commutation dans les commutateurs à transistors à effet de champ
H03K 17/693 - Dispositifs de commutation comportant plusieurs bornes d'entrée et de sortie, p. ex. multiplexeurs, distributeurs
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
53.
VIDEO SIGNAL TRANSMISSION DEVICE, VIDEO SIGNAL RECEPTION DEVICE AND VIDEO SIGNAL TRANSFERRING SYSTEM
The present invention relates to a video signal transmission device that can handle various system specifications. The device is provided with a packer unit, an encoder unit, and a serializer. The packer unit generates, from a video signal of one or more pixels, a plurality of block signals with a packet configuration of a size that depends on the number of pixels and the number of gradation bits of a color signal constituting the video signal. In this case, the packer unit also generates a control signal that includes a pulse of a width that depends on the number of pixels and the number of gradation bits. The encoder unit subjects the block signals to encoding processing in which there are different encoding efficiencies in a first period and a second period of the control signal that are distinguished between by the presence or absence of a pulse.
The signal-multiplexing device according to the present embodiment has a structure sufficiently capable of handling an increase in data rate. The signal-multiplexing device is provided with M pre-stage buffer units and an output buffer unit. An mth pre-stage buffer unit Bm outputs an mth input signal when the signal level of both the mth control signal Cm and the nth control signal Cn, from among M control signals, is significant, and enters a high impedance state when the signal level of the mth control signal Cm and/or the nth control signal Cn is non-significant. The output buffer unit sequentially outputs input signals outputted at different timings from the M pre-stage buffer units.
This embodiment relates to a clock data recovering apparatus capable of improving consecutive identical digits (CID) resistance. The clock data recovering apparatus includes a clock generating apparatus. The clock generating apparatus includes a signal selection unit, a phase detection unit, a phase control unit, a selection unit, a phase delay unit, a time measurement unit, and a phase selection unit. The phase delay unit includes a plurality of delay elements. The phase selection unit selectively outputs an output signal of any one of the plurality of delay elements as a feedback clock. The phase detection unit detects a phase relation between an edge signal and the feedback clock. The phase control unit outputs a control signal to control a signal selection operation by the phase selection unit such that a phase difference detected by the phase detection unit decreases, to the phase selection unit.
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
H04L 7/02 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière
H03L 7/081 - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
56.
TRANSMISSION DEVICE AND TRANSCEIVER SYSTEM INCLUDING SAME
The present embodiment pertains, inter alia, to a transmission device having a structure for minimizing any increase in the area of a semiconductor substrate occupied by the device. This transmission device is provided with an output driver, a duplication driver, a reference voltage generating unit, a first selection unit, a second selection unit, a comparator, and a control unit. The first selection unit selects a first or second test voltage outputted from the duplication driver for which a resistance value is set in mutual association with the output driver. The second selection unit selects a first or second reference voltage outputted from the reference voltage generating unit. The comparator compares the magnitude of the first test voltage and the first reference voltage during a first operation period, and compares the magnitude of the second test voltage and the second reference voltage during a second operation period that is different from the first operation period.
A serializer device 1 is provided with a first latch unit 11, a second latch unit 12, a conversion unit 13, a frequency division unit 14, a load signal generation unit 15, a phase difference detection unit 16, and a reset indication unit 17, making it possible to reduce a bit error rate early by a simple configuration. The phase difference detection unit 16 detects a phase difference between a first clock CLK1 applied to the first latch unit 11 and a third clock CLK3 applied to the second latch unit 12, and the reset indication unit 17 outputs a reset indication signal RSTn to the frequency division unit 14 when the phase difference is not within an intended range.
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
H03K 5/26 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale la caractéristique étant la durée, l'intervalle, la position, la fréquence ou la séquence
H03M 9/00 - Conversion parallèle/série ou vice versa
A semiconductor device includes a first circuit 1 and a second circuit 2 that are connected in series, a first terminal T1 that applies a first potential to a first power supply line DL1 of the first circuit 1, a second terminal T2 that applies a second potential to a second power supply line DL2 of the second circuit 2, a third terminal T3 that is connected to a signal transfer line of the first circuit 1, and a protection circuit that is connected to the third terminal T3, and discharges a current from the third terminal T3 to a fourth terminal T4 when a potential of the third terminal T3 becomes higher than a first threshold value. The first power supply line DL1 and the second power supply line DL2 are separated, and the fourth terminal T4 is not directly connected to the first power supply line DL1 and is electrically connected to a lead.
H01L 23/60 - Protection contre les charges ou les décharges électrostatiques, p. ex. écrans Faraday
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/552 - Protection contre les radiations, p. ex. la lumière
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H05F 3/00 - Enlèvement des charges électrostatiques
A receiving device 20 includes a voltage controlled oscillator 22, a sampling unit 23, a control voltage generating unit 24, an error detecting unit 25, and a control voltage holding unit 26. The control voltage holding unit 26 holds a value of a control voltage Vc output from the control voltage generating unit 24. When the error detecting unit 25 detects an error of a digital signal, a control voltage held before error detection is provided to the voltage controlled oscillator 22.
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
H03L 7/08 - Détails de la boucle verrouillée en phase
60.
Transmission device, reception device, and transmission/reception system
A transmission/reception system 1 includes a transmission device 10 configured to transmit image data and a reception device 20 configured to receive the image data transmitted from the transmission device 10. The transmission device 10 includes a serializer 11, an encoding unit 12, a data buffering unit 13, a data selection unit 14, a counter 15, and a synchronization signal generation unit 16. The data buffering unit 13 buffers data every n bits in synchronization with the clock. The data selection unit 14 outputs m-bit data selected from the data buffered by the data buffering unit 13 on the basis of a count value from the counter 15.
A transmission/reception system 1 includes a transmission apparatus 10A, and a reception apparatus 20A. The transmission apparatus 10A includes a first switch 101, a second switch 102, a first transistor 111, a second transistor 112, a first differential amplifier 121, and a second differential amplifier 122. The reception apparatus 20A includes a first transistor 211, a second transistor 212, a first differential amplifier 221, a second differential amplifier 222, a first resistor 231, a second resistor 232, and a reception unit 240.
The present embodiment relates to, for example, a transceiver system capable of notifying a transmission device of an asynchronous state of a reception device with a simple configuration. The reception device includes an input unit, a synchronous-state detector, a resistance-value controller, and a terminal resistor. When the synchronous-state detector detects the asynchronous state, the resistance-value controller sets a resistance value of the terminal resistor to a resistance value indicating the asynchronous state. The transmission device includes an output unit, an amplitude detector, an output controller, and a transmission resistor. The output controller causes the output unit to output a signal constituting normal data including clock information when the synchronous state of the reception device is detected, and causes the output unit to output a signal constituting training data including the clock information when the asynchronous state of the reception device is detected.
H04L 7/027 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en extrayant le signal d'horloge ou de synchronisation du spectre du signal reçu, p. ex. en utilisant un circuit résonnant ou passe-bande
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
A first communication unit 21 of this host-side transceiver device 20 communicates with a host device 10 in an I2C communication scheme and receives an access request signal transmitted from the host device 10. A second communication unit 22 communicates with a remote-side transceiver device 30 in a communication scheme different from the I2C communication scheme and transmits the access request signal received by the first communication unit 21 to the remote-side transceiver device 30. The first communication unit 21 notifies the host device 10 of having received the access request signal, which has been transmitted from the host device 10, before access to a remote device 40 based on the access request signal transmitted from the second communication unit 22 is terminated.
A signal transmission circuit is provided with: first and second lines L1, L2 to which signals complementary to each other are inputted; first and second buffer circuits BA11, BA21; a first inverter BA12 which connects a first input-side terminal IN1 and a second output-side terminal OUT2; and a second inverter BA22 which connects a second input-side terminal IN2 and a first output-side terminal OUT1.
H03K 5/151 - Dispositions dans lesquelles des impulsions sont délivrées à plusieurs sorties à des instants différents, c.-à-d. distributeurs d'impulsions avec deux sorties complémentaires
H03K 17/16 - Modifications pour éliminer les tensions ou courants parasites
H03K 17/693 - Dispositifs de commutation comportant plusieurs bornes d'entrée et de sortie, p. ex. multiplexeurs, distributeurs
H03K 19/00 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion
H03K 19/173 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
H04J 3/04 - Distributeurs combinés avec des modulateurs ou des démodulateurs
Provided is a reception apparatus capable of shortening a time period until the original data and clock can be recovered from a digital signal after temporary superimposition of noise on the digital signal stops. A reception apparatus 20 includes a receiver unit 21, a voltage-controlled oscillator 22, a sampler unit 23, a control voltage generation unit 24, an error detection unit 25, a training control unit 26, and an equalizer control unit 27. The receiver unit 21 includes an equalizer unit 21A. When the error detection unit 25 detects an error of a digital signal, the reception apparatus 20 causes a phase/frequency comparison by the control voltage generation unit 24 to be stopped.
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
H03L 7/08 - Détails de la boucle verrouillée en phase
H03L 7/091 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
H04L 7/04 - Commande de vitesse ou de phase au moyen de signaux de synchronisation
H04L 7/10 - Dispositions pour synchronisation initiale
67.
RECEPTION DEVICE AND TRANSMISSION/RECEPTION SYSTEM INCLUDING SAME
The present invention relates to a reception device and the like that can be applied to a transmission/reception system that can perform high-speed transmission and that are provided with a structure that makes it possible to perform offset adjustment without increasing circuit area and power consumption. The reception device is provided with a signal input unit that includes an offset adjustment circuit and with an adjustment unit. When a pair of adjustment signals that have an inter-signal voltage that is fixed at 0 V are outputted to the reception device from a transmission device that is connected thereto via a differential signal line that is configured from at least one pair of signal lines, the signal input unit, to which the pair of adjustment signals are inputted, outputs logical value data that corresponds to the inter-signal voltage. On the basis of the logical value data inputted within a fixed period, the adjustment unit decides adjustment value data that is for adjusting the offset of a threshold value that is for obtaining the logical value data.
The present embodiment relates to a transmission/reception system and the like that, by means of a simple configuration, can notify a transmission device when a reception device is in an asynchronous state. The reception device is provided with an input unit, a synchronization state detection unit, a resistance value control unit, and an end-of-line resistor. When an asynchronous state is detected by the synchronization state detection unit, the resistance value control unit sets the resistance value of the end-of-line resistor to a resistance value that indicates the asynchronous state. The transmission device is provided with an output unit, an amplitude detection unit, an output control unit, and a transmission resistor. When a synchronous state is detected at the reception device, the output control unit makes the output unit output a signal that constitutes normal data that includes clock information. When an asynchronous state has been detected at the reception device, the output control unit makes the output unit output a signal that constitutes training data that includes clock information.
A mode switching notification in a first mode is transmitted from a transmission device 10 to a reception device 20 according to a first protocol. In a second mode, training data is transmitted from the transmission device 10 to the reception device 20, clock training is performed in the reception device 20, and a mode switching notification for the first mode is transmitted from the transmission device 10 to the reception device 20 according to a second protocol simpler and faster than the first protocol.
G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation
G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
An imaging system 1 includes an imaging control device 10, an imaging device 20, and a light emitting device 30. The imaging control device 10 is provided for controlling the imaging device 20 and the light emitting device 30, and includes an evaluation unit 13, a light reception adjustment unit 14, and a light emission adjustment unit 15. The evaluation unit 13 evaluates respective brightnesses of the first image data and the second image data that are output from the imaging device 20. The light reception adjustment unit 14 adjusts any of an exposure time, a diaphragm value, and a gain that are to be used when the imaging device 20 captures an image, based on a brightness evaluation result. The light emission adjustment unit 15 causes the light emitting device 30 to emit light of either wavelength band of the first wavelength band and the second wavelength band, and adjusts a light emission intensity of the light, based on an evaluation result.
This semiconductor device is provided with: a first circuit (1) and a second circuit (2), which are connected in series; a first terminal (T1) which applies a first potential to a first power supply line (DL1) of the first circuit (1); a second terminal (T2) which applies a second potential to a second power supply line (DL2) of the second circuit (2); a third terminal (T3) which is connected to a signal transmission line of the first circuit (1); and a protection circuit which is connected to the third terminal (T3) and makes a current released from the third terminal (T3) to a fourth terminal (T4) in cases where the potential of the third terminal (T3) is increased beyond a first threshold. The first power supply line (DL1) and the second power supply line (DL2) are separated from each other; and the fourth terminal (T4) is electrically connected to a lead without being directly connected to the first power supply line (DL1).
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
A receiving device includes a termination circuit to which a received signal is input, a processing circuit which performs a process at a rear stage of the termination circuit, and an error detection circuit which detects an error contained in the received signal. In a case where the error is detected by the error detection circuit, a termination resistance value of the termination circuit is lowered. Therefore, the receiving device can be rapidly restored when a signal containing an error is received.
This transmission/reception system (1) comprises a transmission device (10) that sends image data and a reception device (20) that receives said image data. The transmission device (10) comprises a serializer (11), an encoding unit (12), a data-buffering unit (13), a data selection unit (14), a counter (15), and a synchronization-signal generation unit (16). Synchronized on a clock, data is inputted to the data-buffering unit (13) n bits at a time and buffered. On the basis of a count maintained by the counter (15), the data selection unit (14) outputs m-bit data selected from among the data buffered by the data-buffering unit (13).
A receiving device (20) is provided with a voltage controlled oscillator (22), a sampling unit (23), a control-voltage-generating unit (24), a fault-detecting unit (25), and a control-voltage-maintaining unit (26). The control-voltage-maintaining unit (26): maintains a control voltage Vc value outputted from the control-voltage-generating unit (24); and, when the fault-detecting unit (25) detects a digital signal fault, causes the control voltage maintained before the fault is detected to be applied to the voltage controlled oscillator (22).
H03L 7/14 - Détails de la boucle verrouillée en phase pour assurer une fréquence constante quand la tension d'alimentation ou la tension de correction fait défaut
H03L 7/08 - Détails de la boucle verrouillée en phase
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
Provided is a reception apparatus that can shorten a time in which, after temporary noise superimpositions on a digital signal become nonexistent, the original data and clocks become able to be restored from the digital signal. The reception apparatus (20) comprises a receiver unit (21), a voltage-controlled oscillator (22), a sampler unit (23), a control voltage generation unit (24), an abnormality detection unit (25), a training control unit (26) and an equalizer control unit (27). The receiver unit (21) includes an equalizer unit (21A). When the abnormality detection unit (25) detects an abnormality of a digital signal, the reception apparatus (20) causes phase/frequency comparisons, which are performed by the control voltage generation unit (24), to be stopped.
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
H03L 7/08 - Détails de la boucle verrouillée en phase
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
76.
Clock-generating device and clock data recovery device
An imaging system (1) is provided with an imaging control device (10), an imaging device (20), and a light-emitting device (30). The imaging control device (10) is designed to control the imaging device (20) and the light-emitting device (30), and is provided with an evaluation unit (13), a light-reception adjustment unit (14), and a light-emission adjustment unit (15). The evaluation unit (13) evaluates the brightness of each of first image data and second image data outputted from the imaging device (20). The light-reception adjustment unit (14) adjusts, on the basis of the result of brightness evaluation, one of an exposure time, a diaphragm value, and a gain at the time of imaging by the imaging device (20). The light-emission adjustment unit (15) causes, on the basis of the evaluation result, light of either a first wavelength band or a second wavelength band to be emitted by the light-emitting device (30), and adjusts the intensity of the emitted light.
H04N 5/235 - Circuits pour la compensation des variations de la luminance de l'objet
H04N 9/07 - Générateurs de signaux d'image avec une seule tête de lecture
G03B 7/097 - Circuits numériques pour la commande à la fois du temps d'exposition et de l'ouverture
G03B 7/16 - Réglage de l'exposition par le réglage des obturateurs, des diaphragmes ou des filtres séparément ou conjointement en fonction de l'intensité du flash et de la distance du flash au sujet, p. ex. selon le "nombre-guide" de la lampe flash et la mise au point de l'appareil photographique
G03B 15/00 - Procédés particuliers pour prendre des photographiesAppareillage à cet effet
G03B 15/05 - Combinaisons d'appareils photographiques avec flash électroniqueFlash électronique
Two selection signals (CLK<1> and CLK<2>) that reach significant levels sequentially are inputted to this signal multiplexer (1), as are two input signals (IN<1> and IN<2>). When the mth selection signal (CLK) is at a significant level, the signal multiplexer (1) outputs a signal (OUT) corresponding to the mth input signal (IN) via an output terminal (14). The signal multiplexer (1) is provided with a resistance unit (20) and two drive units (301 and 302). Each drive unit (30m) comprises a driving switch (31m), a selecting switch (32m), and a potential-stabilizing switch (33m). In each drive unit (30m), when that selecting switch (32m) is closed, that potential-stabilizing switch (33m) is open, and vice versa.
A transmission/reception system (1) comprises a transmission apparatus (10A) and a reception apparatus (20A). The transmission apparatus (10A) comprises a first switch (101), a second switch (102), a first transistor (111), a second transistor (112), a first differential amplifier (121) and a second differential amplifier (122). The reception apparatus (20A) comprises a first transistor (211), a second transistor (212), a first differential amplifier (221), a second differential amplifier (222), a first resistor (231), a second resistor (232) and a reception unit (240).
When in a first mode, a mode-switch notification is transmitted from a transmission device (10) to a reception device (20) in accordance with a first protocol. When in a second mode, training data is transmitted from the transmission device (10) to the reception device (20), clock training is performed in the reception device (20), and a mode-switch notification providing notification of a switch to the first mode is transmitted from the transmission device (10) to the reception device (20) in accordance with a second protocol that is simpler and faster than the abovementioned first protocol.
In serial data transmitted from a transmission device (10) to a reception device (20), transitions from a first level to a second level occur each unit period. Image data consists of first-type data in which there are two or more transitions from the second level to the first level in each unit period. Control data consists of second-type data in which there is one transition from the second level to the first level in each unit period and the number of bits at the second level in each unit period corresponds to a control signal.
A video transmission device 10 has: a packer 11 which receives a video signal, a sync signal, and a data-enable signal, and generates a plurality of packet signals by packetizing the video signal and the sync signal based on the data-enable signal and according to the number of bytes of a packet corresponding to the number of gradation bits of the video signal; an encode unit 15 which generates a plurality of encoded packet signals by encoding the plurality of packet signals; and a serializer 14 which generates a serial packet signal by parallel-serial converting the plurality of encoded packet signals. The packer 11 generates a control signal including a pulse with a pulse width corresponding to the number of bytes of the packet, and the encode unit 15 subjects a portion of the packet signals corresponding to the pulse in the control signal from the packer, to an encode process which is different from a process for the other portion.
H04N 7/06 - Systèmes pour la transmission simultanée d'un seul signal de télévision, c.-à-d. l'image et le son transmis par plus d'une porteuse
H04N 5/067 - Dispositions ou circuits du côté émetteur
G06F 3/14 - Sortie numérique vers un dispositif de visualisation
G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation
H04N 5/765 - Circuits d'interface entre un appareil d'enregistrement et un autre appareil
H04N 21/4363 - Adaptation du flux vidéo à un réseau local spécifique, p. ex. un réseau Bluetooth®
83.
CLOCK-GENERATING DEVICE AND CLOCK DATA RECOVERY DEVICE
This clock data recovery device (1) generates a recovered clock and recovered data on the basis of a data in, and is provided with a signal selection unit (10), a phase delay unit (20), a time measurement unit (30), a phase selection unit (40), an edge detection unit (50), a polarity detection unit (60), a logic inversion unit (70), and a data output unit (80). The signal selection unit (10), the phase delay unit (20), the time measurement unit (30), and the phase selection unit (40) configure a clock-generating device (1A). The phase delay unit (20) includes a plurality of delay elements (211 to 21P) in a cascaded connection. The phase selection unit (40) selects the signal output from the delay element at a position corresponding to a unit interval time among the delay elements (211 to 21P), and outputs the result as a feedback clock.
H04L 7/02 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière
84.
TRANSMISSION DEVICE, RECEPTION DEVICE AND TRANSMISSION/RECEPTION SYSTEM
A transmission/reception system (1A) comprises a transmission device (10A) and reception device (20A). The transmission device (10A) comprises an encoding unit (11), serializer (12) and transmission unit (13). The reception device (20A) comprises a decoding unit (21), deserializer (22), reception unit (23), error detection unit (24) and reset instruction unit (25). The encoding unit (11) causes a synchronization signal (encoding/decoding synchronization signal) for synchronizing encoding processing of the encoding unit (11) and decoding processing of the decoding unit (21) to be periodically transmitted as encoded data from the transmission unit (13) to the reception device (20A). Even when a reset instruction signal is received from the reset instruction unit (25) of the reception device (20A), the encoding unit (11) causes the encoding/decoding synchronization signal to be transmitted as encoded data from the transmission unit (13) to the reception device (20A).
Disclosed herein is a sigma-delta modulator, including an integration circuit, a first DAC unit, and a second DAC unit. The integration circuit includes first and second terminals, and integrates a voltage supplied via the first terminal. The first DAC unit alternately supplies a first voltage obtained at one end of a first resistor to the first terminal and the second terminal. The second DAC unit alternately supplies a second voltage at the other end of a second resistor to the second terminal or the first terminal. The second DAC unit supplies the second voltage to the second terminal when the first DAC unit supplies the first voltage to the first terminal. The second DAC unit supplies the second voltage to the first terminal when the first DAC unit supplies the first voltage to the second terminal.
G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation
G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
G09G 3/36 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante utilisant des cristaux liquides
A level shift circuit (2A) comprises: a first PMOS transistor (31); a second PMOS transistor (32); a first NMOS transistor (41); a second NMOS transistor (42); a third NMOS transistor (43); and a fourth NMOS transistor (44). The respective source terminals of the first PMOS transistor (31) and the second PMOS transistor (32) are connected to a second reference potential (Vddh) which is higher than a first reference potential (Vddl). The respective drain terminals of the third NMOS transistor (43) and the fourth NMOS transistor (44) are also connected to the second reference potential (Vddh). It is possible to provide a level shift circuit with which greater power consumption reduction and improved speed are possible.
A clock data restoration device (1A) includes a sampler portion (11), a phase comparison portion (12), a drive portion (13), a charge pump (14), a capacitive element (15), a potential adjustment portion (16) and a voltage control oscillator (17). The phase comparison portion (12) outputs a signal (UP) that becomes a significant value when the phase of a clock (CKX) delays with respect to an input digital signal, and outputs a signal (DN) that becomes a significant value when the phase advances. The drive portion (13) increases or decreases a value δ to or from a variable Δ when the signals (UP) and (DN) become a significant value, and increases or decrease a value N to or from the variable Δ when the value of the variable Δ is equal to or more than +N or when the value of the variable Δ is equal to or less than −N, and signals (UPFRQ) and (DNFRQ) are output to the charge pump (14). The potential adjustment portion (16) increases or decreases a potential at a first end of a capacitive element (15) based on the signals (UP) and (DN).
Disclosed herein are a data transmission circuit and a data communication device that transmit data using an Alternating Current (AC)-coupled transmission line. The data transmission circuit includes a data transmission unit for transmitting data via a transmission line having a single AC-coupled line or a plurality of AC-coupled lines. When transmitting data, the data transmission unit transmits the data via the transmission line by sequentially setting a first electric potential corresponding to the data and a second electric potential different from the first electric potential. When transitioning from data transmission mode to an idle state, the data transmission unit sets an intermediate electric potential between the first electric potential and the second electric potential.
A protection circuit (2) of a first embodiment of the present invention is provided with a variable resistance value switch (10), an overcurrent detection unit (20), a control voltage application unit (30), a capacitive portion (40), a control terminal voltage change portion (50) and an external terminal (11). The variable-resistance switch (10) has a control terminal (10a), a first terminal (10b), and a second terminal (10c). The control terminal voltage change portion (50) includes a switch (51) and a resistor (52) which are serially provided between the control terminal (10a) of the variable resistance value switch (10) and the reference potential terminal.
H03K 17/08 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
91.
Comparator type DC-DC converter using synchronous rectification method
A DC-DC converter 1 is provided with a voltage conversion unit 100 and a control unit 200. The control unit 200 includes: a comparator 20 and a trigger signal generation section 30 which generate a trigger signal when an output voltage is reduced from a reference voltage after having received a minimum off-time signal, a DLL section 40 generating a reference delay signal, a delay section 50 generating delay signals which are delayed from the trigger signal by a predetermined amount, further delayed by an on-time, still further delayed by a second dead time, and yet still further delayed by a minimum off-time, respectively, according to the reference delay signal, and a timing control section 60 determining a start time point and an end time point of an on-pulse, a start time point and an end time point of an off-pulse and also generating a minimum off-time signal, according to these delay signals.
G05F 1/40 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type alternatif utilisant des tubes à décharge ou des dispositifs à semi-conducteurs comme dispositifs de commande finale
A transmitting device (10A) is provided with a transmitting data generating unit (11) and an output buffer unit (12A). The transmitting data generating unit (11) generates data (data1) and a clock (clock1), which are to be transmitted to a receiving device, and outputs the data and the clock to an output buffer unit (12A). The output buffer unit (12A) includes a data transmitting unit (13) and a clock transmitting unit (14A). The clock transmitting unit (14A) generates a clock having phase shifts intermittently applied thereto, and transmits the clock. The data transmitting unit (13) transmits data in synchronization with the clock transmitted from the clock transmitting unit (14A).
A transmitting and receiving system (2) transfers an electrical signal from a transmission device (20) to a receiving device (50A) via a wiring member (10) wherein a plurality of conducting wires (11-17) are arranged in parallel. In the receiving device or the transmitting device, a conducting wire (11) is connected via a connector and a resistor, another conducting wire (14) is connected via a connector and a resistor, and another conducting wire (17) is connected via a connector and a resistor. The transmitting and receiving system is capable of carrying out high quality signal transfer.
A clock data restoration device 1, which restores a clock signal and data on the basis of an inputted digital signal, comprises an equalizer 10, a sampler 20, a clock generator 30, an equalizer controller 40, and a phase monitor 50. A clock signal CK or CKX as a clock signal restored on the basis of the input digital signal is generated through loop processing by the sampler 20 and the clock generator 30. The level adjustment amount of a high frequency component of the digital signal by the equalizer 10 is controlled through loop processing by the equalizer 10, the sampler 20 and the equalizer controller 40.
Provided is a sigma-delta modulation circuit comprising: an integration circuit which has a first terminal and a second terminal, and which integrates voltage supplied by way of the first terminal; a first DAC section which supplies a first reference voltage to one terminal of a first resistance, and alternately supplies a first voltage obtained at the other terminal of the first resistance to the first terminal or the second terminal; and a second DAC section which supplies a second reference voltage to one terminal of a second resistance, and alternately supplies a second voltage obtained at the other terminal of the second resistance to the second terminal or the first terminal. When the first DAC section supplies the first voltage to the first terminal, the second DAC section supplies the second voltage to the second terminal. When the first DAC section supplies the first voltage to the second terminal, the second DAC section supplies the second voltage to the first terminal.
Reception devices (201-20N) are arranged in one dimension in ascending order. Each reception device (20n) is provided with a data input buffer (21), a first clock input buffer (221), and a first clock output buffer (231). The first clock input buffer (221) buffers clocks inputted from first clock terminals (P21,P22) and outputs the clocks to the first clock output buffer (231). The first clock output buffer (231) buffers the clocks inputted from the first clock input buffer (221) and causes the clocks to be outputted from second clock terminals (P31,P32). Data input terminals (P11,P12) are disposed between the first clock terminals and second clock terminals.
G02F 1/133 - Dispositions relatives à la structureExcitation de cellules à cristaux liquidesDispositions relatives aux circuits
G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
98.
TRANSMITTING APPARATUS, RECEIVING APPARATUS, TRANSMITTING/RECEIVING SYSTEM, AND IMAGE DISPLAY SYSTEM
The data receiving unit (21) in a receiving apparatus (20n) receives, from the data transmitting unit (11) in a transmitting apparatus (10), correction data for detecting the data receiving status or the clock receiving status in the receiving apparatus (20n). A decoder unit (24) makes correction sample data transmitted from a transmitting unit (26) to the transmitting apparatus (10), said correction sample data having been obtained by means of a sampler unit (23) by sampling the correction data. The control unit (15) in the transmitting apparatus (10) detects the data receiving status or the clock receiving status of the receiving apparatus (20n), on the basis of the correction sample data which has been received from the receiving apparatus (20n), and the control unit controls the data transmitting unit (11) and the clock transmitting unit (12) on the basis of the detection results.
H04B 15/04 - Réduction des perturbations parasites dues aux appareils électriques avec des moyens disposés sur ou à proximité de la source de perturbation la perturbation étant causée par des ondes essentiellement sinusoïdales, p. ex. dans un récepteur ou un enregistreur à bande magnétique
100.
DATA TRANSMITTING CIRCUIT AND DATA COMMUNICATION APPARATUS
A data transmitting circuit and a data communication apparatus are provided wherein the need of a time period for adjusting the DC balance is eliminated without transmitting any SYNC patterns, thereby shortening the time interval from an idle state to a start of communication and further reducing the power consumption. The data transmitting circuit includes a data transmitting unit for transmitting data via a transmission path having a single AC coupled line or a plurality of AC coupled lines. During the data transmission, the data transmitting unit is sequentially set to a first potential, which corresponds to the data, or a second potential, which is different from the first potential, thereby transmitting the data via the transmission path. During an idle state to which a transition is made from the data transmission, the data transmitting unit is set to an intermediate potential between the first and second potentials.
